SCLS303D − JANUARY 1996 − REVISED AUGUST 2003 D Wide Operating Voltage Range of 2 V to 6 V D High-Current 3-State Outputs Can Drive Up D D D D To 15 LSTTL Loads D Low Power Consumption, 80-µA Max ICC Typical tpd = 8 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max Inverting Logic 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 A2 A1 DIR VCC VCC OE B1 B2 B3 B4 B5 B6 B7 B8 A3 A4 A5 A6 A7 4 3 2 1 20 19 18 5 17 6 16 7 15 14 8 B1 B2 B3 B4 B5 9 10 11 12 13 A8 GND B8 B7 B6 DIR A1 A2 A3 A4 A5 A6 A7 A8 GND OE SN54HC640 . . . FK PACKAGE (TOP VIEW) SN54HC640 . . . J OR W PACKAGE SN74HC640 . . . DW, N, NS, OR PW PACKAGE (TOP VIEW) description/ordering information These octal bus transceivers are designed for asynchronous two-way communication between data buses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending upon the level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated. ORDERING INFORMATION PDIP − N SOIC − DW −40°C −40 C to 85 85°C C SOP − NS TSSOP − PW −55°C −55 C to 125 125°C C ORDERABLE PART NUMBER PACKAGE† TA Tube of 20 SN74HC640N Tube of 25 SN74HC640DW Reel of 2000 SN74HC640DWR Reel of 2000 SN74HC640NSR Tube of 70 SN74HC640PW Reel of 2000 SN74HC640PWR TOP-SIDE MARKING SN74HC640N HC640 HC640 HC640 Reel of 250 SN74HC640PWT CDIP − J Tube of 20 SNJ54HC640J SNJ54HC640J CFP − W Tube of 85 SNJ54HC640W SNJ54HC640W LCCC − FK Tube of 55 SNJ54HC640FK SNJ54HC640FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ '*%$"# $')!" " 123 !)) '!!&"&# !& "&#"&* %)&## ",&.#& "&*+ !)) ",& '*%$"# '*%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCLS303D − JANUARY 1996 − REVISED AUGUST 2003 FUNCTION TABLE (each transceiver) INPUTS OPERATION OE DIR L L B data to A bus L H A data to B bus H X Isolation logic diagram (positive logic) OE DIR A1 19 1 2 18 B1 To Seven Other Transceivers absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCLS303D − JANUARY 1996 − REVISED AUGUST 2003 recommended operating conditions (see Note 3) SN54HC640 VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V High-level input voltage VCC = 6 V VCC = 2 V VIL VI VO ∆t/∆v MIN NOM MAX 2 5 6 Input voltage MAX 2 5 6 3.15 3.15 4.2 4.2 0 VCC = 6 V UNIT V V 0.5 0.5 1.35 1.35 1.8 1.8 VCC VCC VCC = 2 V VCC = 4.5 V Input transition rise/fall time NOM 1.5 0 Output voltage MIN 1.5 VCC = 4.5 V VCC = 6 V Low-level input voltage SN74HC640 0 VCC VCC 0 1000 1000 500 500 400 400 V V V ns TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH TEST CONDITIONS ICC Ci A or B DIR or OE MAX MIN MAX UNIT 1.998 1.9 1.9 IOH = −20 µA 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 IOH = −6 mA IOH = −7.8 mA 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 5.34 2V 0.002 0.1 0.1 0.1 IOL = 20 µA 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V ±0.1 ±100 ±1000 ±1000 nA 6V ±0.01 ±0.5 ±10 ±5 µA 8 160 80 µA 10 10 10 pF VI = VCC or 0 VO = VCC or 0 VI = VCC or 0, MIN SN74HC640 1.9 VI = VIH or VIL DIR or OE SN54HC640 2V IOL = 6 mA IOL = 7.8 mA II IOZ TA = 25°C MIN TYP MAX 4.5 V VI = VIH or VIL VOL VCC IO = 0 6V 2 V to 6 V POST OFFICE BOX 655303 3 • DALLAS, TEXAS 75265 V V 3 SCLS303D − JANUARY 1996 − REVISED AUGUST 2003 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) TA = 25°C TYP MAX SN54HC640 SN74HC640 PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V 29 105 160 130 tpd A or B B or A 4.5 V 10 21 32 26 6V 8 18 27 22 ten OE tdis OE tt A or B A or B A or B MIN MIN MAX MIN MAX 2V 109 230 340 290 4.5 V 27 46 68 58 6V 20 39 58 49 2V 40 150 225 190 4.5 V 18 30 45 38 6V 16 26 38 32 2V 20 60 90 75 4.5 V 8 12 18 15 6V 6 10 15 13 UNIT ns ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd ten FROM (INPUT) A or B OE tt TA = 25°C MIN TYP MAX SN54HC640 SN74HC640 TO (OUTPUT) VCC 2V 44 190 290 235 B or A 4.5 V 14 38 58 47 6V 11 33 49 41 2V 124 315 470 395 4.5 V 31 63 94 79 6V 23 54 80 68 2V 45 210 315 265 4.5 V 17 42 63 53 6V 13 36 53 45 A or B A or B MIN MAX MIN MAX UNIT ns ns ns operating characteristics, TA = 25°C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance No load POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP 40 UNIT pF SCLS303D − JANUARY 1996 − REVISED AUGUST 2003 PARAMETER MEASUREMENT INFORMATION VCC PARAMETER Test Point From Output Under Test tPZH S1 ten RL CL (see Note A) 1 kΩ tPZL tPHZ tdis S2 RL tPLZ tpd or tt 1 kΩ −− LOAD CIRCUIT CL S1 S2 50 pF or 150 pF Open Closed Closed Open Open Closed Closed Open Open Open 50 pF 50 pF or 150 pF VCC Input 50% 50% 0V tPLH In-Phase Output 50% 10% tPHL 90% VOH 50% 10% V OL tf 90% tr tPHL Out-of-Phase Output 90% tPLH 50% 10% 50% 10% 90% VOH VOL tf tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES Output Control (Low-Level Enabling) VCC 50% 50% 0V tPZL Output Waveform 1 (See Note B) tPLZ 10% tPZH Input 50% 10% 90% VCC 90% 50% 10% 0 V tr Output Waveform 2 (See Note B) ≈VCC ≈VCC 50% VOL tPHZ 50% 90% VOH ≈0 V tf VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-87809012A ACTIVE LCCC FK 20 1 TBD 5962-8780901RA ACTIVE CDIP J 20 1 TBD Lead/Ball Finish MSL Peak Temp (3) POST-PLATE N / A for Pkg Type A42 SNPB N / A for Pkg Type N / A for Pkg Type SN54HC640J ACTIVE CDIP J 20 1 TBD A42 SNPB SN74HC640DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC640DWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC640DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC640DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC640N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74HC640NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74HC640NSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC640NSRE4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC640PW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC640PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC640PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC640PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC640PWT ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC640PWTE4 ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SNJ54HC640FK ACTIVE LCCC FK 20 1 TBD SNJ54HC640J ACTIVE CDIP J 20 1 TBD POST-PLATE N / A for Pkg Type A42 SNPB N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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