TI SN64BCT241

SN64BCT241
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCBS046C – FEBRUARY 1990 – REVISED JULY 1998
D
D
D
D
D
DW OR N PACKAGE
(TOP VIEW)
State-of-the-Art BiCMOS Design
Substantially Reduces Standby Current
3-State Outputs Drive Bus Lines or
Buffer-Memory Address Registers
ESD Protection Exceeds 2000 V
Per MIL-STD-883 Method 3015
High-Impedance State During Power Up
and Power Down
Package Options Include Small-Outline
(DW) and Standard Plastic DIPs (N)
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
description
This octal buffer and line driver is designed specifically to improve both the performance and density of 3-state
memory address drivers, clock drivers, and bus-oriented receivers and transmitters. With the SN64BCT240 and
SN64BCT244, these devices provide the choice of selected combinations of inverting and noninverting outputs,
symmetrical active-low output-enable (OE) inputs, and complementary OE and OE inputs.
The SN64BCT241 is characterized for operation from – 40°C to 85°C and 0°C to 70°C.
FUNCTION TABLES
INPUTS
1OE
1A
OUTPUT
1Y
L
H
H
L
L
L
H
X
Z
INPUTS
2OE
2A
OUTPUT
2Y
H
H
H
H
L
L
L
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN64BCT241
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCBS046C – FEBRUARY 1990 – REVISED JULY 1998
logic symbol†
1OE
1A1
1A2
1A3
1A4
1
logic diagram (positive logic)
1
1OE
EN
2
18
4
16
6
14
8
12
1Y1
1A1
2OE
2A1
2A2
2A3
2A4
18
4
16
6
14
8
12
1Y1
1Y2
1Y3
1A2
1Y2
1Y4
1A3
19
2
1Y3
EN
11
9
13
7
15
5
17
3
1A4
1Y4
2Y1
2Y2
2Y3
2OE
19
2Y4
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
2A1
2A2
2A3
11
9
13
7
15
5
17
3
2A4
2Y1
2Y2
2Y3
2Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . . . . . . . . . – 0.5 V to 5.5 V
Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative voltage rating may be exceeded if the input clamp current rating is observed.
2. The package thermal impedance is calculated in acordane with JESD 51, except for through-hole packages, which use a trace length
of zero.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN64BCT241
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCBS046C – FEBRUARY 1990 – REVISED JULY 1998
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
VIL
IIK
Low-level input voltage
IOH
IOL
High-level input voltage
MIN
NOM
MAX
4.5
5
5.5
2
UNIT
V
V
0.8
V
Input clamp current
–18
mA
High-level output current
– 15
mA
Low-level output current
64
mA
TA
Operating free-air temperature
– 40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VCC = 4.5 V,
VCC = 4
4.5
5V
VOH
VCC = 4.75 V,
VCC = 4.5 V,
VOL
IOZH
1OE at 0.8 V,,
2OE at 2 V
II
IIH
IIL
1OE or 2OE
TYP†
II = –18 mA
IOH = – 3 mA
2.4
3.3
IOH = – 15 mA
IOH = – 3 mA
2
3.1
2.7
0.42
VO = 0.5 V
VCC = 0 to 2.3 V (power up)
VCC = 1.8 V to 0 (power down)
VO = 2
2.7
7 V or 0
0.5
5V
V,
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
VCC = 5
5.5
5V
V,
VI = 0
0.5
5V
IOS‡
ICCL
VCC = 5.5 V,
VCC = 5.5 V,
VO = 0
Output open
ICCH
ICCZ
VCC = 5.5 V,
VCC = 5.5 V,
Ci
VCC = 5 V,
VCC = 5 V,
Any A input
MIN
IOH = 64 mA
VO = 2.7 V
VCC = 5.5 V,
VCC = 5.5 V,
IOZL
IOZ
TEST CONDITIONS
UNIT
–1.2
V
V
0.55
V
50
µA
– 50
µA
" 50
" 50
mA
20
µA
– 1.6
– 100
µA
0.1
–1
mA
– 225
mA
23
43
mA
Output open
53
85
mA
Output open
4
10
mA
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
6
pF
11
pF
Co
† All typical values are at VCC = 5 V, TA = 25°C.
‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
POST OFFICE BOX 655303
MAX
• DALLAS, TEXAS 75265
3
SN64BCT241
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCBS046C – FEBRUARY 1990 – REVISED JULY 1998
switching characteristics (see Figure 1)
PARAMETER
4
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Y
tPZH
tPZL
1OE or 2OE
Y
tPHZ
tPLZ
1OE or 2OE
Y
POST OFFICE BOX 655303
VCC = 5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω
Ω,
TA = 25°C
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω
TA = – 40°C
to 85°C
UNIT
TA = 0°C
to 70°C
MIN
MAX
MIN
MAX
MIN
MAX
0.5
4.5
0.5
5.2
0.5
4.9
1
5.4
1
6.3
1
5.9
1
7.8
1
9.1
1
8.7
1
8.6
1
10
1
9.4
1
6.8
1
8.4
1
8.1
1
8.1
1
11
1
9.9
• DALLAS, TEXAS 75265
ns
ns
ns
SN64BCT241
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCBS046C – FEBRUARY 1990 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
7 V (tPZL, tPLZ, O.C.)
S1
Open
(all others)
From Output
Under Test
Test
Point
CL
(see Note A)
R1
From Output
Under Test
R1
Test
Point
CL
(see Note A)
R2
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-COLLECTOR OUTPUTS
High-Level
Pulse
(see Note B)
3V
Timing Input
(see Note B)
3V
1.5 V
1.5 V
0V
1.5 V
tw
0V
Data Input
(see Note B)
3V
th
tsu
Low-Level
Pulse
3V
1.5 V
1.5 V
0V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
3V
Input
(see Note B)
1.5 V
1.5 V
0V
tPLH
In-Phase
Output
(see Note D)
VOH
1.5 V
1.5 V
VOL
1.5 V
1.5 V
1.5 V
0V
tPLZ
1.5 V
Waveform 1
(see Notes C and D)
3.5 V
VOL
tPHZ
tPLH
VOH
1.5 V
tPZL
tPHL
tPHL
Out-of-Phase
Output
(see Note D)
Output
Control
(low-level enable)
0.3 V
tPZH
Waveform 2
(see Notes C and D)
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (see Note D)
VOH
1.5 V
0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, tr = tf ≤ 2.5 ns, duty cycle = 50%.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
E. When measuring propagation delay times of 3-state outputs, switch S1 is open.
Figure 1. Load Circuits and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN64BCT241DW
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
SN64BCT241N
OBSOLETE
PDIP
N
20
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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