TI SN65MLVD047DR

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SLLS606 − MARCH 2004
FEATURES
D Differential Line Drivers for 30-Ω to 55-Ω
Loads and Data Rates(1) Up to 200 Mbps,
Clock Frequencies up to 100 MHz
Supports Multipoint Bus Architectures
Meets the Requirements of TIA/EIA-899
Operates from a Single 3.3-V Supply
D
D
D
D Characterized for Operation from −405C to
855C
D 16-Pin SOIC (JEDEC MS-012) and 16-Pin
TSSOP (JEDEC MS-153) Packaging
APPLICATIONS
D AdvancedTCAE (ATCAE) Clock Bus Driver
D Clock Distribution
D Backplane or Cabled Multipoint Data
Transmission in Telecommunications,
Automotive, Industrial, and Other Computer
Systems
D
D
D
D
Cellular Base Stations
Central-Office and PBX Switching
Bridges and Routers
Low-Power High-Speed Short-Reach
Alternative to TIA/EIA-485
DESCRIPTION
The SN65MLVD047 is a quadruple line driver that
complies with the TIA/EIA-899 standard, Electrical
Characteristics of Multipoint-Low-Voltage Differential
Signaling (M−LVDS). The output current of this M−LVDS
device has been increased, in comparison to standard
LVDS compliant devices, in order to support doubly
terminated transmission lines and heavily loaded
backplane bus applications. Backplane applications
generally require impedance matching termination
resistors at both ends of the bus. The effective impedance
of a doubly terminated bus can be as low as 30 Ω due to
the bus terminations, as well as the capacitive load of bus
interface devices. SN65MLVD047 drivers allow for
operation with loads as low as 30 Ω. The SN65MLVD047
devices allow for multiple drivers to be present on a single
bus. SN65MLVD047 drivers are high impedance when
disabled or unpowered. Driver edge rate control is
incorporated to support operation. The M−LVDS standard
allows up to 32 nodes (drivers and/or receivers) to be
connected to the same media in a backplane when
multiple bus stubs are expected from the main
transmission
line
to
interface
devices.
The
SN65MLVD047 provides 9-kV ESD protection on all bus
pins.
LOGIC DIAGRAM (POSITIVE LOGIC)
EN
EN
1A
2A
3A
4A
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
(1)The data rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
AdvancedTCA and ATCA are trademarks of the PCI Industrial Computer Manufacturers Group.
! "#$ ! %#&'" ($) (#"!
" !%$""! %$ *$ $! $+! !#$! !(( ,-)
(#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!)
Copyright  2004, Texas Instruments Incorporated
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SLLS606 − MARCH 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART NUMBER
PACKAGE MARKING
PACKAGE/CARRIER
SN65MLVD047D
MLVD047
16-Pin SOIC/Tube
16-Pin SOIC/Tape and Reel
SN65MLVD047DR
MLVD047
SN65MLVD047PW
MLVD047
16-Pin TSSOP/Tube
SN65MLVD047PWR
MLVD047
16-Pin TSSOP/Tape and Reel
PACKAGE DISSIPATION RATINGS
PACKAGE
D(16)
PW(16)
PCB JEDEC
STANDARD
Low-K(2)
TA ≤ 25°C
POWER RATING
Low-K(2)
High-K(3)
TA = 85°C
POWER RATING
898 mW
DERATING FACTOR
ABOVE TA = 25°C(1)
7.81 mW/_C
592 mW
5.15 mW/_C
283 mw
429 mW
945 mW
8.22 mW/_C
452 mw
(1) This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.
(2) In accordance with the Low-K thermal metric difinitions of EIA/JESD51−3.
(3) In accordance with the High-K thermal metric difinitions of EIA/JESD51−7.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNITS
Supply voltage range(2), VCC
−0.5 V to 4 V
Input voltage range, VI
A, EN, EN
−0.5 V to 4 V
Output voltage range, VO
Y, Z
−1.8 V to 4 V
Human Body Model(3)
Electrostatic discharge
Charged-Device Model(4)
Machine Model(5)
Junction temperature, TJ
Continuous power dissipation, PD
Y and Z
±9 kV
All pins
±4 kV
All pins
±1500 V
All pins
200 V
140°C
See Dissipation Rating Table
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to the circuit ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114−B.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101−A.
(5) Tested in accordance with JEDEC Standard 22, Test Method A115−A.
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RECOMMENDED OPERATING CONDITIONS (see Figure 1)
MIN
NOM
Supply voltage, VCC
3
3.3
High-level input voltage, VIH
2
Low-level input voltage, VIL
Voltage at any bus terminal (separate or common mode) VY or VZ
Differential load resistance, RL
MAX UNIT
3.6
V
VCC
0.8
V
0
−1.4
3.8
V
55
Ω
30
Signaling rate, 1/tUI
V
200 Mbps
Clock frequency
Junction temperature, TJ
−40
100
MHz
125
°C
THERMAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
Low-K board(1), no airflow
Low-K board(1), no airflow
Junction-to-ambient thermal resistance, ΘJA
Low-K board(1), 150 LFM
Low-K board(1), 250 LFM
MIN
D
High-K board(2)
Junction-to-case thermal resistance, ΘJC
Device power dissipation, PD
MAX
UNIT
128
194.2
PW
High-K board(2), no airflow
Junction-to-board thermal resistance, ΘJB
TYP
°C/W
C/W
146.8
133.1
121.6
D
51.1
PW
85.3
D
45.4
PW
34.7
°C/W
°C/W
EN = VCC, EN = GND, RL = 50 Ω,
Input 100 MHz 50 % duty cycle square wave to
1A:4A, TA = 85°C
288.5
mW
MIN(1) TYP(2)
MAX
UNIT
59
70
2
4
(1) In accordance with the Low-K thermal metric difinitions of EIA/JESD51−3.
(2) In accordance with the High-K thermal metric difinitions of EIA/JESD51−7.
DEVICE ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
ICC
TEST CONDITIONS
Driver enabled
EN = VCC, EN = GND, RL = 50 Ω, All inputs = VCC or
GND
Driver disabled
EN = GND, EN = VCC, RL = No load, All inputs = VCC or
GND
Supply current
mA
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) All typical values are at 25°C and with a 3.3-V supply voltage.
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DEVICE ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN(1)
TYP(2)
MAX
UNIT
LVTTL (EN, EN, 1A:4A)
|IIH|
High-level input current
VIH = 2 V or VCC
0
10
µA
|IIL|
Low-level input current
VIL = GND or 0.8 V
0
10
µA
Ci
Input capacitance
M−LVDS (1Y/1Z:4Y/4Z)
VYZ
Differential output voltage magnitude
∆VYZ
Change in differential output voltage magnitude
between logic states
VOS(SS)
Steady-state common-mode output voltage
∆VOS(SS)
Change in steady-state common-mode output
voltage between logic states
VOS(PP)
Peak-to-peak common-mode output voltage
VY(OC)
Maximum steady-state open-circuit output
voltage
VI = 0.4 sin(30E6πt) + 0.5 V(3)
See Figure 2
See Figure 3
5
pF
480
650
mV
−50
50
mV
0.8
1.2
V
−50
50
mV
150
mV
0
2.4
V
0
2.4
V
1.2 VSS
V
See Figure 7
VZ(OC)
Maximum steady-state open-circuit output
voltage
VP(H)
Voltage overshoot, low-to-high level output
VP(L)
Voltage overshoot, high-to-low level output
IOS
Differential short-circuit output current magnitude
See Figure 4
IOZ
High-impedance state output current
−1.4 V ≤ (VY or VZ) ≤ 3.8 V,
Other output = 1.2 V
IO(OFF)
Power-off output current
−1.4 V ≤ (VY or VZ) ≤ 3.8 V,
Other output = 1.2 V,
VCC = 0 V
CY or CZ
Output capacitance
VY or VZ = 0.4 sin(30E6πt) +
0.5 V, (3)
Other input at 1.2 V, driver disabled
CYZ
Differential output capacitance
VYZ = 0.4 sin(30E6πt) V, (3)
Driver disabled
See Figure 5
−0.2 VSS
V
24
mA
−15
10
µA
−10
10
µA
3
CY/Z
0.99
1.01
Output capacitance balance, (CY/CZ)
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) All typical values are at 25°C and with a 3.3-V supply voltage.
(3) HP4194A impedance analyzer (or equivalent)
4
pF
2.5
pF
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SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
tpLH
Propagation delay time, low-to-high-level output
1
1.5
2.4
ns
tpHL
Propagation delay time, high-to-low-level output
1
1.5
2.4
ns
tr
Differential output signal rise time
1
1.9
ns
tf
Differential output signal fall time
1
1.9
ns
tsk(o)
Output skew
100
ps
tsk(p)
Pulse skew (|tpHL − tpLH|)
100
ps
tsk(pp)
Part-to-part skew(2)
600
ps
tjit(per)
Period jitter, rms (1 standard deviation)(3)
All inputs 100 MHz clock input
1
ps
tjit(c−c)
Cycle-to-cycle jitter(3)
All inputs 100 MHz clock input
5
36
ps
tjit(pp)
Peak-to-peak jitter(3)(4)
All inputs 200 Mbps 215−1 PRBS input
46
158
ps
tpZH
Enable time, high-impedance-to-high-level output
7
ns
tpZL
Enable time, high-impedance-to-low-level output
7
ns
tpHZ
Disable time, high-level-to-high-impedance output
8
ns
See Figure 5
22
See Figure 6
0.2
See Figure 6
tpLZ
8
ns
Disable time, low-level-to-high-impedance output
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) Stimulus jitter has been subtracted from the measurements.
(4) Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)).
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SLLS606 − MARCH 2004
PARAMETER MEASUREMENT INFORMATION
VCC
IY
Y
II
D
VYZ
IZ
VY
Z
VI
VOS
VZ
VY + VZ
2
Figure 1. Driver Voltage and Current Definitions
3.32 kΩ
Y
+
_
49.9 Ω
VYZ
D
Z
−1 V ≤ Vtest ≤ 3.4 V
3.32 kΩ
NOTE: All resistors are 1% tolerance.
Figure 2. Differential Output Voltage Test Circuit
R1
24.9 Ω
Y
C1
1 pF
D
≈ 1.3 V
Z
≈ 0.7 V
VOS(PP)
Z
C2
1 pF
Y
R2
24.9 Ω
VOS
C3
2.5 pF
nVOS(SS)
VOS(SS)
NOTES:A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse frequency = 500 kHz,
duty cycle = 50 ± 5%.
B. C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 and R2 are metal film, surface mount, ±1%, and located within 2 cm of the D.U.T.
D. The measurement of VOS(PP) is made on test equipment with a −3 dB bandwidth of at least 1 GHz.
Figure 3. Test Circuit and Definitions for the Common-Mode Output Voltage
Y
0 V or VCC
IOS
+
Z
VTest
−1 V to 3.4 V
−
Figure 4. Short-Circuit Test Circuit
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SLLS606 − MARCH 2004
Y
C1
1 pF
D
C3
0.5 pF
R1
Output
50 Ω
Z
C2
1 pF
VCC
VCC/2
Input
0V
tpLH
tpHL
VSS
0.9VSS
VP(H)
Output
0V
VP(L)
0.1V
SS
0 V SS
tf
tr
NOTES:A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 500 kHz,
duty cycle = 50 ± 5%.
B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a −3 dB bandwidth of at least 1 GHz.
Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
R1
24.9 Ω
Y
0 V or VCC
C1
1 pF
D
Z
Input
C4
Output
0.5 pF
C2
1 pF
C3
2.5 pF
R2
24.9 Ω
EN or EN
VCC
VCC/2
0V
EN
EN
tpZH
tpHZ
∼ 0.6 V
0.1 V
0V
Output With
D at VCC
Output With
D at 0 V
tpZL
tpLZ
0V
−0.1 V
∼ −0.6 V
NOTES:A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 500 kHz, duty cycle = 50 ±
5%.
B. C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a −3 dB bandwidth of at least 1 GHz.
Figure 6. Driver Enable and Disable Time Circuit and Definitions
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SLLS606 − MARCH 2004
Y
0 V or VCC
Z
1.62 kΩ , ±1%
VY, or VZ
Figure 7. Driver Maximum Steady State Output Voltage
VCC
CLOCK
INPUT
VCC/2
0V
1/f0
Period Jitter
IDEAL
OUTPUT 0 V
VCC
PRBS INPUT
VY −VZ
VCC/2
1/f0
0V
ACTUAL
OUTPUT 0 V
Peak to Peak Jitter
VY −VZ
VY −VZ
tc(n)
tjit(per) =tc(n) −1/f0
OUTPUT
0V
VY −VZ
tjit(pp)
Cycle to Cycle Jitter
OUTPUT
0V
VY − VZ
tc(n)
tc(n+1)
tjit(cc) = | tc(n) − tc(n+1) |
NOTES:A.
B.
C.
D.
All input pulses are supplied by an Agilent 8304A Stimulus System.
The measurement is made on a TEK TDS6604 running TDSJIT3 application software
Period jitter and cycle-to-cycle jitter are measured using a 100 MHz 50 ±1% duty cycle clock input.
Peak-to-peak jitter is measured using a 200 Mbps 215−1 PRBS input.
Figure 8. Driver Jitter Measurement Waveforms
DEVICE INFORMATION
PIN ASSIGNMENTS
D PACKAGE
(TOP VIEW)
EN
1A
2A
VCC
GND
3A
4A
EN
8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PW PACKAGE
(TOP VIEW)
1Z
1Y
2Y
2Z
3Z
3Y
4Y
4Z
EN
1A
2A
VCC
GND
3A
4A
EN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1Z
1Y
2Y
2Z
3Z
3Y
4Y
4Z
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SLLS606 − MARCH 2004
DEVICE FUNCTION TABLE
INPUTS
EN
D
L
H
OPEN
X
X
H
H
H
L or OPEN
X
EN
L
L
L
X
H or OPEN
OUTPUTS
Y
Z
L
H
L
Z
Z
H
L
H
Z
Z
H = high level, L = low level, Z = high impedance, X = Don’t care
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
DRIVER INPUT AND POSITIVE DRIVER ENABLE
VCC
DRIVER OUTPUT
NEGATIVE DRIVER ENABLE
VCC
VCC
360 kΩ
400 Ω
D or EN
7V
400 Ω
Y or Z
360 kΩ
EN
7V
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TYPICAL CHARACTERISTICS
RMS SUPPLY CURRENT
vs
INPUT FREQUENCY
RMS SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
75
70
65
VCC = 3.3 V,
TA = 255C,
EN = VCC,
EN = GND,
RL = 50 W,
All Inputs
I CC − Supply Current − mArms
ICC − Supply Current − mArms
80
65
60
64
VCC = 3.3 V,
f = 50 MHz,
EN = VCC,
EN = GND,
RL = 50 W
63
62
61
55
60
50
25
50
75
100
f − Input Frequency − MHz
−40
125
−15
10
35
60
TA − Free-Air Temperature − °C
Figure 9
Figure 10
DRIVER PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
600
1.54
TA = 255C,
RL = 50 W
VCC = 3.6 V
VCC = 3.3 V
580
1.52
t pd − Propagation Delay Time − ns
VYZ − Differential Output Voltage Magnitude − mV
DIFFERENTIAL OUTPUT VOLTAGE MAGNITUDE
vs
INPUT FREQUENCY
560
540
VCC = 3 V
520
VCC = 3.3 V,
f = 500 kHz,
RL = 50 W
tPHL
1.5
tPLH
1.48
1.46
1.44
1.42
1.4
1.38
1.36
500
25
50
75
100
f − Input Frequency − MHz
Figure 11
10
85
125
1.34
−40
−15
10
35
60
TA − Free-Air Temperature − °C
Figure 12
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TYPICAL CHARACTERISTICS
PEAK-TO-PEAK JITTER
vs
DATA RATE
100
1.8
1.7
VCC = 3.3 V,
f = 500 kHz,
RL = 50 W
90
80
tf
t jit(p-p) − Peak-To-Peak Jitter − ps
t r or tf − Rising or Falling Transition Time − ns
DRIVER TRANSITION TIME
vs
FREE-AIR TEMPERATURE
1.6
tr
1.5
1.4
1.3
1.2
−40
−15
10
35
60
70
60
50
40
30
20
10
85
VCC = 3.3 V,
TA = 255C,
All Inputs = 215−1 PRBS NRZ,
(See Figure 8)
50
100
TA − Free-Air Temperature − °C
Figure 13
t jit(per) − Period Jitter − ps
0.8
10
VCC = 3.3 V,
TA = 255C,
All Inputs = Clock
(See Figure 8)
9
0.7
0.6
0.5
0.4
0.3
0.2
8
VCC = 3.3 V,
TA = 255C,
All Inputs = Clock
(See Figure 8)
7
6
5
4
3
2
1
0.1
0
250
CYCLE-TO-CYCLE JITTER
vs
CLOCK FREQUENCY
t jit(c-c) − Cycle-To-Cycle Jitter − ps
0.9
200
Figure 14
PERIOD JITTER
vs
CLOCK FREQUENCY
1
150
Data Rate − Mbps
25
50
75
100
f − Clock Frequency − MHz
Figure 15
125
0
25
50
75
100
125
f − Clock Frequency − MHz
Figure 16
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APPLICATION INFORMATION
SYNCHRONIZATION CLOCK IN ADVANCEDTCA
Advanced Telecommunications Computing Architecture, also known as AdvancedTCA, is an open architecture to meet
the needs of the rapidly changing communications network infrastructure. M−LVDS bused clocking is recommended by
the ATCA.
The ATCA specification includes requirements for three redundant clock signals. An 8-KHz and a 19.44-MHz clock signal,
as well as an user-defined clock signal are included in the specification. The SN65MLVD047 quad driver supports
distribution of these three ATCA clock signals, supporting operation beyond 100 MHz, which is the highest clock frequency
included in the ATCA specification. A pair of SN65MLVD047 devices can be used to support the ATCA redundancy
requirements.
MULTIPOINT CONFIGURATION
The SN65MLVD047 is designed to meet or exceed the requirement of the TIA/EIA−899 (M−LVDS) standard, which allows
multipoint communication on a shared bus.
Multipoint is a bus configuration with multiple drivers and receivers present. An example is shown in Figure 17. The figure
shows transceivers interfacing to the bus, but a combination of drivers, receivers, and transceivers is also possible.
Termination resistors need to be placed on each end of the bus, with the termination resistor value matched to the loaded
bus impedance.
Figure 17. Multipoint Architecture
MULTIDROP CONFIGURATION
Multidrop configuration is similar to multipoint configuration, but only one driver is present on the bus. A multidrop system
can be configured with the driver at one end of the bus, or in the middle of the bus. When a driver is located at one end,
a single termination resistor is located at the far end, close to the last receiver on the bus. Alternatively, the driver can be
located in the middle of the bus, to reduce the maximum flight time. With a centrally located driver, termination resistors
are located at each end of the bus. In both cases the termination resistor value should be matched to the loaded bus
impedance. Figure 18 shows examples of both cases.
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SLLS606 − MARCH 2004
D
Zt
Zt
Zt
D
Figure 18. Multidrop Architectures With Different Driver Locations
UNUSED CHANNEL
The SN65MLVD047 is designed to meet or exceed the requirement of the TIA/EIA−899 (M−LVDS) standard, which allows
multipoint communication on a standard bus. A 360-kΩ pull-down resistor is built in every LVTTL input. The unused driver
inputs and outputs may be left floating.
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PACKAGE OPTION ADDENDUM
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26-Apr-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65MLVD047D
ACTIVE
SOIC
D
16
SN65MLVD047DR
ACTIVE
SOIC
D
16
SN65MLVD047PW
ACTIVE
TSSOP
PW
16
90
SN65MLVD047PWG4
ACTIVE
TSSOP
PW
16
SN65MLVD047PWR
ACTIVE
TSSOP
PW
SN65MLVD047PWRG4
ACTIVE
TSSOP
PW
40
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TBD
CU NIPDAU
Level-1-220C-UNLIM
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
16
2000
TBD
CU NIPDAU
Level-1-220C-UNLIM
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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