TI SN74AHCT32Q

SN74AHCT32Q
QUADRUPLE 2-INPUT POSITIVE-OR GATE
SGDS025 – FEBRUARY 2002
D
D
D
D
D
D OR PW PACKAGE
(TOP VIEW)
Q Devices Meet Automotive Performance
Requirements
Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
EPIC (Enhanced-Performance Implanted
CMOS) Process
Inputs Are TTL-Voltage Compatible
Latch-Up Performance Exceeds 250 mA Per
JESD 17
1A
1B
1Y
2A
2B
2Y
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
4B
4A
4Y
3B
3A
3Y
description
The SN74AHCT32Q is a quadruple 2-input positive-OR gate. This device performs the Boolean function
Y
+ A • B or Y + A ) B in positive logic.
ORDERING INFORMATION
–40°C
40°C to 125°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SOIC – D
Tape and reel
SN74AHCT32QDR
TSSOP – PW
Tape and reel
SN74AHCT32QPWR
TOP-SIDE
MARKING
AHCT32Q
HB32Q
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
B
OUTPUT
Y
H
X
H
X
H
H
L
L
L
A
logic symbol‡
1A
1B
2A
2B
3A
3B
4A
4B
1
≥1
3
2
1Y
4
6
5
2Y
9
8
10
3Y
12
11
13
4Y
‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74AHCT32Q
QUADRUPLE 2-INPUT POSITIVE-OR GATE
SGDS025 – FEBRUARY 2002
logic diagram, each gate (positive logic)
A
Y
B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
VO
IOH
Output voltage
IOL
∆t/∆v
Low-level output current
High-level input voltage
MIN
MAX
4.5
5.5
2
High-level output current
Input transition rise or fall rate
UNIT
V
V
0.8
V
0
5.5
V
0
VCC
–8
V
mA
8
mA
20
ns/V
TA
Operating free-air temperature
–40
125
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AHCT32Q
QUADRUPLE 2-INPUT POSITIVE-OR GATE
SGDS025 – FEBRUARY 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
VOH
IOH = –50 mA
IOH = –8 mA
45V
4.5
VOL
IOL = 50 mA
IOL = 8 mA
45V
4.5
II
ICC
VI = 5.5 V or GND
VI = VCC or GND,
∆ICC†
One input at 3.4 V,
Other inputs at VCC or GND
MIN
TA = 25°C
TYP
MAX
4.4
4.5
MAX
4.4
3.94
UNIT
V
3.8
0.1
0.1
0.36
0.44
V
±0.1
±1
mA
5.5 V
2
20
mA
5.5 V
1.35
1.5
mA
0 V to 5.5 V
IO = 0
MIN
Ci
VI = VCC or GND
5V
2
10
† This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
pF
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
tPLH
tPHL
A or B
Y
CL = 15 pF
tPLH
tPHL
A or B
Y
CL = 50 pF
TA = 25°C
MIN
TYP
MAX
MIN
MAX
5
6.9
1
8
5
6.9
1
8
5.5
7.9
1
9
5.5
7.9
1
9
MIN
TYP
MAX
UNIT
ns
ns
noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4)
PARAMETER
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.4
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.4
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
4.5
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
V
2
V
0.8
V
TYP
UNIT
11.5
pF
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
f = 1 MHz
3
SN74AHCT32Q
QUADRUPLE 2-INPUT POSITIVE-OR GATE
SGDS025 – FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
RL = 1 kΩ
From Output
Under Test
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
3V
1.5 V
Input
1.5 V
th
tsu
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
1.5 V
tPLZ
≈VCC
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
tPZL
tPZH
tPLH
50% VCC
3V
Output
Control
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
TBD
Lead/
Ball Finish
Call TI
MSL Peak Temp
(3)
Samples
(Requires Login)
SN74AHCT32QDR
ACTIVE
SOIC
D
14
Call TI
SN74AHCT32QDRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74AHCT32QPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74AHCT32QPWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74AHCT32QPWR
Package Package Pins
Type Drawing
TSSOP
PW
14
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
12.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AHCT32QPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
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