SN54/74LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54/ 74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop by simply connecting the J and K pins together. DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY LOGIC DIAGRAM J SUFFIX CERAMIC CASE 620-09 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 16 1 MODE SELECT — TRUTH TABLE INPUTS OUTPUTS OPERATING MODE Set Reset (Clear) *Undetermined Load “1” (Set) Hold Toggle Load “0” (Reset) SD CD J K Q Q L H L H H H H H L L H H H H X X X h l h l X X X h h l l H L H H q q L L H H L q q H ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC LOGIC SYMBOL * Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously. H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Don’t Care l, h (q) = Lower case letters indicate the state of the referenced input (or output) l, h (q) = one set-up time prior to the LOW to HIGH clock transition. 5-181 FAST AND LS TTL DATA SN54/74LS109A GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 74 4.0 8.0 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Min Typ Max Unit 2.0 54 0.7 74 0.8 – 0.65 – 1.5 Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA 54 2.5 3.5 V 74 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 54, 74 0.25 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA 20 40 µA VCC = MAX, VIN = 2.7 V mA VCC = MAX, VIN = 7.0 V – 0.4 – 0.8 mA VCC = MAX, VIN = 0.4 V – 100 mA VCC = MAX 8.0 mA VCC = MAX Input HIGH Current J, K, Clock Set, Clear J, K, Clock Set, Clear IIL Input LOW Current J, K, Clock Set, Clear IOS Output Short Circuit Current (Note 1) ICC Power Supply Current 0.1 0.2 – 20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter fMAX Maximum Clock Frequency tPLH tPHL Clock, Clear, Set to Output Min Typ 25 33 Max Unit Test Conditions MHz 13 25 ns 25 40 ns Max Unit VCC = 5.0 V CL = 15 pF AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ tW Clock High Clear, Set Pulse Width 25 ns ts Data Setup Time — HIGH Data Setup Time — LOW 20 ns 20 ns th Hold time 5.0 ns FAST AND LS TTL DATA 5-182 Test Conditions VCC = 5.0 V Case 751B-03 D Suffix 16-Pin Plastic SO-16 -A- "! ! " " ! " # 1 %# ) ! !" $ !" 8 C -T- D M K " ! #! J F ! Case 648-08 N Suffix 16-Pin Plastic R X 45° G " ! ) #! P ! " " 9 -B- ! 16 & ! ! ° ° ° ° ( ( ( ( "! ! " " ! ! ' " " ! ' ! " # & -A- 16 9 1 8 ! ! $ ! B # ) " ! " # ) !" $ !" ) F L C S -T- K H G M J D " Case 620-09 J Suffix 16-Pin Ceramic Dual In-Line -A- ! ! ! ! ° ° ° ° "! ! " 16 " ) " L K M N J G D " $ " $ ! " " ! ! FAST AND LS TTL DATA 5-183 & # ) !" $ !" ) -T $ " " C F & 8 E ! ! ! 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Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. ◊ FAST AND LS TTL DATA 5-184