SS809/810G 3-Pin Microprocessor Reset Circuits FEATURES DESCRIPTION Ultra-low supply current 1µA (typ.) The SS809G and SS810G are low-power microprocessor Guaranteed reset valid to Vcc=0.9V (µP) supervisory circuits used to monitor power supplies Available in three output types: in µP and digital systems. They improve circuit reliability Open-drain active low (SS809N-xxGx) Push-pull active low and reduce cost by eliminating external components. (SS809-xxGx) Push-pull active high (SS810-xxGx) These devices provide valid signals in applications Power-on reset pulse width min. 140ms Internally fixed threshold 2.3V, 2.6V, 2.9V, 3.1V, with Vcc ranging from 6.0V down to 0.9V. The reset 4.0V, 4.4V, 4.6V signal lasts for a minimum period of 140ms whenever the Tight voltage threshold tolerance: 1.5% VCC supply voltage falls below a preset threshold. Both Packaged in RoHS-compliant SOT-23-3 the SS809G and SS810G were designed with a reset comparator to help identify invalid signals lasting less APPLICATIONS than 140ms. The only difference between the two l Notebook Computers l Digital Still Cameras devices is that one has an active -low RESET output l PDAs and the other an active -high RESET output . l Critical Microprocessor Monitoring Low supply current (1µA) makes the SS809G and SS810G ideal for portable equipment. The devices are available in a SOT-23-3 package. TYPICAL APPLICATION CIRCUIT VCC VCC VCC SS809G ( SS810G) RESET (RESET) µP RESET INPUT GND GND Push -Pull Output 9/20/2006 Rev.3.01 www.SiliconStandard.com 1 of 8 SS809/810G ORDERING INFORMATION PIN CONFIGURATION SS809X-XXGU XX SS810 -XXGU XX SOT-23-3 TOP VIEW 1: GND 2: RESET (RESET) 3: VCC Packing type TR: T ape and reel 3 1 2 Package type GU: RoHS-compliant Pb-free SOT-23-3 Reset threshold voltage 23: 2.3V 26: 2.6V 29: 2.9V 31: 3.1V 40: 4.0V 44: 4.4V 46: 4.6V Output type Default: Push-Pull type N: N-ch open-drain type Example: SS809 -31GU TR à 3.1V , push- pull version in RoHS-compliant SOT -23-3 , shipped in tape and reel SOT -23 Part Marking Part No. Marking Part No. Marking Part No. Marking SS809-23GU RA23P SS809N-23GU RB23P SS810-23GU RD23P SS809-26GU RA26P SS809N-26GU RB26P SS810-26GU RD26P SS809-29GU RA29P SS809N-29GU RB29P SS810-29GU RD29P SS809-31GU RA31P SS809N-31GU RB31P SS810-31GU RD31P SS809-40GU RA40P SS809N-40GU RB40P SS810-40GU RD40P SS809-44GU RA44P SS809N-44GU RB44P SS810-44GU RD44P SS809-46GU RA46P SS809N-46GU RB46P SS810-46GU RD46P 9/20/2006 Rev.3.01 www.SiliconStandard.com 2 of 8 SS809/810G ABSOLUTE MAXIMUM RATINGS VCC -0.3V ~6.5V RESET, RESET -0.3V ~ (VCC+0.3V) Input Current (V CC) 20mA Output Current (RESET or RESET ) 20mA Continuous Power Dissipation (TA = +70°C) 320mW Operating Junction Temperature Range -40°C ~ 85°C Storage Temperature Range - 65°C ~ 125°C Lead Temperature (Soldering) 10 sec 260°C Note1: Any stress beyond the Absolute Maximum Ratings above may cause permanent damage to the device. TEST CIRCUIT Vin 3 Iin VCC RESET 2 GND SS809G 1 9/20/2006 Rev.3.01 www.SiliconStandard.com 3 of 8 SS809/810G ELECTRICAL CHARACTERISTICS (Typical values are at TA=25°C, unless otherwise specified.) PARAMETER SYMBOL Operating Voltage Range VCC Supply Current ICC TEST CONDITIONS VCC = VTH +0.1V SS809-26 SS809-29 VTH SS809-31 SS809-40 SS809-44 SS809-46 TA=+25°C 2.265 TA= -40°C to +85°C 2.254 TA=+25°C 2.561 TA= -40°C to +85°C 2.548 TA=+25°C 2.857 TA= -40°C to +85°C 2.842 TA=+25°C 3.054 TA= -40°C to +85°C 3.038 TA=+25°C 3.940 TA= -40°C to +85°C 3.920 TA=+25°C 4.334 TA= -40°C to +85°C 4.312 TA=+25°C 4.531 TA=-40°C to +85°C 4.508 VCC to Reset Delay TRD VCC=VTH to (VTH -0.1V), VTH=3.1V Reset Active Timeout Period TRP VCC = VTH ( MAX) VOH VCC=VTH+0.1V, ISOURCE =1mA VOL VCC=VTH - 0.1V, ISINK =1mA VOH VCC=VTH-0.1V, ISOURCE =1mA VOL VCC=VTH+0.1V, ISINK =1mA RESET Output Voltage RESET Output Voltage TYP. MAX. UNIT 6 V 1 3 µA 2.3 2.335 0.9 SS809-23 Reset Threshold MIN. 2.346 2.6 2.639 2.652 2.9 2.944 2.958 3.1 3.147 3.162 4.0 4.060 4.080 4.4 4.466 4.488 4.6 4.669 4.692 µS 20 TA=+25°C 140 TA= -40°C to +85°C 100 V 230 560 1030 0.8V CC 0.2Vcc 0.8V CC mS V V 0.2Vcc Note2: RESET output is for the SS809G; RESET output is for the SS810G. Note3: Specifications for operating temperature ranges from -40°C to 85°C are guaranteed by Statistical Quality Controls (SQC), with no production testing. 9/20/2006 Rev.3.01 www.SiliconStandard.com 4 of 8 SS809/810G TYPICAL PERFORMANCE CHARACTERISTICS 120 Supply Current (µA) 1.4 VTH=2.3V 1.3 1.2 1.1 VTH=3.1V 1.0 VTH=4.6V 0.9 0.8 0.7 0.6 Power -Down Reset Delay (µs ) 1.5 110 VTH=2.3V VO D=VTH-VCC 100 90 80 70 VOD=50mV 60 50 VOD=100mV 40 30 VOD=200mV 20 10 0 0.5 - 20 -40 0 40 20 60 80 100 -60 Temperature (° C) -40 -20 0 20 40 60 80 100 Temperature (° C) Fig 2 Power-Down Reset Delay vs. Temperature Fig 1 Supply Current vs. Temperature VTH=3.1V VO D=VTH-VCC 220 200 Power -Down Reset Delay (µs ) Power -Down Reset Delay (µs ) 240 180 160 140 VOD=50mV 120 100 80 60 VOD=100mV 40 VOD=200mV 20 0 VTH=4.6V VOD=50mV 400 VOD=VTH-VCC 300 200 VOD=100mV 100 VOD=200mV 0 -60 - 40 0 -20 20 40 60 80 100 -60 - 40 - 20 0 20 40 60 80 100 Temperature (° C) Temperature (° C) Fig 3 Power-Down Reset Delay vs. Temperature Fig 4 Power-Down Reset Delay vs. Temperature Power -Up Reset Timeout (ms) Normalized Reset Threshold (V) 600 1.015 VTH=4.6V 1.010 1.005 1.000 VTH=3.1V 0.995 VTH=2.3V 0.990 0.985 -40 -20 0 20 40 60 80 100 Temperature (° C) Fig 5 Normalized Reset Threshold vs. Temperature 9/20/2006 Rev.3.01 500 400 VTH=3.1V VTH=4.6V 300 200 VTH=2.3V 100 0 -60 -40 -20 0 20 40 60 80 100 Temperature (° C) Fig 6 Power-Up Reset Timeout vs. Temperature www.SiliconStandard.com 5 of 8 SS809/810G BLOCK DIAGRAM VCC R1 Bandgap - RESET + Reset Generator NMOS R2 GND N-ch Open-Drain Type VCC R1 Bandgap - Reset Generator + RESET (RESET) R2 GND Push-Pull Type PIN DESCRIPTIONS GND Pin : Ground. RESET Pin (SS809G) : Active low output pin. RESET Output remains low while Vcc is below the reset RESET P in (SS810G) : Active high output pin. RESET output remains high while Vcc is below the reset threshold. Vcc Pin : Supply voltage. 9/20/2006 Rev.3.01 www.SiliconStandard.com 6 of 8 SS809/810G DETAIL ED DESCRIPTIONS OF TECHNICAL TERMS threshold, and RESET remains low for the reset RESET OUTPUT The µP will be activated at a valid reset state. These timeout period. µP supervisory circuits assert reset to prevent code BENEFITS execution errors during power-up, power-down, or THRESHOLD brownout conditions. RESET is guaranteed to be a logic low for The SS809G and SS810G with specified voltage as 5V± VTH>VCC>0.9V. Once VCC exceeds the reset threshold, an internal timer keeps RESET low for or 3V ±5% power supply. The reset is guaranteed to the reset timeout period; after this interval, RESET goes high. but before the power drops below the minimum specified operating voltage range of the system ICs. If a brownout condition occurs (VCC drops below the reset threshold), RESET goes low. Any time VCC The pre-trimmed thresholds reduc e the range over which an undesirable reset may occur. OF HIGHLY ACCURATE RESET 10% or 3V±10% are ideal for systems using a 5V±5% assert after the power supply falls out of regulation, goes below the reset threshold, the internal timer resets to zero, and RESET goes low. The internal timer is activated after VCC returns above the reset APPLICATION INFORMATION NEGATIVE-GOING VCC TRANSIENTS of 0.9V. However in applications where RESET In addition to issuing a reset to the µ P during must be valid down to 0V, adding a pull-down resistor power-up, power-down, and brownout conditions, the to RESET causes any leakage currents to flow to SS809G series are relatively resistant to short -duration ground, holding RESET low. negative-going VCC transients. INTERFACING TO A MICROPROCESSOR WITH ENSURING A VALID RESET OUTPUT DOWN TO BIDIRECTIONAL RESET PINS VCC=0 The RESET output on the SS809N is open drain, When VCC falls below 0.9V, the SS809G RESET and this device interfaces easily with µPs that have output no longer sinks current; it becomes an open bidirectional reset circuit. In this case, high-impedance CMOS logic supervisor’s RESET inputs connected to RESET can drift to undetermined voltages. Therefore, the SS809G/810G pins. Connecting output directly the µP to the microcontroller’s RESET pin with a single pull-up resistor allows either device to assert reset. are perfect for most CMOS applications down to VCC 9/20/2006 Rev.3.01 www.SiliconStandard.com 7 of 8 SS809/810G PHYSICAL DIMENSIONS SOT -23-3 (unit: mm) C D SYMBOL MIN MAX A 1.00 1.30 A1 — 0.10 A2 0.70 0.90 b 0.35 0.50 C 0.10 0.25 D 2.70 3.10 E 1.40 1.80 L E H θ1 e e A A2 A1 b 1.90 (TYP) H 2.60 3.00 L 0.37 — θ1 1° 9° Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 9/20/2006 Rev.3.01 www.SiliconStandard.com 8 of 8