ST3M01 TRIPLE VOLTAGE REGULATOR ■ ■ ■ ■ ■ ■ ONLY TWO CELL NEED AS INPUT THREE REGULATED OUTPUT 1) HIGH EFFICENCY PFM DC/DC CONVERTER 3.3V AT 200mA (87% EFFICENCY) 2) VERY LOW NOISE AND VERY LOW DROP VREG (3V AT 20mA) 3) VERY LOW NOISE AAND VERY LOW DROP VREG (1.9V AT 20mA) LOGIC CONTROLLED ELECTRONIC SHUTDOWN LOW BATTERY DETECTOR VIRTUAL GND PIN TEMPERATURA RANGE: -40 TO 85°C SO-14 SCHEMATIC DIAGRAM Vin 150 µF 150 µF 15 µH Lx IN_SW OUT DC/DC Linear A DC/DC DC/DC OUT LA 1 µF IN_Linear OUT LB Linear B 1 µF On-Mode Virtual GND - SHDN + Off-Mode LBO Vref Ref Ref 100 nF 1 KΩ November 2000 GND_SW GND_Signal 1/11 ST3M01 ABSOLUTE MAXIMUM RATINGS Symbol VIN Parameter DC Input Voltage (Both IN_Linear and IN_SW) Value Unit -0.3 to 7 V -0.3 to VIN+0.3 V Switch Voltage -0.3 to 7 V Low Battery Output Voltage -0.3 to 7 V Vvirtual_GND Virtual GND Output Voltage VSHDN VLX VLBO Shutdown Input Voltage -0.3 to 7 V Low Battery Output Maximum Current 30 mA Ivirtual_GND Virtual GND Output Maximum Current 30 mA ILBO Tstg Storage Temperature Range -65 to +150 °C Top Operating Junction Temperature Range -40 to +85 °C Value Unit 160 °C/W THERMAL DATA Symbol Rthj-amb Parameter Thermal Resistance Junction-ambient (*) ORDER CODES 2/11 Type Package Comment ST3M01D ST3M01DTR SO-14 SO-14 (Tape & Reel) 50 parts per tube / 20 tube per box 2500 parts per reel ST3M01 CONNECTION DIAGRAM (top view) PIN DESCRIPTION Pin N° Symbol Name and Function 1 2 3 GND SW GND SW Virtual GND 4 LBO 5 VREF Switching Ground. Must be low impedance; solder directly to GND plane Switching Ground. Must be low impedance; solder directly to GND plane Virtual GND. Open Drain N-Cnannel MOSFET: must be high impedance when the Low Battery condition is detected. Low Battery Output. Open Drain N-Cnannel MOSFET: sinks current when the input voltage drops below 2V typically. Reference Voltage Output. Bypass with 0.1 µF to improve the linears VREF thermal noise performance. 6 7 IN Linear OUT LB 8 SHDN 9 10 GND Signal OUT LA Signal GND. Must be connected togheter with the Switching Ground. Linear A Output port. 3V typically. 11 12 13 14 OUT DC/DC IN SW LX LX DC/DC Output Port: 3.3V typically. SMPS Input. Must be connected togheter with IN_Linear to the input supply. 1.5A N-Channel Power MOSFET Drain. 1.5A N-Channel Power MOSFET Drain. Linear Input. Must be connected togheter with IN SW to the input supply. Linear B Output port. 1.9V typically. Shutdown Input. Disables the SMPS and LA output, but the LB, the referencevoltage and the low batery comparator remain active. 3/11 ST3M01 ELECTRICAL CHARACTERISTICS (Unless otherwise specified, please refer to the typical operating circut of the pag 1 for the external components values and connections. Unless otherwise noted VSHDN=HIGH) Symbol VI VO(DC/DC) ν Parameter Test Conditions Operating Input Voltage DC/DC Converter Output Voltage (Test Circuit A) Min. Typ. 1.9 2.24<VIN<3.3V; 0<IO(LA)<20mA; -40 < TJ < 85 °C 0<IO(DC/DC)<200mA; 0<IO(LB)<20mA; 3.2 DC/DC Converter Efficency VIN=2.4V; IO(DC/DC)=100mA; IO(LA)=0mA; IO(LB)=0mA; TJ = 25°C 3.3 Max. Unit 3.3 V 3.415 V 87 % VO(LA) Linear A Output Voltage (Test Circuit A) 2.24<VIN<3.3V; 0<IO(LA)<20mA; -40 < TJ < 85°C 0<IO(DC/DC)<200mA; 0<IO(LB)<20mA; 2.93 3 3.09 V VO(LB) Linear B Output Voltage (Test Circuit A) 2.24<VIN<3.3V; 0<IO(LA)<20mA; -40 < TJ < 85°C 0<IO(DC/DC)<200mA; 0<IO(LB)<20mA; 1.86 1.9 1.955 V eN(LA) Linear A Thermal Output Noise Voltage (Note 2) VIN=2.4V; VO(DC/DC)=3.5V; IO(LA)=20mA; 10 < f < 80KHz; CO(LA)=1µF; CREF=0.1µF; TJ = 25°C 60 µVrms eN(LB) Linear B Thermal Output Noise Voltage (Note 2) VIN=2.4V; VO(DC/DC)=3.5V; IO(LB)=20mA; 10 < f < 80KHz; CO(LB)=1µF; CREF=0.1µF; TJ = 25°C 35 µVrms Iq(OFF) Quiescent Current OFF Mode DC/DC & LA OFF LB ON) (Test Circuit E) Quiescent Current OFF Mode (DC/DC & LA OFF LB ON) (Test Circuit F) DC/DC Supply Current (Test Circuit B) Linear A Quiescent Current (Test Circuit C) VIN=3.3V; TJ = 25°C No Load; VSHDN=LOW; 75 µA VIN=1.9V; TJ = 25°C No Load; VSHDN=HIGH; 50 µA VIN=2.24V; No Load; TJ = 25°C 100 µA VIN=2.24V; VO(DC/DC)=3.5V; IO(LA)=10mA; TJ = 25°C 220 µA Linear B Quiescent Current VIN=2.24V; VO(DC/DC)=3.5V; (Test Circuit C) IO(LB)=10mA; TJ = 25°C 75 µA Iq(OFF) IS(DC/DC) Iq(LA) Iq(LB) Low Battery Detection Range VBATT(HYS) Low Battery Detection Hysteresys RON(LBO) LBO RDSON VBATT VSHDN=HIGH with falling edge VIN=1.9V; ID=5mA; TJ = 25°C 2 2.04 V 150 200 mV Control Input Logic Low VIN>2.24V; -40 < TJ < 85°C Vil Control Input Logic High VIN>2.24V; -40 < TJ < 85°C Ton Timer On Response Time on DC/DC VIN=2.4V; CO=100µF; TJ = 25°C IO(DC/DC)=200mA VSHDN=from GND to VSHDN(MAX) 0.6 VIN>2.24V; 10 ID=5mA; TJ = 25°C Note 1: For VIN < 1.9V the VO(LB) is out of regulation because of under dropout condition Note 2: VO(DC/DC) = 3.5V force for an external DC source to avoid switching noise Ω 10 Vih RON(V_GND) Virtual GND RDSON 4/11 1.96 0.4 1.5 V V 9 ms Ω ST3M01 DC/DC CONVERTER BLOCK DIAGRAM LINEAR VREG BLOCK DIAGRAM 5/11 ST3M01 TEST CIRCUIT A Vin 150 µF 150 µF 15 µH Lx IN_SW V OUT DC/DC DC/DC DC/DC Linear A OUT LA V IN_Linear OUT LB Linear B V On-Mode 1 µF Virtual GND - SHDN 1 µF + Off-Mode LBO Vref Ref Ref 0.1 µF 1 KΩ GND_SW GND_Signal TEST CIRCUIT B (Isup)DC/DC Vin A 47 µF 150 µF 15 µH Lx IN_SW OUT DC/DC DC/DC DC/DC Linear A OUT LA 1 µF IN_Linear OUT LB Linear B 47 µF 1 µF Virtual GND - + SHDN=HIGH LBO Vref Ref Ref 0.1 µF 1 KΩ 6/11 GND_SW GND_Signal ST3M01 TEST CIRCUIT C (Iq)Ia=(Iin)Ia-(Iout)Ia (Iin)la (Vin)DC/DC Floating A 47 µF (Vout)DC/DC=3.5V 15 µH Lx IN_SW OUT DC/DC DC/DC DC/DC Linear A (Iout)la OUT LA (Vin)Lin=2.24V 1 µF IN_Linear OUT LB Linear B 47 µF 1 µF Virtual GND - + SHDN=HIGH LBO Vref Ref Ref 0.1 µF 1 KΩ GND_SW GND_Signal TEST CIRCUIT D (Iq)Ib=(Iin)Ib-(Iout)Ib (Vin)DC/DC Floating 47 µF (Vin)Lin=3.3V 150 µF 15 µH Lx IN_SW (Iin)lb OUT DC/DC DC/DC DC/DC Linear A OUT LA 1 µF A IN_Linear (Iout)lb OUT LB Linear B 47 µF 1 µF Virtual GND - + SHDN=LOW LBO Vref Ref Ref 0.1 µF 1 KΩ GND_SW GND_Signal 7/11 ST3M01 TEST CIRCUIT E Vin = 3.3V A 150 µF Iq = off 150 µF 15 µH Lx IN_SW OUT DC/DC DC/DC DC/DC Linear A OUT LA 1 µF IN_Linear OUT LB Linear B 1 µF Virtual GND - + SHDN= LOW LBO Vref Ref Ref 0.1 µF 1 KΩ GND_SW GND_Signal TEST CIRCUIT F Vin = 1.9V A 150 µF Iq = off 150 µF 15 µH Lx IN_SW OUT DC/DC DC/DC DC/DC Linear A OUT LA 1 µF IN_Linear OUT LB Linear B 1 µF + SHDN=HIGH Vref Virtual GND - LBO Ref Ref 0.1 µF 1 KΩ 8/11 GND_SW GND_Signal ST3M01 DEMOBOARD CIRCUIT L 22 µH D STPS320U IN DC C1 150 µF 12 IN_SW ON SH OFF 13,14 LX C2 150 µF 11 OUT_DC/DC SHDN OUT_LA 8 A 10 C4 1 µF ST3M01 IN_Linear 6 Virtual_GND 3 4 LBO OUT_LB B 7 GND_SW 1,2 GND_Signal C5 1 µF Vref 9 5 VG LBO C3 100 nF R1 1KOhm VR PC BOARD LAYOUT 9/11 ST3M01 SO-14 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45 (typ.) D 8.55 8.75 0.336 0.344 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 7.62 0.300 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.68 0.026 8 (max.) P013G 10/11 ST3M01 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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