ETC ST72752J4B1

ST7275-2
8-BIT, 42-PIN MCU FOR MONITORS WITH UP TO 32K ROM, 1K
RAM, ADC, TIMER, SYNC, PWM/BRM, DDC/DMA & I2C
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User ROM/OTP/EPROM: up to 32 Kbytes
Data RAM: up to 1 Kbytes (256 bytes stack)
8 MHz Maximum Internal Clock Frequency in
fast mode, 4 MHz in normal mode
Run, Wait and Halt CPU modes
Sync Processor for Mode Recognition, power
management and composite video blanking,
clamping
and
free-running
frequency
generation.
– Corrector mode
– Analyzer mode
Fast I2C Multi Master Interface
DDC Bus Interface fully compliant with DDC1,
2B, 2B+, 2AB, 2Bi standards
23 I/O lines
– 1 high current I/O (10 mA)
– Up to 5 high voltage outputs (9V)
16-bit timer with 2 input captures and 2 output
compare functions (with 1 output pin)
8-bit Analog to Digital Converter with 4 channels
on port B
8 10-bit PWM/BRM Digital to Analog outputs
One 12-bit PWM/BRM Digital to Analog output
Master Reset and Power on/off reset1
Programmable Watchdog for system reliability
42-pin Shrink Dual In line Plastic package
Fully static operation
0 to + 70 oC Operating Temperature Range
4.5V to 5.5V supply operating range
24 MHz Quartz Oscillator
63 basic instructions/17 main address modes
8x8 unsigned multiply instruction
True bit manipulation
Versatile Development Tools (DOS and
Windows) including assembler, linker, Ccompiler, archiver, source level debugger,
programmer, and hardware emulator
PSDIP42
Device Summary
Features
ROM
(bytes)
RAM
(bytes)
ADC
Timer
I2C Bus
DDC/DMA
Sync
PWM
I/O
EPROM
Device
OTP
Device
ST72752J6
ST72752J5
ST72752J4
32K
24K
16K
1K
768
512
4 channels
1
one multimaster
yes
yes
9
23
ST72E752J6D1
ST72T752J6B1
Note 1: Power On/Off reset not implemented in
this revision.
Rev. 1.7
September 2000
1/131
1
Table of Contents
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5 EPROM/OTP PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 CLOCKS, RESET, INTERRUPTS & LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 Crystal Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.3 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
19
19
20
3.2.1 Power On/Off and Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.2 Common Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
....
4.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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2
26
27
28
29
29
29
30
30
32
35
38
40
41
41
41
42
42
42
42
43
43
43
43
55
55
4.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 SYNC PROCESSOR (SYNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.3 Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.4 Input Signal Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.5 Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.6 Input Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.7 Output Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.8 Analyzer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.9 Corrector Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.10 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 DDC / DMA INTERFACE (DDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
56
61
61
61
62
62
62
66
69
70
72
73
80
80
80
80
82
85
85
86
91
4.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.6.2 DDC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.6.3 DMA (Direct Memory Access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.7 PWM/BRM GENERATOR (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
106
106
106
111
113
113
113
114
114
114
115
116
116
117
117
117
117
117
118
118
119
6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
3/131
6.1 POWER CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.2 AC/DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
124
128
128
129
7.2.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
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ST7275-2
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST7275 is a HCMOS microcontroller unit
(MCU) from the ST7 family with dedicated peripherals for Monitor applications.
It is based around an industry standard 8-bit core
and offers an enhanced instruction set. The processor runs with an external clock at 24 MHz with
a 5V supply. Due to the fully static design of this
device, operation down to DC is possible. Under
software control the ST7275 can be placed in
WAIT or HALT mode thus reducing power consumption. The enhanced instruction set and addressing modes afford real programming potential.
In addition to standard 8-bit data management the
ST7 features true bit manipulation, 8x8 unsigned
multiplication and indirect addressing modes.
The device includes an on-chip oscillator, CPU,
Sync Processor for video timing & Vfback analysis, up to 32K ROM, up to 1K RAM, I/O, a timer
with 2 input captures and 2 output compares, a 4channel Analog to Digital Converter, DDC/DMA,
I2C multi Master, Watchdog Reset, and one 12-bit
and eight 10-bit PWM/BRM outputs for analog DC
control of external functions.
Figure 1. ST7275-2 Block Diagram
Up to 32K Bytes
PORT A
ROM/OTP /EPROM
PORT B
Up to 1K Bytes
RAM
ADC
PA1
PA3-PA6
PA7/BLANKOUT
PB0/VFBACK/ AIN0
PB1-PB2/AIN1-AI N2
PB7/AIN3
VDDA
VSSA
PORT C
CONTROL
8-BIT CORE
ALU
ADDRESS AND DATA BUS
RESET
2
I C
DDC
PC0/OCMP/HFB ACK
PC2/RX/SCLD
PC3/SDAD
PC4/SCLI
PC5/SDAI
PC6
TIMER
WATCHDOG
SYNC
OSCIN
OSCOUT
Mode
OSC :3 Selection
PROCESSOR
VDD
VSS
POWER SUPPLY
PORT D
DAC (PWM)
VSYNCI
HSYNCI
PD0/CSYNC I
PD1/HSYNC O
PD2/VSY NCO
PD3/ITC
PD4/ITB
PD5/ITA
PD6/CLAMPOUT
DA0, DA1, DA8
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3
ST7275-2
1.2 PIN DESCRIPTION
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
VSSA
VDDA
AIN3/PB7
AIN2/PB2
AIN1/PB1
VFBACK/AIN0/PB0
VSYNCI
CLAMPOUT/PD6
ITA/PD5
ITB/PD4
ITC/PD3
VSYNCO/PD2
HSYNCO/PD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
RESET Bidirectional. This active low signal forces
the initialization of the MCU. This event is the top
priority non maskable interrupt. This pin is
switched low when the Watchdog has triggered or
VDD is low. It can be used to reset external peripherals.
OSCIN/OSCOUT Input/Output Oscillator pin.
These pins connect a parallel-resonant crystal, or
an external source to the on-chip oscillator.
TEST/VPP: EPROM programming input. This pin
must be held low during normal operating modes.
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42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
DA0
TEST/VPP
RESET
PA1
PA3
PA4
PA5
PA6
PA7/BLANKOUT
OSCIN
OSCOUT
PC6
PC5/SDAI
PC4/SCLI
PC3/SDAD
PC2/RX/SCLD
PC0/OCMP/HFBACK
VDD
HSYNCI
VSS
PD0/CSYNCI
VDD: Power supply voltage (4.5V-5.5V)
VSS: Digital Ground.
VDDA: Power Supply for analog peripheral (ADC).
VDDA and VDD must be connected together on the
PCB.
VSSA: Ground for analog peripheral (ADC). VSSA
and VSS must be connected together on the PCB.
Alternate Functions: several pins of the I/O ports
assume software programmable alternate functions as shown in the pin description.
ST7275-2
PIN DESCRIPTION (Cont’d)
Table 1. Pin Description
Pin
Pin Name
Type
Description
Remarks
1
DA1
O
10-bit PWM/BRM output
2
DA2
O
10-bit PWM/BRM output
3
DA3
O
10-bit PWM/BRM output
4
DA4
O
10-bit PWM/BRM output
5
DA5
O
10-bit PWM/BRM output
6
DA6
O
10-bit PWM/BRM output
7
DA7
O
10-bit PWM/BRM output
8
DA8
O
10-bit PWM/BRM output
9
VSSA
S
Ground for analog peripheral (ADC)
Must be connected externally to Vss
10
VDDA
S
Power Supply for analog peripheral (ADC)
Must be connected externally to VDD
11
PB7/AIN3
I/O
Port B7 or ADC analog input 3
12
PB2/AIN2
I/O
Port B2 or ADC analog input 2
13
PB1/AIN1
I/O
Port B1 or ADC analog input 1
14
PB0/VFBACK/
AIN0
I/O
Port B0 or SYNC Vertical flyback input or ADC analog
input 0
TTL levels with pull-up
(SYNC input)
15
VSYNCI
SYNC vertical synchronisation
TTL levels with pull-upRefer to Figure 16
16
PD6/CLAMPOUT
I/O
Port D6 or SYNC clamping/MOIRE output
17
PD5/ITA
I/O
Port D5 or Interrupt falling edge detector input
18
PD4/ITB
I/O
Port D4 or Interrupt falling edge detector input
19
PD3/ITC
I/O
Port D3 or Interrupt falling edge detector input
20
PD2/VSYNCO
I/O
Port D2 or SYNC vertical synchronisation output
21
PD1/HSYNCO
I/O
Port D1 or SYNC horizontal synchronisation output
22
PD0/CSYNCI
I/O
Port D0 or SYNC composite synchronisation input
23
VSS
S
Ground 0V
24
HSYNCI
I
SYNC horizontal synchronisation input
25
VDD
S
Supply (4V - 5.5V)
26
PC0/HFBACK/
OCMP
I/O
Port C0 or SYNC horizontal flyback input or TIMER out- TTL levels with pull-up
put compare
(SYNC input)
27
PC2/RX/SCLD
I/O
Port C2 or Interrupt falling edge detector input or DDC
serial clock
28
PC3/SDAD
I/O
Port C3 or DDC serial data
29
PC4/SCLI
I/O
Port C4 or I2C serial clock
30
PC5/SDAI
I/O
Port C5 or I2C serial data
31
PC6
I/O
Port C6
I
For analog controls, after external filtering
TTL levels with pull-up
(SYNC input)
TTL levels with pull-up
Refer to Figure 16.
High current
7/131
ST7275-2
PIN DESCRIPTION (Cont’d)
Pin
Pin Name
Type
Description
Remarks
32
OSCOUT
O
Oscillator output
33
OSCIN
I
Oscillator input
34
PA7/BLANKOUT
I/O
Port A7 or SYNC blanking output
35
PA6
I/O
Port A6
High voltage (9V)
36
PA5
I/O
Port A5
High voltage (9V)
37
PA4
I/O
Port A4
High voltage (9V)
38
PA3
I/O
Port A3
High voltage (9V)
39
PA1
I/O
Port A1
High voltage (9V)
40
RESET
I/O
Reset pin
Active low
41
TEST/VPP
S
Test mode pin or EPROM programming voltage (this
pin should be tied low in user mode)
42
DA0
O
12-bit PWM/BRM output
8/131
For analog controls, after external filtering
ST7275-2
1.3 EXTERNAL CONNECTIONS
The following figure shows the recommended external connections for the device.
The VPP pin is only used for programming OTP
and EPROM devices and must be tied to ground in
user mode.
The 10 nF and 0.1 µF decoupling capacitors on
the power supply lines are a suggested EMC performance/cost tradeoff.
The external reset network is intended to protect
the device against parasitic resets, especially in
noisy environments.
Unused I/Os should be tied high to avoid any unnecessary power consumption on floating lines.
An alternative solution is to program the unused
ports as inputs with pull-up.
Figure 2. Recommended External Connections
VPP
VDD
10nF
VDD
+
0.1µF
VSS
V DD
4.7K
0.1µF
RESET
EXTERNAL RESET CIRCUIT
0.1µF
See
Clocks
Section
OSCIN
OSCOUT
Or configure unused I/O ports
by software as input with pull-up
VDD
10K
Unused I/O
9/131
ST7275-2
1.4 MEMORY MAP
Figure 3. Program Memory Map
0000h
HW Registers
(see Table 3)
0060h
Short Addressing
005Fh
0060h
RAM (zero page)
0100h
RAM
Stack
256 bytes
01FFh
035Fh
Reserved
512 bytes
768 bytes
1 Kbytes
7FFFh
8000h
A000h
C000h
FFDFh
16-bit Addressing
025Fh
03FFh
32K Bytes ROM
24K Bytes ROM
16K Bytes
ROM
FFE 0h
Interrupt & Reset Vectors
(see Table 4)
FFFF h
Table 2. ROM and RAM Sizes
Device
ST72752J6
ST72752J5
ST72752J4
10/131
Size (Bytes)
32K (32768)
24K (24576)
16K (16384)
ROM
Start Address
8000h
A000h
C000h
End Address
FFFF h
FFFF h
FFFF h
Size (Bytes)
1K (928)
768
512
RAM
Start Address
60h
60h
60h
End Address
3FFh
35Fh
25Fh
ST7275-2
MEMORY MAP (Cont’d)
Table 3. Hardware Register Memory Map
Address
0000h
0001h
0002h
0003h
0004h
0005h
Block
Port A
Port C
Port D
0006h
0007h
PADR
Register Name
Port A Data Register
Reset
Status
00h
Remarks
R/W
PADDR
Port A Data Direction Register
00h
R/W
PCDR
Port C Data Register
00h
R/W
PCDDR
Port C Data Direction Register
00h
R/W
PDDR
Port D Data Register
00h
R/W
PDDDR
Port D Data Direction Register
00h
R/W
PBDR
Port B Data Register
00h
R/W
PBDDR
Port B Data Direction Register
00h
R/W
0008h
PBICFGR
Port B Input Pull-Up Configuration Register
00h
R/W
0009h
MISCR
Miscellaneous Register
00h
R/W
ADCDR
ADC Data Register
00h
Read only
ADCCSR
ADC Control Status register
00h
R/W
WDGCR
Watchdog Control Register
7Fh
R/W
000Ah
000Bh
000Ch
Port B
Register Label
ADC
WDG
000Dh
Reserved Area (3 bytes)
000Fh
00010h
ITRFRE
Interrupt Register
00h
R/W
0011h
TIMCR2
Timer Control Register 2
00h
R/W
0012h
TIMCR1
Timer Control Register 1
00h
R/W
0013h
TIMSR
Timer Status Register
00h
Read only
0014h
TIMIC1HR
Timer Input Capture 1 High Register
xxh
Read only
0015h
TIMIC1LR
Timer Input Capture 1 Low Register
xxh
Read only
0016h
TIMOC1HR
Timer Output Compare 1 High Register
80h
R/W
0017h
TIMOC1LR
Timer Output Compare 1 Low Register
00h
R/W
0018h
ITR
TIM
TIMCHR
Timer Counter High Register
FFh
Read only
0019h
TIMCLR
Timer Counter Low Register
FCh
R/W
001Ah
TIMACHR
Timer Alternate Counter High Register
FFh
Read only
001Bh
TIMACLR
Timer Alternate Counter Low Register
FCh
R/W
001Ch
TIMIC2HR
Timer Input Capture 2 High Register
xxh
Read only
001Dh
TIMIC2LR
Timer Input Capture 2 Low Register
xxh
Read only
001Eh
TIMOC2HR
Timer Output Compare 2 High Register
80h
R/W
001Fh
TIMOC2LR
Timer Output Compare 2 Low Register
00h
R/W
0020h
0021h
Reserved Area (2 bytes)
11/131
ST7275-2
MEMORY MAP (Cont’d)
Address
Block
Register Label
Register Name
Reset
Status
Remarks
0022h
PWM0
12-BIT PWM Register
80h
R/W
0023h
BRM0
12-BIT BRM Register
C0h
R/W
0024h
PWM1
80h
R/W
0025h
BRM21
00h
R/W
0026h
PWM2
80h
R/W
0027h
PWM3
80h
R/W
BRM43
00h
R/W
PWM4
80h
R/W
80h
R/W
0028h
0029h
PWM
10 BIT PWM / BRM
002Ah
PWM5
002Bh
BRM65
00h
R/W
002Ch
PWM6
80h
R/W
002Dh
PWM7
80h
R/W
002Eh
BRM87
00h
R/W
002Fh
PWM8
80h
R/W
0030h
Reserved Area (16 bytes)
003Fh
0040h
SYNCCFGR
SYNC Configuration Register
00h
R/W
0041h
SYNCMCR
SYNC Multiplexer Register
20h
R/W
0042h
SYNCCCR
SYNC Counter Register
00h
R/W
SYNCPOLR
SYNC Polarity Register
08h
R/W
SYNCLATR
SYNC Latch Register
00h
R/W
0045h
SYNCHGENR
SYNC H Sync Generator Register
00h
R/W
0046h
SYNCVGENR
SYNC V Sync Generator Register
00h
R/W
0047h
SYNCENR
SYNC Processor Enable Register
C3h
R/W
0043h
0044h
12/131
SYNC
ST7275-2
MEMORY MAP (Cont’d)
Address
Block
Register Label
Register Name
Reset
Status
Remarks
0048h
DDCIADHR
DMA Initial High Address Register
xxh
R/W
0049h
DDCIADLR
DMA Initial Low Address Register
xxh
R/W
004Ah
DDCCADHR
DMA current High Address Register
xxh
R/W
004Bh
DDCCADLR
DMA current Low Address Register
xxh
R/W
004Ch
DDCICTR
DMA Initial Counter Register
xxh
R/W
004Dh
DDCCCTR
DMA current Counter Register
xxh
R/W
004Eh
DDCCTLR
DMA Control Register
00h
R/W
0050h
DDCCR
DDC Control Register
00h
R/W
0051h
DDCSR1
DDC Status Register 1
00h
Read only
0052h
DDCSR2
DDC Status Register 2
00h
Read only
0053h
DDCCCR
DDC Clock Control Register
00h
R/W
0054h
DDCOAR
DDC (7 Bits) Slave address Register
00h
R/W
00h
R/W
00h
R/W
004Fh
Reserved
DDC
0055h
Reserved
0056h
DDCDR
DDC Data Register
0057h
Reserved Area (2 bytes)
0058h
0059h
I2CDR
I2C Data Register
005Ah
Reserved
005Bh
005Ch
I2C
005Dh
I2COAR
I2C (7 Bits) Slave Address Register
00h
R/W
I2CCCR
I2C Clock Control Register
00h
R/W
I2CSR2
I2C Status Register 2
00h
Read only
2
005Eh
I2CSR1
I C Status Register 1
00h
Read only
005Fh
I2CCR
I2C Control Register
00h
R/W
Table 4. Interrupt Vector Map
Vector Address
Description
FFE0-FF E1h
Not used
FFE2-FF E3h
FFE4-FF E5h
FFE6-FF E7h
Not used
I2C interrupt vector
Timer Overflow interrupt vector
FFE8-FF E9h
FFEA-FFEBh
FFEC-FF EDh
Timer Output Compare interrupt vector
Timer Input Capture interrupt vector
Not used
FFEE-FF EFh
FFF0-FFF1h
RX falling edge interrupt vector
ITA falling edge interrupt vector
FFF2-FFF3h
FFF4-FFF5h
FFF6-FFF7h
ITB falling edge interrupt vector
ITC falling edge interrupt vector
Not used
FFF8-FFF9h
FFFA-FFFBh
FFFC-FFFDh
DDC/DMA (OR wiring) interrupt vector
Not used
TRAP (software) interrupt vector
FFFE-FFFFh
RESET vector
Remarks
Internal Interrupts
External Interrupts
Internal Interrupt
CPU Interrupt
13/131
ST7275-2
1.5 EPROM/OTP PROGRAM MEMORY
The 32 Kbytes of EPROM/OTP of the ST72E75/
ST72T75 may be programmed using the EPROM
programming boards available from STMicroelectronics.
EPROM Erasing
The EPROM of the windowed package of the
ST72E75 can be erased by exposure to Ultra-Violet light.
The erasure characteristic of the ST72E75 is such
that erasure begins when the memory is exposed
to light with wave lengths shorter than approximately 4000Å. It should be noted that sunlight and
some types of fluorescent lamps have wavelengths in the range 3000-4000Å. It is recom-
14/131
mended to cover the window of the ST72E75
packages by an opaque label to prevent unintentional erasure problems when testing the application in such an environment.
The recommended erasure procedure of the
EPROM is the exposure to short wave ultraviolet
light which have a wave-length 2537Å. The integrated dose (i.e. U.V. intensity x exposure time) for
erasure should be a minimum of 15W-sec/cm2.
The erasure time with this dosage is approximately 30 minutes using an ultraviolet lamp with a
12000 mW/cm2 power rating. The ST72E75
should be placed within 2.5 cm (1 inch) of the lamp
tubes during erasure.
ST7275-2
2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
2.2 MAIN FEATURES
■
■
■
■
■
■
■
■
63 basic instructions
Fast 8-bit by 8-bit multiply
17 main addressing modes
Two 8-bit index registers
16-bit stack pointer
Low power modes
Maskable hardware interrupts
Non-maskable software interrupt
2.3 CPU REGISTERS
The 6 CPU registers shown in Figure 4 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
Index Registers (X and Y)
In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from
the stack).
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
Figure 4. CPU Registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
X INDEX REGISTER
RESET VALUE = XXh
7
0
Y INDEX REGISTER
RESET VALUE = XXh
15
PCH
8 7
PCL
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFF Fh
7
1 1 1 H I
0
N Z C
CONDITIO N CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X
15
8
7
0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
15/131
ST7275-2
CENTRAL PROCESSING UNIT (Cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
Reset Value: 111x1xxx
7
1
0
1
1
H
I
N
Z
C
The 8-bit Condition Code register contains the interrupt mask and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
ter it and reset by the IRET instruction at the end of
the interrupt routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the current interrupt routine.
Bit 2 = N Negative.
This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7th
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 3 = I Interrupt mask.
This bit is set by hardware when entering in interrupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable
because the I bit is set by hardware when you en-
16/131
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
ST7275-2
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
Reset Value: 01 FFh
15
0
8
0
0
0
0
0
0
7
SP7
1
0
SP6
SP5
SP4
SP3
SP2
SP1
SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 5).
Since the stack is 256 bytes deep, the most significant byte is forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack
higher address.
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD instruction.
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously
stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 5.
– When an interrupt is received, the SP is decremented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
Figure 5. Stack Manipulation Example
CALL
Subroutine
PUSH Y
Interrupt
event
POP Y
RET
or RSP
IRET
@ 0100h
SP
SP
CC
A
X
X
X
PCH
PCH
PCH
PCL
PCL
PCL
PCH
PCH
PCH
PCH
PCH
PCL
PCL
PCL
PCL
PCL
SP
@ 01FFh
SP
Y
CC
A
CC
A
SP
SP
Stack Higher Address = 01FFh
Stack Lower Address = 0100h
17/131
ST7275-2
3 CLOCKS, RESET, INTERRUPTS & LOW POWER MODES
3.1 CLOCK SYSTEM
3.1.1 General Description
The MCU accepts either a crystal or an external
clock signal to drive the internal oscillator. The internal clock (CPU CLK running at fCPU) is derived
from the external oscillator frequency (fOSC),
which is first divided by 3 and then optionally further divided by 2, if the normal mode is selected in
the miscellaneous register (fast mode bit =0)..
A division factor of 2 is added to generate the 12
MHz clock for the Sync Processor (clamp function)
as shown in Figure 6. The CPU clock is used also
as clock for the ST7275 peripherals.
Note: In the Sync processor, an additional divider
by two is added in fast mode (same external timing
for this peripheral).
Figure 6. Clock divider chain
%2
OSC
24MHz
18/131
%3
12 MHz
(Sync processor clampout signal)
%2
fCPU: 4 or 8 MHz
normal or fast mode
(CPU and peripherals)
FAST
ST7275-2
CLOCK SYSTEM (Cont’d)
3.1.2 Crystal Resonator
The internal oscillator is designed to operate with
an AT-cut parallel resonant quartz crystal resonator in the frequency range specified for fosc. The
circuit shown in Figure 7 is recommended when
using a crystal, and Table 5 lists the recommended capacitance and feedback resistance values.
The crystal and associated components should be
mounted as close as possible to the input pins in
order to minimize output distortion and start-up
stabilization time.
Figure 7. Crystal/Ceramic Resonator
CRYSTA L CLOCK
OSCIN
CL1
OSCOUT
C L2
1M*
*Recommended for oscillator stability
Table 5. Recommended Crystal Values
24 Mhz
Unit
RSMAX
70
25
20
Ohms
CL1
22
47
56
pf
CL2
22
47
56
pf
Legend:
CL1, CL2 = Maximum total capacitance on pins
OSCIN and OSCOUT (the value includes the external capacitance tied to the pin plus the parasitic
capacitance of the board and of the device).
RSMAX = Maximum series parasitic resistance of
the quartz allowed.
Note: The tables are relative to the quartz crystal
only (not ceramic resonator).
3.1.3 External Clock
An external clock should be applied to the OSCIN
input with the OSCOUT pin not connected as
shown in Figure 8. The Crystal clock specifications
do not apply when using an external clock input.
The equivalent specification of the external clock
source should be used.
Figure 8. External Clock Source Connections
OSCIN
OSCOUT
NC
EXTERNAL
CLOCK
19/131
ST7275-2
3.2 RESET
The Reset procedure is used to provide an orderly
software start-up or to quit low power modes.
Three reset modes are provided: a power on/off
reset, a watchdog reset and an external reset at
the RESET pin.
A reset causes the reset vector to be fetched from
addresses FFFEh and FFFFh in order to be loaded
into the PC and with program execution starting
from this point.
An internal circuitry provides a 4096 CPU clock cycle delay from the time that the oscillator becomes
active.
The Reset pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, the best external network is a double
capacitive decoupling consisting of 0.1 µF to V SS
and 0.1 µF to VDD.
3.2.1 Power On/Off and Watchdog Reset
Power on/off circuitry generates a reset when VDD
is below VTRH when VDD is rising or VTRL when VDD
is falling (refer to Figure 10). This circuitry is active
only when VDD is above VTRM.
During Power on/off Reset, the RESET pin is held
low, thus permitting the MCU to reset other devices.
When a watchdog reset occurs, the RESET pin is
pulled low permitting the MCU to reset other devices in the same way as when Power on/off (Figure
9) occurs.
3.2.2 External Reset
The external reset is an active low input signal applied to the RESET pin of the MCU.
As shown Figure 11, the RESET signal must stay
low for a minimum of one and a half CPU clock cycles.
An internal Schmitt trigger at the RESET pin is provided to improve noise immunity.
Table 6. List of sections affected by RESET, WAIT and HALT (Refer to 3.6 for Wait and Halt Modes)
Section
RESET
CPU clock running at 4 MHz
X
Timer Prescaler reset to zero
X
Timer Counter set to FFFCh
X
All Timer enable bits set to 0 (disabled)
X
Data Direction Registers set to 0 (as Inputs)
X
Set Stack Pointer to 01FFh
X
Force Internal Address Bus to restart vector FFFEh, FFFFh
X
Set Interrupt Mask Bit (I-Bit, CC) to 1 (Interrupt disable)
X
Set Interrupt Mask Bit (I-Bit, CC) to 0 (Interrupt enable)
WAIT
X
HALT
X
Reset HALT latch
X
Reset WAIT latch
X
Disable Oscillator (for 4096 cycles)
X
X
Set Timer Clock to 0
X
X
Watchdog counter reset
X
Watchdog register reset
X
Port data registers reset
X
Other on-chip peripherals: registers reset
X
20/131
ST7275-2
RESET (Cont’d)
Figure 9. POWER ON/OFF Functional Diagram
POWER ON/OFF
VDD
Figure 10. POWER ON/OFF Signal Output
V TRH
RESPOF
FROM
WATCHDOG
RESET
VTRL
VTRM
RESET
INTERNAL
RESET
VTRM
VDD
RESET
Note: Typical hysteresis (VTRH-VTRL) of 250 mV is
expected
Figure 11. Reset Timing Diagram
tDDR
VDD
OSCIN
tOXOV
fCPU
PC
RESET
WATCHDOG RESET
FFFE
FFFF
4096 CPU
CLOCK
CYCLES
DELAY
Note: Refer to Electrical Characteristics for values of tDDR, tOXOV, VTRH, VTRL and VTRM
21/131
ST7275-2
3.3 INTERRUPTS
The ST7275 may be interrupted by one of two different methods: maskable hardware interrupts as
listed in Table 7 and a non-maskable software interrupt (TRAP). The Interrupt processing flowchart
is shown in Figure 12.
The maskable interrupts must be enabled in order
to be serviced. However, disabled interrupts can
be latched and processed when they are enabled.
When an interrupt has to be serviced, the PC, X, A
and CC registers are saved onto the stack and the
interrupt mask (I bit of the Condition Code Register) is set to prevent additional interrupts. The Y
register is not automatically saved.
The PC is then loaded with the interrupt vector of
the interrupt to service and the interrupt service
routine runs (refer to Table 7 for vector addresses). The interrupt service routine should finish with
the IRET instruction which causes the contents of
the registers to be recovered from the stack and
normal processing to resume. Note that the I bit is
then cleared if and only if the corresponding bit
stored in the stack is zero.
Though many interrupts can be simultaneously
pending, a priority order is defined (see Table 7).
The RESET pin has the highest priority.
If the I bit is set, only the TRAP interrupt is enabled.
All interrupts allow the processor to leave the
WAIT low power mode. Only external interrupts
and allow the processor to leave the HALT low
power mode.
Software Interrupt. The software interrupt is the
executable instruction TRAP. The interrupt is recognized when the TRAP instruction is executed,
regardless of the state of the I bit. When the interrupt is recognized, it is serviced according to the
flowchart on Figure 12.
22/131
RX interrupt. The RX (PC2) pin can generate an
interrupt when a falling edge occurs on this pin, if
this interrupt is enabled with the RXITE bit in the
miscellaneous register and the I bit of the CC register is reset. When an enabled interrupt occurs,
normal processing is suspended at the end of the
current instruction execution. It is then serviced
according to the flowchart on Figure 12. Software
in the RX service routine must reset the cause of
this interrupt by clearing the RXLAT or RXITE bits
in the miscellaneous register.
ITA, ITB, ITC interrupts. The ITA (PD5), ITB
(PD4), ITC (PD3) pins can generate an interrupt
when a falling edge occurs on these pins, if these
interrupts are enabled with the ITAITE, ITBITE, ITCITE bits respectively in the ITRFRE register and
the I bit of the CC register is reset.
Peripheral Interrupts. Different peripheral interrupt flags are able to cause an interrupt when they
are active if both the I bit of the CC register is reset
and if the corresponding enable bit is set. If either
of these conditions is false, the interrupt is latched
and thus remains pending.
The interrupt flags are located in the status register. The Enable bits are in the control register.
When an enabled interrupt occurs, normal
processing is suspended at the end of the current
instruction execution. It is then serviced according
to the flowchart on Figure 12.
The general sequence for clearing an interrupt is
an access to the status register while the flag is set
followed by a read or write of an associated register. Note that the clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is executed.
ST7275-2
INTERRUPTS (Cont’d)
INTERRUPT FALLING EDGE
(ITRFRE)
Address: 0010h — Read/Write
Reset Value: 0000 0000 (00h)
REGISTER
7
ITALAT ITBLAT ITCLAT
0
0
ITAITE ITBITE ITCITE
-
Bit 7:5 = ITALAT, ITBLAT, ITCLAT Falling Edge
Detector Latches.
These bits are set by hardware when a falling
edge occurs on pins ITA/PD5 & ITB/PD4 or ITC/
PD3 in Port D. They are cleared by software.
When any of these bits are set, an interrupt is generated if the corresponding ITAITE, ITBITE or ITCITE bit =1 and the I bit in the CC register = 0.
0: No falling edge detected
1: Falling edge detected
Bit 4 = Reserved, forced by hardware to 0.
Bit 3:1 = ITAITE, ITBITE, ITCITE Interrupt Enable
Bits.
These bits are set and cleared by software.
0: Interrupt disabled
1: Interrupt enabled
Bit 0 = Reserved, must always be cleared.
23/131
ST7275-2
INTERRUPTS (Cont’d)
IFigure 12. Interrupt Processing Flowchart
FROM RESET
Y
TRAP?
N
N
I BIT SET?
Y
N
INTERRUPT?
FETCH NEXT INSTRUCTION
Y
N
EXECUTE INSTRUCTION
IRET?
STACK PC, X, A, CC
SET I BIT
LOAD PC FROM INTERRUPT VECTOR
Y
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
VR01172D
24/131
ST7275-2
INTERRUPTS (Cont’d)
Table 7. Interrupt Mapping
Source
Block
RESET
TRAP
Description
Reset
Software
DDC
Port
Port
Port
Port
D
D
D
C
bit
bit
bit
bit
TIM
I2C
DDC Interrupt
3
4
5
2
External Interrupt ITC
External Interrupt ITB
External Interrupt ITA
External Interrupt RX
Input Capture 1
Input Capture 2
Output Compare 1
Output Compare 2
Timer Overflow
I C Peripheral Interrupts
Register
Label
N/A
N/A
SR1
SR2
ITRFRE
MISCR
TIMSR
I2CSR1
I2CSR2
N/A
N/A
Maskable
by I-bit
no
no
Exit from
HALT
yes
no
Vector
Address
FFFEh-FFFF h
FFFCh-FFFDh
**
yes
no
FFF8h-FFF9h
ITCLAT
ITBLAT
ITALAT
RXLAT
ICF1
ICF2
OCF1
OCF2
TOF
yes
yes
yes
yes
yes
yes
yes
yes
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
yes
no
FFEAh-FFEBh
yes
no
FFE8h-FFE9h
yes
no
FFE6h-FFE7h
yes
no
FFE4h-FFE5h
Flag
**
Priority
Order
Lowest
Priority
** Many flags can cause an interrupt, see peripheral interrupt status register description.
25/131
ST7275-2
3.4 POWER SAVING MODES
3.4.1 WAIT Mode
This mode is a low power consumption mode. The
WFI instruction places the MCU in WAIT mode:
The internal clock remains active but all CPU
processing is stopped; however, all other peripherals are still running.
Note: In WAIT mode DMA (DDC) accesses are
possible.
During WAIT mode, the I bit in the condition code
register is cleared to enable all interrupts, which
causes the MCU to exit WAIT mode, causes the
corresponding interrupt vector to be fetched, the
interrupt routine to be executed and normal
processing to resume. A reset causes the program
counter to fetch the reset vector and processing
starts as for a normal reset.
Table 6 gives a list of the different sections affected by the low power modes. For detailed information on a particular device, please refer to the corresponding part.
Figure 13. WAIT Flow Chart
WFI INSTRUCTION
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
ON
ON
OFF
I-BIT
CLEARED
N
RESET
N
Y
INTERRUPT
Y
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
ON
ON
ON
I-BIT
SET
IF RESET
4096 CPU CLOCK
CYCLES DELAY
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is
popped.
26/131
ST7275-2
POWER SAVING MODES (Cont’d)
3.4.2 HALT Mode
The HALT mode is the MCU lowest power consumption mode. The HALT mode is entered by executing the HALT instruction. The internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the
on-chip peripherals. HALT mode cannot be used
when the watchdog is enabled, if the HALT instruction is executed while the watchdog system is
enabled, a watchdog reset is generated thus resetting the entire MCU.
When entering HALT mode, the I bit in the Condition Code Register is cleared. Thus, any of the external interrupts ITALAT, ITBLAT, ITCLAT or
RXLAT are allowed and if an interrupt occurs, the
CPU clock becomes active.
The MCU can exit HALT mode on reception of either an external interrupt on RX, ITA, ITB or ITC or
a reset. The oscillator is then turned on and a stabilization time is provided before releasing CPU
operation. The stabilization time is 4096 CPU clock
cycles.
After the start up delay, the CPU continues operation by servicing the interrupt which wakes it up or
by fetching the reset vector if a reset wakes it up.
Figure 14. HALT Flow Chart
HALT INSTRUCTION
WDG
Y
WATCHDOG
ENABLED?
RESET
N
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
OFF
OFF
OFF
I-BIT
CLEARED
N
RESET
N
EXTERNAL
INTERRUPT*
Y
Y
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
ON
ON
ON
SET
4096 CPU CLOCK
CYCLES DELAY
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is
popped.
27/131
ST7275-2
3.5 MISCELLANEOUS REGISTER
MISCELLANEOUS REGISTER (MISCR)
Address: 0009h — Read/Write
Reset Value: 0000 0000 (00h)
7
RXLAT RXITE FAST
0
-
-
POC2
POC1
POC0
Bit 7 = RXLAT Falling Edge Detector Latch.
This bit is set by hardware when a falling edge occurs on pin RX/PC2 in Port C. An interrupt is generated if RXITE=1 It is cleared by software.
0: No falling edge detected on RX
1: Falling edge detected on RX
Bit 2:0 = POC[2:0] PWM/BRM Output Configuration Bits.
These bits are set and cleared by software. They
select the PWM/BRM output configuration.
PWM
Group Channels
Value
O
DA1.. DA4 P0C0
DA5,DA6 P0C1
push-pull
push-pull
open drain
open drain
DA7,DA8
push-pull
open drain
P0C2
Note. DA0 is only Push-Pull Output.
Bit 6 = RXITE RX Interrupt Enable.
This bit is set and cleared by software.
0: RX interrupt disabled
1: RX interrupt enabled
Bit 5 = FAST Fast Mode.
This bit is set and cleared by software. It is used to
select the normal or fast mode CPU frequency.
0: fCPU = 4 MHz (normal mode)
1: fCPU = 8 MHz (fast mode)
Bit 4:3 = Reserved
28/131
1
ST7275-2
4 ON-CHIP PERIPHERALS
4.1 I/O PORTS
4.1.1 Introduction
The I/O ports allow the transfer of data through
digital inputs and outputs, and, for specific pins,
the input of analog signals or the Input/Output of
alternate signals for on-chip peripherals (DDC,
TIMER...).
Each pin can be programmed independently as
digital input or digital output. Each pin can be an
analog input when an analog switch is connected
to the Analog to Digital Converter (ADC).
Figure 15. I/O Pin Typical Circuit
Alternate enable
Alternate 1
output
VDD
0
P-BUFFER
(if required)
Data Bus
Common Analog Rail
DR
latch
PULL-UP (if required)
Alternate enable
DDR
latch
PAD
Analog Enable
(ADC)
Analog
Switch (if required)
DDR SEL
N-BUFFER
DR SEL
1
Alternate Enable
VSS
0
Digital Enable
Alternate Input
Note: This is the typical I/O pin configuration. For cost optimisation, each port is customised with a specific
configuration.
29/131
ST7275-2
I/O PORTS (Cont’d)
Table 8. I/O Pin Functions
DDR
MODE
0
Input
1
Output
4.1.2 Common Functional Description
Each port pin of the I/O Ports can be individually
configured under software control as either input
or output.
Each bit of a Data Direction Register (DDR) corresponds to an I/O pin of the associated port. This
corresponding bit must be set to configure its associated pin as output and must be cleared to configure its associated pin as input (Table 8). The
Data Direction Registers can be read and written.
The typical I/O circuit is shown on Figure 15. Any
write to an I/O port updates the port data register
even if it is configured as input. Any read of an I/O
port returns either the data latched in the port data
register (pins configured as output) or the value of
the I/O pins (pins configured as input).
Remark: when an I/O pin does not exist inside an
I/O port, the returned value is a logic one (pin configured as input).
At reset, all DDR registers are cleared, which configures all port’s I/Os as inputs with or without pullups (see Table 9 to Table 13). The Data Registers
(DR) are also initialized at reset.
4.1.2.1 Input mode
When DDR=0, the corresponding I/O is configured
in Input mode.
In this case, the output buffer is switched off, the
state of the I/O is readable through the Data Register address, but the I/O state comes directly from
the CMOS Schmitt Trigger output and not from the
Data Register output.
4.1.2.2 Output mode
When DDR=1, the corresponding I/O is configured
in Output mode.
In this case, the output buffer is activated according to the Data Register’s content.
A read operation is directly performed from the
Data Register output.
4.1.2.3 Analog input
Each I/O can be used as analog input by adding
an analog switch driven by the ADC.
The I/O must be configured in Input without pull-up
before using it as analog input.
The CMOS Schmitt trigger is OFF (write FFh twice
in the ICFGR register) and the analog value directly input through an analog switch to the Analog to
Digital Converter, when the analog channel is selected by the ADC.
4.1.2.4 Alternate mode
A signal coming from a on-chip peripheral can be
output on the I/O.
In this case, the I/O is automatically configured in
output mode.
This must be controlled directly by the peripheral
with a signal coming from the peripheral which enables the alternate signal to be output.
A signal coming from an I/O can be input in a onchip peripheral.
Before using an I/O as Alternate Input, it must be
configured in Input mode (DDR=0). So both Alternate Input configuration and I/O Input configuration are the same (with or without pull-up). The signal to be input in the peripheral is taken after the
CMOS Schmitt trigger or TTL Schmitt trigger for
SYNC.
The I/O state is readable as in Input mode by addressing the corresponding I/O Data Register.
4.1.3 Port A
Each Port A bit can be defined as an Input line (no
pull-up) or as an Output Open drain line. PA1,
PA3, PA4, PA5 and PA6 can also be used as high
voltage outputs (9V).
Figure 16. Input Structure for SYNC signals
VDD
pull-up
TTL trigger
SYNC block
Pin
I/O logic (if existing)
30/131
ST7275-2
I/O PORTS (Cont’d)
Table 9. Port A Description
I/O
PORT A
Alternate Function
Input*
Output
Signal
Condition
PA1
without pull-up
open drain (9V)
-
-
PA3
without pull-up
open drain (9V)
-
-
PA4
without pull-up
open drain (9V)
-
-
PA5
without pull-up
open drain (9V)
-
-
PA6
without pull-up
open drain (9V)
-
-
PA7
without pull-up
open drain
BLANKOUT
BLKEN = 1
(ENR[SYNC])
*Reset State
Figure 17. Port A
Alternate enable
Alternate1
output
0
DATA BUS
DR
latch
DDR
latch
PAD
DDR SEL
N-BUFFER
DR SEL
1
Alternate enable
VSS
0
CMOS Schmitt Trigger
31/131
ST7275-2
I/O PORTS (Cont’d)
4.1.4 Port B
Each bit of port B bit can be used as the Analog
source to the Analog to Digital Converter by selecting each individual bit independently in the Port
B Configuration Register [ICFGR].
Only one I/O line must be configured as an analog
input at any time. The user must avoid any situation in which more than one I/O pin is selected as
an analog input simultaneously to avoid device
malfunction.
When the analog function is selected for an I/O
pin, the pull-up of the respective pin of Port B is
disconnected and the digital input is off.
If the SYNC function is selected, Port B bit 0
MUST be set as input to enable the VFBACK timing input.
All unused I/O lines should be tied to an appropriate logic level (either VDD or VSS)
Since the ADC is on the same chip as the microprocessor, the user should not switch heavily loaded signals during conversion, if high precision is
required. Such switching will affect the supply voltages used as analog references. the accuracy of
the conversion depends on the quality of the power supplies (VDD and VSS). The user must take
special care to ensure that a well regulated reference voltage is present on the VDD and VSS pins
(power supply variations must be less than 5V/
ms). This implies, in particular, that a suitable decoupling capacitor is used at the VDD pin.
Table 10. Port B Description
PORT B
I/O
Alternate Function
Input *
Output
PB0
with pull-up
push-pull
PB1
with pull-up
PB2
PB7
*Reset state
32/131
Signal
Condition
analog input (ADC) (without pull-up)
AD0=1 (ICFGR)
VFBACK (input with TTL schmitt trigger)
AD0=0 (ICFGR)
push-pull
analog input (ADC) (without pull-up)
AD1=1 (ICFGR)
with pull-up
push-pull
analog input (ADC) (without pull-up)
AD2=1 (ICFGR)
with pull-up
push-pull
analog input (ADC) (without pull-up)
AD7=1 (ICFGR)
ST7275-2
I/O PORTS (Cont’d)
Figure 18. PB0
V DD
P-BUFFER
Common Analog Rail
DATA BUS
DR
latch
PULL-UP
DDR
latch
ICFGR
latch
PAD
ICFGR SEL
analog enable
(ADC)
Analog
switch
DDR SEL
N-BUFFER
DR SEL
1
0
VSS
CMOS Schmitt Trigger
Alternate input (VFBACK)
TTL Schmitt Trigger
33/131
ST7275-2
I/O PORTS (Cont’d)
Figure 19. PB1, PB2, PB7
VDD
P-BUFFER
Common Analog Rail
DATA BUS
DR
latch
PULL-UP
DDR
latch
ICFGR
latch
PAD
ICFGR SEL
Analog enable
(ADC)
Analog
switch
DDR SEL
N-BUFFER
DR SEL
1
VSS
0
CMOS Schmitt Trigger
34/131
ST7275-2
I/O PORTS (Cont’d)
4.1.5 Port C
The available port pins of port C may be used as
general purpose I/O.
The alternate functions are HFBACK input for
PC0, the I/O pins of the on-chip DDC SCLD & SC-
DAD for PC2:3, the I/O pins of the on-chip I2C
SCLI & SCDAI for PC4:5, the Timer Output Compare OCMP on PC0 and the input trigger falling
edge Detector RX for PC2.
Table 11. Port C Description
I/ O
PORT C
PC0
PC2
Input*
with pull-up
input without pull-up
Alternate Function
Output
push-pull
open-drain
Signal
Condition
OCMP (push-pull)
OC1E =1
(CR2[TIMER])
HFBACK (input with TTL schmitt trigger)
-
SCLD (input with CMOS schmitt trigger or open drain
output)
DDC enable
RX (input)
-
PC3
input without pull-up
open-drain
SDAD (input with CMOS schmitt trigger or open drain
output)
DDC enable
PC4
input without pull-up
open-drain
SCLI (input with CMOS schmitt trigger or open drain
output)
I2C enable
PC5
input without pull-up
open-drain
SDAI (input with CMOS schmitt trigger or open drain
output)
I2C enable
PC6
input without pull-up
open-drain
(10mA, 5V)
* Reset State
35/131
ST7275-2
I/O PORTS (Cont’d)
Figure 20. PC0
OC1E
1
V DD
OCMP
0
P-BUFFER
DR
latch
PULL-UP
OC1E
DDR
latch
DATA BUS
PAD
DDR SEL
N-BUFFER
DR SEL
1
OC1E
0
VSS
CMOS Schmitt Trigger
HFBACK input
36/131
TTL Schmitt Trigger
ST7275-2
I/O PORTS (Cont’d)
Figure 21. PC2 to PC6
Alternate enable
DR
latch
Alternate
output
1
0
DATA BUS
DDR
latch
PAD
DDR SEL
N-BUFFER
DR SEL
1
0
Alternate enable
CMOS Schmitt Trigger
VSS
Alternate input
37/131
ST7275-2
I/O PORTS (Cont’d)
4.1.6 Port D
The Port D I/O pins PD0..3 are normally used for
the input and output of video synchronization signals of the Sync Processor, but are set to I/O Input
with pull-up upon reset. The I/O mode can be set
individually for each port bit to Input with pull-up
and output push-pull through the Port D DDR.
The configuration to support the Sync Processor
requires that the SYNOP (bit7) and CLMPEN
(bit6) of the ENR (Enable Register of SYNC) is reset. SYNOP enables port D bits 1, 2 and CLMPEN
enables Port D bit 6 to the sync outputs.
Port D, bit 5:3 are the alternate inputs ITA, ITB,
ITC (for the interrupt falling edge detector).
When a falling edge occurs on these inputs, an in-
terrupt will be generated according to the status of
the INTX (ITAITE & ITBITE & ITCITE) bits in the
ITRFRE Register.
Port D, bit 6 is switched to the alternate (CLAMPOUT) by resetting the CLMPEN bit of the ENR
Register inside SYNC block.
Note: As these inputs are switched from normal
I/O functionality, the video synchronization signals
may also be monitored directly through the Port D
Data Register for such tasks as checking for the
presence of video signals or checking the polarity
of Horizontal and Vertical synchronization signals
(when the Sync Inputs are switched directly to the
outputs using the multiplexers of the Sync Processor).
Table 12. Port D Description
PORT D
I/O
Inpu t*
Alternate Function
Output
PD0
with pull-up
push-pull
PD1
with pull-up
push-pull
PD2
with pull-up
push-pull
PD3
with pull-up
push-pull
PD4
with pull-up
push-pull
PD5
with pull-up
push-pull
PD6
with pull-up
push-pull
* Reset state
38/131
Signal
CSYNCI
(TTL Schmitt trigger & pull-up)
Condit ion
-
HSYNCO
SYNOP=0
(push pull output)
(ENR [SYNC])
VSYNCO
SYNOP=0
(push pull output)
(ENR [SYNC])
ITC input with
(CMOS schmitt trigger & pull-up)
ITB input with
(CMOS schmitt trigger & pull-up)
ITA input with
(CMOS schmitt trigger & pull-up)
-
CLAMPOUT
CLMPEN=0
(push pull output)
(ENR [SYNC])
ST7275-2
I/O PORTS (Cont’d)
Figure 22. PD0
DATA BUS
VDD
P-BUFFER
DR
latch
PULL-UP
DDR
latch
PAD
DDR SEL
N-BUFFER
1
DR SEL
VSS
0
CMOS Schmitt Trigger
CSYNCI input
TTL Schmitt Trigger
Figure 23. PD1 to PD6
Alternate enable
DATA BUS
Alternate
output
1
V DD
0
P-BUFFER
DR
latch
PULL-UP
Alternate enable
DDR
latch
PAD
DDR SEL
N-BUFFER
DR SEL
Alternate input
1
0
Alternate enable
VSS
CMOS Schmitt Trigger
39/131
ST7275-2
4.1.7 Register Description
Data Registers (PxDR)
Read/Write
Reset Value: 0000 0000 (00h)
PORT B Configuration Register (ICFGR)
Read/Write
Reset Value: 0000 0000 (00h)
7
7
0
0
AD7
MSB
-
-
-
-
AD2
AD1
AD0
LSB
Bit 7 = AD7 Digital/Analog Input Configuration Bit.
0: The pull-up is connected and pin configured as
digital input (reset condition)
1: The pull-up on pin 7i of Port B is disconnected
and the pin is configured as analog input .
Data Direction Registers (PxDDR)
Read/Write
Reset Value: 0000 0000 (00h) (as inputs)
7
0
MSB
LSB
Bit 6:3 = Reserved, forced by hardware to 0.
Bit 2:0 = AD[2:0] Digital/Analog Input Configuration Bits.
0: The pull-up is connected and pin configured as
digital input (reset condition)
1: The pull-up on pin #i of Port B is disconnected
and the pin is configured as analog input .
Table 13. I/O Ports Register Map
Address
(Hex.)
Register
Name
7
00
PADR
MSB
LSB
01
PADDR
MSB
LSB
02
PCDR
MSB
LSB
03
PCDDR
MSB
LSB
04
PDDR
MSB
LSB
05
PDDDR
MSB
LSB
06
PBDR
MSB
LSB
07
PBDDR
MSB
LSB
08
ICFGR
AD7
40/131
6
5
4
Reserved
3
2
AD2
1
AD1
0
AD0
ST7275-2
4.2 WATCHDOG TIMER (WDG)
4.2.1 Introduction
The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to
abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared.
4.2.2 Main Features
■ Programmable timer (64 increments of 49,152
CPU cycles)
■ Programmable reset
■ Reset (if watchdog activated) after a HALT
instruction or when the T6 bit reaches zero
Figure 24. Watchdog Block Diagram
RESET
WATCHDOG CONTROL REGISTER (CR)
WDGA
T6
T5
T4
T3
T2
T1
T0
7-BIT DOWNCOUNTER
fCPU
CLOCK DIVIDER
÷ 49152
41/131
ST7275-2
WATCHDOG TIMER (Cont’d)
4.2.3 Functional Description
The counter value stored in the CR register (bits
T6:T0), is decremented every 49,152 machine cycles, and the length of the timeout period can be
programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T6:T0) rolls over
from 40h to 3Fh (T6 become cleared), it initiates a
reset cycle pulling low the reset pin for typically
500ns.
The application program must write in the CR register at regular intervals during normal operation to
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h
(see Table 14):
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an immediate reset
– The T5:T0 bits contain the number of increments
which represents the time delay before the
watchdog produces a reset.
4.2.4 Low Power Modes
Mode
WAIT
HALT
Description
No effect on Watchdog.
Immediate reset generation as soon as
the HALT instruction is executed if the
Watchdog is activated (WDGA bit is
set).
4.2.5 Interrupts
None.
4.2.6 Register Description
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0111 1111 (7Fh)
7
WDGA
0
T6
T5
T4
T3
T2
T1
T0
Table 14. Watchdog Timing (fCPU = 8 MHz)
Max
Min
CR Register
initial value
FFh
C0h
WDG timeout period
(ms)
393.216
6.144
Notes: Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except
by a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction
will generate a Reset.
Bit 7= WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared) if WDGA=1.
Table 15. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
0C
42/131
Register
Label
7
6
5
4
3
2
1
0
WDGCR
WDGA
T6
T5
T4
T3
T2
T1
T0
Reset Value
0
1
1
1
1
1
1
1
ST7275-2
4.3 16-BIT TIMER
4.3.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
It may be used for a variety of purposes, including
pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU
clock prescaler.
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not
share any resources. They are synchronized after
a MCU reset as long as the timer clock frequencies are not modified.
This description covers one or two 16-bit timers. In
ST7 devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
4.3.2 Main Features
■ Programmable prescaler: fCPU divided by 2, 4 or 8.
■ Overflow status flag and maskable interrupt
■ External clock input (must be at least 4 times
slower than the CPU clock speed) with the choice
of active edge
■ Output compare functions with
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ Input capture functions with
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
■ Pulse width modulation mode (PWM)
■ One pulse mode
■ 5 alternate functions on I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*
4.3.3 Functional Description
4.3.3.1 Counter
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.
Counter Register (CR):
– Counter High Register (CHR) is the most significant byte (MS Byte).
– Counter Low Register (CLR) is the least significant byte (LS Byte).
Alternate Counter Register (ACR)
– Alternate Counter High Register (ACHR) is the
most significant byte (MS Byte).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LS Byte).
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
(see note at the end of paragraph titled 16-bit read
sequence).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit timer). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 16. The
value in the counter register repeats every
131.072, 262.144 or 524.288 CPU clock cycles
depending on the CC[1:0] bits.
The timer frequency can be fCPU/2, fCPU /4, fCPU/8
or an external frequency.
The Block Diagram is shown in Figure 25.
*Note: Some timer pins may not available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
43/131
ST7275-2
16-BIT TIMER (Cont’d)
Figure 25. Timer Block Diagram
ST7 INTERNAL BUS
fCPU
MCU-PERIPHERAL INTERFACE
8 low
8
8
8
low
low
8
high
8
8
high
EXEDG
8
low
high
8
high
8-bit
buffer
low
8 high
16
1/2
1/4
REGISTER
1/8
OUTPUT
COMPARE
REGISTER
2
OUTPUT
COMPARE
REGISTER
1
COUNTER
ALTERNATE
COUNTER
REGISTER
EXTCLK
pin
INPUT
CAPTURE
REGISTER
1
INPUT
CAPTURE
REGISTER
2
16
16
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
CIRCUIT
OUTPUT COMPARE
CIRCUIT
6
ICF1 OCF1 TOF ICF2 OCF2
0
0
EDGE DETECT
CIRCUIT1
ICAP1
pin
EDGE DETECT
CIRCUIT2
ICAP2
pin
LATCH1
OCMP1
pin
LATCH2
OCMP2
pin
0
(Status Register) SR
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
(Control Register 1) CR1
OC1E OC2E OPM PWM
CC1
CC0 IEDG2 EXEDG
(Control Register 2) CR2
(See note)
TIMER INTERRUPT
44/131
Note: If IC, OC and TO interrupt requests have separate vectors
then the last OR is not present (See device Interrupt Vector Table)
ST7275-2
16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Register or the Alternate Counter Register).
Beginning of the sequence
At t0
Read
MS Byte
LS Byte
is buffered
Other
instructions
Read
At t0 +∆t LS Byte
Returns the buffered
LS Byte value at t0
Sequence completed
The user must read the MS Byte first, then the LS
Byte value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they return the LS Byte of the count value at the time of
the read.
Whatever the timer mode used (input capture, output compare, one pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt remains pending to be issued as soon as they are
both true.
Clearing the overflow interrupt request is done in
two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Notes: The TOF bit is not cleared by accesses to
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).
4.3.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in CR2 register.
The status of the EXEDG bit in the CR2 register
determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter.
The counter is synchronised with the falling edge
of the internal CPU clock.
A minimum of four falling edges of the CPU clock
must occur between two consecutive active edges
of the external clock; thus the external clock frequency must be less than a quarter of the CPU
clock frequency.
45/131
ST7275-2
16-BIT TIMER (Cont’d)
Figure 26. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
FFFD FFFE FFFF 0000
COUNTER REGISTER
0001
0002
0003
TIMER OVERFLOW FLAG (TOF)
Figure 27. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
FFFC
FFFD
0000
0001
TIMER OVERFLOW FLAG (TOF)
Figure 28. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
FFFC
FFFD
0000
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
46/131
ST7275-2
16-BIT TIMER (Cont’d)
4.3.3.3 Input Capture
In this section, the index, i, may be 1 or 2 because
there are 2 input capture functions in the 16-bit
timer.
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free running counter after a transition detected by the
ICAPi pin (see figure 5).
ICiR
MS Byte
ICiHR
LS Byte
ICiLR
ICiR register is a read-only register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
counter: (fCPU/CC[1:0]).
Procedure:
To use the input capture function select the following in the CR2 register:
– Select the timer clock (CC[1:0]) (see Table 16).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input).
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as floating input).
When an input capture occurs:
– ICFi bit is set.
– The ICiR register contains the value of the free
running counter on the active transition on the
ICAPi pin (see Figure 30).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both
conditions become true.
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
Notes:
1. After reading the ICiHR register, transfer of
input capture data is inhibited and ICFi will
never be set until the ICiLR register is also
read.
2. The ICiR register contains the free running
counter value which corresponds to the most
recent input capture.
3. The 2 input capture functions can be used
together even if the timer also uses the 2 output
compare functions.
4. In One pulse Mode and PWM mode only the
input capture 2 can be used.
5. The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activate the input capture function.
Moreover if one of the ICAPi pin is configured
as an input and the second one as an output,
an interrupt can be generated if the user toggle
the output pin and if the ICIE bit is set.
This can be avoided if the input capture function i is disabled by reading the ICiHR (see note
1).
6. The TOF bit can be used with interrupt in order
to measure event that go beyond the timer
range (FFFFh).
47/131
ST7275-2
16-BIT TIMER (Cont’d)
Figure 29. Input Capture Block Diagram
ICAP1
pin
ICAP2
pin
(Control Register 1) CR1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
IEDG1
(Status Register) SR
IC2R Register
ICF1
IC1R Register
ICF2
0
16-BIT FREE RUNNING
CC1
CC0
COUNTER
Figure 30. Input Capture Timing Diagram
TIMER CLOCK
FF01
FF02
FF03
ICAPi PIN
ICAPi FLAG
ICAPi REGISTER
Note: Active edge is rising edge.
48/131
0
(Control Register 2) CR2
16-BIT
COUNTER REGISTER
0
FF03
IEDG2
ST7275-2
16-BIT TIMER (Cont’d)
4.3.3.4 Output Compare
In this section, the index, i, may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
This function can be used to control an output
waveform or indicating when a period of time has
elapsed.
When a match is found between the Output Compare register and the free running counter, the output compare function:
– Assigns pins with a programmable value if the
OCIE bit is set
– Sets a flag in the status register
– Generates an interrupt if enabled
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
OCiR
MS Byte
OCiHR
LS Byte
OCiLR
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
Timing resolution is one count of the free running
counter: (fCPU/CC[1:0] ).
Procedure:
To use the output compare function, select the following in the CR2 register:
– Set the OCiE bit if an output is needed then the
OCMPi pin is dedicated to the output compare i
signal.
– Select the timer clock (CC[1:0]) (see Table 16).
And select the following in the CR1 register:
– Select the OLVL i bit to applied to the OCMPi pins
after the match occurs.
– Set the OCIE bit to generate an interrupt if it is
needed.
When a match is found between OCRi register
and CR register:
– OCFi bit is set.
– The OCMPi pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset).
– A timer interrupt is generated if the OCIE bit is
set in the CR2 register and the I bit is cleared in
the CC register (CC).
The OCiR register value required for a specific timing application can be calculated using the following formula:
∆ OCiR =
∆t * fCPU
PRESC
Where:
∆t
= Output compare period (in seconds)
fCPU
= CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 16)
If the timer clock is an external clock, the formula
is:
∆ OCiR = ∆t * fEXT
Where:
∆t
= Output compare period (in seconds)
fEXT
= External timer clock frequency (in hertz)
Clearing the output compare interrupt request (i.e.
clearing the OCFi bit) is done by:
1. Reading the SR register while the OCFi bit is
set.
2. An access (read or write) to the OCiLR register.
The following procedure is recommended to prevent the OCFi bit from being set between the time
it is read and the write to the OCiR register:
– Write to the OCiHR register (further compares
are inhibited).
– Read the SR register (first step of the clearance
of the OCFi bit, which may be already set).
– Write to the OCiLR register (enables the output
compare function and clears the OCFi bit).
49/131
ST7275-2
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OCi HR register, the output compare function is inhibited
until the OCiLR register is also written.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is fCPU/2, OCFi and
OCMPi are set while the counter value equals
the OCiR register value (see Figure 32, on
page 51). This behaviour is the same in OPM
or PWM mode.
When the timer clock is fCPU/4, fCPU/8 or in
external clock mode, OCFi and OCMPi are set
while the counter value equals the OCiR register value plus 1 (see Figure 33, on page 51).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLVi bit should be changed after each successful comparison in order to control an output
waveform or establish a new elapsed timeout.
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
FOLVLi bits have no effect in both one pulse mode
and PWM mode.
Figure 31. Output Compare Block Diagram
16 BIT FREE RUNNING
COUNTER
OC1E OC2E
CC1
CC0
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
16-bit
OCIE
FOLV2 FOLV1 OLVL2
OLVL1
16-bit
Latch
2
OC1R Register
OCF1
OCF2
0
0
0
OC2R Register
(Status Register) SR
50/131
Latch
1
OCMP1
Pin
OCMP2
Pin
ST7275-2
16-BIT TIMER (Cont’d)
Figure 32. Output Compare Timing Diagram, fTIMER =fCPU/2
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0 2ED1 2ED2 2ED3 2ED4
OUTPUT COMPARE REGISTER i (OCR i)
2ED3
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
Figure 33. Output Compare Timing Diagram, fTIMER =fCPU/4
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCR i)
2ECF 2ED0
2ED1 2ED2 2ED3 2ED4
2ED3
COMPARE REGISTER i LATCH
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
51/131
ST7275-2
16-BIT TIMER (Cont’d)
4.3.3.5 One Pulse Mode
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
Procedure:
To use one pulse mode:
1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column).
2. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse.
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
3. Select the following in the CR2 register:
– Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function.
– Set the OPM bit.
– Select the timer clock CC[1:0] (see Table 16).
One pulse mode cycle
When
event occurs
on ICAP1
OCMP1 = OLVL2
Counter is reset
to FFFCh
ICF1 bit is set
When
Counter
= OC1R
OCMP1 = OLVL1
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
52/131
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The OC1R register value required for a specific
timing application can be calculated using the following formula:
OCiR Value =
t * fCPU
-5
PRESC
Where:
t
= Output compare period (in seconds)
fCPU = ICPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 16)
If the timer clock is an external clock the formula is:
∆ OCiR = ∆t * fEXT -5
Where:
∆t
= Output compare period (in seconds)
fEXT
= External timer clock frequency (in hertz)
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 34).
Notes:
1. The OCF1 bit cannot be set by hardware in one
pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
2. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
3. If OLVL1=OLVL2 a continuous signal will be
seen on the OCMP1 pin.
4. The ICAP1 pin can not be used to perform input
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
5. When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode.
ST7275-2
16-BIT TIMER (Cont’d)
Figure 34. One Pulse Mode Timing Example
COUNTER
....
FFFC FFFD FFFE
2ED0
2ED1 2ED2
FFFC FFFD
2ED3
ICAP1
OLVL2
OCMP1
OLVL1
OLVL2
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 35. Pulse Width Modulation Mode Timing Example
COUNTER
34E2
FFFC FFFD FFFE
2ED0 2ED1 2ED2
OLVL2
OCMP1
compare2
OLVL1
compare1
34E2
FFFC
OLVL2
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
53/131
ST7275-2
16-BIT TIMER (Cont’d)
4.3.3.6 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
The pulse width modulation mode uses the complete Output Compare 1 function plus the OC2R
register, and so these functionality can not be
used when the PWM mode is activated.
Procedure
To use pulse width modulation mode:
1. Load the OC2R register with the value corresponding to the period of the signal using the
formula in the opposite column.
2. Load the OC1R register with the value corresponding to the length of the pulse if (OLVL1=0
and OLVL2=1) using the formula in the opposite column.
3. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful
comparison with OC1R register.
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful
comparison with OC2R register.
4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see Table
16).
If OLVL1=1 and OLVL2=0 the length of the positive pulse is the difference between the OC2R and
OC1R registers.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
Pulse Width Modulation cycle
When
Counter
= OC1R
When
Counter
= OC2R
OCMP1 = OLVL1
OCMP1 = OLVL2
Counter is reset
to FFFCh
ICF1 bit is set
54/131
The OCiR register value required for a specific timing application can be calculated using the following formula:
OCiR Value =
t * fCPU
-5
PRESC
Where:
t
= Output compare period (in seconds)
fCPU = ICPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 16)
If the timer clock is an external clock the formula is:
∆ OCiR = ∆t * fEXT -5
Where:
∆t
= Output compare period (in seconds)
fEXT
= External timer clock frequency (in hertz)
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 35)
Notes:
1. After a write instruction to the OCiHR register,
the output compare function is inhibited until the
OCiLR register is also written.
2. The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
3. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
4. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is disconnected to the timer. The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.
5. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
ST7275-2
16-BIT TIMER (Cont’d)
4.3.4 Low Power Modes
Mode
WAIT
HALT
Description
No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter
reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
4.3.5 Interrupts
Event
Flag
Interrupt Event
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
ICF1
ICF2
OCF1
OCF2
TOF
Enable
Control
Bit
ICIE
OCIE
TOIE
Exit
from
Wait
Yes
Yes
Yes
Yes
Yes
Exit
from
Halt
No
No
No
No
No
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the
CC register is reset (RIM instruction).
4.3.6 Summary of Timer modes
MODES
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse Mode
PWM Mode
1)
2)
3)
Input Capture 1
Yes
Yes
No
No
AVAILABLE RESOURCES
Input Capture 2
Output Compare 1 Output Compare 2
Yes
Yes
Yes
Yes
Yes
Yes
Not Recommended 1)
Not Recommended 3)
No
No
Partially 2)
No
See note 4 in Section 4.3.3.5 One Pulse Mode
See note 5 in Section 4.3.3.5 One Pulse Mode
See note 4 in Section 4.3.3.6 Pulse Width Modulation Mode
55/131
ST7275-2
16-BIT TIMER (Cont’d)
4.3.7 Register Description
Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the alternate counter.
CONTROL REGISTER 1 (CR1)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1: Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
1: Forces OLVL1 to be copied to the OCMP1 pin, if
the OC1E bit is set and even if there is no successful comparison.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
bit of the SR register is set.
56/131
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
ST7275-2
16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Reset Value: 0000 0000 (00h)
7
0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 7 = OC1E Output Compare 1 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the Output Compare 1 function of the timer remains active.
0: OCMP1 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit,
the Output Compare 2 function of the timer remains active.
0: OCMP2 pin alternate function disabled (I/O pin
free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Bit 5 = OPM One Pulse Mode.
0: One Pulse Mode is not active.
1: One Pulse Mode is active, the ICAP1 pin can be
used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.
Bit 4 = PWM Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a
programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R register.
Bit 3, 2 = CC[1:0] Clock Control.
The timer clock mode depends on these bits:
Table 16. Clock Control Bits
Timer Clock
fCPU / 4
fCPU / 2
fCPU / 8
External Clock (where
available)
CC1
0
0
1
CC0
0
1
0
1
1
Note: If the external clock pin is not available, programming the external clock configuration stops
the counter.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = EXEDG External Clock Edge.
This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
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ST7275-2
16-BIT TIMER (Cont’d)
STATUS REGISTER (SR)
Read Only
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
7
ICF1
0
OCF1
TOF
ICF2
OCF2
0
0
0
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin
or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) register.
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
1: The free running counter rolled over from FFFFh
to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR
(CLR) register.
Note: Reading or writing the ACLR register does
not clear TOF.
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2
pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has
matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) register.
Bit 2-0 = Reserved, forced by hardware to 0.
58/131
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).
7
0
MSB
LSB
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the input capture 1 event).
7
0
MSB
LSB
OUTPUT COMPARE 1 HIGH REGISTER
(OC1HR)
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
7
0
MSB
LSB
OUTPUT COMPARE 1 LOW REGISTER
(OC1LR)
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
MSB
LSB
ST7275-2
16-BIT TIMER (Cont’d)
OUTPUT COMPARE 2 HIGH REGISTER
(OC2HR)
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the counter value.
7
0
7
0
MSB
LSB
MSB
LSB
OUTPUT COMPARE 2 LOW REGISTER
(OC2LR)
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.
7
0
MSB
LSB
COUNTER HIGH REGISTER (CHR)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part
of the counter value.
7
0
MSB
LSB
COUNTER LOW REGISTER (CLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the SR register clears the TOF bit.
7
0
MSB
LSB
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to SR register does not clear the TOF bit in SR
register.
7
0
MSB
LSB
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).
7
0
MSB
LSB
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the
low part of the counter value (transferred by the Input Capture 2 event).
7
0
MSB
LSB
59/131
ST7275-2
16-BIT TIMER (Cont’d)
Table 17. 16-Bit Timer Register Map
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
11
CR2
OC1E
OC2E
OPM
PWM
CC1
CC0
IEDG2
EXEDG
12
CR1
ICIE
OCIE
TOIE
FOLV2
FOLV1
OLVL2
IEDG1
OLVL1
13
SR
ICF1
OCF1
TOF
ICF2
OCF2
0
0
0
14
IC1HR
MSB
LSB
15
IC1LR
MSB
LSB
16
OC1HR
MSB
LSB
17
OC1LR
MSB
LSB
18
CHR
MSB
LSB
19
CLR
MSB
LSB
1A
ACHR
MSB
LSB
1B
ACLR
MSB
LSB
1C
IC2HR
MSB
LSB
1D
IC2LR
MSB
LSB
1E
OC2HR
MSB
LSB
1F
OC2LR
MSB
LSB
60/131
ST7275-2
4.4 SYNC PROCESSOR (SYNC)
4.4.1 Introduction
The Sync processor handles all the management
tasks of the video synchronization signals, and is
used with the timer and software to provide information and status on the video standard and timings. This block supports multiple video standards
such as: Separate Sync, Composite Sync and (via
an external extractor) Sync on Green. The internal
clock in the Sync processor is 4 MHz.
– Generate free-running frequencies
– Generate a video blanking signal
– Generate a clamping signal or a Moire signal
Analyzer Mode
– Measure the number of scan lines per frame to
simplify OSD vertical centering
– Detect HSYNCI reaching too high a frequency
– Detect pre/post equalization pulses
– Measure the low level of HSYNCO or HFBACK
■
4.4.2 Main Features
■ Input Processing
– Presence of incoming signals (edge detection)
– Read the HSYNCI / VSYNCI input signal levels
– Measure the signal periods
– Detect the sync polarities
– Detect the composite sync and extract VSYNCO
Corrector Mode
– Inhibit Pre/Post equalization pulses
– Program VSYNCO pulse width extension
– Extend VSYNCO pulse widths during:
post-equalization pulse detection only
pre and post-equalization pulse detection
Note: Some external pins are not available on all
devices. Refer to the device pinout description.
■
Output Processing
– Control the sync output polarities
■
Figure 36. Sync Processor Block Diagram
ICAP1 TIMER
1
VSYNCI1
V Sync O
Polarity
Latch
Pulse Detect
VSYNCI
LCV1
VSYNCI2
0
HVSEL
LD
Capture
Register
Vsync*
Control
Logic
VFBACK
LCV1
Sync
&
Edge
Detect
Up / Down
EN
8-Bit Counter
CLK
LCV0
fINT Latch
Latch
00
1F
match match
Prescaler
HSYNCI1
Latch
HVSEL
Pulse Detect
1
0
0
1
Latch
Pulse Detect
HVGEN
0
SYNOP
V Sync
Correction 1
1
BLKEN
Blanking
Generator
0
FBSEL
V
S
Y HFBACK 0
N
C
1
O
Sync Generator
Sync Analyzer
Sync Corrector
Hardware Block
VSYNCO
BLANKOUT
VSYNC Generator
40 - 200 Hz
Typical Pulse Width
20 - 256 µs
HSYNC Generator
15 - 200 kHz
Duty cycle range
(Positive polarity)
3 - 40 %
FBSEL
ICAP2 TIMER
H-Inhibit
ON/OFF
HSYNCI / CSYNCI
HSYNCI2
CSYNCI
PSCD
Polarity
Detector
SYNOP
H Sync O
Polarity
SCI0
1
H Sync O
Correction
Back Porch
Clamp
Generator
0
HVGEN
HFBACK
HSYNCO
Clamp
Polarity
CLPINV
Other
CLAMPOUT
00
CLMPEN
Pull-Up Resistor (if existing)
VFBACK
BP1, BP0
VR02071C
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ST7275-2
SYNC PROCESSOR (SYNC) (Cont’d)
4.4.3 Input Signals
The Sync Processor has the following inputs (TTL
level with pull-up):
– VSYNCI1 Vertical Sync input1
– HSYNCI1 Horizontal Sync input1 or Composite
sync
– VSYNCI2 Vertical Sync input2
– HSYNCI2 Horizontal Sync input2 or Composite
sync
Note: The above input pairs can be used for
DSUB or BNC connectors. To select these inputs
use the HVSEL bit in the POLR register.
– CSYNCI Sync on Green (external extractor)
Note: If the CSYNCI pin is needed for another I/O
function, the composite sync signal can be connected to HSYNCI using the SCI0 bit in the MCR
register.
– HFBACK Horizontal Flyback input
– VFBACK Vertical Flyback input
4.4.4 Input Signal Waveforms
– The input signals must contain only synchronization pulses. In case of serration pulses on CSYNCI/HSYNCI, the pulse width should be less than
8µs.
– The VSYNCI signal is internally connected to
Timer Input Capture 1 (ICAP1).
– The HSYNCI or CSYNCI signal, prescaled by
256, is internally connected to Timer Input Capture 2 (ICAP2).
– Typical timing range: See Figure 37 and 38
– If the timer clock is 2 MHz (external oscillator frequency 24 MHz):
PV accuracy = +/- 1 Timer clock (500ns)
PH*256 accuracy = +/- 1 Timer clock (500ns)
(PV= Vertical pulse, PH = Horizontal pulse)
62/131
4.4.5 Output Signals
The Sync Processor has the following outputs:
HSYNCO Horizontal Sync Output
Enable: SYNOP bit in ENR register
Programmable polarity:
HS0/HS1 bits in MCR register
In case of composite sync signal, the signal can be
blanked by software during the vertical period
(HINH bit in ENR register).
In case of separate sync, no blanking is
generated.
VSYNCO Vertical Sync Output
Enable: SYNOP bit in ENR register
Programmable polarity:
VOP bit in the MCR register
In case of composite sync the delay of the
extracted Vsync signal is:
minimum: 500ns + HSYNCO pulse width
maximum: 8750ns (max. threshold in extraction mode)
ST7275-2
SYNC PROCESSOR (SYNC) (Cont’d)
Figure 37. Typical Horizontal Sync Input Timing
or:
5µs < Typical Hor. Total time < 66.66µs
(200kHz)
(15kHz)
Maximum Sync. pulse width: 7µs
Note: Minimum HPeriod: 500ns + S/W interrupt servicing time
(1 Timer Clock)
VR01961
Figure 38. Vertical Sync Input Timing
or:
5ms < Typical Ver. Total time < 25ms
(200Hz)
(40Hz)
Typical Sync. pulse width: 0.0384ms - 0.600ms
Note: Minimum VPeriod: 500ns + S/W interrupt servicing time
(1 Timer Clock)
VR01961A
63/131
ST7275-2
SYNC PROCESSOR (SYNC) (Cont’d)
ClampOut and Moire Signal
Clamp Output signal
The clamping pulse generator can control the
pulse width and polarity signal and can be configured as pseudo-front porch or back porch.
To use the ClampOut signal:
– Select the Clamping Pulse width:
BP0/BP1 bits in MCR register
– Program the Clamp polarity:
CLPINV bit in POLR register
– Select the ClampOut signal as back-porch (after
falling edge of HSYNCO) or pseudo-front porch
(after the rising edge of HSYNCO):
HS0/HS1 bits in MCR register.
– Enable the CLAMPOUT signal:
CLMPEN bit in ENR register
Moire Signal
The Moire output signal is available (instead of the
clamping signal) to reduce the screen Moire effect
and improve color transitions.
The CLAMPOUT pin is alternatively used to output
a Moire signal.
The output signal toggles at each HFBACK rising
edge. After each VFBACK falling edge, the value
of the Moire output is the opposite of the previous
one, independent of the number of HFBACK pulses during the VFBACK low level.
To use the Moire signal:
– Select the Moire signal:
Reset the BP0/BP1 bits in MCR register
– Enable the output signal:
CLMPEN bit in ENR register
Figure 39. Clamping Pulse (CLAMPOUT) Delay
HSYNCO
Maximum delay:
(Fixed delay of 10 to 30ns) + (fOSC/2) = approx. 110ns.
CLAMPOUT
Programmable clamping width: 0, 167ns, 333ns, 666ns
Figure 40. Moire Output (instead of Clamping Output)
VFBACK
HFBACK
Moire
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ST7275-2
SYNC PROCESSOR (SYNC) (Cont’d)
4.4.5.1 Blanking output signal
The Video Blanking function uses VSYNCO,
HFBACK, VFBACK as input signals and
BLANKOUT output as Video Blanking Output.
This output pin is a 5V open-drain output and can
be AND-wired with any external video blanking
signal.
Note: HFBACK, VFBACK, VSYNCO signals must
have positive polarity.
To use the video blanking signal:
– Program the polarity:
BLKINV bit in POLR register
– Enable the BLANKOUT output:
BLKEN bit in ENR register
Figure 41. Video Blanking Stage Simplified Schematic
HFBACK
To Edge detector (LATR)
To Edge detector (LATR)
BLKINV
VFBACK
BLANKOUT
R
S
BLKEN
VSYNCO
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ST7275-2
SYNC PROCESSOR (SYNC) (Cont’d)
4.4.6 Input Processing
4.4.6.1 Detecting Signal Presence
The Sync Processor provides two ways of checking input signal presence, by directly polling the
LATR Latch Register or using the Timer interrupts.
Polling check
Use the Latch Register (LATR), to detect the presence of HSYNCI, VSYNCI, CSYNCI, HFBACK
and VFBACK signals. These latched bits are set
when the falling edge of the corresponding signal
is detected. They are cleared by software.
Interrupts check
Due to the fact that VSYNCI is connected to Timer
Input Capture 1 and HSYNCI or CSYNCI is connected to Timer Input Capture 2, the Timer interrupts can be used to detect the presence of input
signals. Refer to the 16-bit Timer chapter for the
description of the Timer registers.
To use the interrupt method:
– Select Input Capture1 edge detection:
IEDG1 bit in the Timer CR1 register
– Select Input Capture 2 edge detection (must be
falling edge):
IEDG2 bit = 0 in the Timer CR2 register
– Enable Timer Input Capture interrupts:
ICIE bit in the Timer CR1 register.
– Select the Hsync and Vsync input signals:
HVSEL bit in the POLR register
– Enable the prescaler for HSYNCI or CSYNCI
signal:
PSCD bit in the CCR register.
– Select the normal mode:
LCV1/LCV0 bits in the CCR register.
Perform any of the following:
– Check for VSYNCI presence by monitoring interrupt requests from Timer ICAP1. When VSYNCI
is detected then either detect the VSYNCI polarity or check for HSYNCI presence.
– Check for HSYNCI presence by monitoring interrupt requests from Timer ICAP2. On detecting
HSYNCI, either detect its polarity or check if thecomposite sync on HSYNCI pin is detected or
check for CSYNCI presence.
– Check for CSYNCI presence by monitoring interrupt requests from Timer ICAP2.
66/131
4.4.6.2 Measuring Sync Period
To measure the sync period, the Sync processor
block uses the Timer Input Capture interrupts:
– ICAP1 connected to VSYNCI signal
– ICAP2 connected to HSYNCI/CSYNCI signal
with a 256 prescaler
Calculating the difference between two subsequent Input Captures (16-bit value) gives the period for 256xPH (horizontal period) and PV (vertical
period).
The period accuracy is one timer clock (500ns at 2
MHz), so that the tolerance is 500ns for PH and
256 * PH (PH accuracy =1.95ns).
Notes:
1) In case of composite sync, the HSYNCI period
measurement can be synchronized on the
VSYNCI pulse by setting and resetting the prescaler PSCD bit in the CCR register (for this
function, the ICAP2 detection must be selected
as falling edge).
This avoids errors in the period measurement
due to the Vsync pulse.
2) The Timer Interrupt request should be masked
during a write access to any of the Sync processor control registers.
Important Note:
Since the recognition of the video mode relies
on the accuracy of the measurements, it is highly recommended to implement a counter-style
algorithm which performs several consecutive
measurements before switching between
modes.
The purpose of this algorithm is to filter out any
glitches occurring on the video signals.
ST7275-2
SYNC PROCESSOR (SYNC) (Cont’d)
4.4.6.3 Detecting Signal Polarity
The Sync Processor provides two ways for checking input signal polarity by polling the latches or
using the 5-bit up/down counter.
Polling check
– HSYNCI polarity detection:
UPLAT/DWNLAT bits in LATR register
These bits are directly connected to the 5-bit
Up/Down counter.
UPLAT=1/ DOWNLAT=0 HSYNCI polarity<0
UPLAT=0/ DOWNLAT=1 HSYNCI polarity>0
– VSYNCI Polarity Detection
– VPOL bit (VSYNCO polarity) in POLR and
– VOP bit (VSYNCO polarity control) in MCR
The delay between VSYNCI polarity changes
and the VPOL bit typically toggles within 4
msecs. The polarity detector includes an integrator to filter possible incoming VSYNCI
glitches.
5-bit Up/Down Counter Check
for HSYNCI Polarity
This method involves the internal 5-bit up/down
counter.
The counter value (CV4-CV0 bits) is updated with
the 5-bit counter value at every detected edge on
the signal monitored.
It is incremented when the signal is high, otherwise it is decremented.
– Start the detection phase:
Initialize the 5-bit counter: write ’00000’ in the
CCR register (CV4-CV0 bits).
Select normal mode on falling edge:
LCV1/LCV0 = 0 in the CCR register.
– Software checks the counter value (CV4-CV0)
after an interrupt (with the signal internally connected or ICAP2) or by polling (timeout 150µs).
Positive polarity: The counter value < 1Fh.
Negative polarity: The counter value =1Fh on
the falling edge.
In case of a composite incoming signal, the software just has to check that the VSYNCO period
and polarity are stable.
4.4.6.4 Extracting VSYNCO from CSYNCI
In case of composite sync, the Vertical sync output
signal is extracted with the 5-bit up/down counter.
Initially, the width of an Horizontal Sync component pulse is automatically determined by hardware which defines a threshold for the 5-bit counter with a possible user-defined tolerance.
The circuit then monitors for any incoming period
greater than this previously captured value. This is
then processed as the VSYNCO signal.
To use the Vsync extractor, the following steps are
necessary:
– Detection of a composite sync signal:
When the UPLAT and DOWNLAT bits in LATR
register are set, a composite sync signal or a
HSYNCI polarity change is detected.
If these bits are stable during two subsequent
ICAP2 interrupt, the composite sync signal is
stable.
– Defining a threshold:
Select the normal mode (LCV1/LCV0=0 in the
CCR register).
Initialize the counter capture CV4-CV0 to 0.
This automatically measures the HSYNCI pulse
width. It defines a threshold in the CV4-CV0 bits
used by the 5-bit up/down counter.
It also allows to check the HSYNCI polarity (refer to the “5-bit Up/Down Counter Check” paragraph.
If a user-defined tolerance is to be added, then
an updated value should be written in the CCR
register (CV4-CV0 bits).
In a composite sync signal, Hsync and Vsync
always have the same polarity.
– Starting the VSYNCO hardware extraction
mode:
According to the Composite sync polarity, select the extraction mode (LCV1/LCV0 in CCR
register) and rewrite the counter if necessary.
Negative polarity: minimum threshold (00h)
Positive polarity: maximum threshold (1Fh)
Note:
The extracted VSYNCO signal always has negative polarity.
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ST7275-2
SYNC PROCESSOR (SYNC) (Cont’d)
4.4.6.5 Example of VSYNCO extraction for a
negative composite sync with serration pulses
Refer to Figure 42.
In extraction mode, the 5-bit comparator checks
the counter value with respect to the threshold.
When the incoming signal is high, the counter is increased, otherwise it is decreased.
When the counter reaches the threshold on its way
down, VSYNCO is asserted. During the vertical
blanking, the counter value is decreased down to a
programmable minimum, i.e. it does not underflow.
When the vertical period is finished, the counter
starts counting up and when the maximum is
reached, VSYNCO is negated. The extracted signal may be validated by software since it is input to
Timer ICAP1.
Serration pulses during vertical blanking can be filtered if the serration pulse widths are less than
8µs.
In the same way, positive composite sync signals
can be used by properly selecting the edge sensitivity in HSYNCI width measurement mode (LCV0
bit).
Figure 42. VSYNCO Extraction from a Composite Signal (negative polarity)
Serration pulses
Composite signal
Input
Max Pulse width: 8µs
1F-Threshold
Counter value:
1F=Max
8µs
Threshold
0=Min
VSYNCO
generated
VSYNCO Pulse
Max Delay: 8µs
or threshold
HSYNCO
VR01990
Figure 43. Obtaining the 11-bit Vertical Period (V11BITS)
7
0
CFGR
10
V11BITS
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7
0
VGENR
Q’2 Q’1 Q’0
0
Example:
VGENR=CCh, CFGR = 3h
V11bits=663h
ST7275-2
SYNC PROCESSOR (SYNC) (Cont’d)
4.4.7 Output Processing
4.4.7.1 Generating Free-Running Frequencies
The free-running frequencies function is used to:
– Drive the monitor when no or bad sync signals
are received.
– Stabilize the OSD screen when the monitor is
unlocked.
– Perform fast alignment for maintenance purposes.
Note: When free-running mode is active, the analyzer and corrector modes must be disabled.
– VCORDIS = 1, VEXT = 0 in CFGR and POLR
registers for vertical output measurement
– 2FHINH = 0 in CFGR register for horizontal
low level measurment
– VACQ, HACQ = 0, in CFGR register for analyzer mode
The Sync processor can generate any of the following output sync signals HSYNCO, VSYNCO,
CLAMPOUT, BLANKOUT.
To select the generation mode:
– Program the horizontal period using the HGENR
register.
– Program the vertical period using the VGENR (8
bits) and CFGR (3 bits) registers (2047 scan
lines per frame). Refer to Figure 43.
– Configure the following bits:
SYNOP = 0
HVGEN = 1
HACQ = 0
VACQ = 0
Horizontal Period
PH = Horizontal period = ((HGENR+1)/4) µs
Pulse width: 2 µs => HGENR min=8
Polarity: Positive
HGENR range: [8..255]
Vertical Period
PV = Vertical period = (PH * V11bits) µs
V11bits is a concatenation of VGENR and the Q’2
Q’1 Q’0 bits of the CFGR register.
Refer to Figure 43.
Pulse width: 4 * PH => min value= 8µs
Polarity: Positive
VGENR/CFGR range: [5..7FF]
Table 18. Typical values for generated HSYNC signals
HGENR (hex value)
H Period
HFREQ
Pulse Width
Duty Cycle
13
5 µs
200 kHz
2 µs
40%
1F
8 µs
125 kHz
2 µs
25%
3F
16 µs
62.5 kHz
2 µs
12.5%
7F
32 µs
31.25 kHz
2 µs
6.2%
FF
64 µs
15.6 kHz
2 µs
3.1%
Table 19. Typical values for generated VSYNC signals
HGENR
(hex value)
H Period
H Freq
V11bits
(hex value)
V Period
V Freq
Pulse width
13
5 µs
200 kHz
7FF (2047)
10.2 ms
97.7 Hz
20 µs
13
5 µs
200 kHz
400 (1024)
5.1 ms
195 Hz
20 µs
1F
8 µs
125 kHz
7FF (2047)
16.3 ms
61 Hz
32 µs
1F
8 µs
125 kHz
400 (1024)
8.2 ms
122 Hz
32 µs
3F
16 µs
62.5 kHz
7FF (2047)
32.6 ms
30.6 Hz
64 µs
3F
16 µs
62.5 kHz
400 (1024)
16.4 ms
60.9 Hz
64 µs
7F
32 µs
31.25 kHz
7FF (2047)
65.5 ms
15 Hz
128 µs
7F
32 µs
31.25 kHz
400 (1024)
32.8 ms
30 Hz
128 µs
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