STMICROELECTRONICS ST92185B3T1

ST92185B
16K/24K/32K ROM HCMOS MCU WITH
ON-SCREEN-DISPLAY
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Register File based 8/16 bit Core Architecture
with RUN, WFI, SLOW and HALT modes
0°C to +70°C operating temperature range
Up to 24 MHz. operation @ 5V±10%
Min. instruction cycle time: 165ns at 24 MHz.
16, 24 or 32 Kbytes ROM
256 bytes RAM of Register file (accumulators or
index registers)
256 bytes of on-chip static RAM
2 Kbytes of TDSRAM (Display Storage RAM)
28 fully programmable I/O pins
Serial Peripheral Interface
Flexible Clock controller for OSD, Data Slicer
and Core clocks running from a single low
frequency external crystal.
Enhanced display controller with:
– 26 rows of 40 characters or 24 rows of 80
characters
– Serial and Parallel attributes
– 10x10 dot matrix, 512 ROM characters, definable by user
– 4/3 and 16/9 supported in 50/60Hz and 100/
120 Hz mode
– Rounding, fringe, double width, double height,
scrolling, cursor, full background color, halfintensity color, translucency and half-tone
modes
Integrated Sync Extractor and Sync Controller
14-bit Voltage Synthesis for tuning reference
voltage
Up to 6 external interrupts plus one NonMaskable Interrupt
8 x 8-bit programmable PWM outputs with 5V
open-drain or push-pull capability
16-bit watchdog timer with 8-bit prescaler
One 16-bit standard timer with 8-bit prescaler
4-channel A/D converter; 5-bit guaranteed
October 2003
PSDIP56
PSDIP42
TQFP64
See end of Datasheet for ordering information
Rich instruction set and 14 addressing modes
Versatile
development
tools,
including
Assembler, Linker, C-compiler, Archiver,
Source Level Debugger and hardware
emulators with Real-Time Operating System
available from third parties
■ Pin-compatible EPROM and OTP devices
available (ST92E195D7D1, ST92T195D7B1)
■ Pin-compatible with the ST92195 family with
embedded teletext decoder
Device Summary
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Device
Program
Memory
TDSRAM
VPS/
WSS
ST92185B1
16K ROM
2K
No
ST92185B2
24K ROM
2K
No
ST92185B3
32K ROM
2K
No
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Table of Contents
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ST92185B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.1 ST9+ Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.2 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.3 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.4 TV Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.5 On Screen Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.6 Voltage Synthesis Tuning Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.7 PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.8 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.9 Standard Timer (STIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.10 Analog/Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
6
6
6
6
7
7
7
7
7
9
1.2.1 I/O Port Alternate Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.2.2 I/O Port Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.4 REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2 DEVICE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.1 CORE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2 MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.1 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.2 Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3 SYSTEM REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3.1 Central Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2 Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.3 Register Pointing Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.4 Paged Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.5 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.6 Stack Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
26
27
30
30
32
34
2.5 MEMORY MANAGEMENT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.6 ADDRESS SPACE EXTENSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.6.1 Addressing 16-Kbyte Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.6.2 Addressing 64-Kbyte Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.7 MMU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.7.1 DPR[3:0]: Data Page Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.2 CSR: Code Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.3 ISR: Interrupt Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.4 DMASR: DMA Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 MMU USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
39
39
39
41
2.8.1 Normal Program Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
....
2.8.3 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
41
41
42
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Table of Contents
3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2 INTERRUPT VECTORING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2.1 Divide by Zero trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2.2 Segment Paging During Interrupt Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3 INTERRUPT PRIORITY LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.4 PRIORITY LEVEL ARBITRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.4.1 Priority level 7 (Lowest) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 Maximum depth of nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.3 Simultaneous Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.4 Dynamic Priority Level Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 ARBITRATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
43
44
44
44
3.5.1 Concurrent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.5.2 Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.7 TOP LEVEL INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.8 ON-CHIP PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.9 INTERRUPT RESPONSE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.10 INTERRUPT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4 RESET AND CLOCK CONTROL UNIT (RCCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2 RESET / STOP MANAGER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.3 OSCILLATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.4 CLOCK CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.5 RESET CONTROL UNIT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5 TIMING AND CLOCK CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.1 FREQUENCY MULTIPLIERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.2 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.2.1 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.2 SPECIFIC PORT CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3 PORT CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.4 INPUT/OUTPUT BIT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.5 ALTERNATE FUNCTION ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.5.1 Pin Declared as I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.2 Pin Declared as an Alternate Function Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.3 Pin Declared as an Alternate Function Output . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6 I/O STATUS AFTER WFI, HALT AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
72
72
72
72
7 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.1 TIMER/WATCHDOG (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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7.1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.3 Watchdog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.4 WDT Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 STANDARD TIMER (STIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
75
77
78
80
7.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.3 Interrupt Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.4 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 DISPLAY STORAGE RAM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
81
82
82
83
84
7.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.3 Initialisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4 ON SCREEN DISPLAY (OSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
84
85
86
87
88
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.4.10
7.5 SYNC
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Programming the Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Vertical Scrolling Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Display Memory Mapping Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Font Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Font Mapping Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Application Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
7.5.1 H/V Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.2 Field Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.3 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.4 Sync Controller Working Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
137
137
137
137
140
142
7.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.2 Device-Specific Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.4 Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.5 Working With Other Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.6 I2C-bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.7 S-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.8 IM-bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7 A/D CONVERTER (A/D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
142
142
143
144
145
145
148
149
150
152
7.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
7.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
178
4/178
Table of Contents
7.7.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
7.7.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
7.8 VOLTAGE SYNTHESIS TUNING CONVERTER (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . 156
7.8.1
7.8.2
7.8.3
7.9 PWM
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
156
156
160
161
7.9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.9.2 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
161
162
166
172
172
9.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
9.2.1 Transfer Of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
10 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
5/178
ST92185B - GENERAL DESCRIPTION
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST92185B microcontroller is developed and
manufactured by STMicroelectronics using a proprietary n-well HCMOS process. Its performance
derives from the use of a flexible 256-register programming model for ultra-fast context switching
and real-time event response. The intelligent onchip peripherals offload the ST9 core from I/O and
data management processing tasks allowing critical application tasks to get the maximum use of
core resources. The ST92185B MCU supports low
power consumption and low voltage operation for
power-efficient and low-cost embedded systems.
1.1.1 ST9+ Core
The advanced Core consists of the Central
Processing Unit (CPU), the Register File and the
Interrupt controller.
The general-purpose registers can be used as accumulators, index registers, or address pointers.
Adjacent register pairs make up 16-bit registers for
addressing or 16-bit processing. Although the ST9
has an 8-bit ALU, the chip handles 16-bit operations, including arithmetic, loads/stores, and memory/register and memory/memory exchanges.
Two basic addressable spaces are available: the
Memory space and the Register File, which includes the control and status registers of the onchip peripherals.
1.1.2 Power Saving Modes
To optimize performance versus power consumption, a range of operating modes can be dynamically selected.
Run Mode. This is the full speed execution mode
with CPU and peripherals running at the maximum
clock speed delivered by the Phase Locked Loop
(PLL) of the Clock Control Unit (CCU).
Wait For Interrupt Mode. The Wait For Interrupt
(WFI) instruction suspends program execution until an interrupt request is acknowledged. During
WFI, the CPU clock is halted while the peripheral
6/178
and interrupt controller keep running at a frequency programmable via the CCU. In this mode, the
power consumption of the device can be reduced
by more than 95% (Low power WFI).
Halt Mode. When executing the HALT instruction,
and if the Watchdog is not enabled, the CPU and
its peripherals stop operating and the status of the
machine remains frozen (the clock is also
stopped). A reset is necessary to exit from Halt
mode.
1.1.3 I/O Ports
Up to 28 I/O lines are dedicated to digital Input/
Output. These lines are grouped into up to five I/O
Ports and can be configured on a bit basis under
software control to provide timing, status signals,
timer and output, analog inputs, external interrupts
and serial or parallel I/O.
1.1.4 TV Peripherals
A set of on-chip peripherals form a complete system for TV set and VCR applications:
– Voltage Synthesis
– Display RAM
– OSD
1.1.5 On Screen Display
The human interface is provided by the On Screen
Display module, this can produce up to 26 lines of
up to 80 characters from a ROM defined 512 character set. The character resolution is 10x10 dot.
Four character sizes are supported. Serial attributes allow the user to select foreground and
background colors, character size and fringe background. Parallel attributes can be used to select
additional foreground and background colors and
underline on a character by character basis.
Note: The OSD cell is common to all ST92x195
family devices. However, its capabilities are limited by a TDSRAM memory size of 2Kbytes on the
ST92185 family. Certain display modes using
more than 2Kbytes of memory are not available.
ST92185B - GENERAL DESCRIPTION
INTRODUCTION (Cont’d)
1.1.6 Voltage Synthesis Tuning Control
14-bit Voltage Synthesis using the PWM (Pulse
Width Modulation)/BRM (Bit Rate Modulation)
technique can be used to generate tuning voltages
for TV set applications. The tuning voltage is output on one of two separate output pins.
1.1.7 PWM Output
Control of TV settings can be made with up to
eight 8-bit PWM outputs, with a maximum frequency of 23,437Hz at 8-bit resolution (INTCLK = 12
MHz). Low resolutions with higher frequency operation can be programmed.
1.1.8 Serial Peripheral Interface (SPI)
The SPI bus is used to communicate with external
devices via the SPI, or I²C bus communication
standards. The SPI uses a single data line for data
input and output. A second line is used for a synchronous clock signal.
1.1.9 Standard Timer (STIM)
The ST92185B has one Standard Timer (STIM0)
that includes a programmable 16-bit down counter
and an associated 8-bit prescaler with Single and
Continuous counting modes.
1.1.10 Analog/Digital Converter (ADC)
In addition there is a 4-channel Analog to Digital
Converter with integral sample and hold, fast
5.75µs conversion time and 6-bit guaranteed resolution.
7/178
ST92185B - GENERAL DESCRIPTION
INTRODUCTION (Cont’d)
Figure 1. ST92185B Block Diagram
24/32 Kbytes
ROM
256 bytes
RAM
256 bytes
Register File
8/16-bit
CPU
NMI
INT[7:4]
INT2
INT0
MEMORY BUS
2 Kbytes
TDSRAM TRI
MMU
Interrupt
Management
ST9+ CORE
MCFM
P0[7:0]
I/O
PORT 2
6
P2[5:0]
I/O
PORT 3
4
P3[7:4]
I/O
PORT 4
8
P4[7:0]
I/O
PORT 5
2
P5[1:0]
AIN[4:1]
EXTRG
RCCU
16-BIT
TIMER/
WATCHDOG
SDO/SDI
SCK
8
ADC
SPI
TIMING AND
CLOCK CTRL
STOUT
STANDARD
TIMER
VSO[2:1]
VOLTAGE
SYNTHESIS
REGISTER BUS
OSCIN
OSCOUT
RESET
RESETO
I/O
PORT 0
VSYNC
HSYNC/CSYNC
CSO
SYNC
CONTROL
ON
SCREEN
DISPLAY
FREQ.
PXFM
MULTIP.
R/G/B/FB
TSLU
HT
PWM
D/A CONVERTER
All alternate functions (Italic characters) are mapped on Ports 0, 2, 3, 4 and 5
8/178
PWM[7:0]
ST92185B - GENERAL DESCRIPTION
1.2 PIN DESCRIPTION
RESET Reset (input, active low). The ST9+ is initialised by the Reset signal. With the deactivation
of RESET, program execution begins from the
Program memory location pointed to by the vector
contained in program memory locations 00h and
01h.
R/G/B Red/Green/Blue. Video color analog DAC
outputs.
FB Fast Blanking. Video analog DAC output.
VDD Main power supply voltage (5V±10%, digital)
VPP: On EPROM/OTP devices, V PP is the programming voltage pin. VPP should be tied to GND
in user mode.
MCFM Analog pin for the display pixel frequency
multiplier.
OSCIN, OSCOUT Oscillator (input and output).
These pins connect a parallel-resonant crystal
(24MHz maximum), or an external source to the
on-chip clock oscillator and buffer. OSCIN is the
input of the oscillator inverter and internal clock
generator; OSCOUT is the output of the oscillator
inverter.
VSYNC Vertical Sync. Vertical video synchronisation input to OSD. Positive or negative polarity.
HSYNC/CSYNC Horizontal/Composite sync. Horizontal or composite video synchronisation input to
OSD. Positive or negative polarity.
PXFM Analog pin for the Display Pixel Frequency
Multiplier
AVDD3 Analog V DD of PLL. This pin must be tied
to VDD externally.
GND Digital circuit ground.
AGND Analog circuit ground (must be tied externally to digital GND).
AVDD1, AVDD2 Analog power supplies (must be
tied externally to VDD).
CVBSO, JTDO, JTCK, JTMS Test pins: leave
floating.
TEST0 Test pin: must be tied to AVDD2.
JTRST0 Test pin: must be tied to GND.
Figure 2. 56-Pin Package Pin-Out
INT7/P2.0
RESET
P0.7
P0.6
P0.5
P0.4
P0.3
AIN4/P0.2
P0.1
P0.0
CSO/RESET0/P3.7
P3.6
P3.5
P3.4
B
G
R
FB
SDI/SDO/P5.1
SCK/INT2/P5.0
VDD
JTDO
N.C
VPP
AVDD3
TEST0
MCFM
JTCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
P2.1/INT5/AIN1
P2.2/INT0/AIN2
P2.3/INT6/VS01
P2.4/NMI
P2.5/AIN3/INT4/VS02
OSCIN
OSCOUT
P4.7/PWM7/EXTRG/STOUT
P4.6/PWM6
P4.5/PWM5
P4.4/PWM4
P4.3/PWM3/TSLU/HT
P4.2/PWM2
P4.1/PWM1
P4.0/PWM0
VSYNC
HSYNC/CSYNC
AVDD1
PXFM
JTRSTO
GND
AGND
N.C
N.C
JTMS
AVDD2
CVBSO
N.C
9/178
10/178
C13
4.7nF R3
10k
5.6k
C9
1N4148
D1
R1
10uH
22pF
100nF
C6
C11
10µF
L2
C4
RST
S1
1µF
C2
+5V
100nF
B
G
R
FB
P51
P50
P07
P06
P05
P04
P03
P02
P01
P00
P37
P36
P35
P34
P20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SDIP56
P2.0/INT7
RESETN
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2/AIN4
P0.1
P0.0
P3.7/RESET0/CSO
P3.6
P3.5
P3.4
B
G
R
FB
P5.1/SDI/SDO
P5.0/SCK/INT2
VDD
JTDO
N.C
N.C
AVDD3
TEST0
MCFM
JTCK
U1
P2.1/INT5/AIN1
P2.2/INT0/AIN2
P2.3/INT6/VS01
P2.4/NMI
P 2. 5 / A I N 3 / I NT 4 / V S0 2
OSCIN
OSCOUT
P4.7/PWM7/EXTRG/STOUT
P4.6/PWM6
P4.5/PWM5
P4.4/PWM4
P4.3/PWM3/TSLU
P4.2/PWM2
P4.1/PWM1
{92185}
P4.0/PWM0
VSYNC
HSYNC/CSYNC
AVDD1
PXFM
JTRSTO
GND
AGND
N.C
N.C
JTMS
AVDD2
CVBSO
N.C
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
P47
P46
P45
P44
P43
P42
P41
P40
P21
P22
P23
P24
P25
VSYNC
HSYNC
39pF
C12
39pF
4Mhz
C3
Y1
C1
5.6k
100nF
R2
C8
+5V
C10
22pF
C7
4.7nF
10µF
C5
100nF
10uH
L1
ST92185B - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
Figure 3. ST92185B Required External components (56-pin package)
ST92185B - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
Figure 4.. 42-Pin Package Pin-Out
INT7/P2.0
RESET
P0.7
P0.6
P0.5
P0.4
P0.3
AIN4/P0.2
P0.1
P0.0
CSO/RESET0/P3.7
P3.6
P3.5
P3.4
B
G
R
FB
SDI/SDO/P5.1
SCK/INT2/P5.0
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P2.1/INT5/AIN1
P2.2/INT0/AIN2
P2.3/INT6/VS01
P2.4/NMI
P2.5/AIN3/INT4/VS02
OSCIN
OSCOUT
P4.7/PWM7/EXTRG/STOUT
P4.6/PWM6
P4.5/PWM5
P4.4/PWM4
P4.3/PWM3/TSLU/HT
P4.2/PWM2
P4.1/PWM1
P4.0/PWM0
VSYNC
HSYNC/CSYNC
TEST0
PXFM
MCFM
GND
11/178
12/178
10µF
100nF
C6
RST
S1
1µF
C4
C2
+5V
1N4148
10k
10uH
D1
R1
L1
B
G
R
FB
P51
P50
P07
P06
P05
P04
P03
P02
P01
P00
P37
P36
P35
P34
P20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
SDIP42
P2.0/INT7
RESETN
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2/AIN4
P0.1
P0.0
P3.7/RESET0/CSO
P3.6
P3.5
P3.4
B
G
R
FB
P5.1/SDI/SDO/INT1
P5.0/SCK/INT2
VDD
U1
P2.1/INT5/AIN1
P2.2/INT0/AIN2
P2.3/INT6/VS01
P2.4/NMI
P2.5/AIN3/INT4/VS02
OSCIN
OSCOUT
P4.7/PWM7/EXTRG/STOUT
P4.6/PWM6
P4.5/PWM5
P4.4/PWM4
{92185}
P4.3/PWM3/TSLU
P4.2/PWM2
P4.1/PWM1
P4.0/PWM0
VSYNC
HSYNC
TEST0
PXFM
MCFM
GND
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P47
P46
P45
P44
P43
P42
P41
P40
P21
P22
P23
P24
P25
VSYNC
HSYNC
39pF
C7
4.7nF
C9
4.7nF
C5
22pF
22pF
5.6k
5.6k
C8
R2
R3
39pF
4Mhz
C3
Y1
C1
ST92185B - GENERAL DESCRIPTION
Figure 5. ST92185B Required External Components (42-pin package)
ST92185B - GENERAL DESCRIPTION
VDD
P0.3
P0.4
P0.5
P0.6
P0.7
RESET
P2.0/INT7
P2.1/INT5/AIN1
P2.2/INT0/AIN2
P2.3/INT6/VS01
P2.4/NMI
P2.5/AIN3/INT4/VS02
OSCIN
OSCOUT
VDD
Figure 6. 64-Pin Package Pin-Out
64
48
16
VPP
32
VSS
P4.7/PWM7/EXTRG/STOUT
P4.6/PWM6
P4.5/PWM5
P4.4/PWM4
P4.3/PWM3/TSLU/HT
P4.2/PWM2
P4.1/PWM1
P4.0/PWM0
VSYNC
HSYNC/CSYNC
AVDD1
PXFM
JTRST0
GND
N.C.
AVDD3
TEST0
MCFM
JTCK
N.C
CVBSO
AVDD2
JTMS
N.C
N.C
AGND
N.C.
1
N.C.
N.C.
N.C
GND
AIN4/P0.2
P0.1
P0.0
CSO/RESET0/P3.7
P3.6
P3.5
P3.4
B
G
R
FB
SDO/SDI/P5.1
INT2/SCK/P5.0
VDD
JTDO
Note: N.C = Not connected
13/178
ST92185B - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
P0[7:0], P2[5:0], P3[7:4], P4[7:0], P5[1:0]
I/O Port Lines (Input/Output, TTL or CMOS compatible).
28 lines grouped into I/O ports, bit programmable
as general purpose I/O or as Alternate functions
(see I/O section).
Important: Note that open-drain outputs are for
logic levels only and are not true open drain.
1.2.1 I/O Port Alternate Functions.
Each pin of the I/O ports of the ST92185B may assume software programmable Alternate Functions
(see Table 1).
Table 1. ST92185B I/O Port Alternate Function Summary
Port
Name
General
Purpose I/O
Pin No.
Alternate Functions
SDIP42
SDIP56
P0.0
10
10
P0.1
9
9
P0.2
8
8
P0.3
7
7
I/O
P0.4
6
6
I/O
P0.5
5
5
I/O
P0.6
4
4
I/O
P0.7
3
3
I/O
P2.0
1
1
P2.1
42
56
P2.2
41
55
40
54
39
53
P2.3
P2.4
P2.5
All ports useable
for general purpose I/O (input,
output or bidirectional)
38
52
I/O
I/O
AIN4
INT7
I
I
A/D Analog Data Input 4
External Interrupt 7
AIN1
I
A/D Analog Data Input 1
INT5
I
External Interrupt 5
INT0
I
External Interrupt 0
AIN2
I
A/D Analog Data Input 2
INT6
I
External Interrupt 6
VSO1
O
Voltage Synthesis Output 1
NMI
I
Non Maskable Interrupt Input
AIN3
I
A/D Analog Data Input 3
INT4
I
External Interrupt 4
VSO2
O
Voltage Synthesis Output 2
P3.4
14
14
I/O
P3.5
13
13
I/O
P3.6
12
12
I/O
RESET0
O
Internal Reset Output
CSO
O
Composite Sync output
P3.7
11
11
P4.0
28
42
PWM0
O
PWM Output 0
P4.1
29
43
PWM1
O
PWM Output 1
P4.2
30
44
PWM2
O
PWM Output 2
PWM3
O
PWM Output 3
O
Translucency Digital Output
P4.3
31
45
TSLU
HT
O
Half-tone Output
P4.4
32
46
PWM4
O
PWM Output 4
14/178
ST92185B - GENERAL DESCRIPTION
Port
Name
General
Purpose I/O
Pin No.
Alternate Functions
SDIP42
SDIP56
P4.5
33
47
PWM5
O
PWM Output 5
P4.6
34
48
PWM6
O
PWM Output 6
35
49
P4.7
P5.0
P5.1
All ports useable
for general purpose I/O (input,
output or bidirectional)
20
19
20
19
EXTRG
I
A/D Converter External Trigger Input
PWM7
O
PWM Output 7
STOUT
O
Standard Timer Output
INT2
I
External Interrupt 2
SCK
O
SPI Serial Clock
SDO
O
SPI Serial Data Out
SDI
I
SPI Serial Data In
15/178
ST92185B - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
1.2.2 I/O Port Styles
Pins
P0[7:0]
P2[5,4,3,2]
P2[1,0]
P3.7
P3[6,5,4]
P4[7:0]
P5[1:0]
Weak Pull-Up
no
no
no
yes
no
no
no
Port Style
Standard I/O
Standard I/O
Schmitt trigger
Standard I/O
Standard I/O
Standard I/O
Standard I/O
Reset Values
BID / OD / TTL
BID / OD / TTL
BID / OD / TTL
AF / PP / TTL
BID / OD / TTL
BID / OD / TTL
BID / OD / TTL
Legend:
AF= Alternate Function, BID = Bidirectional, OD = Open Drain
PP = Push-Pull, TTL = TTL Standard Input Levels
How to Read this Table
To configure the I/O ports, use the information in
this table and the Port Bit Configuration Table in
the I/O Ports Chapter on page 69.
Port Style= the hardware characteristics fixed for
each port line.
Inputs:
– If port style = Standard I/O, either TTL or CMOS
input level can be selected by software.
– If port style = Schmitt trigger, selecting CMOS or
TTL input by software has no effect, the input will
always be Schmitt Trigger.
Weak Pull-Up = This column indicates if a weak
pull-up is present or not.
– If WPU = yes, then the WPU can be enabled/disable by software
– If WPU = no, then enabling the WPU by software
has no effect
Alternate Functions (AF) = More than one AF
cannot be assigned to an external pin at the same
time:
An alternate function can be selected as follows.
AF Inputs:
– AF is selected implicitly by enabling the corresponding peripheral. Exception to this are ADC
analog inputs which must be explicitly selected
as AF by software.
AF Outputs or Bidirectional Lines:
– In the case of Outputs or I/Os, AF is selected
explicitly by software.
16/178
Example 1: ADC trigger digital input
AF: EXTRG, Port: P4.7, Port Style: Standard I/O.
Write the port configuration bits (for TTL level):
P4C2.7=1
P4C1.7=0
P4C0.7=1
Enable the ADC trigger by software as described
in the ADC chapter.
Example 2: PWM 0 output
AF: PWM0, Port: P4.0
Write the port configuration bits (for output pushpull):
P4C2.0=0
P4C1.0=1
P4C0.0=1
Example 3: ADC analog input
AF: AIN1, Port : P2.1, Port style: does not apply to
analog inputs
Write the port configuration bits:
P2C2.1=1
P2C1.1=1
P2C0.1=1
ST92185B - GENERAL DESCRIPTION
1.3 MEMORY MAP
Internal ROM
The ROM memory is mapped in a single continuous area starting at address 0000h in MMU segment 00h.
Size
Start
Address
End
Address
ST92185B1
16K
0000h
3FFFh
ST92185B2
24K
0000h
5FFFh
ST92185B3
32K
0000h
7FFFh
Device
Internal RAM, 256 bytes
The internal RAM is mapped in MMU segment
20h; from address FF00h to FFFFh.
Internal TDSRAM
The Internal TDSRAM is mapped starting at address 8000h in MMU segment 22h. It is a fully static memory.
Device
ST92185B1/B2/B3
Size
Start
Address
End
Address
2K
8000h
87FFh
Figure 7. ST92185B Memory Map
2287FFh
Reserved
2Kbytes
TDSRAM
228000h
SEGMENT 22h
64 Kbytes
Internal
RAM
256 bytes
22C000h
22BFFFh
228000h
227FFFh
Reserved
224000h
223FFFh
Reserved
SEGMENT 21h
64 Kbytes
22FFFFh
220000h
21FFFFh
PAGE 91 - 16 Kbytes
PAGE 90 - 16 Kbytes
PAGE 89 - 16 Kbytes
PAGE 88 - 16 Kbytes
Reserved
210000h
20FFFFh
20FFFFh
PAGE 83 - 16 Kbytes
20C000h
20BFFFh
20FF00h
SEGMENT 20h
64 Kbytes
Reserved
PAGE 82 - 16 Kbytes
208000h
207FFFh
PAGE 81 - 16 Kbytes
Reserved
204000h
203FFFh
PAGE 80 - 16 Kbytes
Reserved
200000h
00FFFFh
007FFFh
32 Kbytes
005FFFh
24 Kbytes
003FFFh SEGMENT 0
Internal ROM
64 Kbytes
24K
bytesROM
Internal
16K bytes
000000h
PAGE 3 - 16 Kbytes
00C000h
00BFFFh
Internal ROM
max. 64 Kbytes
PAGE 2 - 16 Kbytes
008000h
007FFFh
PAGE 1 - 16 Kbytes
004000h
003FFFh
PAGE 0 - 16 Kbytes
000000h
17/178
ST92185B - GENERAL DESCRIPTION
1.4 REGISTER MAP
The following pages contain a list of ST92185B
registers, grouped by peripheral or function.
Be very careful to correctly program both:
– The set of registers dedicated to a particular
function or peripheral.
– Registers common to other functions.
In particular, double-check that any registers with
“undefined” reset values have been correctly initialised.
Warning: Note that in the EIVR and each IVR register, all bits are significant. Take care when defining base vector addresses that entries in the Interrupt Vector table do not overlap.
Group F Pages Register Map
Register
R255
Page
0
2
Res.
Res.
3
11
21
32
33
35
38
39
55
59
62
Res.
VS
R254
Res.
Res
SPI
Port 3
R253
TCC
R252
WCR
RCCU
(PLL)
Res.
TDSRAM
TSU
R251
Res.
Res.
MMU
R250
WDT
R249
Res.
Res.
Port 2
R248
OSD
R247
Res.
PWM
R246
Res.
R245
R244
EXT
INT
Res.
R243
Port 5
Res
Res.
Res.
Res.
MMU
SYNC
R242
STIM
R241
Port 0
Res.
R240
18/178
Port 4
A/D
Res.
ST92185B - GENERAL DESCRIPTION
Table 2. Detailed Register Map
Group F
Page
Dec.
Block
Register
Name
Description
Reset
Value
Hex.
R224
P0DR
Port 0 Data Register
FF
Doc.
Page
I/O
R226
P2DR
Port 2 Data Register
FF
Port
R227
P3DR
Port 3 Data Register
FF
0:5
R228
P4DR
Port 4 Data Register
FF
R229
P5DR
Port 5 Data Register
FF
R230
CICR
Central Interrupt Control Register
87
53
R231
FLAGR
Flag Register
00
26
R232
RP0
Pointer 0 Register
xx
28
N/A
Core
INT
0
WDT
SPI
2
Reg.
No.
66
R233
RP1
Pointer 1 Register
xx
28
R234
PPR
Page Pointer Register
xx
30
R235
MODER
Mode Register
E0
30
R236
USPHR
User Stack Pointer High Register
xx
33
R237
USPLR
User Stack Pointer Low Register
xx
33
R238
SSPHR
System Stack Pointer High Reg.
xx
33
R239
SSPLR
System Stack Pointer Low Reg.
xx
33
R242
EITR
External Interrupt Trigger Register
00
53
R243
EIPR
External Interrupt Pending Reg.
00
54
R244
EIMR
External Interrupt Mask-bit Reg.
00
54
R245
EIPLR
External Interrupt Priority Level Reg.
FF
54
R246
EIVR
External Interrupt Vector Register
x6
55
R247
NICR
Nested Interrupt Control
00
55
R248
WDTHR
Watchdog Timer High Register
FF
78
R249
WDTLR
Watchdog Timer Low Register
FF
78
R250
WDTPR
Watchdog Timer Prescaler Reg.
FF
78
R251
WDTCR
Watchdog Timer Control Register
12
78
R252
WCR
Wait Control Register
7F
79
R253
SPIDR
SPI Data Register
xx
150
R254
SPICR
SPI Control Register
00
150
I/O
R240
P0C0
Port 0 Configuration Register 0
00
Port
R241
P0C1
Port 0 Configuration Register 1
00
0
R242
P0C2
Port 0 Configuration Register 2
00
I/O
R248
P2C0
Port 2 Configuration Register 0
00
Port
R249
P2C1
Port 2 Configuration Register 1
00
2
R250
P2C2
Port 2 Configuration Register 2
00
I/O
R252
P3C0
Port 3 Configuration Register 0
00
Port
R253
P3C1
Port 3 Configuration Register 1
00
3
R254
P3C2
Port 3 Configuration Register 2
00
66
19/178
ST92185B - GENERAL DESCRIPTION
Group F
Page
Dec.
3
11
Block
Reg.
No.
Register
Name
Description
Reset
Value
Hex.
I/O
R240
P4C0
Port 4 Configuration Register 0
00
Port
R241
P4C1
Port 4 Configuration Register 1
00
4
R242
P4C2
Port 4 Configuration Register 2
00
I/O
R244
P5C0
Port 5 Configuration Register 0
00
Port
R245
P5C1
Port 5 Configuration Register 1
00
5
R246
P5C2
Port 5 Configuration Register 2
00
R240
STH
Counter High Byte Register
FF
83
STIM
MMU
21
Ext.Mem.
32
OSD
33
35
SYNC
38
TDSRAM
20/178
Doc.
Page
66
R241
STL
Counter Low Byte Register
FF
83
R242
STP
Standard Timer Prescaler Register
FF
83
R243
STC
Standard Timer Control Register
14
83
R240
DPR0
Data Page Register 0
xx
38
R241
DPR1
Data Page Register 1
xx
38
R242
DPR2
Data Page Register 2
xx
38
R243
DPR3
Data Page Register 3
xx
38
R244
CSR
Code Segment Register
00
39
R248
ISR
Interrupt Segment Register
xx
39
R249
DMASR
DMA Segment Register
xx
39
R246
EMR2
External Memory Register 2
0F
56
R240
HBLANKR
Horizontal Blank Register
03
121
R241
HPOSR
Horizontal Position Register
03
121
R242
VPOSR
Vertical Position Register
00
121
R243
FSCCR
Full Screen Color Control Register
00
122
R244
HSCR
Header & Status Control Register
2A
123
R245
NCSR
National Character Set Control Register
00
124
R246
CHPOSR
Cursor Horizontal Position Register
00
125
R247
CVPOSR
Cursor Vertical Position Register
00
125
R248
SCLR
Scrolling Control Low Register
00
126
R249
SCHR
Scrolling Control High Register
00
127
R250
DCM0R
Display Control Mode 0 Register
00
129
R251
DCM1R
Display Control Mode 1 Register
00
130
R252
TDPR
TDSRAM Pointer Register
00
130
R253
DE0R
Display Enable 0 Control Register
FF
131
R254
DE1R
Display Enable 1 Control Register
FF
131
R255
DE2R
Display Enable 2 Control Register
xF
131
R240
DCR
Default Color Register
70
132
R241
CAPVR
Cursor Absolute Vertical Position Register
00
132
R246
TDPPR
TDSRAM Page Pointer Register
x0
132
R247
TDHSPR
TDSRAM Header/Status Pointer Register
x0
132
R242
SCCS0R
Sync Controller Control and Status Register 0
00
140
R243
SCCS1R
Sync Controller Control and Status Register 1
00
141
R252
CONFIG
TDSRAM Interface Configuration Register
02
87
ST92185B - GENERAL DESCRIPTION
Group F
Page
Dec.
39
55
Block
TCC
RCCU
PWM
59
VS
62
ADC
Reg.
No.
Register
Name
R251
PXCCR
R252
SLCCR
Reset
Value
Hex.
Doc.
Page
PLL Clock Control Register
00
66
Slicer Clock Control Register
00
66
Description
R253
MCCR
Main Clock Control Register
00
65
R254
SKCCR
Skew Clock Control Register
00
65
R251
PCONF
PLL Configuration Register
07
61
R254
SDRATH
Clock Slow Down Unit Ratio Register
2x,4x
or 00
61
R240
CM0
Compare Register 0
00
163
R241
CM1
Compare Register 1
00
163
R242
CM2
Compare Register 2
00
163
R243
CM3
Compare Register 3
00
163
R244
CM4
Compare Register 4
00
163
R245
CM5
Compare Register 5
00
163
R246
CM6
Compare Register 6
00
163
R247
CM7
Compare Register 7
00
163
R248
ACR
Autoclear Register
FF
164
R249
CCR
Counter Register
00
164
R250
PCTL
Prescaler and Control Register
0C
164
R251
OCPL
Output Complement Register
00
165
R252
OER
Output Enable Register
00
165
R254
VSDR1
Data and Control Register 1
00
160
R255
VSDR2
Data Register 2
00
160
R240
ADDTR
Channel i Data Register
xx
155
R241
ADCLR
Control Logic Register
00
154
R242
ADINT
AD Interrupt Register
01
155
Note: xx denotes a byte with an undefined value, however some of the bits may have defined values. Refer to register
description for details.
21/178
ST92185B - DEVICE ARCHITECTURE
2 DEVICE ARCHITECTURE
2.1 CORE ARCHITECTURE
The ST9 Core or Central Processing Unit (CPU)
features a highly optimised instruction set, capable
of handling bit, byte (8-bit) and word (16-bit) data,
as well as BCD and Boolean formats; 14 addressing modes are available.
Four independent buses are controlled by the
Core: a 16-bit Memory bus, an 8-bit Register data
bus, an 8-bit Register address bus and a 6-bit Interrupt/DMA bus which connects the interrupt and
DMA controllers in the on-chip peripherals with the
Core.
This multiple bus architecture affords a high degree of pipelining and parallel operation, thus making the ST9 family devices highly efficient, both for
numerical calculation, data handling and with regard to communication with on-chip peripheral resources.
which hold data and control bits for the on-chip
peripherals and I/Os.
– A single linear memory space accommodating
both program and data. All of the physically separate memory areas, including the internal ROM,
internal RAM and external memory are mapped
in this common address space. The total addressable memory space of 4 Mbytes (limited by
the size of on-chip memory and the number of
external address pins) is arranged as 64 segments of 64 Kbytes. Each segment is further
subdivided into four pages of 16 Kbytes, as illustrated in Figure 1. A Memory Management Unit
uses a set of pointer registers to address a 22-bit
memory field using 16-bit address-based instructions.
2.2.1 Register File
The Register File consists of (see Figure 2):
2.2 MEMORY SPACES
– 224 general purpose registers (Group 0 to D,
There are two separate memory spaces:
registers R0 to R223)
– The Register File, which comprises 240 8-bit
– 6 system registers in the System Group (Group
registers, arranged as 15 groups (Group 0 to E),
E, registers R224 to R239)
each containing sixteen 8-bit registers plus up to
– Up to 64 pages, depending on device configura64 pages of 16 registers mapped in Group F,
tion, each containing up to 16 registers, mapped
to Group F (R240 to R255), see Figure 3.
Figure 8. Single Program and Data Memory Address Space
Data
16K Pages
Address
255
254
253
252
251
250
249
248
247
3FFFFFh
3F0000h
3EFFFFh
3E0000h
Code
64K Segments
63
62
up to 4 Mbytes
21FFFFh
210000h
20FFFFh
02FFFFh
020000h
01FFFFh
010000h
00FFFFh
000000h
22/178
Reserved
135
134
133
132
11
10
9
8
7
6
5
4
3
2
1
0
33
2
1
0
ST92185B - DEVICE ARCHITECTURE
MEMORY SPACES (Cont’d)
Figure 9. Register Groups
Figure 10. Page Pointer for Group F mapping
PAGE 63
UP TO
64 PAGES
255
240 F PAGED REGISTERS
239
E SYSTEM REGISTERS
224
223 D
PAGE 5
R255
PAGE 0
C
B
A
R240
9
R234
8
224
GENERAL
PURPOSE
REGISTERS
7
6
PAGE POINTER
R224
5
4
3
2
1
0
15
0
0
VA00432
R0
VA00433
Figure 11. Addressing the Register File
REGISTER FILE
255
240 F PAGED REGISTERS
239 E SYSTEM REGISTERS
224
223 D
GROUP D
C
R195
(R0C3h)
B
R207
A
9
(1100) (0011)
8
GROUP C
7
6
R195
5
4
R192
3
GROUP B
2
1
0
0
15
0
VR000118
23/178
ST92185B - DEVICE ARCHITECTURE
MEMORY SPACES (Cont’d)
2.2.2 Register Addressing
Register File registers, including Group F paged
registers (but excluding Group D), may be addressed explicitly by means of a decimal, hexadecimal or binary address; thus R231, RE7h and
R11100111b represent the same register (see
Figure 4). Group D registers can only be addressed in Working Register mode.
Note that an upper case “R” is used to denote this
direct addressing mode.
Working Registers
Certain types of instruction require that registers
be specified in the form “rx”, where x is in the
range 0 to 15: these are known as Working Registers.
Note that a lower case “r” is used to denote this indirect addressing mode.
Two addressing schemes are available: a single
group of 16 working registers, or two separately
mapped groups, each consisting of 8 working registers. These groups may be mapped starting at
any 8 or 16 byte boundary in the register file by
means of dedicated pointer registers. This technique is described in more detail in Section 1.3.3,
and illustrated in Figure 5 and in Figure 6.
System Registers
The 16 registers in Group E (R224 to R239) are
System registers and may be addressed using any
of the register addressing modes. These registers
are described in greater detail in Section 1.3.
Paged Registers
Up to 64 pages, each containing 16 registers, may
be mapped to Group F. These are addressed using any register addressing mode, in conjunction
with the Page Pointer register, R234, which is one
of the System registers. This register selects the
page to be mapped to Group F and, once set,
does not need to be changed if two or more registers on the same page are to be addressed in succession.
24/178
Therefore if the Page Pointer, R234, is set to 5, the
instructions:
spp #5
ld R242, r4
will load the contents of working register r4 into the
third register of page 5 (R242).
These paged registers hold data and control information relating to the on-chip peripherals, each
peripheral always being associated with the same
pages and registers to ensure code compatibility
between ST9 devices. The number of these registers therefore depends on the peripherals which
are present in the specific ST9 family device. In
other words, pages only exist if the relevant peripheral is present.
Table 3. Register File Organization
Hex.
Address
Decimal
Address
Function
Register
File Group
F0-FF
240-255
Paged
Registers
Group F
E0-EF
224-239
System
Registers
Group E
D0-DF
208-223
Group D
C0-CF
192-207
Group C
B0-BF
176-191
Group B
A0-AF
160-175
Group A
90-9F
144-159
Group 9
80-8F
128-143
70-7F
112-127
60-6F
96-111
50-5F
80-95
Group 5
40-4F
64-79
Group 4
30-3F
48-63
Group 3
20-2F
32-47
Group 2
10-1F
16-31
Group 1
00-0F
00-15
Group 0
Group 8
General
Purpose
Registers
Group 7
Group 6
ST92185B - DEVICE ARCHITECTURE
2.3 SYSTEM REGISTERS
The System registers are listed in Table 2 System
Registers (Group E). They are used to perform all
the important system settings. Their purpose is described in the following pages. Refer to the chapter
dealing with I/O for a description of the PORT[5:0]
Data registers.
Table 4. System Registers (Group E)
R239 (EFh)
SSPLR
R238 (EEh)
SSPHR
R237 (EDh)
USPLR
R236 (ECh)
USPHR
R235 (EBh)
MODE REGISTER
R234 (EAh)
PAGE POINTER REGISTER
R233 (E9h)
REGISTER POINTER 1
R232 (E8h)
REGISTER POINTER 0
R231 (E7h)
FLAG REGISTER
R230 (E6h)
CENTRAL INT. CNTL REG
R229 (E5h)
PORT5 DATA REG.
R228 (E4h)
PORT4 DATA REG.
R227 (E3h)
PORT3 DATA REG.
R226 (E2h)
PORT2 DATA REG.
R225 (E1h)
PORT1 DATA REG.
R224 (E0h)
PORT0 DATA REG.
GCEN TLIP
0
TLI
IEN
IAM
Bit 6 = TLIP: Top Level Interrupt Pending.
This bit is set by hardware when a Top Level Interrupt Request is recognized. This bit can also be
set by software to simulate a Top Level Interrupt
Request.
0: No Top Level Interrupt pending
1: Top Level Interrupt pending
Bit 5 = TLI: Top Level Interrupt bit.
0: Top Level Interrupt is acknowledged depending
on the TLNM bit in the NICR Register.
1: Top Level Interrupt is acknowledged depending
on the IEN and TLNM bits in the NICR Register
(described in the Interrupt chapter).
2.3.1 Central Interrupt Control Register
Please refer to the ”INTERRUPT” chapter for a detailed description of the ST9 interrupt philosophy.
CENTRAL INTERRUPT CONTROL REGISTER
(CICR)
R230 - Read/Write
Register Group: E (System)
Reset Value: 1000 0111 (87h)
7
Note: If an MFT is not included in the ST9 device,
then this bit has no effect.
CPL2 CPL1 CPL0
Bit 7 = GCEN: Global Counter Enable.
This bit is the Global Counter Enable of the Multifunction Timers. The GCEN bit is ANDed with the
CE bit in the TCR Register (only in devices featuring the MFT Multifunction Timer) in order to enable
the Timers when both bits are set. This bit is set after the Reset cycle.
Bit 4 = IEN: Interrupt Enable .
This bit is cleared by interrupt acknowledgement,
and set by interrupt return (iret). IEN is modified
implicitly by iret, ei and di instructions or by an
interrupt acknowledge cycle. It can also be explicitly written by the user, but only when no interrupt
is pending. Therefore, the user should execute a
di instruction (or guarantee by other means that
no interrupt request can arrive) before any write
operation to the CICR register.
0: Disable all interrupts except Top Level Interrupt.
1: Enable Interrupts
Bit 3 = IAM: Interrupt Arbitration Mode.
This bit is set and cleared by software to select the
arbitration mode.
0: Concurrent Mode
1: Nested Mode.
Bits 2:0 = CPL[2:0]: Current Priority Level.
These three bits record the priority level of the routine currently running (i.e. the Current Priority Level, CPL). The highest priority level is represented
by 000, and the lowest by 111. The CPL bits can
be set by hardware or software and provide the
reference according to which subsequent interrupts are either left pending or are allowed to interrupt the current interrupt service routine. When the
current interrupt is replaced by one of a higher priority, the current priority value is automatically
stored until required in the NICR register.
25/178
ST92185B - DEVICE ARCHITECTURE
SYSTEM REGISTERS (Cont’d)
2.3.2 Flag Register
The Flag Register contains 8 flags which indicate
the CPU status. During an interrupt, the flag register is automatically stored in the system stack area
and recalled at the end of the interrupt service routine, thus returning the CPU to its original status.
This occurs for all interrupts and, when operating
in nested mode, up to seven versions of the flag
register may be stored.
FLAG REGISTER (FLAGR)
R231- Read/Write
Register Group: E (System)
Reset value: 0000 0000 (00h)
7
C
0
Z
S
V
DA
H
-
DP
Bit 7 = C: Carry Flag .
The carry flag is affected by:
Addition (add, addw, adc, adcw),
Subtraction (sub, subw, sbc, sbcw),
Compare (cp, cpw),
Shift Right Arithmetic (sra, sraw),
Shift Left Arithmetic (sla, slaw),
Swap Nibbles (swap),
Rotate (rrc, rrcw, rlc, rlcw, ror,
rol),
Decimal Adjust (da),
Multiply and Divide (mul, div, divws).
When set, it generally indicates a carry out of the
most significant bit position of the register being
used as an accumulator (bit 7 for byte operations
and bit 15 for word operations).
The carry flag can be set by the Set Carry Flag
(scf) instruction, cleared by the Reset Carry Flag
(rcf) instruction, and complemented by the Complement Carry Flag (ccf) instruction.
Bit 6 = Z: Zero Flag. The Zero flag is affected by:
Addition (add, addw, adc, adcw),
Subtraction (sub, subw, sbc, sbcw),
Compare (cp, cpw),
Shift Right Arithmetic (sra, sraw),
Shift Left Arithmetic (sla, slaw),
Swap Nibbles (swap),
Rotate (rrc, rrcw, rlc, rlcw, ror,
rol),
Decimal Adjust (da),
Multiply and Divide (mul, div, divws),
Logical (and, andw, or, orw, xor,
xorw, cpl),
Increment and Decrement (inc, incw, dec,
26/178
decw),
Test (tm, tmw, tcm, tcmw, btset).
In most cases, the Zero flag is set when the contents
of the register being used as an accumulator become zero, following one of the above operations.
Bit 5 = S: Sign Flag.
The Sign flag is affected by the same instructions
as the Zero flag.
The Sign flag is set when bit 7 (for a byte operation) or bit 15 (for a word operation) of the register
used as an accumulator is one.
Bit 4 = V: Overflow Flag .
The Overflow flag is affected by the same instructions as the Zero and Sign flags.
When set, the Overflow flag indicates that a two'scomplement number, in a result register, is in error, since it has exceeded the largest (or is less
than the smallest), number that can be represented in two’s-complement notation.
Bit 3 = DA: Decimal Adjust Flag.
The DA flag is used for BCD arithmetic. Since the
algorithm for correcting BCD operations is different for addition and subtraction, this flag is used to
specify which type of instruction was executed
last, so that the subsequent Decimal Adjust (da)
operation can perform its function correctly. The
DA flag cannot normally be used as a test condition by the programmer.
Bit 2 = H: Half Carry Flag.
The H flag indicates a carry out of (or a borrow into) bit 3, as the result of adding or subtracting two
8-bit bytes, each representing two BCD digits. The
H flag is used by the Decimal Adjust (da) instruction to convert the binary result of a previous addition or subtraction into the correct BCD result. Like
the DA flag, this flag is not normally accessed by
the user.
Bit 1 = Reserved bit (must be 0).
Bit 0 = DP: Data/Program Memory Flag .
This bit indicates the memory area addressed. Its
value is affected by the Set Data Memory (sdm)
and Set Program Memory (spm) instructions. Refer to the Memory Management Unit for further details.
ST92185B - DEVICE ARCHITECTURE
SYSTEM REGISTERS (Cont’d)
If the bit is set, data is accessed using the Data
Pointers (DPRs registers), otherwise it is pointed
to by the Code Pointer (CSR register); therefore,
the user initialization routine must include a Sdm
instruction. Note that code is always pointed to by
the Code Pointer (CSR).
Note: In the current ST9 devices, the DP flag is
only for compatibility with software developed for
the first generation of ST9 devices. With the single
memory addressing space, its use is now redundant. It must be kept to 1 with a Sdm instruction at
the beginning of the program to ensure a normal
use of the different memory pointers.
2.3.3 Register Pointing Techniques
Two registers within the System register group,
are used as pointers to the working registers. Register Pointer 0 (R232) may be used on its own as a
single pointer to a 16-register working space, or in
conjunction with Register Pointer 1 (R233), to
point to two separate 8-register spaces.
For the purpose of register pointing, the 16 register
groups of the register file are subdivided into 32 8register blocks. The values specified with the Set
Register Pointer instructions refer to the blocks to
be pointed to in twin 8-register mode, or to the lower 8-register block location in single 16-register
mode.
The Set Register Pointer instructions srp, srp0
and srp1 automatically inform the CPU whether
the Register File is to operate in single 16-register
mode or in twin 8-register mode. The srp instruction selects the single 16-register group mode and
specifies the location of the lower 8-register block,
while the srp0 and srp1 instructions automatically select the twin 8-register group mode and specify the locations of each 8-register block.
There is no limitation on the order or position of
these register groups, other than that they must
start on an 8-register boundary in twin 8-register
mode, or on a 16-register boundary in single 16register mode.
The block number should always be an even
number in single 16-register mode. The 16-register group will always start at the block whose
number is the nearest even number equal to or
lower than the block number specified in the srp
instruction. Avoid using odd block numbers, since
this can be confusing if twin mode is subsequently
selected.
Thus:
srp #3 will be interpreted as srp #2 and will allow using R16 ..R31 as r0 .. r15.
In single 16-register mode, the working registers
are referred to as r0 to r15. In twin 8-register
mode, registers r0 to r7 are in the block pointed
to by RP0 (by means of the srp0 instruction),
while registers r8 to r15 are in the block pointed
to by RP1 (by means of the srp1 instruction).
Caution: Group D registers can only be accessed
as working registers using the Register Pointers,
or by means of the Stack Pointers. They cannot be
addressed explicitly in the form “Rxxx”.
27/178
ST92185B - DEVICE ARCHITECTURE
SYSTEM REGISTERS (Cont’d)
POINTER 0 REGISTER (RP0)
R232 - Read/Write
Register Group: E (System)
Reset Value: xxxx xx00 (xxh)
POINTER 1 REGISTER (RP1)
R233 - Read/Write
Register Group: E (System)
Reset Value: xxxx xx00 (xxh)
7
RG4
RG3
RG2
RG1
RG0
RPS
0
0
7
0
RG4
Bits 7:3 = RG[4:0]: Register Group number.
These bits contain the number (in the range 0 to
31) of the register block specified in the srp0 or
srp instructions. In single 16-register mode the
number indicates the lower of the two 8-register
blocks to which the 16 working registers are to be
mapped, while in twin 8-register mode it indicates
the 8-register block to which r0 to r7 are to be
mapped.
Bit 2 = RPS: Register Pointer Selector.
This bit is set by the instructions srp0 and srp1 to
indicate that the twin register pointing mode is selected. The bit is reset by the srp instruction to indicate that the single register pointing mode is selected.
0: Single register pointing mode
1: Twin register pointing mode
0
RG3
RG2
RG1
RG0
RPS
0
0
This register is only used in the twin register pointing mode. When using the single register pointing
mode, or when using only one of the twin register
groups, the RP1 register must be considered as
RESERVED and may NOT be used as a general
purpose register.
Bits 7:3 = RG[4:0]: Register Group number.
These bits contain the number (in the range 0 to
31) of the 8-register block specified in the srp1 instruction, to which r8 to r15 are to be mapped.
Bit 2 = RPS: Register Pointer Selector.
This bit is set by the srp0 and srp1 instructions to
indicate that the twin register pointing mode is selected. The bit is reset by the srp instruction to indicate that the single register pointing mode is selected.
0: Single register pointing mode
1: Twin register pointing mode
Bits 1:0: Reserved. Forced by hardware to zero.
Bits 1:0: Reserved. Forced by hardware to zero.
28/178
ST92185B - DEVICE ARCHITECTURE
SYSTEM REGISTERS (Cont’d)
Figure 12. Pointing to a single group of 16
registers
REGISTER
GROUP
BLOCK
NUMBER
REGISTER
GROUP
BLOCK
NUMBER
Figure 13. Pointing to two groups of 8 registers
REGISTER
FILE
REGISTER
FILE
31
REGISTER
POINTER 0
&
REGISTER
POINTER 1
F
31
REGISTER
POINTER 0
set by:
F
30
srp #2
29
instruction
E
30
29
E
set by:
28
srp0 #2
28
&
points to:
27
D
27
D
srp1 #7
instructions
26
point to:
26
25
25
addressed by
BLOCK 7
9
4
9
8
4
r15
8
7
GROUP 3
3
7
r8
6
3
6
5
2
5
4
2
4
3
r15
1
3
1
GROUP 1
r7
2
r0
2
r0
1
0
addressed by
BLOCK 2
1
GROUP 1
addressed by
BLOCK 2
0
0
0
29/178
ST92185B - DEVICE ARCHITECTURE
SYSTEM REGISTERS (Cont’d)
2.3.4 Paged Registers
Up to 64 pages, each containing 16 registers, may
be mapped to Group F. These paged registers
hold data and control information relating to the
on-chip peripherals, each peripheral always being
associated with the same pages and registers to
ensure code compatibility between ST9 devices.
The number of these registers depends on the peripherals present in the specific ST9 device. In other words, pages only exist if the relevant peripheral is present.
The paged registers are addressed using the normal register addressing modes, in conjunction with
the Page Pointer register, R234, which is one of
the System registers. This register selects the
page to be mapped to Group F and, once set,
does not need to be changed if two or more registers on the same page are to be addressed in succession.
Thus the instructions:
spp #5
ld R242, r4
will load the contents of working register r4 into the
third register of page 5 (R242).
Warning: During an interrupt, the PPR register is
not saved automatically in the stack. If needed, it
should be saved/restored by the user within the interrupt routine.
PAGE POINTER REGISTER (PPR)
R234 - Read/Write
Register Group: E (System)
Reset value: xxxx xx00 (xxh)
7
PP5
0
PP4
PP3
PP2
PP1
PP0
0
0
Bits 7:2 = PP[5:0]: Page Pointer.
These bits contain the number (in the range 0 to
63) of the page specified in the spp instruction.
Once the page pointer has been set, there is no
30/178
need to refresh it unless a different page is required.
Bits 1:0: Reserved. Forced by hardware to 0.
2.3.5 Mode Register
The Mode Register allows control of the following
operating parameters:
– Selection of internal or external System and User
Stack areas,
– Management of the clock frequency,
– Enabling of Bus request and Wait signals when
interfacing to external memory.
MODE REGISTER (MODER)
R235 - Read/Write
Register Group: E (System)
Reset value: 1110 0000 (E0h)
7
SSP
0
USP
DIV2
PRS2 PRS1
PRS0 BRQEN HIMP
Bit 7 = SSP: System Stack Pointer.
This bit selects an internal or external System
Stack area.
0: External system stack area, in memory space.
1: Internal system stack area, in the Register File
(reset state).
Bit 6 = USP: User Stack Pointer.
This bit selects an internal or external User Stack
area.
0: External user stack area, in memory space.
1: Internal user stack area, in the Register File (reset state).
Bit 5 = DIV2: Crystal Oscillator Clock Divided by 2.
This bit controls the divide-by-2 circuit operating
on the crystal oscillator clock (CLOCK1).
0: Clock divided by 1
1: Clock divided by 2
ST92185B - DEVICE ARCHITECTURE
Bits 4:2 = PRS[2:0]: CPUCLK Prescaler.
These bits load the prescaler division factor for the
internal clock (INTCLK). The prescaler factor selects the internal clock frequency, which can be divided by a factor from 1 to 8. Refer to the Reset
and Clock Control chapter for further information.
Bit 1 = BRQEN: Bus Request Enable.
0: External Memory Bus Request disabled
1: External Memory Bus Request enabled on
BREQ pin (where available).
Note: Disregard this bit if BREQ pin is not available.
Bit 0 = HIMP: High Impedance Enable.
When any of Ports 0, 1, 2 or 6 depending on device configuration, are programmed as Address
and Data lines to interface external Memory, these
lines and the Memory interface control lines (AS,
DS, R/W) can be forced into the High Impedance
31/178
ST92185B - DEVICE ARCHITECTURE
SYSTEM REGISTERS (Cont’d)
state by setting the HIMP bit. When this bit is reset,
it has no effect.
Setting the HIMP bit is recommended for noise reduction when only internal Memory is used.
If Port 1 and/or 2 are declared as an address AND
as an I/O port (for example: P10... P14 = Address,
and P15... P17 = I/O), the HIMP bit has no effect
on the I/O lines.
2.3.6 Stack Pointers
Two separate, double-register stack pointers are
available: the System Stack Pointer and the User
Stack Pointer, both of which can address registers
or memory.
The stack pointers point to the “bottom” of the
stacks which are filled using the push commands
and emptied using the pop commands. The stack
pointer is automatically pre-decremented when
data is “pushed” in and post-incremented when
data is “popped” out.
The push and pop commands used to manage the
System Stack may be addressed to the User
Stack by adding the suffix “u”. To use a stack instruction for a word, the suffix “w” is added. These
suffixes may be combined.
When bytes (or words) are “popped” out from a
stack, the contents of the stack locations are unchanged until fresh data is loaded. Thus, when
data is “popped” from a stack area, the stack contents remain unchanged.
Note: Instructions such as: pushuw RR236 or
pushw RR238, as well as the corresponding
pop instructions (where R236 & R237, and R238
& R239 are themselves the user and system stack
pointers respectively), must not be used, since the
pointer values are themselves automatically
changed by the push or pop instruction, thus corrupting their value.
System Stack
The System Stack is used for the temporary storage of system and/or control data, such as the
Flag register and the Program counter.
The following automatically push data onto the
System Stack:
– Interrupts
When entering an interrupt, the PC and the Flag
Register are pushed onto the System Stack. If the
ENCSR bit in the EMR2 register is set, then the
32/178
Code Segment Register is also pushed onto the
System Stack.
– Subroutine Calls
When a call instruction is executed, only the PC
is pushed onto stack, whereas when a calls instruction (call segment) is executed, both the PC
and the Code Segment Register are pushed onto
the System Stack.
– Link Instruction
The link or linku instructions create a C language stack frame of user-defined length in the
System or User Stack.
All of the above conditions are associated with
their counterparts, such as return instructions,
which pop the stored data items off the stack.
User Stack
The User Stack provides a totally user-controlled
stacking area.
The User Stack Pointer consists of two registers,
R236 and R237, which are both used for addressing a stack in memory. When stacking in the Register File, the User Stack Pointer High Register,
R236, becomes redundant but must be considered as reserved.
Stack Pointers
Both System and User stacks are pointed to by
double-byte stack pointers. Stacks may be set up
in RAM or in the Register File. Only the lower byte
will be required if the stack is in the Register File.
The upper byte must then be considered as reserved and must not be used as a general purpose
register.
The stack pointer registers are located in the System Group of the Register File, this is illustrated in
Table 2 System Registers (Group E).
Stack Location
Care is necessary when managing stacks as there
is no limit to stack sizes apart from the bottom of
any address space in which the stack is placed.
Consequently programmers are advised to use a
stack pointer value as high as possible, particularly when using the Register File as a stacking area.
Group D is a good location for a stack in the Register File, since it is the highest available area. The
stacks may be located anywhere in the first 14
groups of the Register File (internal stacks) or in
RAM (external stacks).
Note. Stacks must not be located in the Paged
Register Group or in the System Register Group.
ST92185B - DEVICE ARCHITECTURE
SYSTEM REGISTERS (Cont’d)
USER STACK POINTER HIGH REGISTER
(USPHR)
R236 - Read/Write
Register Group: E (System)
Reset value: undefined
SYSTEM STACK POINTER HIGH REGISTER
(SSPHR)
R238 - Read/Write
Register Group: E (System)
Reset value: undefined
7
0
USP15 USP14 USP13 USP12 USP11 USP10 USP9
USP8
USER STACK POINTER LOW REGISTER
(USPLR)
R237 - Read/Write
Register Group: E (System)
Reset value: undefined
USP6
USP5 USP4
USP3
USP2
USP1
SSP15 SSP14 SSP13 SSP12 SSP11 SSP10 SSP9
0
7
USP0
SSP7
Figure 14. Internal Stack Mode
0
SSP6
SSP5
REGISTER
FILE
STACK POINTER (LOW)
F
SSP8
SSP4
SSP3
SSP2
SSP1
SSP0
Figure 15. External Stack Mode
REGISTER
FILE
points to:
0
SYSTEM STACK POINTER LOW REGISTER
(SSPLR)
R239 - Read/Write
Register Group: E (System)
Reset value: undefined
7
USP7
7
F
STACK POINTER (LOW)
&
STACK POINTER (HIGH)
point to:
MEMORY
E
E
STACK
D
D
4
4
3
3
2
2
1
1
0
0
STACK
33/178
ST92185B - DEVICE ARCHITECTURE
2.4 MEMORY ORGANIZATION
Code and data are accessed within the same linear address space. All of the physically separate
memory areas, including the internal ROM, internal RAM and external memory are mapped in a
common address space.
The ST9 provides a total addressable memory
space of 4 Mbytes. This address space is arranged as 64 segments of 64 Kbytes; each segment is again subdivided into four 16 Kbyte pages.
34/178
The mapping of the various memory areas (internal RAM or ROM, external memory) differs from
device to device. Each 64-Kbyte physical memory
segment is mapped either internally or externally;
if the memory is internal and smaller than 64
Kbytes, the remaining locations in the 64-Kbyte
segment are not used (reserved).
Refer to the Register and Memory Map Chapter
for more details on the memory map.
ST92185B - DEVICE ARCHITECTURE
2.5 MEMORY MANAGEMENT UNIT
The CPU Core includes a Memory Management
Unit (MMU) which must be programmed to perform memory accesses (even if external memory
is not used).
The MMU is controlled by 7 registers and 2 bits
(ENCSR and DPRREM) present in EMR2, which
may be written and read by the user program.
These registers are mapped within group F, Page
21 of the Register File. The 7 registers may be
Figure 16. Page 21 Registers
sub-divided into 2 main groups: a first group of four
8-bit registers (DPR[3:0]), and a second group of
three 6-bit registers (CSR, ISR, and DMASR). The
first group is used to extend the address during
Data Memory access (DPR[3:0]). The second is
used to manage Program and Data Memory accesses during Code execution (CSR), Interrupts
Service Routines (ISR or CSR), and DMA transfers (DMASR or ISR).
Page 21
FFh
R255
FEh
R254
FDh
R253
FCh
R252
FBh
R251
FAh
R250
F9h
DMASR
R249
F8h
ISR
R248
F7h
Relocation of P[3:0] and DPR[3:0] Registers
MMU
R247
F6h
EMR2
R246
F5h
EMR1
R245
F4h
CSR
R244
F3h
DPR3
R243
F2h
DPR2
R242
F1h
DPR1
R241
F0h
DPR0
R240
EM
MMU
MMU
SSPLR
SSPHR
USPLR
USPHR
MODER
PPR
RP1
RP0
FLAGR
CICR
P5DR
P4DR
P3DR
P2DR
P1DR
P0DR
DMASR
ISR
EMR2
EMR1
CSR
DPR3
DPR2
1
DPR0
Bit DPRREM=0
(default setting)
SSPLR
SSPHR
USPLR
USPHR
MODER
PPR
RP1
RP0
FLAGR
CICR
P5DR
P4DR
DPR3
DPR2
DPR1
DPR0
DMASR
ISR
EMR2
EMR1
CSR
P3DR
P2DR
P1DR
P0DR
Bit DPRREM=1
35/178
ST92185B - DEVICE ARCHITECTURE
2.6 ADDRESS SPACE EXTENSION
To manage 4 Mbytes of addressing space, it is
necessary to have 22 address bits. The MMU
adds 6 bits to the usual 16-bit address, thus translating a 16-bit virtual address into a 22-bit physical
address. There are 2 different ways to do this depending on the memory involved and on the operation being performed.
2.6.1 Addressing 16-Kbyte Pages
This extension mode is implicitly used to address
Data memory space if no DMA is being performed.
The Data memory space is divided into 4 pages of
16 Kbytes. Each one of the four 8-bit registers
(DPR[3:0], Data Page Registers) selects a different 16-Kbyte page. The DPR registers allow access to the entire memory space which contains
256 pages of 16 Kbytes.
Data paging is performed by extending the 14 LSB
of the 16-bit address with the contents of a DPR
register. The two MSBs of the 16-bit address are
interpreted as the identification number of the DPR
register to be used. Therefore, the DPR registers
Figure 17. Addressing via DPR[3:0]
are involved in the following virtual address ranges:
DPR0: from 0000h to 3FFFh;
DPR1: from 4000h to 7FFFh;
DPR2: from 8000h to BFFFh;
DPR3: from C000h to FFFFh.
The contents of the selected DPR register specify
one of the 256 possible data memory pages. This
8-bit data page number, in addition to the remaining 14-bit page offset address forms the physical
22-bit address (see Figure 10).
A DPR register cannot be modified via an addressing mode that uses the same DPR register. For instance, the instruction “POPW DPR0” is legal only
if the stack is kept either in the register file or in a
memory location above 8000h, where DPR2 and
DPR3 are used. Otherwise, since DPR0 and
DPR1 are modified by the instruction, unpredictable behaviour could result.
16-bit virtual address
MMU registers
DPR0
DPR1
DPR2
DPR3
00
01
10
11
8 bits
14 LSB
22-bit physical address
36/178
2M
SB
ST92185B - DEVICE ARCHITECTURE
ADDRESS SPACE EXTENSION (Cont’d)
2.6.2 Addressing 64-Kbyte Segments
This extension mode is used to address Data
memory space during a DMA and Program memory space during any code execution (normal code
and interrupt routines).
Three registers are used: CSR, ISR, and DMASR.
The 6-bit contents of one of the registers CSR,
ISR, or DMASR define one out of 64 Memory segments of 64 Kbytes within the 4 Mbytes address
space. The register contents represent the 6
MSBs of the memory address, whereas the 16
LSBs of the address (intra-segment address) are
given by the virtual 16-bit address (see Figure 11).
2.7 MMU REGISTERS
The MMU uses 7 registers mapped into Group F,
Page 21 of the Register File and 2 bits of the
EMR2 register.
Most of these registers do not have a default value
after reset.
2.7.1 DPR[3:0]: Data Page Registers
The DPR[3:0] registers allow access to the entire 4
Mbyte memory space composed of 256 pages of
16 Kbytes.
2.7.1.1 Data Page Register Relocation
If these registers are to be used frequently, they
may be relocated in register group E, by programming bit 5 of the EMR2-R246 register in page 21. If
this bit is set, the DPR[3:0] registers are located at
R224-227 in place of the Port 0-3 Data Registers,
which are re-mapped to the default DPR's locations: R240-243 page 21.
Data Page Register relocation is illustrated in Figure 9.
Figure 18. Addressing via CSR, ISR, and DMASR
16-bit virtual address
MMU registers
CSR
1
1
2
3
Fetching program
instruction
Data Memory
accessed in DMA
Fetching interrupt
instruction or DMA
access to Program
Memory
DMASR
2
ISR
3
6 bits
22-bit physical address
37/178
ST92185B - DEVICE ARCHITECTURE
MMU REGISTERS (Cont’d)
DATA PAGE REGISTER 0 (DPR0)
R240 - Read/Write
Register Page: 21
Reset value: undefined
This register is relocated to R224 if EMR2.5 is set.
7
0
DATA PAGE REGISTER 2 (DPR2)
R242 - Read/Write
Register Page: 21
Reset value: undefined
This register is relocated to R226 if EMR2.5 is set.
7
0
DPR0_7 DPR0_6 DPR0_5 DPR0_4 DPR0_3 DPR0_2 DPR0_1 DPR0_0
DPR2_7 DPR2_6 DPR2_5 DPR2_4 DPR2_3 DPR2_2 DPR2_1 DPR2_0
Bits 7:0 = DPR0_[7:0]: These bits define the 16Kbyte Data Memory page number. They are used
as the most significant address bits (A21-14) to extend the address during a Data Memory access.
The DPR0 register is used when addressing the
virtual address range 0000h-3FFFh.
Bits 7:0 = DPR2_[7:0]: These bits define the 16Kbyte Data memory page. They are used as the
most significant address bits (A21-14) to extend
the address during a Data memory access. The
DPR2 register is involved when the virtual address
is in the range 8000h-BFFFh.
DATA PAGE REGISTER 1 (DPR1)
R241 - Read/Write
Register Page: 21
Reset value: undefined
This register is relocated to R225 if EMR2.5 is set.
DATA PAGE REGISTER 3 (DPR3)
R243 - Read/Write
Register Page: 21
Reset value: undefined
This register is relocated to R227 if EMR2.5 is set.
7
0
7
0
DPR1_7 DPR1_6 DPR1_5 DPR1_4 DPR1_3 DPR1_2 DPR1_1 DPR1_0
DPR3_7 DPR3_6 DPR3_5 DPR3_4 DPR3_3 DPR3_2 DPR3_1 DPR3_0
Bits 7:0 = DPR1_[7:0]: These bits define the 16Kbyte Data Memory page number. They are used
as the most significant address bits (A21-14) to extend the address during a Data Memory access.
The DPR1 register is used when addressing the
virtual address range 4000h-7FFFh.
Bits 7:0 = DPR3_[7:0]: These bits define the 16Kbyte Data memory page. They are used as the
most significant address bits (A21-14) to extend
the address during a Data memory access. The
DPR3 register is involved when the virtual address
is in the range C000h-FFFFh.
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ST92185B - DEVICE ARCHITECTURE
MMU REGISTERS (Cont’d)
2.7.2 CSR: Code Segment Register
This register selects the 64-Kbyte code segment
being used at run-time to access instructions. It
can also be used to access data if the spm instruction has been executed (or ldpp, ldpd, lddp).
Only the 6 LSBs of the CSR register are implemented, and bits 6 and 7 are reserved. The CSR
register allows access to the entire memory space,
divided into 64 segments of 64 Kbytes.
To generate the 22-bit Program memory address,
the contents of the CSR register is directly used as
the 6 MSBs, and the 16-bit virtual address as the
16 LSBs.
Note: The CSR register should only be read and
not written for data operations (there are some exceptions which are documented in the following
paragraph). It is, however, modified either directly
by means of the jps and calls instructions, or
indirectly via the stack, by means of the rets instruction.
CODE SEGMENT REGISTER (CSR)
R244 - Read/Write
Register Page: 21
Reset value: 0000 0000 (00h)
7
0
0
0
CSR_5
CSR_4
CSR_3
CSR_2
CSR_1
CSR_0
Bits 7:6 = Reserved, keep in reset state.
Bits 5:0 = CSR_[5:0]: These bits define the 64Kbyte memory segment (among 64) which contains the code being executed. These bits are
used as the most significant address bits (A21-16).
0
0
0
Bits 7:6 = Reserved, keep in reset state.
Bits 5:0 = ISR_[5:0]: These bits define the 64Kbyte memory segment (among 64) which contains the interrupt vector table and the code for interrupt service routines and DMA transfers (when
the PS bit of the DAPR register is reset). These
bits are used as the most significant address bits
(A21-16). The ISR is used to extend the address
space in two cases:
– Whenever an interrupt occurs: ISR points to the
64-Kbyte memory segment containing the interrupt vector table and the interrupt service routine
code. See also the Interrupts chapter.
– During DMA transactions between the peripheral
and memory when the PS bit of the DAPR register is reset : ISR points to the 64 K-byte Memory
segment that will be involved in the DMA transaction.
2.7.4 DMASR: DMA Segment Register
DMA SEGMENT REGISTER (DMASR)
R249 - Read/Write
Register Page: 21
Reset value: undefined
7
0
0
0
DMA
SR_5
DMA
SR_4
DMA
SR_3
DMA
SR_2
DMA
SR_1
DMA
SR_0
Bits 7:6 = Reserved, keep in reset state.
2.7.3 ISR: Interrupt Segment Register
INTERRUPT SEGMENT REGISTER (ISR)
R248 - Read/Write
Register Page: 21
Reset value: undefined
7
ISR and ENCSR bit (EMR2 register) are also described in the chapter relating to Interrupts, please
refer to this description for further details.
ISR_5 ISR_4 ISR_3 ISR_2 ISR_1 ISR_0
Bits 5:0 = DMASR_[5:0]: These bits define the 64Kbyte Memory segment (among 64) used when a
DMA transaction is performed between the peripheral's data register and Memory, with the PS bit of
the DAPR register set. These bits are used as the
most significant address bits (A21-16). If the PS bit
is reset, the ISR register is used to extend the address.
39/178
ST92185B - DEVICE ARCHITECTURE
MMU REGISTERS (Cont’d)
Figure 19. Memory Addressing Scheme (example)
4M bytes
3FFFFFh
16K
294000h
DPR3
240000h
23FFFFh
DPR2
DPR1
DPR0
16K
20C000h
16K
200000h
1FFFFFh
64K
040000h
03FFFFh
030000h
DMASR
020000h
40/178
ISR
64K
CSR
16K
64K
010000h
00C000h
000000h
ST92185B - DEVICE ARCHITECTURE
2.8 MMU USAGE
2.8.1 Normal Program Execution
Program memory is organized as a set of 64Kbyte segments. The program can span as many
segments as needed, but a procedure cannot
stretch across segment boundaries. jps, calls
and rets instructions, which automatically modify
the CSR, must be used to jump across segment
boundaries. Writing to the CSR is forbidden during
normal program execution because it is not synchronized with the opcode fetch. This could result
in fetching the first byte of an instruction from one
memory segment and the second byte from another. Writing to the CSR is allowed when it is not being used, i.e during an interrupt service routine if
ENCSR is reset.
Note that a routine must always be called in the
same way, i.e. either always with call or always
with calls, depending on whether the routine
ends with ret or rets. This means that if the routine is written without prior knowledge of the location of other routines which call it, and all the program code does not fit into a single 64-Kbyte segment, then calls/rets should be used.
In typical microcontroller applications, less than 64
Kbytes of RAM are used, so the four Data space
pages are normally sufficient, and no change of
DPR[3:0] is needed during Program execution. It
may be useful however to map part of the ROM
into the data space if it contains strings, tables, bit
maps, etc.
If there is to be frequent use of paging, the user
can set bit 5 (DPRREM) in register R246 (EMR2)
of Page 21. This swaps the location of registers
DPR[3:0] with that of the data registers of Ports 03. In this way, DPR registers can be accessed
without the need to save/set/restore the Page
Pointer Register. Port registers are therefore
moved to page 21. Applications that require a lot of
paging typically use more than 64 Kbytes of external memory, and as ports 0, 1 and 2 are required
to address it, their data registers are unused.
2.8.2 Interrupts
The ISR register has been created so that the interrupt routines may be found by means of the
same vector table even after a segment jump/call.
When an interrupt occurs, the CPU behaves in
one of 2 ways, depending on the value of the ENCSR bit in the EMR2 register (R246 on Page 21).
If this bit is reset (default condition), the CPU
works in original ST9 compatibility mode. For the
duration of the interrupt service routine, the ISR is
used instead of the CSR, and the interrupt stack
frame is kept exactly as in the original ST9 (only
the PC and flags are pushed). This avoids the
need to save the CSR on the stack in the case of
an interrupt, ensuring a fast interrupt response
time. The drawback is that it is not possible for an
interrupt service routine to perform segment
calls/jps: these instructions would update the
CSR, which, in this case, is not used (ISR is used
instead). The code size of all interrupt service routines is thus limited to 64 Kbytes.
If, instead, bit 6 of the EMR2 register is set, the
ISR is used only to point to the interrupt vector table and to initialize the CSR at the beginning of the
interrupt service routine: the old CSR is pushed
onto the stack together with the PC and the flags,
and then the CSR is loaded with the ISR. In this
case, an iret will also restore the CSR from the
stack. This approach lets interrupt service routines
access the whole 4-Mbyte address space. The
drawback is that the interrupt response time is
slightly increased, because of the need to also
save the CSR on the stack. Compatibility with the
original ST9 is also lost in this case, because the
interrupt stack frame is different; this difference,
however, would not be noticeable for a vast majority of programs.
Data memory mapping is independent of the value
of bit 6 of the EMR2 register, and remains the
same as for normal code execution: the stack is
the same as that used by the main program, as in
the ST9. If the interrupt service routine needs to
access additional Data memory, it must save one
(or more) of the DPRs, load it with the needed
memory page and restore it before completion.
2.8.3 DMA
Depending on the PS bit in the DAPR register (see
DMA chapter) DMA uses either the ISR or the
DMASR for memory accesses: this guarantees
that a DMA will always find its memory segment(s), no matter what segment changes the application has performed. Unlike interrupts, DMA
transactions cannot save/restore paging registers,
so a dedicated segment register (DMASR) has
been created. Having only one register of this kind
means that all DMA accesses should be programmed in one of the two following segments:
the one pointed to by the ISR (when the PS bit of
the DAPR register is reset), and the one referenced by the DMASR (when the PS bit is set).
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ST92185B - INTERRUPTS
3 INTERRUPTS
3.1 INTRODUCTION
3.2 INTERRUPT VECTORING
The ST9 responds to peripheral and external
events through its interrupt channels. Current program execution can be suspended to allow the
ST9 to execute a specific response routine when
such an event occurs, providing that interrupts
have been enabled, and according to a priority
mechanism. If an event generates a valid interrupt
request, the current program status is saved and
control passes to the appropriate Interrupt Service
Routine.
The ST9 CPU can receive requests from the following sources:
– On-chip peripherals
– External pins
– Top-Level Pseudo-non-maskable interrupt
According to the on-chip peripheral features, an
event occurrence can generate an Interrupt request which depends on the selected mode.
Up to eight external interrupt channels, with programmable input trigger edge, are available. In addition, a dedicated interrupt channel, set to the
Top-level priority, can be devoted either to the external NMI pin (where available) to provide a NonMaskable Interrupt, or to the Timer/Watchdog. Interrupt service routines are addressed through a
vector table mapped in Memory.
The ST9 implements an interrupt vectoring structure which allows the on-chip peripheral to identify
the location of the first instruction of the Interrupt
Service Routine automatically.
When an interrupt request is acknowledged, the
peripheral interrupt module provides, through its
Interrupt Vector Register (IVR), a vector to point
into the vector table of locations containing the
start addresses of the Interrupt Service Routines
(defined by the programmer).
Each peripheral has a specific IVR mapped within
its Register File pages.
The Interrupt Vector table, containing the addresses of the Interrupt Service Routines, is located in
the first 256 locations of Memory pointed to by the
ISR register, thus allowing 8-bit vector addressing.
For a description of the ISR register refer to the
chapter describing the MMU.
The user Power on Reset vector is stored in the
first two physical bytes in memory, 000000h and
000001h.
The Top Level Interrupt vector is located at addresses 0004h and 0005h in the segment pointed
to by the Interrupt Segment Register (ISR).
With one Interrupt Vector register, it is possible to
address several interrupt service routines; in fact,
peripherals can share the same interrupt vector
register among several interrupt channels. The
most significant bits of the vector are user programmable to define the base vector address within the vector table, the least significant bits are
controlled by the interrupt module, in hardware, to
select the appropriate vector.
Note: The first 256 locations of the memory segment pointed to by ISR can contain program code.
3.2.1 Divide by Zero trap
The Divide by Zero trap vector is located at addresses 0002h and 0003h of each code segment;
it should be noted that for each code segment a
Divide by Zero service routine is required.
Warning. Although the Divide by Zero Trap operates as an interrupt, the FLAG Register is not
pushed onto the system Stack automatically. As a
result it must be regarded as a subroutine, and the
service routine must end with the RET instruction
(not IRET ).
Figure 20. Interrupt Response
n
NORMAL
PROGRAM
FLOW
INTERRUPT
INTERRUPT
SERVICE
ROUTINE
CLEAR
PENDING BIT
IRET
INSTRUCTION
VR001833
42/178
ST92185B - INTERRUPTS
INTERRUPT VECTORING (Cont’d)
3.2.2 Segment Paging During Interrupt
Routines
The ENCSR bit in the EMR2 register can be used
to select between original ST9 backward compatibility mode and ST9+ interrupt management
mode.
ST9 backward compatibility mode (ENCSR = 0)
If ENCSR is reset, the CPU works in original ST9
compatibility mode. For the duration of the interrupt service routine, ISR is used instead of CSR,
and the interrupt stack frame is identical to that of
the original ST9: only the PC and Flags are
pushed.
This avoids saving the CSR on the stack in the
event of an interrupt, thus ensuring a faster interrupt response time.
It is not possible for an interrupt service routine to
perform inter-segment calls or jumps: these instructions would update the CSR, which, in this
case, is not used (ISR is used instead). The code
segment size for all interrupt service routines is
thus limited to 64K bytes.
ST9+ mode (ENCSR = 1)
If ENCSR is set, ISR is only used to point to the interrupt vector table and to initialize the CSR at the
beginning of the interrupt service routine: the old
CSR is pushed onto the stack together with the PC
and flags, and CSR is then loaded with the contents of ISR.
In this case, iret will also restore CSR from the
stack. This approach allows interrupt service routines to access the entire 4 Mbytes of address
space. The drawback is that the interrupt response
time is slightly increased, because of the need to
also save CSR on the stack.
Full compatibility with the original ST9 is lost in this
case, because the interrupt stack frame is different.
ENCSR Bit
0
1
Mode
ST9 Compatible
ST9+
Pushed/Popped
PC, FLAGR,
PC, FLAGR
Registers
CSR
Max. Code Size
64KB
No limit
for interrupt
Within
1
segment
Across
segments
service routine
3.3 INTERRUPT PRIORITY LEVELS
The ST9 supports a fully programmable interrupt
priority structure. Nine priority levels are available
to define the channel priority relationships:
– The on-chip peripheral channels and the eight
external interrupt sources can be programmed
within eight priority levels. Each channel has a 3bit field, PRL (Priority Level), that defines its priority level in the range from 0 (highest priority) to
7 (lowest priority).
– The 9th level (Top Level Priority) is reserved for
the Timer/Watchdog or the External Pseudo
Non-Maskable Interrupt. An Interrupt service
routine at this level cannot be interrupted in any
arbitration mode. Its mask can be both maskable
(TLI) or non-maskable (TLNM).
3.4 PRIORITY LEVEL ARBITRATION
The 3 bits of CPL (Current Priority Level) in the
Central Interrupt Control Register contain the priority of the currently running program (CPU priority). CPL is set to 7 (lowest priority) upon reset and
can be modified during program execution either
by software or automatically by hardware according to the selected Arbitration Mode.
During every instruction, an arbitration phase
takes place, during which, for every channel capable of generating an Interrupt, each priority level is
compared to all the other requests (interrupts or
DMA).
If the highest priority request is an interrupt, its
PRL value must be strictly lower (that is, higher priority) than the CPL value stored in the CICR register (R230) in order to be acknowledged. The Top
Level Interrupt overrides every other priority.
3.4.1 Priority level 7 (Lowest)
Interrupt requests at PRL level 7 cannot be acknowledged, as this PRL value (the lowest possible priority) cannot be strictly lower than the CPL
value. This can be of use in a fully polled interrupt
environment.
3.4.2 Maximum depth of nesting
No more than 8 routines can be nested. If an interrupt routine at level N is being serviced, no other
Interrupts located at level N can interrupt it. This
guarantees a maximum number of 8 nested levels
including the Top Level Interrupt request.
43/178
ST92185B - INTERRUPTS
PRIORITY LEVEL ARBITRATION (Cont’d)
3.4.3 Simultaneous Interrupts
If two or more requests occur at the same time and
at the same priority level, an on-chip daisy chain,
specific to every ST9 version, selects the channel
with the highest position in the chain, as shown in
Table 5.
Table 5. Daisy Chain Priority for the ST92185B
Highest Position
Lowest Position
INTA0
INTA1
INTB0
INTB1
INTC0
INTC1
INTD0
INTD1
INT0/WDT
INT1/Standard Timer
INT2/SPI
INT3/AD Converter
INT4/SYNC (EOFVBI)
INT5/SYNC (FLDST)
INT6
INT7
3.4.4 Dynamic Priority Level Modification
The main program and routines can be specifically
prioritized. Since the CPL is represented by 3 bits
in a read/write register, it is possible to modify dynamically the current priority value during program
execution. This means that a critical section can
have a higher priority with respect to other interrupt requests. Furthermore it is possible to prioritize even the Main Program execution by modifying the CPL during its execution. See Figure 21
Figure 21. Example of Dynamic priority
level modification in Nested Mode
INTERRUPT 6 HAS PRIORITY LEVEL 6
Priority Level
CPL is set to 7
4
by MAIN program
ei
INT6
5
MAIN
CPL is set to 5
CPL6 > CPL5:
6
INT6 pending
7
INT 6
CPL=6
MAIN
CPL=7
3.5 ARBITRATION MODES
The ST9 provides two interrupt arbitration modes:
Concurrent mode and Nested mode. Concurrent
mode is the standard interrupt arbitration mode.
Nested mode improves the effective interrupt response time when service routine nesting is required, depending on the request priority levels.
44/178
The IAM control bit in the CICR Register selects
Concurrent Arbitration mode or Nested Arbitration
Mode.
3.5.1 Concurrent Mode
This mode is selected when the IAM bit is cleared
(reset condition). The arbitration phase, performed
during every instruction, selects the request with
the highest priority level. The CPL value is not
modified in this mode.
Start of Interrupt Routine
The interrupt cycle performs the following steps:
– All maskable interrupt requests are disabled by
clearing CICR.IEN.
– The PC low byte is pushed onto system stack.
– The PC high byte is pushed onto system stack.
– If ENCSR is set, CSR is pushed onto system
stack.
– The Flag register is pushed onto system stack.
– The PC is loaded with the 16-bit vector stored in
the Vector Table, pointed to by the IVR.
– If ENCSR is set, CSR is loaded with ISR contents; otherwise ISR is used in place of CSR until
iret instruction.
End of Interrupt Routine
The Interrupt Service Routine must be ended with
the iret instruction. The iret instruction executes the following operations:
– The Flag register is popped from system stack.
– If ENCSR is set, CSR is popped from system
stack.
– The PC high byte is popped from system stack.
– The PC low byte is popped from system stack.
– All unmasked Interrupts are enabled by setting
the CICR.IEN bit.
– If ENCSR is reset, CSR is used instead of ISR.
Normal program execution thus resumes at the interrupted instruction. All pending interrupts remain
pending until the next ei instruction (even if it is
executed during the interrupt service routine).
Note: In Concurrent mode, the source priority level
is only useful during the arbitration phase, where it
is compared with all other priority levels and with
the CPL. No trace is kept of its value during the
ISR. If other requests are issued during the interrupt service routine, once the global CICR.IEN is
re-enabled, they will be acknowledged regardless
of the interrupt service routine’s priority. This may
cause undesirable interrupt response sequences.
ST92185B - INTERRUPTS
ARBITRATION MODES (Cont’d)
Examples
In the following two examples, three interrupt requests with different priority levels (2, 3 & 4) occur
simultaneously during the interrupt 5 service routine.
Example 1
In the first example, (simplest case, Figure 22) the
ei instruction is not used within the interrupt service routines. This means that no new interrupt can
be serviced in the middle of the current one. The
interrupt routines will thus be serviced one after
another, in the order of their priority, until the main
program eventually resumes.
Figure 22. Simple Example of a Sequence of Interrupt Requests with:
- Concurrent mode selected and
- IEN unchanged by the interrupt routines
0
INTERRUPT 2 HAS PRIORITY LEVEL 2
Priority Level of
Interrupt Request
INTERRUPT 3 HAS PRIORITY LEVEL 3
INTERRUPT 4 HAS PRIORITY LEVEL 4
INTERRUPT 5 HAS PRIORITY LEVEL 5
1
2
INT 2
CPL = 7
3
INT 3
CPL = 7
INT 2
INT 3
INT 4
4
5
INT 4
CPL = 7
INT 5
ei
CPL = 7
6
INT 5
7
MAIN
CPL is set to 7
MAIN
CPL = 7
45/178
ST92185B - INTERRUPTS
ARBITRATION MODES (Cont’d)
Example 2
In the second example, (more complex, Figure
23), each interrupt service routine sets Interrupt
Enable with the ei instruction at the beginning of
the routine. Placed here, it minimizes response
time for requests with a higher priority than the one
being serviced.
The level 2 interrupt routine (with the highest priority) will be acknowledged first, then, when the ei
instruction is executed, it will be interrupted by the
level 3 interrupt routine, which itself will be interrupted by the level 4 interrupt routine. When the
level 4 interrupt routine is completed, the level 3 interrupt routine resumes and finally the level 2 interrupt routine. This results in the three interrupt serv-
ice routines being executed in the opposite order
of their priority.
It is therefore recommended to avoid inserting
the ei instruction in the interrupt service routine in Concurrent mode. Use the ei instruction only in nested mode.
WARNING: If, in Concurrent Mode, interrupts are
nested (by executing ei in an interrupt service
routine), make sure that either ENCSR is set or
CSR=ISR, otherwise the iret of the innermost interrupt will make the CPU use CSR instead of ISR
before the outermost interrupt service routine is
terminated, thus making the outermost routine fail.
Figure 23. Complex Example of a Sequence of Interrupt Requests with:
- Concurrent mode selected
- IEN set to 1 during interrupt service routine execution
0
Priority Level of
Interrupt Request
INTERRUPT 2 HAS PRIORITY LEVEL 2
INTERRUPT 3 HAS PRIORITY LEVEL 3
INTERRUPT 4 HAS PRIORITY LEVEL 4
1
INTERRUPT 5 HAS PRIORITY LEVEL 5
2
3
INT 2
INT 2
CPL = 7
CPL = 7
ei
INT 2
INT 3
INT 4
4
5
INT 5
ei
6
CPL = 7
INT 3
CPL = 7
INT 3
CPL = 7
ei
ei
INT 4
CPL = 7
INT 5
CPL = 7
ei
INT 5
7
MAIN
CPL is set to 7
46/178
MAIN
CPL = 7
ST92185B - INTERRUPTS
ARBITRATION MODES (Cont’d)
3.5.2 Nested Mode
The difference between Nested mode and Concurrent mode, lies in the modification of the Current Priority Level (CPL) during interrupt processing.
The arbitration phase is basically identical to Concurrent mode, however, once the request is acknowledged, the CPL is saved in the Nested Interrupt Control Register (NICR) by setting the NICR
bit corresponding to the CPL value (i.e. if the CPL
is 3, the bit 3 will be set).
The CPL is then loaded with the priority of the request just acknowledged; the next arbitration cycle
is thus performed with reference to the priority of
the interrupt service routine currently being executed.
Start of Interrupt Routine
The interrupt cycle performs the following steps:
– All maskable interrupt requests are disabled by
clearing CICR.IEN.
– CPL is saved in the special NICR stack to hold
the priority level of the suspended routine.
– Priority level of the acknowledged routine is
stored in CPL, so that the next request priority
will be compared with the one of the routine currently being serviced.
– The PC low byte is pushed onto system stack.
– The PC high byte is pushed onto system stack.
– If ENCSR is set, CSR is pushed onto system
stack.
– The Flag register is pushed onto system stack.
– The PC is loaded with the 16-bit vector stored in
the Vector Table, pointed to by the IVR.
– If ENCSR is set, CSR is loaded with ISR contents; otherwise ISR is used in place of CSR until
iret instruction.
Figure 24. Simple Example of a Sequence of Interrupt Requests with:
- Nested mode
- IEN unchanged by the interrupt routines
Priority Level of
Interrupt Request
INTERRUPT 0 HAS PRIORITY LEVEL 0
INTERRUPT 2 HAS PRIORITY LEVEL 2
1
INT0
2
INT 2
CPL=2
3
INTERRUPT 4 HAS PRIORITY LEVEL 4
CPL6 > CPL3:
INT6 pending
INT2
INT3
INT4
5
ei
INT 5
CPL=5
6
INT5
MAIN
CPL is set to 7
CPL2 < CPL4:
Serviced next
INTERRUPT 5 HAS PRIORITY LEVEL 5
INTERRUPT 6 HAS PRIORITY LEVEL 6
INT 2
CPL=2
INT6
INT 3
CPL=3
4
7
INTERRUPT 3 HAS PRIORITY LEVEL 3
INT 0
CPL=0
0
INT2
INT 4
CPL=4
INT 6
CPL=6
MAIN
CPL=7
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ST92185B - INTERRUPTS
ARBITRATION MODES (Cont’d)
End of Interrupt Routine
The iret Interrupt Return instruction executes
the following steps:
– The Flag register is popped from system stack.
– If ENCSR is set, CSR is popped from system
stack.
– The PC high byte is popped from system stack.
– The PC low byte is popped from system stack.
– All unmasked Interrupts are enabled by setting
the CICR.IEN bit.
– The priority level of the interrupted routine is
popped from the special register (NICR) and
copied into CPL.
– If ENCSR is reset, CSR is used instead of ISR,
unless the program returns to another nested
routine.
The suspended routine thus resumes at the interrupted instruction.
Figure 24 contains a simple example, showing that
if the ei instruction is not used in the interrupt
service routines, nested and concurrent modes
are equivalent.
Figure 25 contains a more complex example
showing how nested mode allows nested interrupt
processing (enabled inside the interrupt service
routinesi using the ei instruction) according to
their priority level.
Figure 25. Complex Example of a Sequence of Interrupt Requests with:
- Nested mode
- IEN set to 1 during the interrupt routine execution
Priority Level of
Interrupt Request
0
INTERRUPT 0 HAS PRIORITY LEVEL 0
INTERRUPT 2 HAS PRIORITY LEVEL 2
INT 0
CPL=0
1
INT0
2
INT 2
CPL=2
3
INTERRUPT 4 HAS PRIORITY LEVEL 4
INT2
INT3
INT4
5
INT 5
CPL=5
ei
6
ei
INT5
MAIN
CPL is set to 7
48/178
INTERRUPT 5 HAS PRIORITY LEVEL 5
INTERRUPT 6 HAS PRIORITY LEVEL 6
CPL6 > CPL3:
INT6 pending
INT 2
CPL=2
INT 2
CPL=2
INT6
INT 3
CPL=3 INT2
ei
4
7
INTERRUPT 3 HAS PRIORITY LEVEL 3
ei
CPL2 < CPL4:
Serviced just after ei
INT 4
CPL=4
ei
INT 4
CPL=4
INT 5
CPL=5
INT 6
CPL=6
MAIN
CPL=7
ST92185B - INTERRUPTS
3.6 EXTERNAL INTERRUPTS
The standard ST9 core contains 8 external interrupts sources grouped into four pairs.
Table 6. External Interrupt Channel Grouping
External Interrupt
Channel
INT7
INT6
INTD1
INTD0
INT5
INT4
INTC1
INTC0
INT3
INT2
INTB1
INTB0
INT1
INT0
INTA1
INTA0
Each source has a trigger control bit TEA0,..TED1
(R242,EITR.0,..,7 Page 0) to select triggering on
the rising or falling edge of the external pin. If the
Trigger control bit is set to “1”, the corresponding
pending bit IPA0,..,IPD1 (R243,EIPR.0,..,7 Page
0) is set on the input pin rising edge, if it is cleared,
the pending bit is set on the falling edge of the input pin. Each source can be individually masked
through
the
corresponding
control
bit
IMA0,..,IMD1 (EIMR.7,..,0). See Figure 27.
The priority level of the external interrupt sources
can be programmed among the eight priority levels with the control register EIPLR (R245). The priority level of each pair is software defined using
the bits PRL2, PRL1. For each pair, the even
channel (A0,B0,C0,D0) of the group has the even
priority level and the odd channel (A1,B1,C1,D1)
has the odd (lower) priority level.
Figure 26 shows an example of priority levels.
Figure 27 gives an overview of the External interrupt control bits and vectors.
– The source of the interrupt channel INTA0 can
be selected between the external pin INT0 (when
IA0S = “1”, the reset value) or the On-chip Timer/
Watchdog peripheral (when IA0S = “0”).
– INTA1: by selecting INTS equal to 0, the standard Timer is chosen as the interrupt.
– The source of the interrupt channel INTB0 can
be selected between the external pin INT2 (when
(SPEN,BMS)=(0,0)) or the SPI peripheral.
– INTB1: setting AD-INT.0 to 1 selects the ADC as
the interrupt source for channel INTB1.
– Setting bit 2 of the CSYCT to 1 selects EOFVBI
interrupt as the source for INTC0. Setting this bit
to 0 selects external interrupt on INT4.
– Setting FSTEN (bit 3 of the CSYCT register) to 1
selects FLDST interrupt for channel INTC1. Setting this bit to 0 selects external interrupt INT5.
Interrupt channels INTD0 and INTD1 have an input pin as source. However, the input line may be
multiplexed with an on-chip peripheral I/O or connected to an input pin that performs also another
function.
Warning: When using channels shared by both
external interrupts and peripherals, special care
must be taken to configure their control registers
for both peripherals and interrupts.
Table 7. Internal/External Interrupt Source
Figure 26. Priority Level Examples
PL2D PL1D PL2C PL1C PL2B PL1B PL2A PL1A
Channel
Internal Interrupt
Source
External Interrupt
Source
INTA0
Timer/Watchdog
INT0
SOURCE PRIORITY
INTA1
Standard Timer
None
INT.D0: 100=4
INT.A0: 010=2
INTB0
SPI Interrupt
INT2
INT.D1: 101=5
INT.A1: 011=3
INTB1
A/D Converter
None
INT.C0: 000=0
INT.B0: 100=4
INTC0
INT4
INT.C1: 001=1
INT.B1: 101=5
EOFVBI
(SYNC inter)
INTC1
FLDST
(SYNC inter)
INT5
INTD0
none
INT6
INTD1
none
INT7
1
SOURCE PRIORITY
0
0
0
1
0
0
1
EIPLR
VR000151
n
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ST92185B - INTERRUPTS
EXTERNAL INTERRUPTS (Cont’d)
Figure 27. External Interrupts Control Bits and
Vectors
n
Watchdog/Timer IA0S
End of count
TEA0
“0”
V7 V6 V5 V4 0 0
VECTOR
Priority level
PL2A PL1A 0
Mask bit IMA0
“1”
INT 0 pin
0 0
INT A0
request
Pending bit IPA0
*
INTS
Std. Timer
“0”
V7 V6 V5 V4 0 0
VECTOR
Priority level
PL2A PL1A 1
Not connected
“1”
Mask bit IMA1
1 0
INT A1
request
Pending bit IPA1
SPEN,BMS
TEB0
SPI Interrupt
INT 2 pin
“1,x”
V7 V6 V5 V4 0 1
VECTOR
Priority level
PL2B PL1B 0
“0,0”
Mask bit IMB0
0 0
INT B0
request
Pending bit IPB0
*
ADINT
ADC
“0”
V7 V6 V5 V4 0 1
VECTOR
Priority level
PL2B PL1B 1
Not connected
“1”
Mask bit IMB1
TEC0
EOFVBI
(SYNC inter)
1 0
INT B1
request
Pending bit IPB1
VBEN
“1”
V7 V6 V5 V4 1 0
VECTOR
Priority level
PL2C PL1C 0
“0”
Mask bit IMC0
0 0
INT C0
request
INT 4 pin
TEC1
INT 5 pin
Pending bit IPC0
FSTEN
FLDST
(SYNC inter)
“1”
V7 V6 V5 V4 1 0
VECTOR
Priority level
PL2C PL1C 1
“0”
Mask bit IMC1
1 0
INT C1
request
Pending bit IPC1
TED0
V7 V6 V5 V4 1 1
VECTOR
PL2D PL1D 0
Priority level
INT 6 pin
Mask bit IMD0
0 0
INT D0
request
Pending bit IPD0
TED1
V7 V6 V5 V4 1 1
VECTOR
Priority level
PL2D PL1D 1
INT 7 pin
Mask bit IMD1
*
n
50/178
Shared channels, see warning
1 0
Pending bit IPD1
INT D1
request
ST92185B - INTERRUPTS
3.7 TOP LEVEL INTERRUPT
The Top Level Interrupt channel can be assigned
either to the external pin NMI or to the Timer/
Watchdog according to the status of the control bit
EIVR.TLIS (R246.2, Page 0). If this bit is high (the
reset condition) the source is the external pin NMI.
If it is low, the source is the Timer/ Watchdog End
Of Count. When the source is the NMI external
pin, the control bit EIVR.TLTEV (R246.3; Page 0)
selects between the rising (if set) or falling (if reset)
edge generating the interrupt request. When the
selected event occurs, the CICR.TLIP bit (R230.6)
is set. Depending on the mask situation, a Top
Level Interrupt request may be generated. Two
kinds of masks are available, a Maskable mask
and a Non-Maskable mask. The first mask is the
CICR.TLI bit (R230.5): it can be set or cleared to
enable or disable respectively the Top Level Interrupt request. If it is enabled, the global Enable Interrupt bit, CICR.IEN (R230.4) must also be enabled in order to allow a Top Level Request.
The second mask NICR.TLNM (R247.7) is a setonly mask. Once set, it enables the Top Level Interrupt request independently of the value of
CICR.IEN and it cannot be cleared by the program. Only the processor RESET cycle can clear
this bit. This does not prevent the user from ignoring some sources due to a change in TLIS.
The Top Level Interrupt Service Routine cannot be
interrupted by any other interrupt or DMA request,
in any arbitration mode, not even by a subsequent
Top Level Interrupt request.
Warning. The interrupt machine cycle of the Top
Level Interrupt does not clear the CICR.IEN bit,
and the corresponding iret does not set it. Furthermore the TLI never modifies the CPL bits and
the NICR register.
3.8 ON-CHIP PERIPHERAL INTERRUPTS
The general structure of the peripheral interrupt
unit is described here, however each on-chip peripheral has its own specific interrupt unit containing one or more interrupt channels, or DMA channels. Please refer to the specific peripheral chapter for the description of its interrupt features and
control registers.
The on-chip peripheral interrupt channels provide
the following control bits:
– Interrupt Pending bit (IP). Set by hardware
when the Trigger Event occurs. Can be set/
cleared by software to generate/cancel pending
interrupts and give the status for Interrupt polling.
– Interrupt Mask bit (IM). If IM = “0”, no interrupt
request is generated. If IM =“1” an interrupt request is generated whenever IP = “1” and
CICR.IEN = “1”.
– Priority Level (PRL, 3 bits). These bits define
the current priority level, PRL=0: the highest priority, PRL=7: the lowest priority (the interrupt
cannot be acknowledged)
– Interrupt Vector Register (IVR, up to 7 bits).
The IVR points to the vector table which itself
contains the interrupt routine start address.
Figure 28. Top Level Interrupt Structure
n
WATCHDOG ENABLE
WDEN
CORE
RESET
TLIP
WATCHDOG TIMER
END OF COUNT
PENDING
MUX
MASK
TOP LEVEL
INTERRUPT
REQUEST
OR
NMI
TLIS
TLTEV
TLNM
TLI
IEN
VA00294
n
51/178
ST92185B - INTERRUPTS
3.9 INTERRUPT RESPONSE TIME
The interrupt arbitration protocol functions completely asynchronously from instruction flow and
requires 5 clock cycles. One more CPUCLK cycle
is required when an interrupt is acknowledged.
Requests are sampled every 5 CPUCLK cycles.
If the interrupt request comes from an external pin,
the trigger event must occur a minimum of one
INTCLK cycle before the sampling time.
When an arbitration results in an interrupt request
being generated, the interrupt logic checks if the
current instruction (which could be at any stage of
execution) can be safely aborted; if this is the
case, instruction execution is terminated immediately and the interrupt request is serviced; if not,
the CPU waits until the current instruction is terminated and then services the request. Instruction
execution can normally be aborted provided no
write operation has been performed.
For an interrupt deriving from an external interrupt
channel, the response time between a user event
and the start of the interrupt service routine can
range from a minimum of 26 clock cycles to a maximum of 55 clock cycles (DIV instruction), 53 clock
52/178
cycles (DIVWS and MUL instructions) or 49 for
other instructions.
For a non-maskable Top Level interrupt, the response time between a user event and the start of
the interrupt service routine can range from a minimum of 22 clock cycles to a maximum of 51 clock
cycles (DIV instruction), 49 clock cycles (DIVWS
and MUL instructions) or 45 for other instructions.
In order to guarantee edge detection, input signals
must be kept low/high for a minimum of one
INTCLK cycle.
An interrupt machine cycle requires a basic 18 internal clock cycles (CPUCLK), to which must be
added a further 2 clock cycles if the stack is in the
Register File. 2 more clock cycles must further be
added if the CSR is pushed (ENCSR =1).
The interrupt machine cycle duration forms part of
the two examples of interrupt response time previously quoted; it includes the time required to push
values on the stack, as well as interrupt vector
handling.
In Wait for Interrupt mode, a further cycle is required as wake-up delay.
ST92185B - INTERRUPTS
3.10 INTERRUPT REGISTERS
CENTRAL INTERRUPT CONTROL REGISTER
(CICR)
R230 - Read/Write
Register Group: System
Reset value: 1000 0111 (87h)
7
GCEN TLIP
0
TLI
IEN
IAM
the IEN bit when interrupts are disabled or when
no peripheral can generate interrupts. For example, if the state of IEN is not known in advance,
and its value must be restored from a previous
push of CICR on the stack, use the sequence DI;
POP CICR to make sure that no interrupts are being arbitrated when CICR is modified.
CPL2 CPL1 CPL0
Bit 7 = GCEN: Global Counter Enable.
This bit enables the 16-bit Multifunction Timer peripheral.
0: MFT disabled
1: MFT enabled
Bit 6 = TLIP: Top Level Interrupt Pending.
This bit is set by hardware when Top Level Interrupt (TLI) trigger event occurs. It is cleared by
hardware when a TLI is acknowledged. It can also
be set by software to implement a software TLI.
0: No TLI pending
1: TLI pending
Bit 5 = TLI: Top Level Interrupt.
This bit is set and cleared by software.
0: A Top Level Interrupt is generared when TLIP is
set, only if TLNM=1 in the NICR register (independently of the value of the IEN bit).
1: A Top Level Interrupt request is generated when
IEN=1 and the TLIP bit are set.
Bit 4 = IEN: Interrupt Enable.
This bit is cleared by the interrupt machine cycle
(except for a TLI).
It is set by the iret instruction (except for a return
from TLI).
It is set by the EI instruction.
It is cleared by the DI instruction.
0: Maskable interrupts disabled
1: Maskable Interrupts enabled
Note: The IEN bit can also be changed by software using any instruction that operates on register CICR, however in this case, take care to avoid
spurious interrupts, since IEN cannot be cleared in
the middle of an interrupt arbitration. Only modify
Bit 3 = IAM: Interrupt Arbitration Mode.
This bit is set and cleared by software.
0: Concurrent Mode
1: Nested Mode
Bit 2:0 = CPL[2:0]: Current Priority Level.
These bits define the Current Priority Level.
CPL=0 is the highest priority. CPL=7 is the lowest
priority. These bits may be modified directly by the
interrupt hardware when Nested Interrupt Mode is
used.
EXTERNAL INTERRUPT TRIGGER REGISTER
(EITR)
R242 - Read/Write
Register Page: 0
Reset value: 0000 0000 (00h)
7
0
TED1 TED0 TEC1 TEC0 TEB1 TEB0 TEA1 TEA0
Bit 7 = TED1: INTD1 Trigger Event
Bit 6 = TED0: INTD0 Trigger Event
Bit 5 = TEC1: INTC1 Trigger Event
Bit 4 = TEC0: INTC0 Trigger Event
Bit 3 = TEB1: INTB1 Trigger Event
Bit 2 = TEB0: INTB0 Trigger Event
Bit 1 = TEA1: INTA1 Trigger Event
Bit 0 = TEA0: INTA0 Trigger Event
These bits are set and cleared by software.
0: Select falling edge as interrupt trigger event
1: Select rising edge as interrupt trigger event
53/178
ST92185B - INTERRUPTS
INTERRUPT REGISTERS (Cont’d)
EXTERNAL INTERRUPT PENDING REGISTER
(EIPR)
R243 - Read/Write
Register Page: 0
Reset value: 0000 0000 (00h)
7
IPD1 IPD0
0
IPC1
IPC0 IPB1 IPB0
IPA1 IPA0
Bit 7 = IPD1: INTD1 Interrupt Pending bit
Bit 6 = IPD0: INTD0 Interrupt Pending bit
Bit 5 = IPC1: INTC1 Interrupt Pending bit
Bit 4 = IPC0: INTC0 Interrupt Pending bit
Bit 3 = IPB1: INTB1 Interrupt Pending bit
Bit 2 = IPB0: INTB0 Interrupt Pending bit
Bit 1 = IPA1: INTA1 Interrupt Pending bit
Bit 0 = IPA0: INTA0 Interrupt Pending bit
These bits are set by hardware on occurrence of a
trigger event (as specified in the EITR register)
and are cleared by hardware on interrupt acknowledge. They can also be set by software to implement a software interrupt.
0: No interrupt pending
1: Interrupt pending
EXTERNAL INTERRUPT MASK-BIT REGISTER
(EIMR)
R244 - Read/Write
Register Page: 0
Reset value: 0000 0000 (00h)
7
Bit 3 = IMB1: INTB1 Interrupt Mask
Bit 2 = IMB0: INTB0 Interrupt Mask
Bit 1 = IMA1: INTA1 Interrupt Mask
Bit 0 = IMA0: INTA0 Interrupt Mask
These bits are set and cleared by software.
0: Interrupt masked
1: Interrupt not masked (an interrupt is generated if
the IPxx and IEN bits = 1)
EXTERNAL INTERRUPT PRIORITY
REGISTER (EIPLR)
R245 - Read/Write
Register Page: 0
Reset value: 1111 1111 (FFh)
7
0
PL2D PL1D PL2C PL1C PL2B PL1B PL2A PL1A
Bit 7:6 = PL2D, PL1D: INTD0, D1 Priority Level.
Bit 5:4 = PL2C, PL1C: INTC0, C1 Priority Level.
Bit 3:2 = PL2B, PL1B: INTB0, B1 Priority Level.
Bit 1:0 = PL2A, PL1A: INTA0, A1 Priority Level.
These bits are set and cleared by software.
The priority is a three-bit value. The LSB is fixed by
hardware at 0 for Channels A0, B0, C0 and D0 and
at 1 for Channels A1, B1, C1 and D1.
PL2x
PL1x
0
0
0
1
1
0
1
1
0
IMD1 IMD0 IMC1 IMC0 IMB1 IMB0 IMA1 IMA0
Bit 7 = IMD1: INTD1
Bit 6 = IMD0: INTD0
Bit 5 = IMC1: INTC1
Bit 4 = IMC0: INTC0
54/178
Interrupt Mask
Interrupt Mask
Interrupt Mask
Interrupt Mask
LEVEL
Hardware
bit
0
1
0
1
0
1
0
1
Priority
0 (Highest)
1
2
3
4
5
6
7 (Lowest)
ST92185B - INTERRUPTS
INTERRUPT REGISTERS (Cont’d)
EXTERNAL INTERRUPT VECTOR REGISTER
(EIVR)
R246 - Read/Write
Register Page: 0
Reset value: xxxx 0110b (x6h)
7
V7
0
V6
V5
V4
TLTEV TLIS IAOS EWEN
Bit 7:4 = V[7:4]: Most significant nibble of External
Interrupt Vector.
These bits are not initialized by reset. For a representation of how the full vector is generated from
V[7:4] and the selected external interrupt channel,
refer to Figure 27.
Bit 3 = TLTEV: Top Level Trigger Event bit.
This bit is set and cleared by software.
0: Select falling edge as NMI trigger event
1: Select rising edge as NMI trigger event
Bit 2 = TLIS: Top Level Input Selection.
This bit is set and cleared by software.
0: Watchdog End of Count is TL interrupt source
1: NMI is TL interrupt source
Bit 1 = IA0S: Interrupt Channel A0 Selection.
This bit is set and cleared by software.
0: Watchdog End of Count is INTA0 source
1: External Interrupt pin is INTA0 source
0: WAITN pin disabled
1: WAITN pin enabled (to stretch the external
memory access cycle).
Note: For more details on Wait mode refer to the
section describing the WAITN pin in the External
Memory Chapter.
NESTED INTERRUPT CONTROL (NICR)
R247 - Read/Write
Register Page: 0
Reset value: 0000 0000 (00h)
7
TLNM HL6
0
HL5
HL4
HL3
HL2
HL1
HL0
Bit 7 = TLNM: Top Level Not Maskable.
This bit is set by software and cleared only by a
hardware reset.
0: Top Level Interrupt Maskable. A top level request is generated if the IEN, TLI and TLIP bits
=1
1: Top Level Interrupt Not Maskable. A top level
request is generated if the TLIP bit =1
Bit 6:0 = HL[6:0]: Hold Level x
These bits are set by hardware when, in Nested
Mode, an interrupt service routine at level x is interrupted from a request with higher priority (other
than the Top Level interrupt request). They are
cleared by hardware at the iret execution when
the routine at level x is recovered.
Bit 0 = EWEN: External Wait Enable.
This bit is set and cleared by software.
55/178
ST92185B - INTERRUPTS
INTERRUPT REGISTERS (Cont’d)
EXTERNAL MEMORY REGISTER 2 (EMR2)
R246 - Read/Write
Register Page: 21
Reset value: 0000 1111 (0Fh)
7
0
0
ENCSR
0
0
1
1
1
1
Bit 7, 5:0 = Reserved, keep in reset state. Refer to
the external Memory Interface Chapter.
Bit 6 = ENCSR: Enable Code Segment Register.
This bit is set and cleared by software. It affects
the ST9 CPU behaviour whenever an interrupt request is issued.
0: The CPU works in original ST9 compatibility
mode. For the duration of the interrupt service
routine, ISR is used instead of CSR, and the interrupt stack frame is identical to that of the original ST9: only the PC and Flags are pushed.
This avoids saving the CSR on the stack in the
event of an interrupt, thus ensuring a faster in-
56/178
terrupt response time. The drawback is that it is
not possible for an interrupt service routine to
perform inter-segment calls or jumps: these instructions would update the CSR, which, in this
case, is not used (ISR is used instead). The
code segment size for all interrupt service routines is thus limited to 64K bytes.
1: ISR is only used to point to the interrupt vector
table and to initialize the CSR at the beginning
of the interrupt service routine: the old CSR is
pushed onto the stack together with the PC and
flags, and CSR is then loaded with the contents
of ISR. In this case, iret will also restore CSR
from the stack. This approach allows interrupt
service routines to access the entire 4 Mbytes of
address space; the drawback is that the interrupt response time is slightly increased, because of the need to also save CSR on the
stack. Full compatibility with the original ST9 is
lost in this case, because the interrupt stack
frame is different; this difference, however,
should not affect the vast majority of programs.
ST92185B - RESET AND CLOCK CONTROL UNIT (RCCU)
4 RESET AND CLOCK CONTROL UNIT (RCCU)
4.1 INTRODUCTION
The Reset Control Unit comprises two distinct sections:
– An oscillator that uses an external quartz crystal.
– The Reset/Stop Manager, which detects and
flags Hardware, Software and Watchdog generated resets.
4.2 RESET / STOP MANAGER
The RESET/STOP Manager resets the device
when one of the three following triggering events
occurs:
– A hardware reset, consequence of a low level on
the RESET pin.
– A software reset, consequence of an HALT instruction when enabled.
– A Watchdog end of count.
The RESET input is schmitt triggered.
Note: The memorized Internal Reset (called RESETO) will be maintained active for a duration of
32768 Oscin periods (about 8 ms for a 4 MHz crystal) after the external input is released (set high).
This RESETO internal Reset signal is output on
the I/O port bit P3.7 (active low) during the whole
reset phase until the P3.7 configuration is changed
by software. The true internal reset (to all macrocells) will only be released 511 Reference clock
periods after the Memorized Internal reset is released.
It is possible to know which was the last RESET
triggering event, by reading bits 5 and 6 of register
SDRATH.
Figure 29. Reset Overview
n
RESET
Build-up Counter
RCCU
RESETO
True
Internal
Reset
Memorized
Reset
57/178
ST92185B - RESET AND CLOCK CONTROL UNIT (RCCU)
4.3 OSCILLATOR CHARACTERISTICS
The on-chip oscillator circuit uses an inverting gate
circuit with tri-state output.
Notes: Owing to the Q factor required, Ceramic
Resonators may not provide a reliable oscillator
source.
The oscillator can not support quartz crystal or ceramic working at the third harmonic without external tank circuits.
OSCOUT must not be used to drive external circuits.
Halt mode is set by means of the HALT instruction.
In this mode the parallel resistor, R, is disconnected and the oscillator is disabled. This forces the internal clock to a high level and OSCOUT to a high
impedance state.
To exit the HALT condition and restart the oscillator, an external RESET pulse is required.
It should be noted that, if the Watchdog function is
enabled, a HALT instruction will not disable the oscillator. This to avoid stopping the Watchdog if a
HALT code is executed in error. When this occurs,
the CPU will be reset when the Watchdog times
out or when an external reset is applied.
When an HALT instruction is executed, the main
crystal oscillator is stoped and any spurious clock
are ignored. Other analog systems such as the onchip line PLL or the whole Video chain (Sync Extraction) must be stopped separately by the software as they will induce static consumption.
Figure 30. Crystal Oscillator
CRYSTAL CLOCK
ST9
OSCIN
OSCOUT
CL1
CL2
VR02116A
Note: Depending on the application it may be better not to implement CL1
Figure 31. Internal Oscillator Schematic
HALT
R
ROUT
RIN
OSCOUT
OSCIN
Table 8. Oscillator Transconductance
VR02086A
gm
Min
Typ
Max
mA/V
0.77
1.5
2.4
Figure 32. External Clock
n
EXTERNAL CLOCK
OSCIN
OSCOUT
NC
CLOCK
INPUT
VR02116B
58/178
ST92185B - RESET AND CLOCK CONTROL UNIT (RCCU)
OSCILLATOR CHARACTERISTICS (Cont’d)
The following table is relative to the fundamental
quartz crystal only; assuming:
– Rs: parasitic series resistance of the quartz crystal (upper limit)
– C0: parasitic capacitance of the crystal (upper
limit, ≤ 7 pF)
– C1,C2: maximum total capacitance on pins OSCIN/OSCOUT (value including external capacitance tied to the pin plus the parasitic
capacitance of the board and device).
Table 9. Crystal Specification (C0 ≤ 7 pF)
Freq.
MHz.
CL1=CL2=
39 pF
Rs Max
8
65
4
260
Legend:
Rs: Parasitic Series Resistance of the quartz crystal (upper limit) C0: Parasitic capacitance of the quartz crystal
(upper limit, < 7 pF)
CL1, CL2: Maximum Total Capacitance on pins OSCIN
and OSCOUT (the value includes the external capacitance tied to the pin plus the parasitic capacitance of the
board and of the device)
gm: Transconductance of the oscillator
Note.The tables are relative to the fundamental quartz
crystal only (not ceramic resonator).
59/178
ST92185B - RESET AND CLOCK CONTROL UNIT (RCCU)
4.4 CLOCK CONTROL REGISTERS
WAIT CONTROL REGISTER (WCR)
R252 - Read/Write
Register Page: 0
Reset Value: 0111 1111 (7Fh)
MODE REGISTER (MODER)
R235 - Read/Write
Register Group: E (System)
Reset Value: 1110 0000 (E0h)
7
1
1
DIV2
PRS2
PRS1
PRS0
0
0
7
0
0
Bit 7:6 = Bits described in Device Architecture
chapter.
Bit 5 = DIV2: OSCIN Divided by 2.
This bit controls the divide by 2 circuit which operates on the OSCIN Clock.
0: No division of OSCIN Clock
1: OSCIN clock is internally divided by 2
0
WDGEN WDM2 WDM1 WDM0 WPM2 WPM1 WPM0
Bit 7 = Reserved, read as “0”.
Bit 6 = WDGEN: refer to Timer/Watchdog chapter.
WARNING. Resetting this bit to zero has the effect
of setting the Timer/Watchdog to the Watchdog
mode. Unless this is desired, this must be set to
“1”.
Bit 4:2 = PRS[2:0]: Clock Prescaling.
These bits define the prescaler value used to
prescale CPUCLK from INTCLK. When they are
reset, the CPUCLK is not prescaled, and is equal
to INTCLK; in all other cases, the internal clock is
prescaled by the value of these three bits plus one.
Bit 5:3 = WDM[2:0]: Data Memory Wait Cycles.
These bits contain the number of INTCLK cycles
to be added automatically to external Data memory accesses. WDM = 0 gives no additional wait cycles. WDM = 7 provides the maximum 7 INTCLK
cycles (reset condition).
Bit 1:0 = Bits described in Device Architecture
chapter.
Bit 2:0 = WPM[2:0]: Program Memory Wait Cycles.
These bits contain the number of INTCLK cycles
to be added automatically to external Program
memory accesses. WPM = 0 gives no additional
wait cycles, WPM = 7 provides the maximum 7
INTCLK cycles (reset condition).
Note: The number of clock cycles added refers to
INTCLK and NOT to CPUCLK.
WARNING. The reset value of the Wait Control
Register gives the maximum number of Wait cycles for external memory. To get optimum performance from the ST9 when used in single-chip
mode (no external memory) the user should write
the WDM2,1,0 and WPM2,1,0 bits to “0”.
60/178
ST92185B - RESET AND CLOCK CONTROL UNIT (RCCU)
4.5 RESET CONTROL UNIT REGISTERS
The RCCU consists of two registers. They are
PCONF and SDRATH. Unless otherwise stated,
unused register bits must be kept in their reset value in order to avoid problems with the device behaviour.
PLL CONFIGURATION REGISTER (PCONF)
R251 - Read/Write
Register Page: 55
Reset value: 0000 0111 (07h)
CLOCK SLOW DOWN UNIT RATIO REGISTER
(SDRATH)
R254 - Read/Write
Register Page: 55
Reset value:
0010 0xxx (2xh) after software reset
0100 0xxx (4xh) after watchdog reset
0000 0000 (00h) after external reset
7
0 WDGRES SFTRES
7
SRESEN
0
0
0
x
x
x
0
0
0
0
0
1
1
1
Bit 7= SRESEN. Software Reset Enable.
0: RCCU PLL and CSDU are turned off when a
HALT instruction is performed.
1: RCCU will reset the microcontroller when a
HALT instruction is performed.
Bit 6:0= Reserved bits. Leave in their reset state.
Bit 7 = Reserved bit. Leave in its reset state.
Bit 6 = WDGRES. Watchdog Reset. WDGRES is
automatically set if the last reset was a watchdog
Reset. This is a read only bit.
Bit 5 = SFTRES. Software Reset. SFTRES is automatically set if the last reset was a software Reset. This is a read only bit.
Bit 4:0 = Reserved bits. Please leave in their reset
state.
61/178
ST92185B - TIMING AND CLOCK CONTROLLER
5 TIMING AND CLOCK CONTROLLER
5.1 FREQUENCY MULTIPLIERS
Three on-chip frequency multipliers generate the
proper frequencies for: the Core/Real time Peripherals, the Display related time base.
For both the Core and the Display frequency multipliers, a 4 bit programmable feed-back counter
allows the adjustment of the multiplying factor to
the application need (a 4 MHz or 8 MHz crystal is
assumed).
Figure 33. Timing and Clock Controller Block Diagram
Hsync
SKHPLS
SKDIV2
PXFM
Async.
Handler
Frequency
Multiplier
SKWEN
Divide
by 2
Skew Corrector
Synchronized DOTCK / 2 to Display
(2X Pixel clock for 1X width characters)
(Synchronized DOTCK) SKDIV2
Divide
by 2
SKWL(3:0)
4 MHz real time
MCFM
Frequency
Multiplier
SLDIV2
Divide
by 2
FMEN
FML(3:0)
Divide
by 2
Memory Wait
BREQ
WFI
OSCIN
Fimf
Xtal
Oscillator
Div-2
OSCOUT
FMEN
FMSL
Asynch.
Handler
Main Clock Controller
62/178
to Display Storage RAM (TRI)
Prescaler
1 to 8
Clock
Control
CPUCLK
INTCLK
MODER.5
ST9 Clock Control Unit (RCCU)
VR02095A
ST92185B - TIMING AND CLOCK CONTROLLER
FREQUENCY MULTIPLIERS (Cont’d)
For the Off-chip filter components please refer to
the Required External Components figure provided in the first section of the data sheet.
The frequency multipliers are off during and upon
exiting from the reset phase. The user must program the desired multiplying factor, start the multiplier and then wait for its stability.
Once the Core/Peripherals multiplier is stabilized,
the Main Clock controller can be re-programmed
(through the FMSL bit, MCCR.6) to provide the final frequency (INTCLK) to the CPU.
The frequency multipliers are automatically
switched off when the µP enters in HALT mode
(the HALT mode forces the control register to its
reset status).
Table 10. Examples of CPU speed choice
Crystal
Frequency
4 MHz
FML
(3:0)
4
Internal Frequency
(Fimf)
10 MHz
4 MHz
4 MHz
4 MHz
4 MHz
4 MHz
5
6
7
8
11
12 MHz
14 MHz
16 MHz
18 MHz
24 MHz
Note: 24 MHz is the max. CPU authorized frequency.
Table 11. DOTCK/2 frequency choices
SKW
(3:0)
8
9
10
11
(*) Preferred values for 4/3.
DOTCK/2
18 MHz
20 MHz(*)
22 MHz
24 MHz (**)
(**) 16/9 screen formats.
Note: 18 MHz is the min. DOTCK/2 authorized frequency.
Table 12. External PLL Filter Stabilisation time
Clock Pin Name
MCFM
PXFM
Clock Name
Main Clock PLL Filter Input Pin
Pixel Clock PLL Filter Input Pin
Control Register
MCCR
PXCCR
Stabilization Period
35 ms.
35 ms
63/178
ST92185B - TIMING AND CLOCK CONTROLLER
Figure 34. Programming the MCCR
Set the PLL frequency
FML (3:0)
Example:
spp
Start the PLL by setting
FMEN = 1
#27h ;Set the page
ld MCCR, #04h ;Set FML bits to the value needed e.g. 10 MHz
or MCCR, #80h ;Starts the PLL
Wait for Clock
Stabilization
Wait for stabilization time
or MCCR, #40h ;Validate the PLL as the main CPU Clock
Validate PLL as Main
CPU Clock
Figure 35. Programming the SKCCR, PXCCR
Set the PLL frequency
SKW (3:0)
Example:
spp
Start the PLL by setting
SKWEN = 1
#27h ;Set the page
ld SKCCR, #04h ;Set SKW bits to the value needed
or SKCCR, #80h ;Starts the PLL
Wait for Clock
Stabilization
Validate PLL is fed to
TDSRAM and OSD
64/178
Wait for stabilization time
or PXCCR, #80h ;PLL is fed as DOTCK to the TDSRAM & OSDPLL
ST92185B - TIMING AND CLOCK CONTROLLER
5.2 REGISTER DESCRIPTION
MAIN CLOCK CONTROL REGISTER (MCCR)
R253 - Read/ Write
Register Page: 39
Reset value: 0000 0000 (00h)
7
6
FMEN FMSL
5
4
0
0
3
2
1
0
FML3 FML2 FML1 FML0
The HALT mode forces the register to its initialization state.
Bit 7 = FMEN. Frequency Multiplier Enable bit.
0: FM disabled (reset state), low-power consumption mode.
1: FM is enabled, providing clock to the CPU. The
FMEN bit must be set only after programming
the FML(3:0) bits.
Bit 6= FMSL. Frequency Multiplier Select bit.
This bit controls the choice of the ST9+ core internal frequency between the external crystal frequency and the Main Clock issued by the frequency multiplier.
In order to secure the application, the ST9+ core
internal frequency is automatically switched back
to the external crystal frequency if the frequency
multiplier is switched off (FMEN =0) regardless of
the value of the FMSL bit. Care must be taken to
reset the FMSL bit before any frequency multiplier
can restart (FMEN set back to 1).
After reset, the external crystal frequency is always sent to the ST9+ Core.
Bit 5:4 = These bits are reserved.
SKEW CLOCK CONTROL REGISTER (SKCCR)
R254 - Read/ Write
Register Page: 39
Reset value: 0000 0000 (00h)
7
6
SKW
SKDIV2
EN
5
4
0
0
3
2
1
0
SKW3 SKW2 SKW1 SKW0
The HALT mode forces the register to its initialization state.
Bit 7= SKWEN. Frequency Multiplier Enable bit.
0: FM disabled (reset state), low-power consumption mode.
1: FM is enabled, supplying the clock to the Skew
corrector. The SKWEN bit must be set only after
programming the SKW(3-0) bits.
Bit 6= SKDIV2. Divide-by-2 enable
This bit determines whether a divide-by-2 downscaling factor is applied to the output of the Skew
Corrector.
0 = Divide-by-2 enabled
1 = Divide-by-2 disabled
Bit 5:4 = These bits are reserved.
Bit 3:0 = SKW[3:0]. Frequency bits
These 4 bits program the down-counter inserted in
the feedback loop of the Frequency Multiplier
which generates the internal multiplied frequency
DOTCK. The DOTCK value is calculated as follows :
F(DOTCK) = Crystal frequency * [ (SKW(3:0) + 1) ]
Bit 3:0 = FML[3:0] Frequency bits.
These 4 bits program the down-counter inserted in
the feed-back loop of the Frequency Multiplier
which generates the internal multiplied frequency
Fimf. The Fimf value is calculated as follows :
Fimf = Crystal frequency * [ (FML(3:0) + 1) ] /2
65/178
ST92185B - TIMING AND CLOCK CONTROLLER
REGISTER DESCRIPTION (Cont’d)
Bit 7:5 = These bits are reserved.
PLL CLOCK CONTROL REGISTER (PXCCR)
R251 - Read/Write
Register Page: 39
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
PXCE
0
0
0
0
0
0
0
Bit 7= PXCE. Pixel Clock Enable bit.
0: Pixel and TDSRAM interface clocks are blocked
1: Pixel clock is sent to the display controller and
TDSRAM interface.
Bit 6:0= These bits are reserved.
SLICER
CLOCK
CONTROL
(SLCCR)
R252 - Read/ Write
Register Page: 39
Reset value: 0000 0000 (00h)
REGISTER
7
6
5
4
3
2
1
0
0
0
0
VMOD
0
0
0
0
The HALT mode forces the register to its initialization state.
66/178
Bit 4= VMOD: Video mode selection.
This bit is used to select either 50Hz or 60Hz video
mode. It is set and cleared by software.
0: 50 Hz.
1: 60 Hz.
Bit 3:0= These bits are reserved.
5.2.1 Register Mapping
The Timing Controller has 4 dedicated registers,
mapped in a ST9+ register file page (the page address is 39 (27h)), as follows :
FEh
FDh
FCh
FBh
Page 39 (27h)
Skew Corrector Control Register
Main Clock Control Register
SLicer Clock Control Register
Pixel Clock Control Register
SKCCR
MCCR
SLCCR
PXCCR
ST92185B - I/O PORTS
6 I/O PORTS
6.1 INTRODUCTION
6.2 SPECIFIC PORT CONFIGURATIONS
ST9 devices feature flexible individually programmable multifunctional input/output lines. Refer to
the Pin Description Chapter for specific pin allocations. These lines, which are logically grouped as
8-bit ports, can be individually programmed to provide digital input/output and analog input, or to
connect input/output signals to the on-chip peripherals as alternate pin functions. All ports can be individually configured as an input, bi-directional,
output or alternate function. In addition, pull-ups
can be turned off for open-drain operation, and
weak pull-ups can be turned on in their place, to
avoid the need for off-chip resistive pull-ups. Ports
configured as open drain must never have voltage
on the port pin exceeding VDD (refer to the Electrical Characteristics section). Depending on the
specific port, input buffers are software selectable
to be TTL or CMOS compatible, however on Schmitt trigger ports, no selection is possible.
Refer to the Pin Description chapter for a list of the
specific port styles and reset values.
6.3 PORT CONTROL REGISTERS
Each port is associated with a Data register
(PxDR) and three Control registers (PxC0, PxC1,
PxC2). These define the port configuration and allow dynamic configuration changes during program execution. Port Data and Control registers
are mapped into the Register File as shown in Figure 1. Port Data and Control registers are treated
just like any other general purpose register. There
are no special instructions for port manipulation:
any instruction that can address a register, can address the ports. Data can be directly accessed in
the port register, without passing through other
memory or “accumulator” locations.
Figure 36. I/O Register Map
GROUP E
System
Registers
E5h
E4h
E3h
E2h
E1h
E0h
P5DR
P4DR
P3DR
P2DR
P1DR
P0DR
R229
R228
R227
R226
R225
R224
FFh
FEh
FDh
FCh
FBh
FAh
F9h
F8h
F7h
F6h
F5h
F4h
F3h
F2h
F1h
F0h
GROUP F
PAGE 2
Reserved
P3C2
P3C1
P3C0
Reserved
P2C2
P2C1
P2C0
Reserved
P1C2
P1C1
P1C0
Reserved
P0C2
P0C1
P0C0
GROUP F
PAGE 3
P7DR
P7C2
P7C1
P7C0
P6DR
P6C2
P6C1
P6C0
Reserved
P5C2
P5C1
P5C0
Reserved
P4C2
P4C1
P4C0
GROUP F
PAGE 43
P9DR
P9C2
P9C1
P9C0
P8DR
P8C2
P8C1
P8C0
Reserved
R255
R254
R253
R252
R251
R250
R249
R248
R247
R246
R245
R244
R243
R242
R241
R240
67/178
ST92185B - I/O PORTS
PORT CONTROL REGISTERS (Cont’d)
During Reset, ports with weak pull-ups are set in
bidirectional/weak pull-up mode and the output
Data Register is set to FFh. This condition is also
held after Reset, except for Ports 0 and 1 in ROMless devices, and can be redefined under software
control.
Bidirectional ports without weak pull-ups are set in
high impedance during reset. To ensure proper
levels during reset, these ports must be externally
connected to either V DD or VSS through external
pull-up or pull-down resistors.
Other reset conditions may apply in specific ST9
devices.
6.4 INPUT/OUTPUT BIT CONFIGURATION
By programming the control bits PxC0.n and
PxC1.n (see Figure 2) it is possible to configure bit
Px.n as Input, Output, Bidirectional or Alternate
Function Output, where X is the number of the I/O
port, and n the bit within the port (n = 0 to 7).
When programmed as input, it is possible to select
the input level as TTL or CMOS compatible by programming the relevant PxC2.n control bit.
This option is not available on Schmitt trigger ports.
The output buffer can be programmed as pushpull or open-drain.
A weak pull-up configuration can be used to avoid
external pull-ups when programmed as bidirectional (except where the weak pull-up option has
been permanently disabled in the pin hardware assignment).
68/178
Each pin of an I/O port may assume software programmable Alternate Functions (refer to the device Pin Description and to Section 1.5). To output
signals from the ST9 peripherals, the port must be
configured as AF OUT. On ST9 devices with A/D
Converter(s), configure the ports used for analog
inputs as AF IN.
The basic structure of the bit Px.n of a general purpose port Px is shown in Figure 3.
Independently of the chosen configuration, when
the user addresses the port as the destination register of an instruction, the port is written to and the
data is transferred from the internal Data Bus to
the Output Master Latches. When the port is addressed as the source register of an instruction,
the port is read and the data (stored in the Input
Latch) is transferred to the internal Data Bus.
When Px.n is programmed as an Input:
(See Figure 4).
– The Output Buffer is forced tristate.
– The data present on the I/O pin is sampled into
the Input Latch at the beginning of each instruction execution.
– The data stored in the Output Master Latch is
copied into the Output Slave Latch at the end of
the execution of each instruction. Thus, if bit Px.n
is reconfigured as an Output or Bidirectional, the
data stored in the Output Slave Latch will be reflected on the I/O pin.
ST92185B - I/O PORTS
INPUT/OUTPUT BIT CONFIGURATION (Cont’d)
Figure 37. Control Bits
Bit 7
Bit n
Bit 0
PxC2
PxC27
PxC2n
PxC20
PxC1
PxC17
PxC1n
PxC10
PxC0
PxC07
PxC0n
PxC00
n
Table 13. Port Bit Configuration Table (n = 0, 1... 7; X = port number)
General Purpose I/O Pins
A/D Pins
0
0
0
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
PXn Configuration
BID
BID
OUT
OUT
IN
IN
AF OUT
AF OUT
AF IN
PXn Output Type
WP OD
OD
PP
OD
HI-Z
HI-Z
PP
OD
HI-Z(1)
TTL
TTL
TTL
TTL
CMOS
TTL
TTL
TTL
PXn Input Type
(or Schmitt
(or Schmitt
(or Schmitt
(or Schmitt
(or Schmitt
(or Schmitt
(or Schmitt
(or Schmitt
Trigger)
Trigger)
Trigger)
Trigger)
Trigger)
Trigger)
Trigger)
Trigger)
PXC2n
PXC1n
PXC0n
(1)
Analog
Input
For A/D Converter inputs.
Legend:
X
=
n
=
AF
=
BID =
CMOS=
HI-Z =
IN
=
OD
=
OUT =
PP
=
TTL =
WP =
Port
Bit
Alternate Function
Bidirectional
CMOS Standard Input Levels
High Impedance
Input
Open Drain
Output
Push-Pull
TTL Standard Input Levels
Weak Pull-up
69/178
ST92185B - I/O PORTS
INPUT/OUTPUT BIT CONFIGURATION (Cont’d)
Figure 38. Basic Structure of an I/O Port Pin
I/O PIN
PUSH-PULL
TRISTATE
OPEN DRAIN
WEAK PULL-UP
TTL / CMOS
(or Schmitt Trigger)
TO PERIPHERAL
INPUTS AND
INTERRUPTS
OUTPUT SLAVE LATCH
FROM
PERIPHERAL
OUTPUT
ALTERNATE
FUNCTION
INPUT
BIDIRECTIONAL
ALTERNATE
FUNCTION
OUTPUT
INPUT
OUTPUT
BIDIRECTIONAL
OUTPUT MASTER LATCH
INPUT LATCH
INTERNAL DATA BUS
Figure 40. Output Configuration
Figure 39. Input Configuration
I/O PIN
I/O PIN
OPEN DRAIN
PUSH-PULL
TTL / CMOS
(or Schmitt Trigger)
TRISTATE
TO PERIPHERAL
INPUTS AND
INTERRUPTS
OUTPUT SLAVE LATCH
OUTPUT MASTER LATCH
70/178
TO PERIPHERAL
INPUTS AND
INTERRUPTS
OUTPUT SLAVE LATCH
INPUT LATCH
OUTPUT MASTER LATCH
INTERNAL DATA BUS
n
n
TTL
(or Schmitt Trigger)
INPUT LATCH
INTERNAL DATA BUS
n
ST92185B - I/O PORTS
INPUT/OUTPUT BIT CONFIGURATION (Cont’d)
When Px.n is programmed as an Output:
(Figure 5)
– The Output Buffer is turned on in an Open-drain
or Push-pull configuration.
– The data stored in the Output Master Latch is
copied both into the Input Latch and into the Output Slave Latch, driving the I/O pin, at the end of
the execution of the instruction.
When Px.n is programmed as Bidirectional:
(Figure 6)
– The Output Buffer is turned on in an Open-Drain
or Weak Pull-up configuration (except when disabled in hardware).
– The data present on the I/O pin is sampled into
the Input Latch at the beginning of the execution
of the instruction.
– The data stored in the Output Master Latch is
copied into the Output Slave Latch, driving the I/
O pin, at the end of the execution of the instruction.
WARNING: Due to the fact that in bidirectional
mode the external pin is read instead of the output
latch, particular care must be taken with arithmetic/logic and Boolean instructions performed on a
bidirectional port pin.
These instructions use a read-modify-write sequence, and the result written in the port register
depends on the logical level present on the external pin.
This may bring unwanted modifications to the port
output register content.
For example:
Port register content, 0Fh
external port value, 03h
(Bits 3 and 2 are externally forced to 0)
A bset instruction on bit 7 will return:
Port register content, 83h
external port value, 83h
(Bits 3 and 2 have been cleared).
To avoid this situation, it is suggested that all operations on a port, using at least one bit in bidirectional mode, are performed on a copy of the port
register, then transferring the result with a load instruction to the I/O port.
When Px.n is programmed as a digital Alternate Function Output:
(Figure 7)
– The Output Buffer is turned on in an Open-Drain
or Push-Pull configuration.
– The data present on the I/O pin is sampled into
the Input Latch at the beginning of the execution
of the instruction.
– The signal from an on-chip function is allowed to
load the Output Slave Latch driving the I/O pin.
Signal timing is under control of the alternate
function. If no alternate function is connected to
Px.n, the I/O pin is driven to a high level when in
Push-Pull configuration, and to a high impedance state when in open drain configuration.
Figure 41. Bidirectional Configuration
I/O PIN
WEAK PULL-UP
OPEN DRAIN
TTL
(or Schmitt Trigger)
TO PERIPHERAL
INPUTS AND
OUTPUT SLAVE LATCH
INTERRUPTS
OUTPUT MASTER LATCH
INPUT LATCH
INTERNAL DATA BUS
n
n
Figure 42. Alternate Function Configuration
I/O PIN
OPEN DRAIN
PUSH-PULL
TTL
(or Schmitt Trigger)
TO PERIPHERAL
INPUTS AND
OUTPUT SLAVE LATCH
INTERRUPTS
FROM
PERIPHERAL
OUTPUT
INPUT LATCH
INTERNAL DATA BUS
n
n
n
n
n
n
71/178
ST92185B - I/O PORTS
6.5 ALTERNATE FUNCTION ARCHITECTURE
Each I/O pin may be connected to three different
types of internal signal:
– Data bus Input/Output
– Alternate Function Input
– Alternate Function Output
6.5.1 Pin Declared as I/O
A pin declared as I/O, is connected to the I/O buffer. This pin may be an Input, an Output, or a bidirectional I/O, depending on the value stored in
(PxC2, PxC1 and PxC0).
6.5.2 Pin Declared as an Alternate Function
Input
A single pin may be directly connected to several
Alternate Function inputs. In this case, the user
must select the required input mode (with the
PxC2, PxC1, PxC0 bits) and enable the selected
Alternate Function in the Control Register of the
peripheral. No specific port configuration is required to enable an Alternate Function input, since
the input buffer is directly connected to each alternate function module on the shared pin. As more
than one module can use the same input, it is up to
the user software to enable the required module
as necessary. Parallel I/Os remain operational
even when using an Alternate Function input. The
exception to this is when an I/O port bit is permanently assigned by hardware as an A/D bit. In this
case , after software programming of the bit in AFOD-TTL, the Alternate function output is forced to
logic level 1. The analog voltage level on the corresponding pin is directly input to the A/D (See Figure 8).
6.5.3 Pin Declared as an Alternate Function
Output
The user must select the AF OUT configuration
using the PxC2, PxC1, PxC0 bits. Several Alternate Function outputs may drive a common pin. In
such case, the Alternate Function output signals
are logically ANDed before driving the common
pin. The user must therefore enable the required
Alternate Function Output by software.
WARNING: When a pin is connected both to an alternate function output and to an alternate function
input, it should be noted that the output signal will
always be present on the alternate function input.
6.6 I/O STATUS AFTER WFI, HALT AND RESET
The status of the I/O ports during the Wait For Interrupt, Halt and Reset operational modes is
shown in the following table. The External Memory
Interface ports are shown separately. If only the internal memory is being used and the ports are acting as I/O, the status is the same as shown for the
other I/O ports.
Mode
WFI
Figure 43. A/D Input Configuration
I/O PIN
TOWARDS
A/D CONVERTER
TRISTATE
HALT
GND
RESET
INPUT
BUFFER
OUTPUT SLAVE LATCH
OUTPUT MASTER LATCH
INPUT LATCH
INTERNAL DATA BUS
72/178
Ext. Mem - I/O Ports
P1, P2,
P0
P6, P9
High Impedance or next
address (depending on
Next
the last
Address
memory operation performed on
Port)
High ImpedNext
ance
Address
I/O Ports
Not Affected (clock
outputs running)
Not Affected (clock
outputs stopped)
Bidirectional Weak
Alternate function push- Pull-up (High impedance when disapull (ROMless device)
bled in hardware).
ST92185B - TIMER/WATCHDOG (WDT)
7 ON-CHIP PERIPHERALS
7.1 TIMER/WATCHDOG (WDT)
Important Note: This chapter is a generic description of the WDT peripheral. However depending
on the ST9 device, some or all of WDT interface
signals described may not be connected to external pins. For the list of WDT pins present on the
ST9 device, refer to the device pinout description
in the first section of the data sheet.
7.1.1 Introduction
The Timer/Watchdog (WDT) peripheral consists of
a programmable 16-bit timer and an 8-bit prescaler. It can be used, for example, to:
– Generate periodic interrupts
– Measure input signal pulse widths
– Request an interrupt after a set number of events
– Generate an output signal waveform
– Act as a Watchdog timer to monitor system integrity
The main WDT registers are:
– Control register for the input, output and interrupt
logic blocks (WDTCR)
– 16-bit counter register pair (WDTHR, WDTLR)
– Prescaler register (WDTPR)
The hardware interface consists of up to five signals:
– WDIN External clock input
– WDOUT Square wave or PWM signal output
– INT0 External interrupt input
– NMI Non-Maskable Interrupt input
– HW0SW1 Hardware/Software Watchdog enable.
Figure 44. Timer/Watchdog Block Diagram
INEN INMD1 INMD2
WDIN1
INPUT
&
CLOCK CONTROL LOGIC
MUX
WDT
CLOCK
WDTPR
8-BIT PRESCALER
WDTRH, WDTRL
16-BIT
DOWNCOUNTER
END OF
COUNT
INTCLK/4
OUTMD
WROUT
OUTEN
OUTPUT CONTROL LOGIC
NMI 1
INT01
WDOUT1
HW0SW11
MUX
WDGEN
INTERRUPT
IAOS
TLIS
CONTROL LOGIC
RESET
TOP LEVEL INTERRUPT REQUEST
1
Pin not present on some ST9 devices.
INTA0 REQUEST
73/178
ST92185B - TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
7.1.2 Functional Description
7.1.2.1 External Signals
The HW0SW1 pin can be used to permanently enable Watchdog mode. Refer to Section 0.1.3.1.
The WDIN Input pin can be used in one of four
modes:
– Event Counter Mode
– Gated External Input Mode
– Triggerable Input Mode
– Retriggerable Input Mode
The WDOUT output pin can be used to generate a
square wave or a Pulse Width Modulated signal.
An interrupt, generated when the WDT is running
as the 16-bit Timer/Counter, can be used as a Top
Level Interrupt or as an interrupt source connected
to channel A0 of the external interrupt structure
(replacing the INT0 interrupt input).
The counter can be driven either by an external
clock, or internally by INTCLK divided by 4.
7.1.2.2 Initialisation
The prescaler (WDTPR) and counter (WDTRL,
WDTRH) registers must be loaded with initial values before starting the Timer/Counter. If this is not
done, counting will start with reset values.
7.1.2.3 Start/Stop
The ST_SP bit enables downcounting. When this
bit is set, the Timer will start at the beginning of the
following instruction. Resetting this bit stops the
counter.
If the counter is stopped and restarted, counting
will resume from the last value unless a new constant has been entered in the Timer registers
(WDTRL, WDTRH).
A new constant can be written in the WDTRH,
WDTRL, WDTPR registers while the counter is
running. The new value of the WDTRH, WDTRL
registers will be loaded at the next End of Count
(EOC) condition while the new value of the
WDTPR register will be effective immediately.
End of Count is when the counter is 0.
When Watchdog mode is enabled the state of the
ST_SP bit is irrelevant.
74/178
7.1.2.4 Single/Continuous Mode
The S_C bit allows selection of single or continuous mode.This Mode bit can be written with the
Timer stopped or running. It is possible to toggle
the S_C bit and start the counter with the same instruction.
Single Mode
On reaching the End Of Count condition, the Timer
stops, reloads the constant, and resets the Start/
Stop bit. Software can check the current status by
reading this bit. To restart the Timer, set the Start/
Stop bit.
Note: If the Timer constant has been modified during the stop period, it is reloaded at start time.
Continuous Mode
On reaching the End Of Count condition, the counter automatically reloads the constant and restarts.
It is stopped only if the Start/Stop bit is reset.
7.1.2.5 Input Section
If the Timer/Counter input is enabled (INEN bit) it
can count pulses input on the WDIN pin. Otherwise it counts the internal clock/4.
For instance, when INTCLK = 24MHz, the End Of
Count rate is:
2.79 seconds for Maximum Count
(Timer Const. = FFFFh, Prescaler Const. = FFh)
166 ns for Minimum Count
(Timer Const. = 0000h, Prescaler Const. = 00h)
The Input pin can be used in one of four modes:
– Event Counter Mode
– Gated External Input Mode
– Triggerable Input Mode
– Retriggerable Input Mode
The mode is configurable in the WDTCR.
7.1.2.6 Event Counter Mode
In this mode the Timer is driven by the external
clock applied to the input pin, thus operating as an
event counter. The event is defined as a high to
low transition of the input signal. Spacing between
trailing edges should be at least 8 INTCLK periods
(or 333ns with INTCLK = 24MHz).
Counting starts at the next input event after the
ST_SP bit is set and stops when the ST_SP bit is
reset.
ST92185B - TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
7.1.2.7 Gated Input Mode
This mode can be used for pulse width measurement. The Timer is clocked by INTCLK/4, and is
started and stopped by means of the input pin and
the ST_SP bit. When the input pin is high, the Timer counts. When it is low, counting stops. The
maximum input pin frequency is equivalent to
INTCLK/8.
7.1.2.8 Triggerable Input Mode
The Timer (clocked internally by INTCLK/4) is
started by the following sequence:
– setting the Start-Stop bit, followed by
– a High to Low transition on the input pin.
To stop the Timer, reset the ST_SP bit.
7.1.2.9 Retriggerable Input Mode
In this mode, the Timer (clocked internally by
INTCLK/4) is started by setting the ST_SP bit. A
High to Low transition on the input pin causes
counting to restart from the initial value. When the
Timer is stopped (ST_SP bit reset), a High to Low
transition of the input pin has no effect.
7.1.2.10 Timer/Counter Output Modes
Output modes are selected by means of the OUTEN (Output Enable) and OUTMD (Output Mode)
bits of the WDTCR register.
No Output Mode
(OUTEN = “0”)
The output is disabled and the corresponding pin
is set high, in order to allow other alternate functions to use the I/O pin.
Square Wave Output Mode
(OUTEN = “1”, OUTMD = “0”)
The Timer outputs a signal with a frequency equal
to half the End of Count repetition rate on the WDOUT pin. With an INTCLK frequency of 20MHz,
this allows a square wave signal to be generated
whose period can range from 400ns to 6.7 seconds.
Pulse Width Modulated Output Mode
(OUTEN = “1”, OUTMD = “1”)
The state of the WROUT bit is transferred to the
output pin (WDOUT) at the End of Count, and is
held until the next End of Count condition. The
user can thus generate PWM signals by modifying
the status of the WROUT pin between End of
Count events, based on software counters decremented by the Timer Watchdog interrupt.
7.1.3 Watchdog Timer Operation
This mode is used to detect the occurrence of a
software fault, usually generated by external interference or by unforeseen logical conditions, which
causes the application program to abandon its
normal sequence of operation. The Watchdog,
when enabled, resets the MCU, unless the program executes the correct write sequence before
expiry of the programmed time period. The application program must be designed so as to correctly write to the WDTLR Watchdog register at regular intervals during all phases of normal operation.
7.1.3.1
Hardware
Watchdog/Software
Watchdog
The HW0SW1 pin (when available) selects Hardware Watchdog or Software Watchdog.
If HW0SW1 is held low:
– The Watchdog is enabled by hardware immediately after an external reset. (Note: Software reset or Watchdog reset have no effect on the
Watchdog enable status).
– The initial counter value (FFFFh) cannot be modified, however software can change the prescaler
value on the fly.
– The WDGEN bit has no effect. (Note: it is not
forced low).
If HW0SW1 is held high, or is not present:
– The Watchdog can be enabled by resetting the
WDGEN bit.
7.1.3.2 Starting the Watchdog
In Watchdog mode the Timer is clocked by
INTCLK/4.
If the Watchdog is software enabled, the time base
must be written in the timer registers before entering Watchdog mode by resetting the WDGEN bit.
Once reset, this bit cannot be changed by software.
If the Watchdog is hardware enabled, the time
base is fixed by the reset value of the registers.
Resetting WDGEN causes the counter to start, regardless of the value of the Start-Stop bit.
In Watchdog mode, only the Prescaler Constant
may be modified.
If the End of Count condition is reached a System
Reset is generated.
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ST92185B - TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
7.1.3.3 Preventing Watchdog System Reset
In order to prevent a system reset, the sequence
AAh, 55h must be written to WDTLR (Watchdog
Timer Low Register). Once 55h has been written,
the Timer reloads the constant and counting restarts from the preset value.
To reload the counter, the two writing operations
must be performed sequentially without inserting
other instructions that modify the value of the
WDTLR register between the writing operations.
The maximum allowed time between two reloads
of the counter depends on the Watchdog timeout
period.
7.1.3.4 Non-Stop Operation
In Watchdog Mode, a Halt instruction is regarded
as illegal. Execution of the Halt instruction stops
further execution by the CPU and interrupt acknowledgment, but does not stop INTCLK, CPUCLK or the Watchdog Timer, which will cause a
System Reset when the End of Count condition is
reached. Furthermore, ST_SP, S_C and the Input
Mode selection bits are ignored. Hence, regardless of their status, the counter always runs in
Continuous Mode, driven by the internal clock.
The Output mode should not be enabled, since in
this context it is meaningless.
Figure 45. Watchdog Timer Mode
COUNT
VALUE
TIMER START COUNTING
RESET
WRITE WDTRH,WDTRL
WDGEN=0
WRITE AAh,55h
INTO WDTRL
PRODUCE
COUNT RELOAD
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SOFTWARE FAIL
(E.G. INFINITE LOOP)
OR PERIPHERAL FAIL
VA00220
ST92185B - TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
7.1.4 WDT Interrupts
The Timer/Watchdog issues an interrupt request
at every End of Count, when this feature is enabled.
A pair of control bits, IA0S (EIVR.1, Interrupt A0 selection bit) and TLIS (EIVR.2, Top Level Input Selection bit) allow the selection of 2 interrupt sources
(Timer/Watchdog End of Count, or External Pin)
handled in two different ways, as a Top Level Non
Maskable Interrupt (Software Reset), or as a
source for channel A0 of the external interrupt logic.
A block diagram of the interrupt logic is given in
Figure 3.
Note: Software traps can be generated by setting
the appropriate interrupt pending bit.
Table 1 below, shows all the possible configurations of interrupt/reset sources which relate to the
Timer/Watchdog.
A reset caused by the watchdog will set bit 6,
WDGRES of R242 - Page 55 (Clock Flag Register). See section CLOCK CONTROL REGISTERS.
Figure 46. Interrupt Sources
TIMER WATCHDOG
RESET
WDGEN (WCR.6)
0
MUX
INT0
INTA0 REQUEST
1
IA0S (EIVR.1)
0
TOP LEVEL
INTERRUPT REQUEST
MUX
NMI
1
TLIS (EIVR.2)
VA00293
Table 14. Interrupt Configuration
Control Bits
Enabled Sources
Operating Mode
WDGEN
IA0S
TLIS
Reset
INTA0
Top Level
0
0
0
0
0
0
1
1
0
1
0
1
WDG/Ext Reset
WDG/Ext Reset
WDG/Ext Reset
WDG/Ext Reset
SW TRAP
SW TRAP
Ext Pin
Ext Pin
SW TRAP
Ext Pin
SW TRAP
Ext Pin
Watchdog
Watchdog
Watchdog
Watchdog
1
1
1
1
0
0
1
1
0
1
0
1
Timer
Timer
Ext Pin
Ext Pin
Timer
Ext Pin
Timer
Ext Pin
Timer
Timer
Timer
Timer
Ext
Ext
Ext
Ext
Reset
Reset
Reset
Reset
Legend:
WDG = Watchdog function
SW TRAP = Software Trap
Note: If IA0S and TLIS = 0 (enabling the Watchdog EOC as interrupt source for both Top Level and INTA0
interrupts), only the INTA0 interrupt is taken into account.
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ST92185B - TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
7.1.5 Register Description
The Timer/Watchdog is associated with 4 registers
mapped into Group F, Page 0 of the Register File.
WDTHR: Timer/Watchdog High Register
WDTLR: Timer/Watchdog Low Register
WDTPR: Timer/Watchdog Prescaler Register
WDTCR: Timer/Watchdog Control Register
Three additional control bits are mapped in the following registers on Page 0:
Watchdog Mode Enable, (WCR.6)
Top Level Interrupt Selection, (EIVR.2)
Interrupt A0 Channel Selection, (EIVR.1)
Note: The registers containing these bits also contain other functions. Only the bits relevant to the
operation of the Timer/Watchdog are shown here.
Counter Register
This 16-bit register (WDTLR, WDTHR) is used to
load the 16-bit counter value. The registers can be
read or written “on the fly”.
TIMER/WATCHDOG HIGH REGISTER (WDTHR)
R248 - Read/Write
Register Page: 0
Reset value: 1111 1111 (FFh)
7
R15
0
R14
R13
R12
R11
R10
R9
R8
Bits 7:0 = R[15:8] Counter Most Significant Bits .
TIMER/WATCHDOG LOW REGISTER (WDTLR)
R249 - Read/Write
Register Page: 0
Reset value: 1111 1111b (FFh)
7
R7
7
0
PR7
PR6
PR5
PR4
PR3
PR2
PR1
PR0
Bits 7:0 = PR[7:0] Prescaler value.
A programmable value from 1 (00h) to 256 (FFh).
Warning: In order to prevent incorrect operation of
the Timer/Watchdog, the prescaler (WDTPR) and
counter (WDTRL, WDTRH) registers must be initialised before starting the Timer/Watchdog. If this
is not done, counting will start with the reset (un-initialised) values.
WATCHDOG TIMER CONTROL REGISTER
(WDTCR)
R251- Read/Write
Register Page: 0
Reset value: 0001 0010 (12h)
7
0
ST_SP
S_C
INMD1
INMD2
INEN
OUTMD
WROUT
OUTEN
Bit 7 = ST_SP: Start/Stop Bit .
This bit is set and cleared by software.
0: Stop counting
1: Start counting (see Warning above)
Bit 6 = S_C: Single/Continuous.
This bit is set and cleared by software.
0: Continuous Mode
1: Single Mode
0
R6
R5
R4
R3
R2
R1
R0
Bits 7:0 = R[7:0] Counter Least Significant Bits.
78/178
TIMER/WATCHDOG PRESCALER REGISTER
(WDTPR)
R250 - Read/Write
Register Page: 0
Reset value: 1111 1111 (FFh)
Bits 5:4 = INMD[1:2]: Input mode selection bits.
These bits select the input mode:
INMD1
INMD2
INPUT MODE
0
0
Event Counter
0
1
Gated Input (Reset value)
1
0
Triggerable Input
1
1
Retriggerable Input
ST92185B - TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
Bit 3 = INEN: Input Enable.
This bit is set and cleared by software.
0: Disable input section
1: Enable input section
by the user program. At System Reset, the Watchdog mode is disabled.
Note: This bit is ignored if the Hardware Watchdog
option is enabled by pin HW0SW1 (if available).
Bit 2 = OUTMD: Output Mode.
This bit is set and cleared by software.
0: The output is toggled at every End of Count
1: The value of the WROUT bit is transferred to the
output pin on every End Of Count if OUTEN=1.
Bit 1 = WROUT: Write Out.
The status of this bit is transferred to the Output
pin when OUTMD is set; it is user definable to allow PWM output (on Reset WROUT is set).
WAIT CONTROL REGISTER (WCR)
R252 - Read/Write
Register Page: 0
Reset value: 0111 1111 (7Fh)
7
0
WDGEN
x
x
x
x
7
x
0
x
x
x
x
TLIS
IA0S
x
Bit 2 = TLIS: Top Level Input Selection.
This bit is set and cleared by software.
0: Watchdog End of Count is TL interrupt source
1: NMI is TL interrupt source
Bit 0 = OUTEN: Output Enable bit.
This bit is set and cleared by software.
0: Disable output
1: Enable output
x
EXTERNAL INTERRUPT VECTOR REGISTER
(EIVR)
R246 - Read/Write
Register Page: 0
Reset value: xxxx 0110 (x6h)
x
x
Bit 6 = WDGEN: Watchdog Enable (active low).
Resetting this bit via software enters the Watchdog mode. Once reset, it cannot be set anymore
Bit 1 = IA0S: Interrupt Channel A0 Selection.
This bit is set and cleared by software.
0: Watchdog End of Count is INTA0 source
1: External Interrupt pin is INTA0 source
Warning: To avoid spurious interrupt requests,
the IA0S bit should be accessed only when the interrupt logic is disabled (i.e. after the DI instruction). It is also necessary to clear any possible interrupt pending requests on channel A0 before enabling this interrupt channel. A delay instruction
(e.g. a NOP instruction) must be inserted between
the reset of the interrupt pending bit and the IA0S
write instruction.
Other bits are described in the Interrupt section.
79/178
ST92185B - STANDARD TIMER (STIM)
7.2 STANDARD TIMER (STIM)
Important Note: This chapter is a generic description of the STIM peripheral. Depending on the ST9
device, some or all of the interface signals described may not be connected to external pins. For
the list of STIM pins present on the particular ST9
device, refer to the pinout description in the first
section of the data sheet.
7.2.1 Introduction
The Standard Timer includes a programmable 16bit down counter and an associated 8-bit prescaler
with Single and Continuous counting modes capability. The Standard Timer uses an input pin (STIN)
and an output (STOUT) pin. These pins, when
available, may be independent pins or connected
as Alternate Functions of an I/O port bit.
STIN can be used in one of four programmable input modes:
– event counter,
– gated external input mode,
– triggerable input mode,
– retriggerable input mode.
STOUT can be used to generate a Square Wave
or Pulse Width Modulated signal.
The Standard Timer is composed of a 16-bit down
counter with an 8-bit prescaler. The input clock to
the prescaler can be driven either by an internal
clock equal to INTCLK divided by 4, or by
CLOCK2 derived directly from the external oscillator, divided by device dependent prescaler value,
thus providing a stable time reference independent from the PLL programming or by an external
clock connected to the STIN pin.
The Standard Timer End Of Count condition is
able to generate an interrupt which is connected to
one of the external interrupt channels.
The End of Count condition is defined as the
Counter Underflow, whenever 00h is reached.
Figure 47. Standard Timer Block Diagram
n
INEN INMD1 INMD2
STIN1
INPUT
&
(See Note 2) CLOCK CONTROL LOGIC
INTCLK/4
STP
8-BIT PRESCALER
MUX
STANDARD TIMER
CLOCK
STH,STL
16-BIT
DOWNCOUNTER
END OF
COUNT
CLOCK2/x
OUTMD1 OUTMD2
STOUT1
OUTPUT CONTROL LOGIC
EXTERNAL
INTERRUPT 1
INTERRUPT
INTS
CONTROL LOGIC
INTERRUPT REQUEST
Note 1: Pin not present on all ST9 devices.
Note 2: Depending on device, the source of the INPUT & CLOCK CONTROL LOGIC block
may be permanently connected either to STIN or the RCCU signal CLOCK2/x. In devices without STIN and CLOCK2, the
INEN bit must be held at 0.
80/178
ST92185B - STANDARD TIMER (STIM)
STANDARD TIMER (Cont’d)
7.2.2 Functional Description
7.2.2.1 Timer/Counter control
Start-stop Count. The ST-SP bit (STC.7) is used
in order to start and stop counting. An instruction
which sets this bit will cause the Standard Timer to
start counting at the beginning of the next instruction. Resetting this bit will stop the counter.
If the counter is stopped and restarted, counting
will resume from the value held at the stop condition, unless a new constant has been entered in
the Standard Timer registers during the stop period. In this case, the new constant will be loaded as
soon as counting is restarted.
A new constant can be written in STH, STL, STP
registers while the counter is running. The new
value of the STH and STL registers will be loaded
at the next End of Count condition, while the new
value of the STP register will be loaded immediately.
WARNING: In order to prevent incorrect counting of
the Standard Timer, the prescaler (STP) and counter
(STL, STH) registers must be initialised before the
starting of the timer. If this is not done, counting will
start with the reset values (STH=FFh, STL=FFh,
STP=FFh).
Single/Continuous Mode.
The S-C bit (STC.6) selects between the Single or
Continuous mode.
SINGLE MODE: at the End of Count, the Standard
Timer stops, reloads the constant and resets the
Start/Stop bit (the user programmer can inspect
the timer current status by reading this bit). Setting
the Start/Stop bit will restart the counter.
CONTINUOUS MODE: At the End of the Count, the
counter automatically reloads the constant and restarts. It is only stopped by resetting the Start/Stop bit.
The S-C bit can be written either with the timer
stopped or running. It is possible to toggle the S-C
bit and start the Standard Timer with the same instruction.
7.2.2.2 Standard Timer Input Modes (ST9
devices with Standard Timer Input STIN)
Bits INMD2, INMD1 and INEN are used to select
the input modes. The Input Enable (INEN) bit ena-
bles the input mode selected by the INMD2 and
INMD1 bits. If the input is disabled (INEN="0"), the
values of INMD2 and INMD1 are not taken into account. In this case, this unit acts as a 16-bit timer
(plus prescaler) directly driven by INTCLK/4 and
transitions on the input pin have no effect.
Event Counter Mode (INMD1 = "0", INMD2 = "0")
The Standard Timer is driven by the signal applied
to the input pin (STIN) which acts as an external
clock. The unit works therefore as an event counter. The event is a high to low transition on STIN.
Spacing between trailing edges should be at least
the period of INTCLK multiplied by 8 (i.e. the maximum Standard Timer input frequency is 3 MHz
with INTCLK = 24MHz).
Gated Input Mode (INMD1 = "0", INMD2 = “1”)
The Timer uses the internal clock (INTCLK divided
by 4) and starts and stops the Timer according to
the state of STIN pin. When the status of the STIN
is High the Standard Timer count operation proceeds, and when Low, counting is stopped.
Triggerable Input Mode (INMD1 = “1”, INMD2 = “0”)
The Standard Timer is started by:
a) setting the Start-Stop bit, AND
b) a High to Low (low trigger) transition on STIN.
In order to stop the Standard Timer in this mode, it
is only necessary to reset the Start-Stop bit.
Retriggerable Input Mode (INMD1 = “1”, INMD2
= “1”)
In this mode, when the Standard Timer is running
(with internal clock), a High to Low transition on
STIN causes the counting to start from the last
constant loaded into the STL/STH and STP registers. When the Standard Timer is stopped (ST-SP
bit equal to zero), a High to Low transition on STIN
has no effect.
7.2.2.3 Time Base Generator (ST9 devices
without Standard Timer Input STIN)
For devices where STIN is replaced by a connection to CLOCK2, the condition (INMD1 = “0”,
INMD2 = “0”) will allow the Standard Timer to generate a stable time base independent from the PLL
programming.
81/178
ST92185B - STANDARD TIMER (STIM)
STANDARD TIMER (Cont’d)
7.2.2.4 Standard Timer Output Modes
OUTPUT modes are selected using 2 bits of the
STC register: OUTMD1 and OUTMD2.
No Output Mode (OUTMD1 = “0”, OUTMD2 = “0”)
The output is disabled and the corresponding pin
is set high, in order to allow other alternate functions to use the I/O pin.
Square Wave Output Mode (OUTMD1 = “0”,
OUTMD2 = “1”)
The Standard Timer toggles the state of the
STOUT pin on every End Of Count condition. With
INTCLK = 24MHz, this allows generation of a
square wave with a period ranging from 333ns to
5.59 seconds.
PWM Output Mode (OUTMD1 = “1”)
The value of the OUTMD2 bit is transferred to the
STOUT output pin at the End Of Count. This allows the user to generate PWM signals, by modifying the status of OUTMD2 between End of Count
events, based on software counters decremented
on the Standard Timer interrupt.
7.2.3 Interrupt Selection
The Standard Timer may generate an interrupt request at every End of Count.
Bit 2 of the STC register (INTS) selects the interrupt source between the Standard Timer interrupt
and the external interrupt pin. Thus the Standard
Timer Interrupt uses the interrupt channel and
takes the priority and vector of the external interrupt channel.
If INTS is set to “1”, the Standard Timer interrupt is
disabled; otherwise, an interrupt request is generated at every End of Count.
Note: When enabling or disabling the Standard
Timer Interrupt (writing INTS in the STC register)
an edge may be generated on the interrupt channel, causing an unwanted interrupt.
To avoid this spurious interrupt request, the INTS
bit should be accessed only when the interrupt log-
82/178
ic is disabled (i.e. after the DI instruction). It is also
necessary to clear any possible interrupt pending
requests on the corresponding external interrupt
channel before enabling it. A delay instruction (i.e.
a NOP instruction) must be inserted between the
reset of the interrupt pending bit and the INTS
write instruction.
7.2.4 Register Mapping
Depending on the ST9 device there may be up to 4
Standard Timers (refer to the block diagram in the
first section of the data sheet).
Each Standard Timer has 4 registers mapped into
Page 11 in Group F of the Register File
In the register description on the following page,
register addresses refer to STIM0 only.
STD Timer Register
STIM0
STH0
R240
STL0
R241
STP0
R242
STC0
R243
STIM1
STH1
R244
STL1
R245
STP1
R246
STC1
R247
STIM2
STH2
R248
STL2
R249
STP2
R250
STC2
R251
STIM3
STH3
R252
STL3
R253
STP3
R254
STC3
R255
Register Address
(F0h)
(F1h)
(F2h)
(F3h)
(F4h)
(F5h)
(F6h)
(F7h)
(F8h)
(F9h)
(FAh)
(FBh)
(FCh)
(FDh)
(FEh)
(FFh)
Note: The four standard timers are not implemented on all ST9 devices. Refer to the block diagram
of the device for the number of timers.
ST92185B - STANDARD TIMER (STIM)
STANDARD TIMER (Cont’d)
7.2.5 Register Description
STANDARD TIMER CONTROL
(STC)
R243 - Read/Write
Register Page: 11
Reset value: 0001 0100 (14h)
COUNTER HIGH BYTE REGISTER (STH)
R240 - Read/Write
Register Page: 11
Reset value: 1111 1111 (FFh)
7
0
ST.15 ST.14 ST.13 ST.12 ST.11 ST.10 ST.9
ST.8
COUNTER LOW BYTE REGISTER (STL)
R241 - Read/Write
Register Page: 11
Reset value: 1111 1111 (FFh)
ST.7
0
ST.6
ST.5
ST.4
ST.3
ST.2
ST.1
ST-SP
0
S-C
INMD1 INMD2 INEN
INTS OUTMD1 OUTMD2
Bit 6 = S-C: Single-Continuous Mode Select.
This bit is set and cleared by software.
0: Continuous Mode
1: Single Mode
ST.0
Bits 7:0 = ST.[7:0]: Counter Low Byte.
Writing to the STH and STL registers allows the
user to enter the Standard Timer constant, while
reading it provides the counter’s current value.
Thus it is possible to read the counter on-the-fly.
STANDARD TIMER PRESCALER REGISTER
(STP)
R242 - Read/Write
Register Page: 11
Reset value: 1111 1111 (FFh)
7
7
Bit 7 = ST-SP: Start-Stop Bit.
This bit is set and cleared by software.
0: Stop counting
1: Start counting
Bits 7:0 = ST.[15:8]: Counter High-Byte.
7
REGISTER
0
STP.7 STP.6 STP.5 STP.4 STP.3 STP.2 STP.1 STP.0
Bits 7:0 = STP.[7:0]: Prescaler.
The Prescaler value for the Standard Timer is programmed into this register. When reading the STP
register, the returned value corresponds to the
programmed data instead of the current data.
00h: No prescaler
01h: Divide by 2
FFh: Divide by 256
Bits 5:4 = INMD[1:2]: Input Mode Selection.
These bits select the Input functions as shown in
Section 0.1.2.2, when enabled by INEN.
INMD1
0
0
1
1
INMD2
0
1
0
1
Mode
Event Counter mode
Gated input mode
Triggerable mode
Retriggerable mode
Bit 3 = INEN: Input Enable.
This bit is set and cleared by software. If neither
the STIN pin nor the CLOCK2 line are present,
INEN must be 0.
0: Input section disabled
1: Input section enabled
Bit 2 = INTS: Interrupt Selection.
0: Standard Timer interrupt enabled
1: Standard Timer interrupt is disabled and the external interrupt pin is enabled.
Bits 1:0 = OUTMD[1:2]: Output Mode Selection.
These bits select the output functions as described
in Section 0.1.2.4.
OUTMD1
0
0
1
OUTMD2
0
1
x
Mode
No output mode
Square wave output mode
PWM output mode
83/178
ST92185B - DISPLAY STORAGE RAM INTERFACE
7.3 DISPLAY STORAGE RAM INTERFACE
7.3.1 Introduction
The Display RAM (TDSRAM) is used to hold the
OSD data for display.
It can be shared by the following units:
– Display Unit (DIS). This OSD generator is described in a separate chapter.
– CPU accesses for control.
The necessary time slots are provided to each unit
for realtime response.
FEATURES:
■ Memory mapped in CPU Memory Space
■ Direct CPU access without significant slowdown
Figure 48. General Block Diagram
VR02094B
84/178
ST92185B - DISPLAY STORAGE RAM INTERFACE
TDSRAM (Cont’d)
7.3.2 Functional Description
The Data Storage RAM Interface (TRI) manages
the data flows between the different sub-units (display and CPU interface) and the internal RAM. A
specific set of buses (8 bit data TRIDbus, 13 bit
address TRIAbus) is dedicated to these data
flows.
As this TDSRAM interface has to manage TV oriented real time signals (On-Screen-Display):
– Its timing generator uses the same frequency
generator as for the Display (Pixel frequency
multiplier),
– Its controller is hardware synchronized to the basic horizontal and vertical sync signals got
through the CSYNC Controller,
– Its architecture gives priority to the TV real time
constraints: whenever there is any access contention between the CPU (only in case of direct
CPU access) and one of the hardware units, the
CPU automatically enters a "wait" configuration
until its request is serviced.
7.3.2.1 TV Line Timesharing
During a TV line, to maintain maximum performance, a continuous cycle is run repetitively. This
cycle is divided in 8 sub-cycles called "slots".
This 8-slot cycle is repeated continuously until the
next TV line-start occurs (horizontal sync pulse detected). When a horizontal sync pulse is detected,
the running slot is completed and the current cycle
is broken.
The following naming convention is used: "CPU"
stands for direct CPU access slot, "DIS" stands for
Display reading slot. Each slot represents a single
byte exchange (read or write) between the TDSRAM memory and the other units:
Display Reading (DIS). 1 byte is read from the
TDSRAM and sent to the display unit, the address
being defined by the display address generator.
CPU Access (CPU). 1 byte is exchanged (read or
written) between the TDSRAM and the CPU, the
address being defined by the CPU address bus.
85/178
ST92185B - DISPLAY STORAGE RAM INTERFACE
TDSRAM (Cont’d)
7.3.3 Initialisation
7.3.3.1 Clock Initialisation
Before initialising the TRI, first initialise the pixel
clock. Refer to the Application Examples in the
OSD chapter and to the RCCU chapter for a description of the clock control registers.
7.3.3.2 TRI Initialisation
It is recommended to wait for a stable clock issued
from the Pixel frequency multiplier before enabling
the TDSRAM interface.
86/178
Use the CONFIG register to initialise and start
the TRI. Note: The DON bit can only be changed
while GEN=0
Example:
spp #0x26
ld config, #0x02 ; DON,GEN=0
or config, #0x01 ; set GEN=1
During and after a reset, the TDSRAM interface is
forced into its "disable" mode where the sequencer
is forced into its idle state.
ST92185B - DISPLAY STORAGE RAM INTERFACE
TDSRAM (Cont’d)
7.3.4 Register Description
RAM INTERFACE CONFIGURATION REGISTER (CONFIG )
R252 - Read/Write
Register Page: 38
Reset Value: 0000 0010 (02h)
7
0
0
0
0
0
0
0
DON GEN
Bit 7:2 = Reserved, keep in reset state.
Bit 1 = DON: Display ON/OFF .
0: No display reading allowed (display slot completely used for CPU access).
1: Display reading enabled during the respective
access slot.
Note: DON can be changed only when the TRI is
off (GEN = 0).
<
Bit 0 = GEN: RAM Interface General Enable.
0: TRI off. Display reading and CPU accesses are
not allowed. When GEN=0, the Automatic Wait
Cycle insertion, while trying to access the
TDSRAM, is disabled.
1: TRI on.
87/178
ST92185B - ON SCREEN DISPLAY (OSD)
7.4 ON SCREEN DISPLAY (OSD)
7.4.1 Introduction
The OSD displays Teletext or other character data
and menus on a TV screen.
In serial mode, characters are coded on one byte.
The display is fully compliant with the WST Teletext level 1.5.
In parallel mode, characters are coded on two
bytes, one byte being the font address (character
code), the second byte being used for attribute
control, which can be combined with the serial attribute capabilities. In this mode, the display meets
a significant part of the WST Teletext level 2 specification.
In order to save memory resources (reduce system cost), two display modes are provided with either a page mode display mode (teletext standard, 26 rows) or a line mode (up to 12 rows) for
non teletext specific menus.
The OSD is seen by the ST9 as a peripheral which
has registers mapped in the Paged Register
space.
The character codes to be displayed are taken
from the TDSRAM memory. They are addressed
by the display with the real time sequencer
through the TDSRAM interface character by character.
The font ROM contains 512 characters. The standard European font contains all characters required to support Eastern and Western European
languages. Each character can be defined by the
user with the OSD Screen/Font Editor. All fonts
(except the G1 mosaic font) are fully definable by
masking the pixel ROM content.
Display is done under control of the ST9 CPU and
the vertical and horizontal TV synchro lines.
The OSD provides the Red, Green, Blue signals
and the Fast Blanking switching signal through
four analog outputs. The three Color outputs use a
3-level DAC which can generate half-intensity colors in addition to the standard saturated colors.
The Display block diagram is shown on Figure 1.
88/178
A smart pixel processing unit provides enhanced
features such as rounding or fringe for a better picture quality. Other smart functions such as true
Scrolling and cursor modes allow designing a high
quality display application.
7.4.2 General Features
■ Serial Character Mode supporting Teletext level
1.5
■ Parallel Character Mode for TV character
displays (for example channel selection or
volume control menus)
■ 40 or 80 characters/row
■ Full Page Mode:
23 rows plus 1 Header and 2 Status Rows
■ Line Mode:
Up to 12 rows plus 1 Header and 2 Status Rows.
■ 4/3 or 16/9 screen format
■ Synchronization to TV deflection, by Hsync and
Vsync or Csync.
■ Box Mode: Display text inside and outside box
solid, transparant or blank
■ Rounding and Fringing
■ Cursor Control
■ Concealing
■ Scrolling
■ Semi-transparent mode (text windowing inside
video picture)
■ Half-Tone mode (reduces video intensity inside
a box)
■ Normal character size 10 x 10 dots.
■ Other character sizes available as follows:
(SH: Single Height, SW: Single Width, DH: Double
Height, DW: Double Width, DS: Double Size)
Both Serial and
Parallel Display Mode
Parallel Mode
SH x SW = 10 * 10 dots
only
SH x DW = 10 * 20 dots
DS=DH x DW = 20 * 20
dots
DH x SW = 20 * 10 dots
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
■ Serial character attributes:
– Foreground Color (8 possibilities in Serial Full
page display mode)
– Background Color (8 possibilities)
– Flash / Steady
– Start Box / End Box
– Double height
– Conceal / display
– Fringe
– Contiguous Mosaic / Separated Mosaic
– Hold / Release Mosaic
– G0 font switch (in triple G0 mode)
■ Parallel character attributes (in parallel display
mode):
– Underline
– Double height & Double width
– Upper Half-Character
– Smooth Rounding
– Box mode
– Font Selection G0/Extended menu
– Selection of 15 background Colors
– Selection of 8 foreground Colors
■ Global Screen attributes:
– Fine and coarse Horizontal Adjustment (for
the whole 26 rows)
– Vertical Adjustment (for the whole page)
– Blanking Adjustment
– Default Background Color (up 15 colors with
use of half-intensity attribute)
– Default Foreground Color (up 15 colors with
use of half-intensity attribute)
– Semi transparent display (active only on background)
– Translucency: OSD background color mixed
with video picture.
– Full screen Color (15)
Mode
G0
Triple G0
Single G0
3*96
1*83
■
■
■
National
Set
N/A
15*13
– National Character set selection
– National Character mode selection
– Global Double Height display (Zooming Function)
– Global Fringe Enable
– Global Rounding Enable
Cursor Control:
– Horizontal position (by character)
– Vertical position (by row)
– Flash, Steady or Underline Cursor Modes
– Color Cursor with inverted foreground / inverted background
Scrolling Control:
– Vertical scrolling available:
Programmable rolling window if Normal
Height and 40 char/row
– Top-Down or Bottom-Up shift
– Freeze Display
Character fonts:
576 different characters available:
– 128 mosaic matrix characters (G1), hardware
defined (64 contiguous, 64 separated).
– 512 character ROM fonts, all user defined:
– 96-character basic character set (G0)
– 128 characters shared between G2 X/26 and
Menu characters
– 96 Extended Menu Characters
– Two national character set modes (mutually
exclusive ROM options):
Single G0 mode
A font combining 83 characters from
the G0 basic set (latin) and 13 characters selected from 15 National character subsets
Triple G0 mode allowing different alphabets
Three 96-character fonts (e.g. latin,
arabic, cyrillic ...)
G2 (X26+
Menu)
128
128
Extended
Menu
96
96
G1
(mosaic)
64
64
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ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Figure 49. Display Block Diagram
RAM INTERFACE
RAM @
Gen RAM Add
Row Counter
Comp 10/20
Char Counter
Comp VPOS
Pixel Counter
Line Counter
Scroll N Row
HPOS
CURSOR
CONTROL
SCROLLING
CONTROL
Scroll 1 Row
Comp 10/20
Comp HPOS
VPOS
Char Cursor
Gen PLA Cmd
Row Cursor
Gen ROM Add
Mode Ctrl
MOSAIC
PIXEL
CONTROL
ROM
PLA
Serial/Parallel Attributes
Shift Register (10b)
TSLU
Full Screen
R
Def. Backg
Def. Foreg
G
B
Cur. Backg
Pixel Control
L1/L1+
Cur. Foreg
mux
Char Decoding
mux
L1/L1+
Fast Blanking
TRB
FB
Attributes Decoding
ST9 Access
Character Code
Parallel Attributes
RAM INTERFACE
On Hsync
On Ckpix
VR02112E
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ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.3 Functional Description
7.4.3.1 Screen Display Area
The screen is divided in 26 rows of basically 40
characters. From row 1 to row 23, it is possible to
display 80 characters per row with the following restrictions:
– Serial mode only
– No rounding or fringe
The three special rows, a Header and two Status
rows have specific meanings and behaviour. They
are always displayed the same way (40 characters) and at the same place. In these rows, size attributes, scrolling and 80-character modes are not
allowed.
All row content, including the Header and Status
rows, is fully user-definable.
Figure 50. Definition of Displayed Areas
ROW 0 “HEADER”
26 LINES
(TEXT PAGE)
“FULL SCREEN”
AREA
ROW 24 “STATUS ROW 0”
ROW 25 “STATUS ROW 1”
40/80 CHARACTERS
Figure 51. Screen Display Area.
91/178
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.3.2 Color Processing
The color of any pixel on screen is the result of a
priority processing among several layers which
are (going from the lowest priority to the highest
one):
■ Full Screen Color where nothing is processed
■ Default Background Color (it assumes pixel is
off)
■ Serial
Background Color (pixel off, but
background color serial attributes activated)
■ Parallel
Background Color (pixel off, but
background color parallel attribute activated)
■ Default Foreground Color (pixel on, but no
foreground attribute activated)
■ Serial
Foreground Color (pixel on and
foreground serial attribute activated)
■ Parallel
Foreground Color (pixel on and
foreground parallel attribute activated)
Color processing is also the result of register control bits (for global color attributes) and color oriented attribute bits (from serial or parallel attributes), refer to the Figure 0.1.4.3
7.4.3.3 Pixel Clock Control
The pixel clock is generated outside of the display
macrocell by the on-chip Pixel Frequency multiplier which provides great frequency flexibility controlled by software (refer to the RCCU chapter).
For example, reconfiguring the application from a
4/3 screen format to a 16/9 format is just a matter
of increasing the pixel frequency (i.e. reprogramming the pixel frequency multiplier to its new value).
The output signal of the pixel frequency multiplier
is rephased by the Skew Corrector to be perfectly
in phase with the horizontal sync signal which
drives the display.
7.4.3.4 Display Character
Each character is made up of a 10 x 10 dots matrix. All character matrix contents are fully user definable and are stored in the pixel ROM (except the
G1 mosaic set which is hardware defined).
92/178
A set of colors defines the final color of the current
pixel.
In general, the character matrix content is displayed as it is, the pixel processing adding the
shape and the color information received from the
current attributes. Only three kinds of attributes alter the displayed pixel. They are the following:
7.4.3.5 Rounding
Rounding can be enabled for the whole display using the GRE global attribute bit (See Figure 1) In
this effect one half-dot is added in order to smooth
the diagonal lines. This processing is built into the
hardware. The half-dot is painted as foreground.
This half-dot is field-sensitive for minimum vertical
size (Figure 4).
An extra ‘smooth rounding’ capability is also builtin (see Figure 5). In smooth rounding, a pixel is
added even if dots make an ‘L’. This capability is
activated using a parallel attribute (See Table 4)
7.4.3.6 Underline
In this effect the last TV line of the character is displayed as foreground (Figure 4).
7.4.3.7 Fringe
The fringe is a half-dot black border surrounding
completely the character foreground. This half-dot
is field sensitive for minimum vertical size (Figure
4).
7.4.3.8 Translucency
Certain video processors are able to mix the RGB
and video signals. This function of the chroma processor is then driven by the TSLU output pin of the
ST9 device. See Figure 7.
7.4.3.9 Half-Tone
If the HT signal is activated, for example, while a
text box is displayed and a transparant background selected for all the display (MM bit =1 in
the FSCCR register), the HT signal performs a
contrast reduction to the background inside the
box. See Figure 8.
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Figure 52. Display Character scheme
NORMAL MODE
ROUNDING MODE
FRINGE MODE
Background
Background
Foreground
Foreground
Smooth Rounding
Fringe
Underline
VR02112B
Figure 53. Rounding and Fringe Effects
Dot (four pixels)
Added pixel
Added pixel
Added pixel
Smooth Rounding Effect
Global Rounding Effect
Fringe Effect
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ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.4 Programming the Display
All the characteristics of the display are managed
by programmable attributes:
■ Global Attributes
■ Serial Attributes
■ Parallel Attributes (active until a superseding
serial or parallel attribute).
Table 15. Global Attributes
Global Attributes
Display Enable (DE)
4/3 or 16/9 Format (SF)
Conceal Enable (CE)
Fringe Enable (FRE)
Global Fringe Enable (GFR)
Global Rounding Enable
(GRE)
Semi-transparent Mode
(STE)
Cursor Control
Scrolling Control
7.4.4.1 Global Attributes
These global attributes are defined through their
corresponding registers (see the Register Description).
■
■
Description
0= Display Off (Default)
1= Display On
0= 4/3 Screen Format (Default)
1= 16/9 Screen Format
0= Reveal any text defined as concealed by serial attributes (Default)
1= Conceal any text defined as concealed by serial attributes
0= Fringe Disabled (Default)
1= If SWE in NCSR register is reset, it acts as Fringe enable (toggle with
serial attribute 1Bh). Active on the whole page but not in 80-character
mode.
0= Global fringe mode off
1= Display all text in page in fringe mode
0= Disabled (Default)
1= Rounding active on the whole page but not in 80-character mode.
0=Disabled (default)
Control
Register
DCM0R
R250 (FAh)
Page 32
DCM0R
DCM0R
DCM0R
DCM0R
DCM0R
1=Enabled
The Fast Blanking signal is toggled with the double pixel clock rate on Back- DCM0R
ground and full screen area in 40 character mode.
Note: Semi-transparent mode shows a visible grid on screen.
NCSR R245
The TSLU signal is active when the OSD displays the background and full
(F5h) Page
Translucency (HTC and
screen area and is inactive during foreground or if no display. This output
32 and FSCTSLE)
pin is used with a Chroma processor to mix the video input with the RGB to
CR R243
get full translucency.
Page 32
NCSR R245
(F5h) Page
The HT signal is active when the OSD displays the background and full
Half-Tone (HTC and TSLE) screen area and is inactive during foreground or if no display. The HT signal 32 and FSCCR R243
is used with a video processor to perform a contrast reduction.
Page 32
0=Single page (40 Characters per row) (default)
40/80 Chars/Row (S/D)
1= Two pages are displayed contiguously (80 Characters per row). In this DCM0R
mode, only serial mode is available.
DCM1R
0=Display when Fast Blanking output is low (default)
Fast Blanking Active Level
R251 (FBh)
1=Display when Fast Blanking output is high
Page 32
0= Serial Mode (Default)
Serial/Parallel Mode (SPM)
DCM1R
1= Parallel Mode
Page or Line Display Mode 0 = Full Page Mode (Default) 23 lines plus 1 header and two status lines.
DCM1R
(PM)
1= Line Mode
94/178
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Table 16. Global Attributes (Cont’d)
Global Attributes
Box Control ModeText In/
Out
Vertical Adjustment
Horizontal Adjustment
National Character Subset
Selection
Control
Register
FSCCR
Text In/ Text Out Box configurable with 3 bits. Refer to FSCCR register deR243 (F3h)
scription for details.
Page 32
Refer to the register description for bit settings. Active on the whole page,
VPOSR
this setting adjusts the vertical delay between the rising edge of Vsync and
R242 (F2h)
the beginning of the display area. The display color in this delay adjustment
Page 32
area is defined by the Full Screen color.
Refer to the register description for bit settings. Active on the whole page,
this adjustment is the horizontal delay between the rising edge of Hsync
and the beginning of the display area. The display in this delay area is the
HPOSR
full row color.
R241 (F1h)
Two kinds of horizontal adjustment are available. When the tube is in a 4/3 Page 32
format, only a horizontal delay is necessary before starting the active display area. When the tube is in 16/9 format, an additional horizontal adjustment is necessary to keep the display area centered on the screen.
NCSR R245
Refer to the register description for bit settings. Chooses which national font
(F5h) Page
sub-set is to be used with the G0 character set.
32
0 = Single G0 character set mode (default)
Description
Single G0 or Triple G0 mode 1 = Triple G0 character set mode
NCSR
selection
In applications with multiple alphabets in the same display, it is possible to
switch from one character set to another on the fly (see serial attributes).
SCLR
R248 (F8h)
Active on the whole page with header, but not on the status rows. When
Global Double Height
Global Double Height is active, either the top half or the bottom half of the and SCHR
R249 (F9h)
screen is visible.
Page 32
DCR R240
This color is displayed as background color if no serial or parallel attributes
(F0h) Page
Background default color
are defined for the displayed row.
33
This color is displayed as foreground color if no serial or parallel attributes
Foreground default color
are defined for the displayed row. These default colors are selected at each DCR
beginning of a line and are defined by means of the corresponding register.
FSCCR
Full screen color
Color displayed outside of the vertical display area.
R243 (F3h)
Page 32
95/178
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Figure 54. Semi-Transparent Display Scheme and Fast Blanking Behaviour
NORMAL DISPLAY
SEMI TRANSPARENT DISPLAY
line 3 Field odd
line 4 Field even
Fringe
Solid Background
Solid Foreground + Rounding
Video
LINE 3 NORMAL DISPLAY
CKPIX
LINE 3 SEMI TRANSPARANT DISPLAY
CKPIX
R, G, B
FB
R, G, B
RGB
FB
VIDEO
LINE 4 NORMAL DISPLAY
LINE 4 SEMI TRANSPARANT DISPLAY
CKPIX
CKPIX
R, G, B
FB
R, G, B
FB
VR02112C
Figure 55. Translucent Display Scheme
line 3
Fringe
Solid Background
Solid Foreground + Rounding
Video
NORMAL DISPLAY LINE 3
CKPIX
R, G, B(40c)
FB
TSLU
VR02112J
96/178
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Figure 56. Half-Tone Display Scheme
VIDEO PROCESSOR
RGB
Switch
Internal Red
Internal Green
Rout
Gout
Contrast
Reduction
Bout
Internal Blue
HT
R G B FB
ST9 MCU
97/178
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.4.2 Row Attributes
The header and status row attributes are set using
the HSCR R244 (F4h) Page 32 register. The row
enable bits as set in registers DE0R .. 2 R253
..255 Page 32.
Header Enable
When the display is in line mode, row 0, called the
header, is also usable. It no longer acts as a header but simply as an additional row.
Status Row Enable
The display of the two status rows can be enabled
individually.
Row Enable Bits
1 bit per row, for rows from 1 to 23, in page mode.
Serial Attributes
Serial Mode is selected by resetting the SPM bit in
register DCM1R R251 (FBh) Page 32.
Serial attributes are active until the end of the line
or a superseding serial attribute.
In this display mode, the attribute code and the
character code are in the same memory area (Figure 9).
The attribute takes the place of an alpha character, and the OSD displays a space character defined on 1 byte in Serial Mode:
Figure 57. Example of a Row in Serial Mode
FLASHING
Display
AA
Z A RDOZ
AAA
Propagation
can be half intensity
global
Default background
Default foreground
Memory location
AA
Fh Sc Bb
Length of row = 40 Characters
Z A RDOZ
Sty
AAA
Characters
Steady attribute
Black background attribute
Foreground color attribute
Flashing attribute
VR02115A
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ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Table 17. Serial Attribute Codes
b[7:3]
00000
00001
00010
00011
b[2:0]
Foreground Color
000
001
010
011
100
101
110
111
(Alpha Chars)
Black
Red
Green
Yellow
Blue
Magenta
Cyan
White (1)
Foreground Color
Flash
Steady (1, 2)
Box OFF (1)
Box ON
Normal Height (1,2)
Double Height
Notes:
(1) Presumed at the start of each display row or
can be defined in global register
(2) Action “set at” (on current character) others are
“set after” (on next character)
(3) ALWAYS active (even in Full Page Serial
Mode, i.e. for Text Level 1)
(4) Toggles action if the Fringe Enable is set (bit 5
in register DCM0R R250 (FAh) Page 32. Selects a
second G0 if the Switch Enable bit is set (bit 5 in
register NCSR R245 (F5h) Page 32)
Flash: (/= Steady) The next characters are displayed with the foreground color alternatively
equal to background and foreground on a period
based on Vsync (32 Vsync: foreground, 16 Vsync:
background) until a Steady serial attribute.
Fringe: If the Fringe Enable bit is set in the global
attribute register DCM0R R250 (FAh) Page 32, the
next characters are displayed with a black fringe
(half dot) until the decoding of another fringe attribute coded 1Bh (toggle effect).
Conceal: (/= Reveal) The next characters are displayed as space characters (Background color)
until a foreground color character is encountered.
Conceal mode is set by the conceal enable control
bit in the register DCM0R R250 (FAh) Page 32.
Boxing: A part of the page (where this bit is active)
is inserted in a specific window depending on 3
control bits defined in the FSCCR register. (see
Figure 11)
(Mosaic Chars)
Black (3)
Red
Green
Yellow
Blue
Magenta
Cyan
White
Conceal (2)
Contiguous Mosaic (1, 2)
Separated Mosaic (2)
Fringe or 2nd G0 font (3, 4)
Black Background (1, 2)
New Background (2)
Hold Mosaic (2)
Release Mosaic (1)
To respect the Teletext Norm, the box in serial
mode, starts when two Box-on attributes are encountered, and stops when two Box-offs are encountered.
Double Height: The upper halves of the characters are displayed in the current row, the corresponding lower halves of characters are displayed
(with same display attributes) in the next row (information received for this row must be ignored).
Note: When a serial double height attribute is decoded in Row 23, the characters of the first status
row are not displayed. To avoid this effect, remove
the serial double height attribute from Row 23.
Figure 58. Mosaic Characters
Contiguous Mosaic
Separated Mosaic
Note: Hold Mosaic: (/= Release) The last mosaic
character is repeated once instead of the current
space character.
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ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Figure 59. Example of Boxing Attribute in Serial Mode
TEXT outside box
not displayed*
TEXT inside box is visible*
Display
< b o x
>
Propagation
Default background
Length of row = 40 Characters
Memory location
AA
< b o x
Bb BO BO
>
BF BF SC Nb
A
BOX-ON attribute BOX-OFF attribute
Default foreground
VR02115B
*Depending on FSCCR
Figure 60. Example of Double Height Attribute in Serial Mode
3 contiguous Rows displayed in serial mode
Display
ABC
Z A R D OZ
DEF
AA
Z A RDOZ
AAA
FLASHING
on screen, the 2nd line is overlapped
Memory Location
ABC
1 2 3
A A Fh
DH
Sc Bb
Z A R D O Z NS D E F
HI DDEN 4 5 6
Z A R D O Z Sty A A A
VR02115C
.
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ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.4.3 Parallel Attributes
Figure 61. Example of Row in Parallel Mode
Display
A A A * * Z A RDOZ * A A A
Propagation
Default foreground
Default background
global
Foreground (full intensity)
Background (half intensity)
Attributes Location
Characters Location
A A A * * Z A RDOZ * A A A
VR02115D
Each character is defined on 2 bytes in Parallel
Mode (see Figure 13.)
Parallel Mode is selected by setting the SPM bit in
the DCM1R register R251 (FBh) Page 32.
It requires 2 bytes per character. Display characters are coded through a second byte processed in
parallel with the character code.
It does not handle Teletext and is used mainly for
TV menus (e.g. for channel searching or volume
control).
The attribute can be one of two types defined by
most significant bit (PS):
– Color attribute
– Shape attribute
US: Underline / Separate Mosaic graphics (see
above).
DH: Double Height: The half character is displayed
in the current row depending on the Upper Height
control bit. The Double Height action is not propagated in the row.
Note: When a parallel double height attribute is
decoded in Row 23, the characters of the first status row are not affected and are still displayed.
UH: Upper Half. This bit is active when the currently displayed row writes the upper half-character in
case of double height or double size attribute.
DW: Double Width (see above).
BX: Boxing window.
SR: Smooth Rounding.
FR, FG, FB: Foreground color.
BR, BG, BB: Background color.
HI: Half Intensity (background only).
CSS: Character extended menu code selection.
PS: Parallel attribute selection
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ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Table 18. Parallel Color and Shape Attributes.
BIT
0
1
2
3
4
5
6
7
NAME
BR
BG
BB
HI
FR
FG
FB
PS= 0
FUNCTION
Background Red
Background Green
Background Blue
Half-Intensity
Foreground Red
Foreground Green
Foreground Blue
Parallel Attribute Selection
0
CSS
1
2
US
DH
Underline/Seperated mosaic
Double height
3
DW
Double width
4
5
6
7
UH
BX
SR
PS= 1
Character set selection
Upper half character (if 1)
Box mode
Smooth rounding
Parallel Attribute Selection
REMARKS
Only for Background.
Color mode of parallel attributes
G2-Menu characters or G1/Extended menu characters selection
Dual function depending on character code
The character is 20 pixels high .
The character is 20 pixels wide. Available in Parallel
mode or in Line mode. Characters are stretched horizontally, to occupy in addition, the next character
space. It is possible to mix it with double height. To
display a double width character the attribute must be
“double width” on the character and “simple width” on
the next which can be a serial attribute. In this case
the first character is memorised. If two “double width”
attributes are on two adjacent characters, the first half
of the second is displayed instead of the second half
of the first one.
Active only if Double Height or Size requested
Boxing window created (if 1)
Special rounding effect (See Figure 5 )
Shape mode of parallel attributes
Double Size: (available in Parallel mode or in Line mode) by setting Double Width plus Double Height attributes.
Figure 62. Parallel Color and Shape Attributes
Attribute
location
Character
location
DW SS
31 4F
31 88 80
A B
A B
A B
A
B
VR02115E
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ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.4.4 Font Selection using Parallel Attributes
Parallel attributes have an immediate effect. They
are applied to the associated character. These attributes can also have a “serial” effect, the defined
attribute being still defined on the following characters: this is known as attribute propagation.
Shape attributes (US,DH,BX,SR) are propagated
when PS is toggled to 0. In the same way, color attributes are propagated when PS is toggled to 1.
CSS has two kinds of behaviour:
– If PS is set once, the CSS attribute is applied on
the current character only.
– If PS is set twice, the CSS of the first character
with PS=1 is propagated.
Note: The value stored as a preceding CSS value
is forced when alpha or mosaic color serial attributes are used. Alpha serial attributes reset the
memorized CSS: Mosaic serial attributes set the
memorized CSS.
Table 19. Font Selection using Parallel Attributes
Parallel
Attribute
Character Code
00..1F
20..7F
80..FF
00..1F
PS= 0
PS= 1
CSS used for character
set selection
20..7F
80..FF
Character
Definition
32 Control Characters (serial attributes function table)
96 Basic Characters chosen from G0 or G1 font
128 extended characters G2-based X/26 and Menu Characters
32 Control Characters (serial attributes function table)
CSS= 0: G0 or G1 selection depending on color serial attribute
CSS= 1: G1 selection
CSS= 0: Select G2-based X/26 + Menu
CSS= 1: Select extended Menu + 32 reserved characters
In the example in Table 6,, a string of six characters is displayed. In the line “Display with” we can
see that, starting from Char(n) and ending with
Char n+2, the CSS setting made at Char (n-2) is
propagated.
Table 20. Example of Character Set Selection
PS=
CSS=
Display with
Stored CSS
Char(n-2)
1
CSSn-2
CSSn-2
CSSn-2
Char(n-1)
1
CSSn-1
CSSn-1
CSSn-2
Char(n)
0
none
CSSn-2
CSSn-2
Char(n+1)
0
none
CSSn-2
CSSn-2
Char(n+2)
1
CSSn+2
CSSn+2
CSSn-2
Char(n+3)
1
CSSn+3
CSSn+3
CSSn+2
103/178
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Figure 63. Parallel Mode Display Example 1 Showing Character and Attribute Byte Pairs:
RAM content in Parallel Mode
Parallel Attribute
Characters
A
A
A
A
A
NF
X SA A
I
NF A
A
B NF
A
B NF
I
I
DS
A
NC DW NC
SS
SS NC
DH
NC
DS
A
SS DW
SS DW
SS NC
UH=0
DH
NC
DH
UH=1 UH=1
NC
DH
UH =0 UH=0
NC
NF : New Foreground (Serial Attribute)
SS : Simple Size b7 = 0
NC : New Colour b7 = 0
SA : Serial Attribute
DW : Double Width b7 = 1
DS : Double Size b7 = 1
Display
A
A
AA
A
A
A
AB
A
Parallel Mode Display Example 2:
Me n u B a s s 1
T r eb l e
104/178
UH=1
VR02112F
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.4.5 Rules When Using Size Attributes
Secondary effects can be generated when the
shape format is not respected.
The 3 figures below describe the combination of
parallel size attributes to obtain the different character sizes:
· Double Width
· Double Height
· Double Size
7.4.4.6 Example of using Double Width
Attribute
In parallel mode, double width on character can be
obtained using the following rule (Figure 16):
It is important to set Double Width (bit 3 of the
shape attribute) on the current character attribute
and Single Size on the following one. The second
character location can be either a serial attribute or
another character.
On the contrary, if a new color or a Double Width
attribute is set in the second attribute location, the
second part of the character is overlapped.
Figure 64. Double Width Examples
Double width
A
Double width
AB
first half of the second
character is displayed
Attributes
location
Characters
location
Double
width
Simple size
Double
width
New color
DW SS
DW NC
A
A B
1 ROW
NF
New foreground
(serial attribute)
New foreground
(parallel attribute)
1 ROW
VR02115G
105/178
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.4.7 Example of using Double Height
Attribute
In parallel mode, Double Height characters can be
obtained as follows. The Double Height attribute
concerns two consecutive rows. Repeat the char-
acter to magnify in the two rows. Set Bit 2 DH of
the shape attribute in the two locations and set or
reset bit 4 UH to define if it is the top or bottom
half-character.
Figure 65. Double Height Example
Double height
Display
Shape
Propagation with
color
AB
Previous/default color
Double height
upper half
DH
UH=1
DH
UH=0
Attributs
location
Characters
location
Double height
lower half
A B
A B
2 ROWS
106/178
New color
VR02115H
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.4.8 Example of using Double Size Attribute
In parallel mode, Double Size characters can be
obtained as follows. This attribute concerns two
consecutive rows. The character to magnify must
be repeated on the two rows. Bits 2 and 3 of the
shape attribute must be set on the two locations. In
addition bit 4 must be set or reset to define the top
or bottom half-character.
Figure 66. Double Size Examples
Display
A
Double size
Double size
lower half
Double size
upper half
Double Height
DS
UH=1
DS
UH=0
Attribute
location
DH
DH
Double Height
Character
location
A
NF
A
NF
2 ROWS
VR02115J
107/178
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.4.9 Example of using Underline Attribute
In parallel mode, the Underline mode on character
can be obtained simply by setting the bit 1 ‘US’ of
the shape attribute. To underline double height
characters, set the US bit on the attribute associated with the lower part of the character.
The underline attribute is ignored in the upper halfcharacter.
Figure 67. Underline Example
Display
Double height
UL
DH DH
UH=1 UH=1
DH DH
UH=0 UH=0
Attribute
location
Underline (US=1)
Character
location
U L
U L
2 ROWS
108/178
Underline (US=1)
VR02115K
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.4.10 Attribute Rules
The default colors for foreground and background
are defined through the register DCR R240 (F0h)
Page 33.
A display defined in parallel mode can accept a serial color attribute, and propagation is available until a new color attribute (serial or parallel) is encountered.
■ Rule for Shape Attributes:
– In parallel mode, shape attributes are not
propagated on the following characters of the
row except if this character has a colour attribute. The propagation lasts as long as a colour attribute is applied to a character.
– In parallel mode, the double height (bit 2 of the
shape attribute) is active only on its own character. Setting one double height attribute does
not cover the following characters of the row
(different from double height in serial mode).
Figure 68. Rule for Serial and Parallel Color
Combination
Highest priority
PARALLEL COLOR
defined in TDSRAM
SERIAL COLOR
defined in TDSRAM
DEFAULT COLOR
defined in page register
Lowest priority
109/178
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.4.11 Cursor Control
■ Horizontal position (by character)
■ Vertical position (by row)
■ Color or Underline Cursor Modes
■ Color Cursor with inverted foreground / inverted
background
■ Flash or Steady mode Color Cursor
Cursor display is controlled using two registers:
– Cursor Horizontal Position R246 (F6h) Page 32
– Cursor Vertical Position R247 (F7h) Page 32.
Notes:
1. Cursor operation in “Underline” mode: any
screen location where the foreground color is
identical to the background color behaves as a
“lost cursor” (i.e. cursor not visible). Assuming a
serial mode display, the screen location placed
on the lower row after a double height character
will lead to a “lost cursor”.
2. Ghost fringing: assuming a cursor operation in
color inversion mode, assuming a serial mode
display, assuming the fringe is activated, the
screen location placed on the lower row after a
double height character may show a “ghost
fringing” effect (the ghost color being an
inverted background one).
3. Static or flash cursor Mode: the horizontal cursor value indicates the character position (i.e.
first character pointed with a “1” value); in
Underline Mode, the horizontal cursor value
gives the position minus “1”.
7.4.5 Vertical Scrolling Control
■ Top-Down or Bottom-Up shift
■ Freeze Display function
■ Shift speed control
■ Double Height Display scrolling
Scrolling is performed in a programmable rolling
window if the characters are in normal height.
110/178
In Line mode, the scrolling window must be entirely filled by programmed rows (each scrolled location is defined by one of the 11 available rows).
Notes:
1. 80-characters combined with scrolling can only
be used in Line mode
2. In Parallel (Level 1+) mode, scrolling is possible
without serial attributes DS and DH.
Use these two registers to control scrolling:
– Scrolling Control Low R248 (F8h) Page 32
– Scrolling Control High R249 (F9h) Page 32
7.4.5.1 RGB & FB DAC and TSLU Outputs
The R, G, B and FB pins of the ST92195/
ST92R195 are analog outputs controlled by true
Digital to Analog Converters. These outputs are
specially designed to directly drive the Video Processor.
The R, G and B outputs are referred to Ground
and they can drive up to 1.0V; they are loaded onchip by a 0.5K ohms typical load.
The effective DAC output level is controlled by a 3
bit digital code issued by the display control logic
with respect to the real time value of R, G or B and
the Half-Intensity control bit, as follows:
R/G/B DAC code
0
0
0
0
1
1
1
1
1
Display aspect during FB
No Color
Half-Intensity Color
Full-Intensity Color
The FB (fast switch) output is also referred to
Ground and can drive up to 3.0V with an on-chip
0.5K ohm load. This analog FB output provides the
best phase matching with the R, G, B signals.
An example of the Fast Blanking Signal is shown
in Figure 6.
The TLSU pin is a digital output (0-5V).
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.6 Display Memory Mapping Examples
The display content is stored in TDSRAM, (2 to 8K
bytes starting at address 8000h). Use register
TDPR R252 (FCh) Page 32 to address the memory blocks containing the display data. Two 4-bit address pointers (bits PG and HS) must be given that
point to separate blocks containing the display
page and the header/status rows.
Alternatively, the PG and HS pointers can be written to the TDPPR R246 Page 33 and TDHSPR
R247 Page 33 registers.
7.4.6.1 Building a Serial Mode Full Page 40Char Display
Page Location:
The 1 Kbyte block of page content is stored in the
TDSRAM location pointed to by the PG3..PG0
bits.
Header & Status Rows Location:
The 0.5 Kbyte block containing the Header, Status
Row 0 and Status Row 1 is pointed to by the
HS3..HS0 bits.
Row Scrolling Buffer Location:
The scrolling buffer corresponds to the 40 bytes
following the Row 23 when the scrolling feature is
used.
Figure 69. Serial Mode (40 Characters) - Page Mapping
1K TDSRAM
Row 1
Row 23
Scrolling Buffer
Free Space
Block
Number(1K)
TDSRAM
Address (hex)
0
1
2
3
4
5
6
7
8000
8400
8800
8C00
9000
9400
9800
9C00
TDPR
Value (hex)
PG3..PG0
0
2
4
6
8
A
C
E
2K
6K
8K
Resolution 1K bytes
Figure 70. Serial Mode (40 Characters) - Header and Status Mapping
0.5K TDSRAM
Header
Status Row 0
Status Row 1
Free Space
Resolution 0.5K bytes
Block Number
(0.5K)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TDSRAM
Address (hex.)
8000
8200
8400
8600
8800
8A00
8C00
8E00
9000
9200
9400
9600
9800
9A00
9C00
9E00
TDPR Value
(Hex.) HS3..HS0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
2K
6K
8K
111/178
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.6.2 Building a Parallel Mode, 40-Char, Full
Page Display
Page Location:
The pair of adjacent 1 Kbyte blocks of page content is stored in the TDSRAM location pointed to
by the PG3..PG0 bits. The first block contains the
characters, the second block contains the attribute
bytes.
Header & Status Rows Location:
The 0.5 Kbyte block containing the Header, Status
Row 0 and Status Row 1 is pointed to by the
HS3..HS0 bits. The Header/Status attributes are
stored in this block at offset 80h.
Row Scrolling Buffer Location:
The scrolling buffer corresponds to the 40 bytes
following Row 23 when the scrolling feature is
used.
Figure 71. Parallel Mode (40 Characters) - Page Mapping
1K TDSRAM
1K TDSRAM
Row 1 Char.
Row 1 Attr.
Row 23 Char.
Row 23 Attr.
Scrolling Buffer
Scrolling Buffer
Free Space
Free Space
TDPR
TDSRAM
TDSRAM
Block
Number Address (hex) Address (hex) Value (hex)
PG3..PG0
Attr.
Char.
(2K)
0
8000
8400
0
1
8800
8C00
4
2
9000
9400
8
3
9800
9C00
C
2K
6K
8K
Resolution 2K bytes
Figure 72. Parallel Mode (40 Characters) - Header and Status Mapping
0.5K TDSRAM
Header Char.
Status Row 0 Char.
Status Row 1 Char.
Free Space
Header Attr.
Status Row 0 Attr.
Status Row 1 Attr.
Free Space
Resolution 0.5K bytes
112/178
80h
Block
Number (0.5K)
TDSRAM
Address (hex)
TDPR
Value (hex)
HS3..HS0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
8000
8200
8400
8600
8800
8A00
8C00
8E00
9000
9200
9400
9600
9800
9A00
9C00
9E00
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
2K
6K
8K
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.6.3 Building a Serial Mode, 40-Char, Line
Mode Display
Half-Page Location:
The 0.5 Kbyte block of half-page content is stored
in the TDSRAM location pointed to by the
PG3..PG0 bits.
Header & Status Rows Location:
The 0.5 Kbyte block containing the Header, Status
Row 0 and Status Row 1 is pointed to by the
HS3..HS0 bits. The Row attribute (row count) is
stored in this block at offset 100h and contains 12
bytes for line mode (see DCM1R register description).
Row Scrolling Buffer Location:
The scrolling buffer corresponds to Row 12 when
the scrolling feature is used (in this case 11 rows
are scrolled).
Figure 73. Serial (40 Characters) Line Mode Mapping
0.5K TDSRAM
0.5K TDSRAM
Row 1
Row 11
Row 12/ Scrolling Buffer
Free Space
Resolution 0.5K bytes
Block
Number
(0.5K)
TDSRAM
Address
(hex.)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
8000
8200
8400
8600
8800
8A00
8C00
8E00
9000
9200
9400
9600
9800
9A00
9C00
9E00
TDPR
Value
(Hex.)
PG3..PG0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Header Char.
Status Row 0
Status Row 1
2K
Free Space
100h
Row Attr.
6K
Free Space
8K
Resolution 0.5K bytes
See Figure 22 for
Address Values
113/178
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.6.4 Building a Parallel Mode, 40 Char, Line
mode Display
Half-Page Location:
The pair of adjacent 0.5 Kbyte blocks of half page
content is stored in the TDSRAM location pointed
to by the PG3..PG0 bits. One block contains the
characters, the other block contains the attribute
bytes.
Header & Status Rows Location:
The 0.5 Kbyte block containing the Header, Status
Row 0 and Status Row 1 is pointed to by the
HS3..HS0 bits.
The Header/Status attributes are stored in this
block at offset 80h.
The Row attribute (row count) is stored in this
block at offset 100h and contains 12 bytes for line
mode (see DCM1R register description).
Row Scrolling Buffer Location:
The scrolling buffer corresponds to the Row 12
when the scrolling feature is used (in this case 11
rows are scrolled).
Figure 74. Parallel (40 Characters) Line Mode Mapping
0.5K TDSRAM
Row 1 Char.
0.5K TDSRAM
Row 1 Attr.
0.5K TDSRAM
Header Char.
Status Row 0
Status Row 1
Free Space
80h
Header Attr.
Status Row 0
Status Row 1
Row 11 Char.
Row 11 Attr.
Free Space
Row 12/Scrolling Buffer
Row 12/Scrolling Buffer
Row Attr.
Free Space
Free Space
Free Space
Resolution 1K bytes
See Figure 21 for Address Values
114/178
100h
Resolution 0.5K bytes
See Figure 22 for Address Values
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.6.5 Building a Serial Mode, 80 Char, Full
Page Display
Half-Page Location:
The pair of adjacent 1 Kbyte blocks of page content is stored in the TDSRAM location pointed to
by the PG3..PG0 bits. The first block contains the
left side of the page, the second block contains the
right side of the page.
Header & Status Rows Location:
The 0.5 Kbyte block containing the Header, Status
Row 0 and Status Row 1 is pointed to by the
HS3..HS0 bits.
Row Scrolling Buffer Location:
The scrolling buffer corresponds to the 40 bytes
following the Row 23 when the scrolling feature is
used.
Figure 75. Serial Mode (80 Characters) - Page Mapping
1K TDSRAM
1K TDSRAM
Row 1 Left
Row 1 Right
0.5K TDSRAM
Header
Status Row 0
Status Row 1
Row 23
Row 23
Scrolling Buffer
Free Space
Free Space
Scrolling Buffer
Free Space
Resolution 2K bytes
See Figure 23 for Address Values
Resolution 0.5K bytes
See Figure 22 for Address Values
115/178
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.6.6 Building a Serial Mode, 80 Char, Line
Mode Display
Half-Page Location:
The pair of 0.5 Kbyte blocks of half page content is
stored in the TDSRAM location pointed to by the
PG3..PG0 bits. The first block contains the left half
rows, the other block contains the right half rows.
Header/Status Rows Location:
The 0.5 Kbyte block containing the Header, Status
Row 0 and Status Row 1 is pointed to by the
HS3..HS0 bits.
The Row attribute (row count) is stored in this
block at offset 100h and contains 12 bytes for line
mode (see DCM1R register description).
Row Scrolling Buffer Location:
The scrolling buffer corresponds to Row 12 when
the scrolling feature is used (in this case 11 rows
are scrolled).
Figure 76. Serial (80 Characters) Line Mode Mapping
0.5K TDSRAM
0.5K TDSRAM
Row 11
Row 12/Scroll Buffer
Free Space
TDSRAM
TDSRAM
TDPR
Block
Address Left Address Right Value (hex)
Number(1K)
(hex)
(hex)
PG3..PG0
0
8000
8200
0
1
8400
8600
2
2
8800
8A00
4
3
8C00
8E00
6
4
9000
9200
8
Row 11
5
9400
9600
A
Row 12/Scroll Buffer
6
9800
9A00
C
Free Space
7
9C00
9E00
E
Row 1 Right
Row 1 Left
Resolution 1K bytes
Figure 77. Serial (80 Characters) Line Mode - Header and Status Mapping
0.5K TDSRAM
Header
Status Row 0
Status Row 1
See Figure 22 for Address Values
Free Space
100h
Row Attr.
Free Space
Resolution 0.5K bytes
116/178
2K
6K
8K
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
7.4.7 Font Mapping
G0 is the basic character font.
G1 is the mosaic font. It is not stored in ROM but is
implemented in hardware. In serial mode it is addressed by a serial attribute (See Figure 3). In parallel mode it is accessed by bit 0 (CSS) of the parallel shape attribute and bit 1 (US) for separated
mosaic (See Figure 4).
G2 is a font of X/26 based + Menu shared characters.
An Extended Menu character font available in parallel mode. It is accessed via bit 0 (CSS) in the parallel shape attribute (Character Set Selection).
The Extended Menu font is not accessible in serial
mode.
7.4.8 Font Mapping Modes
There are two font mapping modes selected
by the NCM bit in the NCSR register R245 (F5h)
Page 32:
Single G0 mode
A set combining 83 characters from
the G0 basic set plus 13 characters
selected from 15 National character
subsets. The National character subsets are selected by four bits (NC3:0)
in the NCSR register R245 (F5h)
Page 32.
Triple G0 mode
Three 96-character character sets
(G0-0, G0-1 and G0-2) for multi alphabet applications. Character set
selection is done by four bits (NC1:0
or NC3:2) in the NCSR register R245
(F5h) Page 32.
– In Serial Mode (Level 1), only 256 Character
Codes are available using an 8-bit code. The
character codes plus some serial attributes and
some additional programmable options address
566 chars: 256 + 182 NS chars + 128 mosaics in
single G0 mode.
– In Parallel Mode (Enhanced Level 1), 512 Character Codes are available using a 9-bit code. The
character codes plus some serial and parallel attributes, and some additional programmable options address 662 chars: 256 + 182 NS chars +
128 mosaic + 96 extended chars. in single G0
mode.
Display ROM Font Entry:
The user must define his own fonts for:
– 278 characters: - 15 x 13 G0 National Character
subsets + 83 G0 Character set
or
– 288 characters: 3 x 96-character character sets
– 128 G2 based X/26 and Menu characters
– 96 Extended Menu characters
Table 21. Triple G0 Mode - Font Mapping
ROM
Address
000h to 01Fh
020h to 07Fh
080h to 0FFh
100h to 15Fh
160h to 1BFh
1C0h to 1FFh
Character
CSS
Font Usage
Code
0E0h to 0FFh
1
Extended menu
020h to 07Fh
G0 set 0
0
080h to 0FFh
G2 + Menu
(or serial
020h to 07Fh mode)
G0 set 1
020h to 07Fh
G0 set 2
0A0h to 0DFh
1
Extended menu
117/178
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Table 22. National Character Subset Mapping
(Ordered by their G0 address)
1st
23h
8th
5Fh
2nd
24h
9th
60h
3rd
40h
10th
7Bh
4th
5Bh
11th
7Ch
5th
5Ch
12th
7Dh
6th
5Dh
13th
7Eh
7th
5Eh
Figure 78. Font Mapping
Addresses
0
1F
SERIAL
ATTRIBUTES
SERIAL MODE
Char. Codes
7F 80
(32 CODES) G1* (32)
0
1F
FF
G2 BASED
G0 + OPTIONAL NATIONAL SET
(96 CODES)
3F
+ MENU
(128 CODES)
G1* (32)
7F 80
5F
FF
*If Serial Attributes 19, 1A are used
Addresses
0
1F
SERIAL
PARALLEL MODE ATTRIBUTES
(PS=x, CSS=0) (32 CODES)
Char. Codes 0
Addresses
100
PARALLEL MODE
(PS=1, CSS=1)
FF
G2 BASED
G0 + OPTIONAL NATIONAL SET
(96 CODES)
+ MENU
(128 CODES)
1F
7F 80
11F
17F 180
FF
19F
ATTRIBUTES G1 (32)
G0 (32)
(32 CODES)
1F
1FF
EXTENDED
SERIAL
Char. Codes 0
118/178
7F 80
3F
5F
G1 (32)
RESERVED
(32)
7F 80
9F
MENU CHARACTERS
(96 CODES)
FF
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Table 23. Single G0 Mode - Font Mapping
ROM Address
000h to 01Fh
020h to 07Fh
080h to 0FFh
100h to 10Ch
10Dh to 119h
11Ah to 126h
127h to 133h
134h to 140h
141h to 14Dh
14Eh to 15Ah
15Bh to 167h
168h to 174h
175h to 181h
182h to 18Eh
18Fh to 19Bh
19Ch to 1A8h
1A9h to 1B5h
1C0h to 1FFh
Character Code
0E0h to 0FFh
020h to 07Fh
080h to 0FFh
(see table below)
(see table below)
(see table below)
(see table below)
(see table below)
(see table below)
(see table below)
(see table below)
(see table below)
(see table below)
(see table below)
(see table below)
(see table below)
(see table below)
0A0h to 0DFh
CSS
1
0
1
Font Usage
Extended menu
G0 + National Character Subset 0 (96 chars)
G2 + Menu (128 chars)
National Character Subset 1 (13 chars)
National Character Subset 2 (13 chars)
National Character Subset 3 (13 chars)
National Character Subset 4 (13 chars)
National Character Subset 5 (13 chars)
National Character Subset 6 (13 chars)
National Character Subset 7 (13 chars)
National Character Subset 8 (13 chars)
National Character Subset 9 (13 chars)
National Character Subset 10 (13 chars)
National Character Subset 11 (13 chars)
National Character Subset 12 (13 chars)
National Character Subset 13 (13 chars)(Free for user)
National Character Subset 14 (13 chars) (Menu chars.)
Extended menu
NC(3:0)
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
Table 24. National Character Subsets
Subset Name
Subset No.
(Decimal)
Character Code (Hex)
23 24 40 5B 5C 5D 5E 5F 60 7B 7C 7D 7E
Czech/Slovak
3
English
0
Estonian
9
French
1
German
4
Italian
6
Lettish/
Lithuanian
10
Polish
8
Portugese/
Spanish
5
Rumanian
7
Serbian/
Croatian/
Slovenian
12
Swedish/
Finnish
2
Turkish
11
119/178
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Figure 79. Pan-European Font (East/West) Character Codes (Hex.)
National Character Subset 0
Extended
Menu
G0_0
G2-Menu
National
Char.
Subsets
1..14d
Extended
Menu
Figure 80. OSD Picture in Parallel Mode
120/178
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY(Cont’d)
7.4.9 Register Description
HORIZONTAL BLANK REGISTER (HBLANKR)
R240 - Read/Write
Register Page: 32
Reset Value: 0000 0011 (03h)
7
HB7
0
HB6
HB5
HB4
HB3
HB2
HB1
HB0
It controls the length of the Horizontal Blank which
follows the horizontal sync pulse.
Bit 7:0 = HB[7:0]: The horizontal blank period is
calculated with a pixel down counter loaded on
each Hsync by HB[7:0]. During this period, FB = 0
and (R, G, B) = black.
Thblank = [(HB7*128 + HB6*64 + HB5*32 +
HB4*16 + HB3*8 + HB2*4 + HB1*2 + HB0) * Tpix]
VERTICAL POSITION REGISTER (VPOSR)
R242 - Read/Write
Register Page: 32
Reset Value: 0000 0000 (00h)
7
0
0
0
VP5
VP4
VP3
VP2
VP1
VP0
Bit 7:6 = Reserved, keep in reset state.
Bit 5:0 = VP[5:0]: The vertical start position is calculated with a line downcounter decremented on
each Hsync by VP[5:0]. The Display of the first row
begins when the counter turns to zero.
Vert delay = (VP5*32 + VP4*16 + VP3*8 + VP2*4
+ VP1*2 + VP0) * Tline (Tline= 64 µs)
HORIZONTAL POSITION REGISTER (HPOSR)
R241 - Read/Write
Register Page: 32
Reset Value: 0000 0011 (03h)
7
HP7
0
HP6
HP5
HP4
HP3
HP2
HP1
HP0
Bit 7:0 = HP[7:0]: The horizontal start position is
calculated with a pixel down-counter loaded on
each Hsync by HP[7:0]. The first character display
starts when the counter turns to zero.
Hori delay= [(HP7*128 + HP6*64 + HP5*32 +
HP4*16 + HP3*8 + HP2*4 + HP1*2 + HP0) * Tpix]
+ Thblank
121/178
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
FULL SCREEN COLOR CONTROL REGISTER
(FSCCR)
R243 - Read/Write
Register Page: 32
Reset Value: 0000 0000 (00h)
7
0
BE
TIO
MM
HTC
FSC3
FSC2
FSC1
FSC0
Bit 4 = HTC: Half-Tone/Translucency Control Bit
This bit allows the selection of TSLU or HT as alternate function output.
0: TSLU is selected as I/O pin alternate function
1: HT is selected as I/O pin alternate function
Bit 3:0 = FSC[3:0]: Full Screen Color control bits:
FSC[3:0]= (Half-intensity, R, G, B)
Table of Color Values (hex)
Bit 7 = BE: Box Enable, see Table 11.
Bit 6 = TIO: Text out/not in, see Table 11.
Bit 5 = MM: Mixed Mode, see Table 11.
Note: When Flash and Box attributes are decoded
at the same time on the characters of a header
(when BE=1, MM=1, TIO=1) the full screen over
the characters is displayed as transparant.
0 Black
1 Blue
2 Green
3 Cyan
4 Red
5 Magenta
6 Yellow
7 White
8 Black
9 Dark blue
A Dark green
B Dark cyan
C Dark red
D Dark magenta
E Dark yellow
F Grey
Table 25. Box Mode/Translucency Configurations
BE
0
0
TIO
x
x
MM
0
1
1
0
0
1
0
1
1
1
0
1
1
1
122/178
If Translucency is not used
Solid Background for all the display
Transparent Background for all the display
If Translucency is used
Translucent Background for all the display
Transparent Background for all the display
Text inside box translucent, Text outside box
Text inside box solid, Text outside box blanked
blanked
Text inside box with solid background Text out- Text inside box with translucent background Text
side box with transparent background
outside box with transparent background
Text inside box not displayed, transparent backText inside box not displayed, transparent background. Text outside box with translucent background. Text outside box with solid background
ground
Text inside box with transparent background.
Text inside box with transparent background. Text
Text outside box with solid background
outside box with translucent background
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
HEADER & STATUS CONTROL REGISTER
(HSCR)
R244 - Read/Write
Register Page: 32
Reset Value: 0010 1010 (2Ah)
7
0
Bit 4,2 = NS[1:0]: Serial/Parallel Mode Status
Rows display control bits. If the corresponding bit
is reset, the Status Row uses only serial attributes.
If the corresponding bit is set, the Status Row uses
parallel attributes (except size attributes).
0
0
ES1
NS1
ES0
NS0
EH
NH
Bit 7:6 = Reserved.
Bit 5,3 = ES[1:0]: Enable Status Rows [1:0] display control bits. If the bit is reset, the corresponding Status Row is filled with the full screen color; if
the bit is set, the corresponding Status Row is displayed (Status Row 1 is assumed to be the bottom
one).
Bit 1 = EH: Enable Header display control bit. If
set, the Header row is displayed; if reset, the
Header row is filled with the full screen color.
Bit 0 = NH: Serial/Parallel Mode Header display
control bit. If the bit is reset, the Header uses only
serial attributes. If the bit is set, the Header uses of
parallel attributes.
123/178
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
NATIONAL CHARACTER SET REGISTER
(NCSR)
R245 - Read/Write
Register Page: 32
Reset Value: 0000 0000 (00h)
7
TSLE
0
0
SWE
NCM
NC3
NC2
NC1
NC0
The register bit values are sampled and then activated only at each field start (on Vsync pulse).
Bit 7 = TSLE: Translucency/Half-Tone Output Enable bit.
0: Translucency/Half-Tone signal disabled
1: Translucency/Half-Tone is enabled. Translucency or Half-Tone realtime control signal is
routed in the TSLU/HT pin (depending on the
HTC bit in the FSCCR register).
Note: Translucent display depends also on the
BE, TIO and MM bits, see Table 11.
– either a single G0 alphabet with up to 15 national
sub-sets,
– or 3 different G0 alphabets.
If NCM is reset, a single G0 alphabet configuration
is activated and the 15 national sub-sets are selected through the NC[3:0] bits.
If NCM is set, a triple G0 alphabet configuration is
activated, the selection of the G0 set used for the
display is done through either NC[3:2] or NC[1:0]
bits, depending upon the SWE control bit and the
serial attribute 1Bh values.
Bit 3:0 = NC[3:0]: National Character Set Selection.
If the NCM bit is reset, these bits define which national sub-set has to be used to complete the basic
currently used G0 alphabet set.
If the NCM is set, these bits define which G0 is
used.
Figure 81. National Characters Selection
0
NCM
Bit 6 = Reserved.
Bit 5 = SWE: G0 Switch Enable Control Bit.
In case of a multiple G0 alphabet configuration
(NCM=1), this bit allows to switch from a first to a
second predefined G0 alphabet, using a single serial attribute (1Bh). In case of a single G0 alphabet
configuration (NCM=0), the SWE bit will have no
effect.
If SWE is reset, the used G0 alphabet is pointed
through NC[1:0].
If SWE is set, the used G0 alphabet is pointed
through NC[3:2] and NC[1:0] toggled by 1Bh serial
attribute.
Bit 4 = NCM: National Character Mode control bit.
This bit reconfigures a part of the font set as defining:
124/178
NC[3:0]
NS0
NS1
1
0
SWE
NC[1:0]
G0-0
G0-1
G0-2
NS14
15 NATIONAL 3 G0 SETS
CHAR. SETS
1
SERIAL ATTR. 1Bh
TOGGLE
NC[1:0]
G0-0
G0-1
G0-2
NC[3:2]
G0-0
G0-1
G0-2
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
CURSOR HORIZONTAL POSITION REGISTER
(CHPOSR)
R246 - Read/Write
Register Page: 32
Reset Value: 0000 0000 (00h)
7
0
0
CHP6 CHP5 CHP4 CHP3 CHP2 CHP1 CHP0
Bit 7 = Reserved.
Bit 6:0 = CHP[6:0]: Cursor Horizontal Position.
The cursor is positioned by character.
CHP= 0 points to the first character
CHP= 39d points to the end of the row (single
page display)
CHP= 79d points to the last character in the row
(double page display)
CURSOR VERTICAL POSITION REGISTER
(CVPOSR)
R247 - Read/Write
Register Page: 32
Reset Value: 0000 0000 (00h)
7
FON
TV fields followed by a "1" state during the 16 next
TV fields. This flag provides a 1Hz time reference
for an easy software control of all flashing effects
(assuming a 50 Hz TV signal, the FON total period
will be 0.96 seconds).
This bit is READ ONLY. Trying to write any value
will have no effect.
Bit 6:5 = CM[1:0]: Cursor Mode control bits .
CM1 CM0
Cursor Mode
0
0
Cursor Disable
Static Cursor (inverted foreground & invert0
1
ed background colours)
Flash Cursor (flash from current to inverted
1
0
colours & vice versa)
Cursor done with Underline (use of current
1
1
foreground color)
Bit 4:0 = CVP[4:0]: Cursor Vertical Position.
The cursor is positioned by row. The cursor is always single size.
CVP= 0 locates the cursor on the Header row
CVP= 25d locates the cursor on the last Status
row.
0
CM1
CM0
CVP4
CVP3
CVP2
CVP1
CVP0
Bit 7 = FON: "Flash On" flag bit.
The FON bit remains at "0" during 32 consecutive
125/178
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
SCROLLING CONTROL LOW
(SCLR)
R248 - Read/Write
Register Page: 32
Reset Value: 0000 0000 (00h)
REGISTER
7
0
SCE
FSC
SS
FRS4
FRS3
FRS2
FRS1
FRS0
Bit 7 = SCE: Scrolling Enable
Before enabling scrolling, the scrolling area must
be defined by the FRS[4:0] and LRS[4:0] bits. The
scrolling direction is defined by the UP/D bit.
0: Disable scrolling
1: Enable scrolling
Bit 6 = FSC: Freeze scrolling
Note: The 2 control bits SCE and FSC must be set
to "1" before enabling the Global double height
(see the DH bit in the SCHR register).
Bit 5 = SS: Scrolling Speed Control bit.
0: The display is shifted by 2 TV lines at each TV
frame (i.e. after 2 Vertical sync pulses).
1: The display is shifted by 4 TV lines at each TV
frame.
Bit 4:0 = FRS[4:0]: These bits define the uppermost Row value to be scrolled (rows are numbered from 1 to 23). In case of global double height
mode programming, FRS[4:0] must mandatorily
be equal to 00000.
Table 26. Scrolling Control Bits
DH
0
SCE
0
FSC
x
0
1
x
1
0
x
126/178
UP/D
x
1
0
1
0
FRS[4:0] LRS[4:0]
Meaning
x
x
No Global Double Height, No Scrolling
x
x
No Global Double Height, Scroll up
x
x
No Global Double Height, Scroll down
0
x
Global Double Height, No Scrolling, Display top half
0
x
Global Double Height, No Scrolling, Display bottom half
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
SCROLLING CONTROL HIGH
(SCHR)
R249 - Read/Write
Register Page: 32
Reset Value: 0000 0000b (00h)
REGISTER
7
DH
0
EER
UP/D
LRS4
LRS3
LRS2
LRS1
LRS0
Bit 7 = DH: Global Double Height control bit.
This bit must only be used in Page Mode. When
DH is set, the display is turned in double height including the header, excluding the vertical offset
before the display area. The status rows are not
affected by the DH bit and they remain in normal
height. Depending on the value of the UP/D control bit, when DH is set, the first or second half of
the page is displayed in double height. This bit assumes a zooming function.
Notes:
– In global double height, when the top half page
is displayed, if row 11 has a double height attribute, the first status row is corrupted. To avoid
this effect, save row 11, remove the serial double
height attribute from this row and display the upper part of the page. Then, before displaying the
lower part of the page, restore the serial DH attribute in row 11.
– When the bottom half page is displayed, if row 23
has a double height attribute, the first status row
is not displayed. To avoid this effect remove the
serial double height attribute from row 23.
Bit 6 = EER: End of Extra Row flag bit.
This bit is forced to "1" by hardware when the last
line of the extra row is displayed in case of scrolling in normal height. This bit is Read only.
In Global double height, the EER bit is set to "1"
each time the last line of a new displayed row appears.
Bit 5 = UP/D: Scrolling Up/Down
This bit has two functions: to control the scrolling
direction and to select the half part of the page in
Global Double Height display.
Scrolling direction:
0: Top-Down shift
1: Bottom-up shift
Half-page selection:
When DH is set, if UP/D is set, the upper half of the
page is displayed (i.e. Header and the page rows 1
to 11).
When DH is set, if UP/D is reset, the lower half of
the page is displayed (i.e. rows 12 to 23 and the
Status rows).
The UP/D control bit must be defined before setting the Global height (DH bit); changing UP/D after DH is set, will not change the already selected
half page.
Bit 4:0 = LRS[4:0]: Last row to be scrolled (1 to
23). In case of scrolling in global double height, the
Last row must be equal to 0x 10111 to display the
status row in the two half pages.
127/178
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
Figure 82. Memory Management for Scrolling Window
Freeze off
after 5 Vsync
Normal Height
T0
3 rows to be
scrolled
Freeze on
after 5 Vsync
New TDSRAM address
after EER=1
ROW A
ROW A
ROW A
ROW B
ROW B
ROW B
ROW C
ROW C
ROW C
EER=0
T + 5 VSYNC
ROW A
ROW A
ROW A
ROW B
ROW B
ROW B
ROW C
ROW C
ROW C
ROW D
ROW D
ROW D
EER=0
ROW A
TDSRAM
CONTENT
DISPLAY
AREA
ROW C
Row 24
ROW D
NEW
TDSRAM
CONTENT
ROW B
ROW B
ROW C
ROW D
ROW B
T + 10 VSYNC
ROW C
ROW D
ROW A
ROW B
ROW B
ROW C
ROW C
ROW D
ROW D
EER=1
T + 15 VSYNC
ROW A
ROW A
ROW B
ROW B
ROW B
ROW C
ROW C
ROW C
ROW D
ROW D
ROW D
ROW E
EER=0
A = First row to scroll
C= Last row to scroll
E= Extra row
128/178
Row 24
ROW E
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
DISPLAY CONTROL MODE
(DCM0R)
R250 - Read/Write
Register Page: 32
Reset Value: 0000 0000 (00h)
0
REGISTER
7
DE
0
STE
FRE
CE
GFR
GRE
SF
Bit 6 = STE: Semi-Transparent Enable bit.
This bit is active only in Single page display mode.
While the Display is disabled, the horizontal and
vertical sequencers are forced in their reset state
and the RGB & FB DACs are not off (still presenting on-chip resistors to Ground).
Note: This mode shows a visible grid on the
screen.
Bit 5 = FRE: Fringe Enable control bit.
If this bit is set, and the SWE bit is reset (refer to
the National Character Set Register description)
the serial attribute 1Bh has a fringe toggle function.
SWE
0
1
0
1
Bit 3 = GFR: Global Fringe Enable control bit.
If this bit is set, the whole display is in fringe mode
(except if a Double page display mode is programmed).
S/D
Bit 7 = DE: Display Enable control bit.
If DE is reset, no display will be performed. If DE is
set, a display will be done as defined through the
various control bits.
FRE
0
0
1
1
1: Conceal any text defined as concealed by serial
attributes
1Bh Serial attribute acts as:
No Action
G0 Toggle
Fringe Toggle
G0 Toggle
Bit 4 = CE: Conceal Enable control bit.
0: Reveal any text defined as concealed by serial
attributes (Default)
Bit 2 = GRE: Global Rounding Enable control bit.
If this bit is set, the whole display is in rounding
mode (except if a Double page display mode is
programmed).
Bit 1 = SF: Screen Format control bit.
0: Configures the Display for 4/3 TV screen format.
1: A fixed offset of 128 Pixel clock periods is added
before any character is displayed; the Full
Screen Color attribute is used while the offset is
running.
The SF bit intended for displaying on 16/9 TV
screen format tubes, the display picture will be recentered.
Bit 0 = S/D: Single or Double page control bit.
0: A single page is displayed on screen (i.e. 40character width).
1: A set of two pages is displayed contiguously
(i.e. 80-character width).
Note: In 80 characters per row and in full page
mode, line 25 of each field is displayed as a
transparant line (as this line is not in the visible
part of the screen, this should not present a limitation).
Programming a Double page display will automatically mask the Fringe, Rounding and Parallel
Mode control bits. Their register values are not
changed and they will automatically recover their
initial effect if the display is switched back in a Single page mode.
129/178
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
DISPLAY CONTROL MODE
(DCM1R)
R251 - Read/Write
Register Page: 32
Reset Value: 0000 0000 (00h)
1
REGISTER
7
0
0
0
0
0
EXTF
FBL
PM
SPM
Bit 7:4 = Reserved bits, keep in reset state.
mode, i.e. a character or attribute is coded with a
single byte. If the SPM bit is set, the display is
done in Parallel mode, i.e. a character or an attribute is coded on two bytes.
TDSRAM POINTER REGISTER (TDPR)
R252 - Read/Write
Register Page: 32
Reset Value: 0000 0000 (00h)
7
HS3
Bit 3 = EXTF: External Font.
Only when the emulator is used, this bit selects the
font memory containing a user-defined OSD font.
In normal user application, this bit has no effect.
0: Internal font memory of the emulator chip.
1: External font RAM of the emulator board.
Bit 2 = FBL: Fast Blanking Active Level control bit.
The FBL bit must be reset if the on-screen display
is done while the FB output is low. The FBL bit
must be set if the on-screen display is done while
the FB output is high. This bit also controls the
TSLU AF output polarity with the same rule as for
FB.
Bit 1 = PM: Line Mode control bit.
If PM is reset, the display is working in Full page
mode, i.e. the screen is composed of one header,
23 text rows plus 2 status rows. If PM is set, the
display works in Line mode.
Line mode allows up to 12 rows to be displayed
anywhere on the screen. The row attribute (see
TDSRAM mapping) contains the row numbers on
the screen. The byte position of the row attribute
conrresponds to the row in the TDSRAM. For example, if the 3rd byte of the row attribute contains
6, the 3rd row in TDSRAM will be displayed as the
6th row on the screen.
Bit 0 = SPM: Serial/Parallel Mode control bit.
If the SPM bit is reset, the display is done in Serial
130/178
0
HS2
HS1
HS0
PG3
PG2
PG1
PG0
Bit 7:4 = HS[3:0]: Location of the current Header
and Status Rows in the TDSRAM.
Bit 3:0 = PG[3:0]: Location of the current Page
content (rows 1 to 23) in the TDSRAM. For more
details, refer to Section .
The HS[3:0] and PG[3:0] bits described by the
R246 and R247 registers in page 32. Display locations, Head/Stat location, Page location, are physically the same: these sets of address bits can be
modified through two different programming accesses.
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
DISPLAY ENABLE 0 CONTROL REGISTER
(DE0R)
R253 -Read/Write
Register Page: 32
Reset Value: 1111 1111 (FFh)
7
R8
R7
R6
R5
R4
R3
R2
0
7
R1
x
Bit 7:0 = R[8:1]: Row display enable control bit.
When the “Ri” bit is set (Reset value), the corresponding row (with row in the page, numbered
from 1 to 23) will be displayed. When the “Ri” bit is
reset, the full screen color is displayed.
DISPLAY ENABLE 1 CONTROL REGISTER
(DE1R)
R254 -Read/Write
Register Page: 32
Reset Value: 1111 1111 (FFh)
7
R16
DISPLAY ENABLE 2 CONTROL REGISTER
(DE2R)
R255 -Read/Write
Register Page: 32
Reset Value: x111 1111 (xFh)
0
R23
R22
R21
R20
R19
R18
R17
Bit 7 = Reserved
.
Bit 6:0 = R[23:17]: Row display enable control bit.
When the “Ri” bit is set (Reset value), the corresponding row (with row in the page, numbered
from 1 to 23) will be displayed. When the “Ri” bit is
reset, the full screen color is displayed.
0
R15
R14
R13
R12
R11
R10
R9
Bit 7:0 = R[16:9]: Row display enable control bit.
When the “Ri” bit is set (Reset value), the corresponding row (with row in the page, numbered
from 1 to 23) will be displayed. When the “Ri” bit is
reset, the full screen color is displayed.
131/178
ST92185B - ON SCREEN DISPLAY (OSD)
ON SCREEN DISPLAY (Cont’d)
DEFAULT COLOR REGISTER (DCR)
R240 - Read/Write
Register Page: 33
Reset Value: 0111 0000 (70h)
TDSRAM PAGE POINTER REGISTER (TDPPR)
R246 - Read/Write
Register Page: 33
Reset Value: xxx0 0000 (x0h)
7
0
DFG3 DFG2 DFG1 DFG0 DBG3 DBG2 DBG1 DBG0
Bit 7:4 = DFG[3:0]: Default Foreground Color.
DFG[3:0] = (Half-Intensity, R, G, B)
x
8 Black
9 Dark blue
A Dark green
B Dark cyan
C Dark red
D Dark magenta
E Dark yellow
F Grey
0
ACP4
ACP3
ACP2
ACP1
ACP0
Bit 7:5 = Reserved, keep in reset state.
Bit 4:0 = ACP[4:0]: Absolute Vertical Position of
the cursor in case of double height or scrolling.
132/178
0
PG3
PG2
PG1
7
0
0
x
PG0
TDSRAM HEADER/STATUS POINTER REGISTER (TDHSPR)
R247 - Read/Write
Register Page: 33
Reset Value: xxx0 0000 (x0h)
CURSOR ABSOLUTE VERTICAL POSITION
REGISTER (CAPVR)
R241 - Read/Write
Register Page: 33
Reset Value: 0000 0000 (00h)
0
x
Bit 7:4 = Reserved, keep in reset state.
x
7
0
Bit 3:0 = PG[3:0]: Page Pointer
Location of the current Page content (rows 1 to 23)
in the TDSRAM. For more details, refer to the Display Memory Mapping Section .
Bit 3:0 = DBG[3:0]: Default Background Color
DBG[3:0] = (Half-Intensity, R, G, B)
Table of Color Values (hex)
0 Black
1 Blue
2 Green
3 Cyan
4 Red
5 Magenta
6 Yellow
7 White
7
0
x
x
0
HS3
HS2
HS1
HS0
Bit 7:4 = Reserved, keep in reset state.
Bit 3:0 = HS[3:0]: Header/Status Rows Pointer
Location of the current Header and Status Rows in
the TDSRAM. For more details, refer to the Display Memory Mapping paragraph Section .
ST92185B - ON SCREEN DISPLAY (OSD)
7.4.10 Application Software Examples
Before starting an OSD Display, it is very important to start all the internal clock/timings
To understand the software routines given below, make a thorough study of the chapters on the Reset
and Clock Control Unit (RCCU) and the TDSRAM Interface.
Initialization of the Internal Clock
;=========================================================================
;
MAIN CLOCK INIT
;=========================================================================
CLOCKS::
;--------- CPU MAIN CLOCK -----------; C K M A I N provided by the freq. multplier
spp #TCCR_PG; Timings & clock Controller registers page
; page 39 or 27
ld MCCR,#0x05; program the frequency multiplier down
; counter in the feed-back loop (253 =FD)
; freq=(5+1)*2 =12Mhz
; freq=(7+1)*2 =16Mhz
; freq=(8+1)*2 =18Mhz
ld MCCR,#0x85; enable the freq. multiplier
srp #BK20
ldw rr0,#0x2FFF;
time_stab1:
; for frequency multiplier stabilization
decw rr0; change CPU source clock & wait clock stabilization
cpw rr0,#0x00;
jxnz time_stab1;
ld MCCR,#0xC5 ; select the freq. multiplier as main clock
pop ppr
;=========================================================================
;
SYNCHRO START
;=========================================================================
spp #SYCR_PG
; set page pointer to page 23h or 35 decimal
ld CSYCTR,#000h; R243, Hsync and Vsync from deflection part
(external)
ld CSYSUR,#0C4h; R242 Sync Controller Set-up register
; Standard mode, Positive polarity of Hsync & Vsync
; delay on Hsync/Vsync HSF(3:0)=9
;=========================================================================
;
DISPLAY PIXEL CLOCK
;=========================================================================
;
spp #TCCR_PG; Timings & clock Controller registers page
; set page pointer to page 39 decimal
ld SKCCR, #0x09; FE, Skew clock control register
; program the frequency multiplier down
; counter in the feed-back loop
133/178
ST92185B - ON SCREEN DISPLAY (OSD)
; dot_freq= 4Mhz(4+1)=20Mhz (4/3)
; dot_freq= 4Mhz(5+1)=24Mhz (16/9)
; divide by 2
ld SKCCR, #0x89; enable the freq. multiplier
srp #BK20
ldw rr0,#0x0FFF;
time_stab2:
; for frequency multiplier stabilization
decw rr0; SKEW clock stabilization
cpw rr0,#0x00 ;
jxnz time_stab2;
ld PXCCR,#0x80;(PXCCR) start Pixel Line PLL
spp #TDSR_PG2; page 26h, TDSRAM Controller registers third page
srp #000h
ld CONFIG, #003h; FC, ram Interface Configuration register
; enable display and Dram access
;=======================================================================
Initialization of the OSD in Serial Mode
;=======================================================================
; INIT DISPLAY ROUTINE
;=======================================================================
INIT::
;-----------Display Position & Black Reference
spp #DMP1_PG; page 020h Display memory map registers page
ld HBLANKR,#0x45; HBLANKR register [7: 0]; reset=03
; important delay for black reference on RGB cathod
ld HPOSR,#0x35; HPOSR register [7:0]; reset=03
ld VPOSR,#0x10; VPOSR register [5:0]; reset=00
;----------------spp #DMP1_PG; page 020h Display memory map registers page
; F3, Full Screen Color register
ld FSCCR, #0x01 ; no subtitle mode
; BE, Box enable
; TIO, Text in/out
; MM, Mixed Mode
; FSC[3:0]=half blue full screen
ld HSCR, #03Fh; bit5,
4,
3,
2, 1, 0
; ES1 , NS1, ES0, NS0, EH, NH
; 0x3F > set header and status in level 1+
;
(parallel)
; 0x2a > set header and status in level 1
; F5, National Characters register
ld NC, #010h; SWE, NCM, NC[3:0]
;------- Scrolling INIT ---------spp #DMP1_PG; page 020h Display memory map registers page
134/178
ST92185B - ON SCREEN DISPLAY (OSD)
; F8, Scrolling Control Line register
ld SCLR ,#000h ; SCE, FSC, SS, FIRSTROWSCRO[4:0]
; F9, Scrolling Control Horizontal register
ld SCHR ,#02fh ; DH, ER, UP/D, LASTROWSCRO[4:0]
;------- Cursor position
; F8, Scrolling Control Line register
ld SCLR ,#000h ; SCE, FSC, SS, FIRSTROWSCRO[4:0]
; F9, Scrolling Control Horizontal register
ld SCHR ,#02fh ; DH, ER, UP/D, LASTROWSCRO[4:0]
; F6, Cursor Horizontal Position register
ld CHPOSR , #005h; CURSOR HPOS [6:0]
; F7, Cursor Vertical Position register
ld CVPOSR , #000h; FON, CM[1:0], CURSOR VPOS[4:0]
;------- Control
; FA, Control Mode 0 register
ld DCM0R,#0a0h; DE, STE, FRE, CE, GFR, GRE, SF=4/3, S/D=40
; display enable
; solid mode
; toggle fringe enable
ld DCM1R,#0x04; register 251 (FBh) Control Mode 1 register
; DAT[6:4]/bits 7,6,5 & TDR/bit4
; FNEX=0, on-chip font
; FBL=1 fastblanking active high
; PM =0 Full page mode
; SPM =0 serial mode
;--------Dram location: header/status rows, current display
; FC, Dram Location register
ld TDPR, #080h; HS[3:0], AD[3:0]
; for header bit12=1
;------- foreground/background
spp #DMP2_PG; page 021h Display memory map registers page
ld DC, #07Fh ; reg. F0h, DFG [3:0], DBG [3:0]
; FG full white
; BG grey (half white)
;----------------------------spp #DMP1_PG; page 020h Display memory map registers page
ld DE0R, #0FFh; ROWEN [8:1]
ld DE1R, #0FFh; ROWEN [16:9]
ld DE2R, #0FFh; ROWEN [23:17]
ret
=======================================================================
135/178
ST92185B - SYNC CONTROLLER
7.5 SYNC CONTROLLER
sharing by the Display Controller and the CPU (for
more details refer to the TDSRAM Controller chapter). Field information is also available for the Display Controller.
The SYNC Controller unit also generates two interrupt sources corresponding respectively the TV
field start and to the end of VBI event (“VBI” stands
for Vertical Blank Interval).
The SYNC Controller implements also a “Composite Sync” signal generator which provides a composite sync output signal (called CSO) available
through an I/O port alternate function.
The SYNC Controller receives Horizontal / Vertical
sync information coming from the chassis. The
VSYNC and HSYNC inputs use schmitt triggers to
guarantee sufficient noise rejection.
The SYNC Controller unit provides the H internal
sync signal to the Display Skew Corrector, which
rephases the Pixel clock.
It provides also the H and V internal sync signals
to the TDSRAM Controller to perform correct TV
line counting, thus generating the necessary time
windows for a proper TDSRAM access real time
Figure 83. Sync Controller Block Diagram
n
VSYNC
Vout
(to DISPLAY, etc.)
VPOL
VSEP
HSYNC
CSYNC
FLDST
interrupt
Vertical
Sync Extr.
Pulse
shaper
HPOL
VDLY
VPOL
Field
(from Sync Ext.)
MOD1
MOD0
4 MHz
Vcso
Vertical Pulse
Generator
1
MOD0
0
Internal
H generator
(64 µs)
0
1
MOD1
Vertical
Controller
Equalization Pulse
Hpls
CSO_AF
& Line Sequencer
Composite Sync.
Generator
(MOD0+MOD1)*VSEP
HSF(3:0)
Vout
Hpls
Skew
Corrector
HPOL VDLY
MOD1 FLDEV EOFVBI VBIEN
VPOL
MOD0 FLDST FSTEN
VSEP HSF(3:0)
Hint
pgmble
delay
Field
detect.
FLDEV
Vout
Pulse
shaper
EOFVBI
line counter
HFLG
interrupt
Hout (to DISPLAY, etc.)
SCCS0 Register
SCCS1R Register
VR02092A
136/178
ST92185B - SYNC CONTROLLER
SYNC CONTROLLER (Cont’d)
7.5.1 H/V Polarity Control
Two control bits manage the H/V polarities. HPOL
(SCCS0R.6) manages the HSYNC polarity (a positive polarity assumes the leading edge is the rising one). VPOL (SCCS0R.7) controls the VSYNC
polarity.
7.5.2 Field Detection
Field detection is necessary information for the
Display controller for fringe and rounding features.
To determine correctly the field in case of using
separate H and V input signals, it is necessary to
provide an internal compensation of the hardware
delay generated on VSYNC (VSYNC is generally
issued by integrating the equalization pulses).
Therefore the VSYNC leading edge is compared
to the leading edge of an internally delayed
HSYNC.
The delay applied to HSYNC is software programmable through the SCCS0R (3:0) bits (from 0 to 63
µs). It must be calculated by the user as being the
time constant (modulo 64 µs) used to extract
VSYNC by the other components of the chassis.
7.5.3 Interrupt Generation
The SYNC Controller unit can provide two different
interrupts to the ST9+ Core. The first interrupt appears at each beginning of field upon detection of
the Vertical Sync pulse coming from the deflection
circuitry (i.e. from VSYNC); it is called the “Field
start” interrupt. A flag is associated to this interrupt, called “FLDST” (SCCS1R.6). This flag is set
to “1” by hardware when the Vertical Sync pulse
appears. It must be cleared by software.
The second interrupt appears at the end of each
Vertical Blank Interval. It is generated at the begin-
ning of the line 25 counted from the deflection circuitry (i.e. from VSYNC); and is called the “End OF
VBI” interrupt. A flag is associated to this interrupt,
called “EOFVBI” (SCCS1R.7). This flag is set to
“1” by hardware when the line 25 starts. It must be
cleared by software.
These two interrupts EOFVBI and FLDST are respectively attached to the INT4 and INT5 external
interrupt inputs of the ST9+ Core. The leading
edges of the 2 interrupt requests are the falling
ones. (For more details, refer to the Interrupts
chapter).
7.5.4 Sync Controller Working Modes
Different working modes are available fully controlled by software.
The first two working modes assume that TV deflection sync signals are available and stable.
The last two modes assume that no TV signal is
available. The chip works in a free-running mode
providing standard TV Sync signals based on the
main internal 4 MHz clock.
Switching from one mode to any other is done under full software control, through the programming
of two control bits called as MOD1 and MOD0.
These control bits are described in the SCCS1R
register
7.5.4.1 Standard Sync Input Mode
This mode is accessed when both MOD1 and
MOD0 bits are reset.
In this mode, the µP receives the chassis synchro
through two separate inputs. These are VSYNC
and HSYNC. It also assumes the VSEP
(SCCS0R.5) is reset.
137/178
ST92185B - SYNC CONTROLLER
SYNC CONTROLLER (Cont’d)
7.5.4.2 Composite Sync Input Mode
This mode is very similar to the “Standard Sync Input Mode” described above. It is also accessed
when both MOD1 and MOD0 bits are reset.
In Composite Sync mode, a single CSYNC/
HSYNC input pin is used to enter both the horizontal and vertical sync pulses (VSEP control bit is set
to 1). In this mode, the VSYNC pin must be tied to
VSS on the application board to prevent a floating
CMOS input configuration.
The CSYNC signal characteristics are assumed to
perfectly respect the STV2160 TXTOUT pin specification which is reviewed in Figure 84 & Figure
85.
The vertical sync signal is extracted from the
CSYNC signal by the mean of an Up/Down counter used as a digital integrator. The counter works
in “Up” mode during the sync pulses.
Two time constants can be programmed using the
VDLY control bit (refer to the register description).
The smallest one corresponds to 16µs; the second
one being 32µs.
Figure 84. STV2160 TXTOUT Timings
n
1st TV Field
623
624
625
8µs
TXTOUT
1
2
8µs
58µs
3
4
5
6
38µs 8µs
2nd TV Field
311
TXTOUT
138/178
312
8µs
313
8µs
314
58µs
315
6µs
8µs
316
317
318
319
VR02092B
ST92185B - SYNC CONTROLLER
SYNC CONTROLLER (Cont’d)
7.5.4.3 Free-Running Monitor Sync Mode
This mode is accessed when the MOD1 bit is set.
In this mode, the chassis HSYNC and VSYNC signals are not used. They are replaced by the sync
signals which are fully Crystal based (use of the internal main 4 MHz Clock).
Two free-running monitor modes are available:
when the MOD0 bit is reset the Composite Sync
output (CSO) is generated for a 60Hz format;
when the MOD0 bit is set to “1” the Composite
Sync output (CSO) is generated for a 50Hz format.
For both formats, the TV line period is 64µs.
The Composite Sync alternate function Output
(CSO) can be activated or disabled under control
of the VSEP bit.
In Free-Running Monitor Sync mode, the VPOL
control bit is used to control whether an interlaced
or non-interlaced TV context must be generated.
When the non-interlaced context is programmed,
only the “1st TV Field” configuration is generated.
Figure 85. Even/Odd Field Timings
n
1st TV Field
d1
d1
d2
622
623
624
625
1
2
3
4
5
6
(50 Hz Mode)
522
523
524
525
1
2
3
4
5
6
(60 Hz Mode)
d1 = 4.75 µs
2nd TV Fieldd1
d2 = 2.25 µs
d2
310
311
312
313
314
315
316
317
318
319 (50 Hz Mode)
260
261
262
263
264
265
266
267
268
269 (60 Hz Mode)
VR02092C
139/178
ST92185B - SYNC CONTROLLER
SYNC CONTROLLER (Cont’d)
7.5.5 Register Description
For other cases:
SYNC CONTROLLER CONTROL AND STATUS
REGISTER 0 (SCCS0R)
R242 - Read/Write
Register Page: 35
Reset value: 0000 0000 (00h)
0
VPOL
HPOL
VSEP
VDLY
HSF3 HSF2
HSF1
HSF0
Bit 7= VPOL. VSYNC Polarity
When MOD[1:0] are reset, this bit configures the
polarity of the VSYNC input.
0: Negative polarity (leading edge is falling edge)
1: Positive polarity (leading edge is rising edge)
For other cases:
MOD1
0
x
x
1
1
MOD0 VPOL
0
x
VSYNC polarity control
1
0
interlaced
1
1
non-interlaced
x
0
interlaced
x
1
non-interlaced
Bit 6= HPOL. HSYNC/CSYNC Polarity .
0: Negative polarity (leading edge is falling edge)
1: Positive polarity (leading edge is rising edge)
Bit 5= VSEP. Separate Sync
When MOD[1:0] are reset:
0: The standard mode using two inputs (VSYNC
and HSYNC) is activated.
1: The Composite Sync mode is activated; the
HSYNC/CSYNC input will be used to get both H
and V signals.
140/178
MOD1
0
x
x
1
1
MOD0
0
1
1
x
x
VSEP
x
0
1
0
1
CSO alternate function
disabled
disabled
enabled
disabled
enabled
Bit 4= VDLY. Vertical Delay control bit.
This bit is active only if the Composite Sync mode
is enabled. The selection of this bit can effect
noise margin (longer delay is better) and the field
detection.
0: Vertical is generated after detecting a pulse
greater than 16µs
1: Vertical is generated after detecting a pulse
greater than 32µs
Bit 3:0= HSF. Horizontal Shift for Field detection.
These 4 bits program the delay, in steps of 4µs,
applied to the HSYNC pulse in order to properly
determine the field information by comparison with
VSYNC. This value is a chassis constant depending upon the way the separate H/V signals are
generated.
ST92185B - SYNC CONTROLLER
SYNC CONTROLLER (Cont’d)
SYNC CONTROLLER CONTROL AND STATUS
REGISTER 1 (SCCS1R)
R243 - Read/Write
Register Page: 35
Reset value: 0000 0000 (00h)
7
0
EOFVBI FLDST FLDEV HFLG FSTEN VBIEN MOD1 MOD0
Bit 7= EOFVBI: End Of VBI Flag.
This bit is set to “1” by hardware at the beginning
of the line 25 of the current field, when the End of
VBI interrupt request is sent to the Core. The
EOFVBI flag must be reset by software before the
end of the current field.
Bit 6= FLDST: Field Start Flag .
This bit is set to “1” by hardware on the leading
edge of the vertical sync pulse when the field start
interrupt request is forwarded to the Core. The
FLDST flag must be reset by software before the
end of the current field.
Bit 5= FLDEV: Field Even Flag.
This bit is read-only. It indicates which field is currently running;
0: First field is running
1: Second field is running
Bit 4= HFLG: Horizontal Sync Flag.
This bit is read-only. It just copies the Horizontal
sync transient information issued by the horizontal
pulse shape unit. The bit is read at “1” at during
each H sync pulse and lasts to “1” up to 4 µs.
Bit 3= FSTEN: Field Start Interrupt Enable.
0: The FLDST interrupt is disabled and the external interrupt pin becomes the interrupt input.
1: The FLDST interrupt is enabled and the interrupt from the external pin is disabled.
Bit 2= VBIEN: VBI Interrupt Enable.
0: The EOFVBI interrupt is disabled and the external interrupt pin becomes the interrupt input.
1: The EOFVBI interrupt is enabled and the interrupt from the external pin is disabled.
Bit 1:0= MOD[1:0]:
& V sync
MOD1 MOD0 Hsources
chassis
0
0
sync pulses
0
1
reserved
from Xtal
1
0
(60 Hz)
from Xtal
1
1
(50 Hz)
CSO
no
yes
yes
CSO generator
reserved
on-chip timing generator; free-running
on-chip timing generator; free-running
n
141/178
ST92185B - SERIAL PERIPHERAL INTERFACE (SPI)
7.6 SERIAL PERIPHERAL INTERFACE (SPI)
7.6.1 Introduction
The Serial Peripheral Interface (SPI) is a general
purpose on-chip shift register peripheral. It allows
communication with external peripherals via an
SPI protocol bus.
In addition, special operating modes allow reduced software overhead when implementing I2Cbus and IM-bus communication standards.
The SPI uses up to 3 pins: Serial Data In (SDI),
Serial Data Out (SDO) and Synchronous Serial
Clock (SCK). Additional I/O pins may act as device
selects or IM-bus address identifier signals.
The main features are:
■ Full duplex synchronous transfer if 3 I/O pins are
used
Master operation only
■ 4 Programmable bit rates
■ Programmable clock polarity and phase
■ Busy Flag
■ End of transmission interrupt
■ Additional hardware to facilitate more complex
protocols
7.6.2 Device-Specific Options
Depending on the ST9 variant and package type,
the SPI interface signals may not be connected to
separate external pins. Refer to the Peripheral
Configuration Chapter for the device pin-out.
■
Figure 86. Block Diagram
SDI SCK/INT2
SDO
READ BUFFER
SERIAL PERIPHERAL INTERFACE DATA REGISTER
( SPIDR )
*
R253
DATA BUS
INT2
END OF
TRANSMISSION
INT2
POLARITY
PHASE
MULTIPLEXER
1
0
BAUD RATE
INTCLK
SPEN BMS
ST9 INTERRUPT
INTB0
ARB BUSY CPOL CPHA SPR1 SPR0
SERIAL PERIPHERAL CONTROL REGISTER ( SPICR )
* Common for Transmit and Receive
n
142/178
R254
INTERNAL
SERIAL
CLOCK
TO MSPI
CONTROL
LOGIC
VR000347
ST92185B - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
7.6.3 Functional Description
The SPI, when enabled, receives input data from
the internal data bus to the SPI Data Register
(SPIDR). A Serial Clock (SCK) is generated by
controlling through software two bits in the SPI
Control Register (SPICR). The data is parallel
loaded into the 8 bit shift register during a write cycle. This is shifted out serially via the SDO pin,
MSB first, to the slave device, which responds by
sending its data to the master device via the SDI
pin. This implies full duplex transmission if 3 I/O
pins are used with both the data-out and data-in
synchronized with the same clock signal, SCK.
Thus the transmitted byte is replaced by the received byte, eliminating the need for separate “Tx
empty” and “Rx full” status bits.
When the shift register is loaded, data is parallel
transferred to the read buffer and becomes available to the CPU during a subsequent read cycle.
The SPI requires three I/O port pins:
SCK
Serial Clock signal
SDO
Serial Data Out
SDI
Serial Data In
An additional I/O port output bit may be used as a
slave chip select signal. Data and Clock pins I²C
Bus protocol are open-drain to allow arbitration
and multiplexing.
Figure 2 below shows a typical SPI network.
Figure 87. A Typical SPI Network
n
7.6.3.1 Input Signal Description
Serial Data In (SDI)
Data is transferred serially from a slave to a master on this line, most significant bit first. In an SBUS/I2C-bus configuration, the SDI line senses
the value forced on the data line (by SDO or by another peripheral connected to the S-bus/I2C-bus).
7.6.3.2 Output Signal Description
Serial Data Out (SDO)
The SDO pin is configured as an output for the
master device. This is obtained by programming
the corresponding I/O pin as an output alternate
function. Data is transferred serially from a master
to a slave on SDO, most significant bit first. The
master device always allows data to be applied on
the SDO line one half cycle before the clock edge,
in order to latch the data for the slave device. The
SDO pin is forced to high impedance when the SPI
is disabled.
During an S-Bus or I2C-Bus protocol, when arbitration is lost, SDO is set to one (thus not driving
the line, as SDO is configured as an open drain).
Master Serial Clock (SCK)
The master device uses SCK to latch the incoming
data on the SDI line. This pin is forced to a high impedance state when SPI is disabled (SPEN,
SPICR.7 = “0”), in order to avoid clock contention
from different masters in a multi-master system.
The master device generates the SCK clock from
INTCLK. The SCK clock is used to synchronize
data transfer, both in to and out of the device,
through its SDI and SDO pins. The SCK clock
type, and its relationship with data is controlled by
the CPOL (Clock Polarity) and CPHA (Clock
Phase) bits in the Serial Peripheral Control Register (SPICR). This input is provided with a digital filter which eliminates spikes lasting less than one
INTCLK period.
Two bits, SPR1 and SPR0, in the Serial Peripheral
Control Register (SPICR), select the clock rate.
Four frequencies can be selected, two in the high
frequency range (mostly used with the SPI protocol) and two in the medium frequency range
(mostly used with more complex protocols).
143/178
ST92185B - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 88. SPI I/O Pins
n
SCK
SDO
SPI
SDI
DATA BUS
PORT
BIT
SDI
LATCH
PORT
BIT
SCK
LATCH
INT2
PORT
BIT
SDO
LATCH
INT2
7.6.4 Interrupt Structure
The SPI peripheral is associated with external interrupt channel B0 (pin INT2). Multiplexing between the external pin and the SPI internal source
is controlled by the SPEN and BMS bits, as shown
in Table 1 Interrupt Configuration.
The two possible SPI interrupt sources are:
– End of transmission (after each byte).
– S-bus/I2C-bus start or stop condition.
Care should be taken when toggling the SPEN
and/or BMS bits from the “0,0” condition. Before
changing the interrupt source from the external pin
to the internal function, the B0 interrupt channel
should be masked. EIMR.2 (External Interrupt
Mask Register, bit 2, IMBO) and EIPR.2 (External
Interrupt Pending Register bit 2, IMP0) should be
“0” before changing the source. This sequence of
events is to avoid the generating and reading of
spurious interrupts.
A delay instruction lasting at least 4 clock cycles
(e.g. 2 NOPs) should be inserted between the
SPEN toggle instruction and the Interrupt Pending
bit reset instruction.
The INT2 input Function is always mapped together with the SCK input Function, to allow Start/Stop
bit detection when using S-bus/I2C-bus protocols.
A start condition occurs when SDI goes from “1” to
“0” and SCK is “1”. The Stop condition occurs
when SDI goes from “0” to “1” and SCK is “1”. For
both Stop and Start conditions, SPEN = “0” and
BMS = “1”.
Table 27. Interrupt Configuration
144/178
SPEN
BMS
Interrupt Source
0
0
External channel INT2
0
1
S-bus/I2C bus start or stop condition
1
X
End of a byte transmission
ST92185B - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
7.6.5 Working With Other Protocols
The SPI peripheral offers the following facilities for
operation with S-bus/I 2C-bus and IM-bus protocols:
■ Interrupt request on start/stop detection
■ Hardware clock synchronisation
■ Arbitration lost flag with an automatic set of data
line
Note that the I/O bit associated with the SPI should
be returned to a defined state as a normal I/O pin
before changing the SPI protocol.
The following paragraphs provide information on
how to manage these protocols.
7.6.6 I2C-bus Interface
The I 2C-bus is a two-wire bidirectional data-bus,
the two lines being SDA (Serial DAta) and SCL
(Serial CLock). Both are open drain lines, to allow
arbitration. As shown in Figure 5, data is toggled
with clock low. An I²C bus start condition is the
transition on SDI from 1 to 0 with the SCK held
high. In a stop condition, the SCK is also high and
the transition on SDI is from 0 to 1. During both of
these conditions, if SPEN = 0 and BMS = 1 then
an interrupt request is performed.
Each transmission consists of nine clock pulses
(SCL line). The first 8 pulses transmit the byte
(MSB first), the ninth pulse is used by the receiver
to acknowledge.
Figure 89. S-Bus / I2C-bus Peripheral
Compatibility without S-Bus Chip Select
145/178
ST92185B - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 28. Typical I2C-bus Sequences
Phase
Software
INITIALIZE
SPICR.CPOL, CPHA = 0, 0
SPICR.SPEN = 0
SPICR.BMS = 1
SCK pin set as AF output
SDI pin set as input
Set SDO port bit to 1
SCK, SDO in HI-Z
SCL, SDA = 1, 1
Set polarity and phase
SPI disable
START/STOP interrupt
Enable
SDO pin set as output
Open Drain
Set SDO port bit to 0
SDA = 0, SCL = 1
interrupt request
START condition
receiver START detection
TRANSMISSION
SPICR.SPEN = 1
SDO pin as Alternate Function output load data into
SPIDR
SCL = 0
Start transmission
Interrupt request at end of
byte transmission
Managed by interrupt routine load FFh when receiving end of transmission
detection
ACKNOWLEDGE
SPICR.SPEN = 0
Poll SDA line
Set SDA line
SPICR.SPEN = 1
SCK, SDO in HI-Z
SCL, SDA = 1
SPI disable
only if transmitting
only if receiving
only if transmitting
START
Hardware
SCL = 0
SDO pin set as output
Open Drain
SPICR.SPEN = 0
Set SDO port bit to 1
STOP
Notes
SDA = 1
interrupt request
STOP condition
Figure 90. SPI Data and Clock Timing (for I2C protocol)
th
n BYTE
1st BYTE
SDA
AcK
AcK
SCL
1
START
CONDITION
2
8
9
CLOCK PULSE
FOR ACKNOWLEDGEMENT
DRIVEN BY SOFTWARE
1
2
8
9
CLOCK PULSE
FOR ACKNOWLEDGEMENT
DRIVEN BY SW
STOP
CONDITION
VR000188
n
146/178
ST92185B - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
The data on the SDA line is sampled on the low to
high transition of the SCL line.
SPI working with an I2C-bus
To use the SPI with the I 2C-bus protocol, the SCK
line is used as SCL; the SDI and SDO lines, externally wire-ORed, are used as SDA. All output pins
must be configured as open drain (see Figure 4).
Table 2. illustrates the typical I2C-bus sequence,
comprising 5 phases: Initialization, Start, Transmission, Acknowledge and Stop. It should be noted that only the first 8 bits are handled by the SPI
peripheral; the ACKNOWLEDGE bit must be managed by software, by polling or forcing the SCL
and SDO lines via the corresponding I/O port bits.
During the transmission phase, the following I2Cbus features are also supported by hardware.
Clock Synchronization
In a multimaster I2C-bus system, when several
masters generate their own clock, synchronization
is required. The first master which releases the
SCL line stops internal counting, restarting only
when the SCL line goes high (released by all the
other masters). In this manner, devices using dif-
ferent clock sources and different frequencies can
be interfaced.
Arbitration Lost
When several masters are sending data on the
SDA line, the following takes place: if the transmitter sends a “1” and the SDA line is forced low by
another device, the ARB flag (SPICR.5) is set and
the SDO buffer is disabled (ARB is reset and the
SDO buffer is enabled when SPIDR is written to
again). When BMS is set, the peripheral clock is
supplied through the INT2 line by the external
clock line (SCL). Due to potential noise spikes
(which must last longer than one INTCLK period to
be detected), RX or TX may gain a clock pulse.
Referring to Figure 6, if device ST9-1 detects a
noise spike and therefore gains a clock pulse, it
will stop its transmission early and hold the clock
line low, causing device ST9-2 to freeze on the 7th
bit. To exit and recover from this condition, the
BMS bit must be reset; this will cause the SPI logic
to be reset, thus aborting the current transmission.
An End of Transmission interrupt is generated following this reset sequence.
Figure 91. SPI Arbitration
ST9-1
INTERNAL SERIAL
CLOCK
ST9-2
INTERNAL SERIAL
CLOCK
SCK
0
SCK
0
MSPI
MSPI
CONTROL
CONTROL
LOGIC
LOGIC
1
INT 2
INT 2
BHS
ST9-2-SCK
1
BHS
1
2
3
4
5
6
7
5
6
7
8
SPIKE
ST9-1-SCK
1
2
3
4
VR001410
n
n
147/178
ST92185B - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
7.6.7 S-Bus Interface
The S-bus is a three-wire bidirectional data-bus,
possessing functional features similar to the I2Cbus. As opposed to the I2C-bus, the Start/Stop
conditions are determined by encoding the information on 3 wires rather than on 2, as shown in
Figure 8. The additional line is referred as SEN.
Figure 92. Mixed S-bus and I 2C-bus System
SCL
SDA
SEN
1
START
2
3
4
5
6
STOP
VA00440
n
Figure 93. S-bus Configuration
n
148/178
SPI Working with S-bus
The S-bus protocol uses the same pin configuration as the I2C-bus for generating the SCL and
SDA lines. The additional SEN line is managed
through a standard ST9 I/O port line, under software control (see Figure 4).
ST92185B - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
7.6.8 IM-bus Interface
The IM-bus features a bidirectional data line and a
clock line; in addition, it requires an IDENT line to
distinguish an address byte from a data byte (Figure 10). Unlike the I2C-bus protocol, the IM-bus
protocol sends the least significant bit first; this requires a software routine which reverses the bit order before sending, and after receiving, a data
byte. Figure 9 shows the connections between an
IM-bus peripheral and an ST9 SPI. The SDO and
SDI pins are connected to the bidirectional data
pin of the peripheral device. The SDO alternate
function is configured as Open-Drain (external
2.5KΩ pull-up resistors are required).
With this type of configuration, data is sent to the
peripheral by writing the data byte to the SPIDR
register. To receive data from the peripheral, the
user should write FFh to the SPIDR register, in order to generate the shift clock pulses. As the SDO
line is set to the Open-Drain configuration, the incoming data bits that are set to “1” do not affect the
SDO/SDI line status (which defaults to a high level
due to the FFh value in the transmit register), while
incoming bits that are set to “0” pull the input line
low.
In software it is necessary to initialise the ST9 SPI
by setting both CPOL and CPHA to “1”. By using a
general purpose I/O as the IDENT line, and forcing
it to a logical “0” when writing to the SPIDR register, an address is sent (or read). Then, by setting
this bit to “1” and writing to SPIDR, data is sent to
the peripheral. When all the address and data
pairs are sent, it is necessary to drive the IDENT
line low and high to create a short pulse. This will
generate the stop condition.
Figure 94. ST9 and IM-bus Peripheral
VDD
2x
2.5 K
SCK
SDI
SDO
PORTX
CLOCK
DATA
IDENT
IM-BUS
SLAVE
DEVICE
ST9 MCU
IM-BUS
PROTOCOL
VR001427
n
Figure 95. IM bus Timing
IDENT
CLOCK LINE
DATA LINE
LSB
1
2
3
4
5
6
MSB
LSB
1
2
3
4
5
6 MSB
VR000172
149/178
ST92185B - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
7.6.9 Register Description
It is possible to have up to 3 independent SPIs in
the same device (refer to the device block diagram). In this case they are named SPI0 thru
SPI2. If the device has one SPI converter it uses
the register adresses of SPI0. The register map is
the following:
Register
SPIn
Page
SPIDR R253
SPI0
0
SPICR R254
SPI0
0
SPIDR1 R253
SPI1
7
SPICR1 R254
SPI1
7
SPIDR2 R245
SPI2
7
SPICR2 R246
SPI2
7
Note: In the register description on the following
pages, register and page numbers are given using
the example of SPI0.
SPI DATA REGISTER (SPIDR)
R253 - Read/Write
Register Page: 0
Reset Value: undefined
7
D7
0
D6
D5
D4
D3
D2
D1
D0
1: Both alternate functions SCK and SDO are enabled.
Note: furthermore, SPEN (together with the BMS
bit) affects the selection of the source for interrupt
channel B0. Transmission starts when data is written to the SPIDR Register.
Bit 6 = BMS: S-bus/I2C-bus Mode Selector.
0: Perform a re-initialisation of the SPI logic, thus
allowing recovery procedures after a RX/TX failure.
1: Enable S-bus/I2C-bus arbitration, clock synchronization and Start/ Stop detection (SPI used in
an S-bus/I2C-bus protocol).
Note: when the BMS bit is reset, it affects (together with the SPEN bit) the selection of the source
for interrupt channel B0.
Bit 5 = ARB: Arbitration flag bit.
This bit is set by hardware and can be reset by
software.
0: S-bus/I2C-bus stop condition is detected.
1: Arbitration lost by the SPI in S-bus/I2C-bus
mode.
Note: when ARB is set automatically, the SDO pin
is set to a high value until a write instruction on
SPIDR is performed.
Bit 7:0 = D[0:7]: SPI Data.
This register contains the data transmitted and received by the SPI. Data is transmitted bit 7 first,
and incoming data is received into bit 0. Transmission is started by writing to this register.
Bit 4 = BUSY: SPI Busy Flag.
This bit is set by hardware. It allows the user to
monitor the SPI status by polling its value.
0: No transmission in progress.
1: Transmission in progress.
Note: SPIDR state remains undefined until the
end of transmission of the first byte.
Bit 3 = CPOL: Transmission Clock Polarity.
CPOL controls the normal or steady state value of
the clock when data is not being transferred.
Please refer to the following table and to Figure 11
to see this bit action (together with the CPHA bit).
Note: As the SCK line is held in a high impedance
state when the SPI is disabled (SPEN = “0”), the
SCK pin must be connected to VSS or to V CC
through a resistor, depending on the CPOL state.
Polarity should be set during the initialisation routine, in accordance with the setting of all peripherals, and should not be changed during program
execution.
SPI CONTROL REGISTER (SPICR)
R254 - Read/Write
Register Page: 0
Reset Value: 0000 0000 (00h)
7
SPEN
0
BMS
ARB
BUSY
CPOL
CPHA
SPR1
Bit 7 = SPEN: Serial Peripheral Enable.
0: SCK and SDO are kept tristate.
150/178
SPR0
ST92185B - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
Bit 2 = CPHA: Transmission Clock Phase.
CPHA controls the relationship between the data
on the SDI and SDO pins, and the clock signal on
the SCK pin. The CPHA bit selects the clock edge
used to capture data. It has its greatest impact on
the first bit transmitted (MSB), because it does (or
does not) allow a clock transition before the first
data capture edge. Figure 11 shows the relationship between CPHA, CPOL and SCK, and indicates active clock edges and strobe times.
CPOL
CPHA
SCK
(in Figure 11)
0
0
1
1
0
1
0
1
(a)
(b)
(c)
(d)
Bit 1:0 = SPR[1:0]: SPI Rate.
These two bits select one (of four) baud rates, to
be used as SCK.
SPR1 SPR0
0
0
1
1
0
1
0
1
Clock
Divider
8
16
128
256
SCK Frequency
(@ INTCLK = 24MHz)
3000kHz
1500kHz
187.5kHz
93.75kHz
(T =
(T =
(T =
(T =
0.33µs)
0.67µs)
5.33µs)
10.66µs)
Figure 96. SPI Data and Clock Timing
151/178
ST92185B - A/D CONVERTER (A/D)
7.7 A/D CONVERTER (A/D)
7.7.1 Introduction
The 8 bit Analog to Digital Converter uses a fully
differential analog configuration for the best noise
immunity and precision performance. The analog
voltage references of the converter are connected
to the internal AVDD & AVSS analog supply pins of
the chip if they are available, otherwise to the ordinary VDD and V SS supply pins of the chip. The
guaranteed accuracy depends on the device (see
Electrical Characteristics). A fast Sample/Hold allows quick signal sampling for minimum warping
effect and conversion error.
7.7.2 Main Features
■ 8-bit resolution A/D Converter
■ Single Conversion Time (including Sampling
Time):
– 138 internal system clock periods in slow
mode (~5.6 µs @25Mhz internal system
clock);
– 78 INTCLK periods in fast mode (~6.5 µs @
12MHZ internal system clock)
■ Sample/Hold: Tsample=
– 84 INTCLK periods in slow mode (~3.4 µs
@25Mhz internal system clock)
– 48 INTCLK periods in fast mode (~4 µs
@12Mhz internal system clock)
■ Up to 4 Analog Inputs (the number of inputs is
device dependent, see device pinout)
■
■
■
■
■
Single/Continuous Conversion Mode
External/Internal source Trigger (Alternate
synchronization)
Power Down mode (Zero Power Consumption)
1 Control Logic Register
1 Data Register
7.7.3 General Description
Depending on the device, up to 8 analog inputs
can be selected by software.
Different conversion modes are provided: single,
continuous, or triggered. The continuous mode
performs a continuous conversion flow of the selected channel, while in the single mode the selected channel is converted once and then the logic waits for a new hardware or software restart.
A data register (ADDTR) is available, mapped in
page 62, allowing data storage (in single or continuous mode).
The start conversion event can be managed by
software, writing the START/STOP bit of the Control Logic Register or by hardware using either:
– An external signal on the EXTRG triggered input
(negative edge sensitive) connected as an Alternate Function to an I/O port bit
– An On Chip Event generated by another peripheral, such as the MFT (Multifunction Timer).
Figure 97. A/D Converter Block Diagram
n
SUCCESSIVE
APPROXIMATION
REGISTER
ST9 BUS
Ain0
S/H
DATA
REGISTER
ANALOG
MUX
Ainx
EXTRG
CONTROL LOGIC
INTRG
(On Chip Event)
152/178
Ain1
ST92185B - A/D CONVERTER (A/D)
A/D CONVERTER (Cont’d)
The conversion technique used is successive approximation, with AC coupled analog fully differential comparators blocks plus a Sample and Hold
logic and a reference generator.
The internal reference (DAC) is based on the use
of a binary-ratioed capacitor array. This technique
allows the specified monotonicity (using the same
ratioed capacitors as sampling capacitor). A Power Down programmable bit sets the A/D converter
analog section to a zero consumption idle status.
7.7.3.1 Operating Modes
The two main operating modes, single and continuous, can be selected by writing 0 (reset value) or
1 into the CONT bit of the Control Logic Register.
Single Mode
In single mode (CONT=0 in ADCLR) the STR bit is
forced to '0' after the end of channel i-th conversion; then the A/D waits for a new start event. This
mode is useful when a set of signals must be sampled at a fixed frequency imposed by a Timer unit
or an external generator (through the alternate
synchronization feature). A simple software routine monitoring the STR bit can be used to save
the current value before a new conversion ends
(so to create a signal samples table within the internal memory or the Register File). Furthermore,
if the R242.0 bit (register AD-INT, bit 0) is set, at
the end of conversion a negative edge on the connected external interrupt channel (see Interrupts
Chapter) is generated to allow the reading of the
converted data by means of an interrupt routine.
Continuous Mode
In continuous mode (CONT=1 in ADCLR) a continuous conversion flow is entered by a start event
on the selected channel until the STR bit is reset
by software.
At the end of each conversion, the Data Register
(ADCDR) content is updated with the last conversion result, while the former value is lost. When the
conversion flow is stopped, an interrupt request is
generated with the same modality previously described.
7.7.3.2 Alternate Synchronization
This feature is available in both single/continuous
modes. The negative edge of external EXTRG signal or the occurrence of an on-chip event generated by another peripheral can be used to synchronize the conversion start with a trigger pulse.
These events can be enabled or masked by programming the TRG bit in the ADCLR Register.
The effect of alternate synchronization is to set the
STR bit, which is cleared by hardware at the end of
each conversion in single mode. In continuous
mode any trigger pulse following the first one will
be ignored. The synchronization source must provide a pulse (1.5 internal system clock, 125ns @
12 MHz internal clock) of minimum width, and a
period greater (in single mode) than the conversion time (~6.5us @ 12 MHz internal clock). If a
trigger occurs when the STR bit is still '1' (conversions still in progress), it is ignored (see Electrical
Characteristics).
WARNING: If the EXTRG or INTRG signals are already active when TRG bit is set, the conversion
starts immediately.
7.7.3.3 Power-Up Operations
Before enabling any A/D operation mode, set the
POW bit of the ADCLR Register at least 60 µs before the first conversion starts to enable the biasing circuits inside the analog section of the converter. Clearing the POW bit is useful when the
A/D is not used so reducing the total chip power
consumption. This state is also the reset configuration and it is forced by hardware when the core is
in HALT state (after a HALT instruction execution).
7.7.3.4 Register Mapping
It is possible to have two independent A/D converters in the same device. In this case they are
named A/D 0 and A/D 1. If the device has one A/D
converter it uses the register addresses of A/D 0.
The register map is the following:
Register Address
ADn
Page 62 (3Eh)
F0h
A/D 0
ADDTR0
F1h
A/D 0
ADCLR0
F2h
A/D 0
ADINT0
F3-F7h
A/D 0
Reserved
F8h
A/D 1
ADDTR1
ADCLR1
F9h
A/D 1
FAh
A/D 1
ADINT1
FB-FFh
A/D 1
Reserved
If two A/D converters are present, the registers are
renamed, adding the suffix 0 to the A/D 0 registers
and 1 to the A/D 1 registers.
153/178
ST92185B - A/D CONVERTER (A/D)
A/D CONVERTER (Cont’d)
7.7.4 Register Description
A/D CONTROL LOGIC REGISTER (ADCLR)
R241 - Read/Write
Register Page: 62
Reset value: 0000 0000 (00h)
7
C2
0
C1
C0
FS
TRG POW CONT STR
This 8-bit register manages the A/D logic operations. Any write operation to it will cause the current conversion to be aborted and the logic to be
re-initialized to the starting configuration.
Bit 7:5 = C[2:0]: Channel Address.
These bits are set and cleared by software. They
select channel i conversion as follows:
C2
0
0
0
0
1
C1
0
0
1
1
0
C0
0
1
0
1
0
Channel Enabled
Channel 0
Channel 1
Channel 2
Channel 4
Channel 3
Bit 4 = FS: Fast/Slow.
This bit is set and cleared by software.
0: Fast mode. Single conversion time: 78 x
INTCLK (5.75µs at INTCLK = 12 MHz)
1: Slow mode. Single conversion time: 138 x
INTCLK (11.5µs at INTCLK = 12 MHz)
Note: Fast conversion mode is only allowed for internal speeds which do not exceed 12 MHz.
Bit 3 = TRG: External/Internal Trigger Enable.
This bit is set and cleared by software.
154/178
0: External/Internal Trigger disabled.
1: Either a negative (falling) edge on the EXTRG
pin or an On Chip Event writes a “1” into the
STR bit, enabling start of conversion.
Note: Triggering by on chip event is available on
devices with the multifunction timer (MFT) peripheral.
Bit 2 = POW: Power Enable.
This bit is set and cleared by software.
0: Disables all power consuming logic.
1: Enables the A/D logic and analog circuitry.
Bit 1 = CONT: Continuous/Single Mode Select.
This bit it set and cleared by software.
0: Single mode: after the current conversion ends,
the STR bit is reset by hardware and the converter logic is put in a wait status. To start another conversion, the STR bit has to be set by software or hardware.
1: Select Continuous Mode, a continuous flow of
A/D conversions on the selected channel, starting when the STR bit is set.
Bit 0 = STR: Start/Stop.
This bit is set and cleared by software. It is also set
by hardware when the A/D is synchronized with an
external/internal trigger.
0: Stop conversion on channel i. An interrupt is
generated if the STR was previously set and the
AD-INT bit is set.
1: Start conversion on channel i
WARNING: When accessing this register, it is recommended to keep the related A/D interrupt channel masked or disabled to avoid spurious interrupt
requests.
ST92185B - A/D CONVERTER (A/D)
A/D CONVERTER (Cont’d)
A/D CHANNEL i DATA REGISTER (ADDTR)
R240 - Read/Write
Register Page: 62
Reset value: undefined
7
R.7
R.6
R.5
R.4
R.3
R.2
R.1
A/D INTERRUPT REGISTER (ADINT)
Register Page: 62
R242 - Read/write
Reset value: 0000 0001 (01h)
0
7
R.0
0
The result of the conversion of the selected channel is stored in the 8-bit ADDTR, which is reloaded
with a new value every time a conversion ends.
Bit 7:0 = R[7:0]: Channel i conversion result.
0
0
0
0
0
0
0
AD-INT
Bit 7:1 = Reserved.
Bit 0 = AD-INT: AD Converter Interrupt Enable.
This bit is set and cleared by software. It allows the
interrupt source to be switched between the A/D
Converter and an external interrupt pin (See Interrupts chapter).
0: A/D Interrupt disabled. External pin selected as
interrupt source.
1: A/D Interrupt enabled
155/178
ST92185B - VOLTAGE SYNTHESIS TUNING CONVERTER (VS)
7.8 VOLTAGE SYNTHESIS TUNING CONVERTER (VS)
7.8.1 Description
The on-chip Voltage Synthesis (VS) converter allows the generation of a tuning reference voltage
in a TV set application. The peripheral is composed of a 14-bit counter that allows the conversion of the digital content in a tuning voltage, available at the VS output pin, by using PWM (Pulse
Width Modulation) and BRM (Bit Rate Modulation)
techniques. The 14-bit counter gives 16384 steps
which allow a resolution of approximately 2 mV
over a tuning voltage of 32 V. This corresponds to
a tuning resolution of about 40 KHz per step in
UHF band (the actual value will depend on the
characteristics of the tuner).
The tuning word consists of a 14-bit word contained in the registers VSDR1 (R254) and VSDR2
(R255) both located in page 59.
Coarse tuning (PWM) is performed using the seven most significant bits. Fine tuning (BRM) is performed using the the seven least significant bits.
With all “0”s loaded, the output is 0. As the tuning
voltage increases from all “0”s, the number of pulses in one period increases to 128 with all pulses
being the same width. For values larger than 128,
the PWM takes over and the number of pulses in
one period remains constant at 128, but the width
changes. At the other end of the scale, when almost all “1”s are loaded, the pulses will start to link
together and the number of pulses will decrease.
When all “1”s are loaded, the output will be almost
100% high but will have a low pulse (1/16384 of
the high pulse).
156/178
7.8.2 Output Waveforms
Included inside the VS are the register latches, a
reference counter, PWM and BRM control circuitry. The clock for the 14-bit reference counter is derived from the main system clock (referred to as
INTCLK) after a division by 4. For example, using
an internal 12 MHz on-chip clock (see Timing &
Clock Controller chapter) leads to a 3 MHz input
for the VS counter.
From the point of view of the circuit, the seven
most significant bits control the coarse tuning,
while the seven least significant bits control the
fine tuning. From the application and software
point of view, the 14 bits can be considered as one
binary number.
As already mentioned the coarse tuning consists
of a PWM signal with 128 steps: we can consider
the fine tuning to cover 128 coarse tuning cycles.
The VS Tuning Converter is implemented with 2
separate outputs (VSO1 and VSO2) that can drive
2 separate Alternate Function outputs of 2 standard I/O port bits. A control bit allows you to choose
which output is activated (only one output can be
activated at a time).
When a VS output is not selected because the VS
is disabled or because the second output is selected, it stays at a logical “one” level, allowing you to
use the corresponding I/O port bit either as a normal I/O port bit or for a possible second Alternate
Function output.
A second control bit allows the VS function to be
started (or stopped) by software.
ST92185B - VOLTAGE SYNTHESIS TUNING CONVERTER (VS)
VOLTAGE SYNTHESIS (Cont’d)
PWM Generation
The counter increments continuously, clocked at
INTCLK divided by 4. Whenever the 7 least significant bits of the counter overflow, the VS output is
set.
The state of the PWM counter is continuously
compared to the value programmed in the 7 most
significant bits of the tuning word. When a match
occurs, the output is reset thus generating the
PWM output signal on the VS pin.
This Pulse Width modulated signal must be filtered, using an external RC network placed as
close as possible to the associated pin. This provides an analog voltage proportional to the average charge passed to the external capacitor. Thus
for a higher mark/space ratio (High time much
greater than Low time) the average output voltage
is higher. The external components of the RC network should be selected for the filtering level required for control of the system variable.
Figure 98. Typical PWM Output Filter
1K
PWM OUT
R ext
OUTPUT
VOLTAGE
Cext
Figure 99. PWM Generation
COUNTER
127
OVERFLOW
OVERFLOW
OVERFLOW
7-BIT PWM
VALUE
000
t
PWM OUTPUT
t
INTCLK/4 x 128
157/178
ST92185B - VOLTAGE SYNTHESIS TUNING CONVERTER (VS)
VOLTAGE SYNTHESIS (Cont’d)
Figure 100. PWM Simplified Voltage Output After Filtering (2 examples)
V DD
PWMOUT
0V
Vripple (mV)
V DD
OUTPUT
VOLTAGE
V OUTAVG
0V
"CHARGE"
V
"DISCHARGE"
"CHARGE"
"DISCHARGE"
DD
PWMOUT
0V
V DD
V ripple (mV)
OUTPUT
VOLTAGE
0V
V OUTAVG
"CHARGE"
"DISCHARGE"
"CHARGE"
"DISCHARGE"
VR01956
158/178
ST92185B - VOLTAGE SYNTHESIS TUNING CONVERTER (VS)
VOLTAGE SYNTHESIS (Cont’d)
BRM Generation
The BRM bits allow the addition of a pulse to widen a standard PWM pulse for specific PWM cycles. This has the effect of “fine-tuning” the PWM
Duty cycle (without modifying the base duty cycle),
thus, with the external filtering, providing additional
fine voltage steps.
The incremental pulses (with duration of TINTCLK/
4) are added to the beginning of the original PWM
pulse and thus cause the PWM high time to be extended by this time with a corresponding reduction
in the low time. The PWM intervals which are added to are specified in the lower 7 bits of the tuning
word and are encoded as shown in the following
table.
Table 29. 7-Bit BRM Pulse Addition Positions
Fine Tuning
No. of Pulses added at the
following Cycles
0000001
64
0000010
32, 96
0000100
16, 48, 80, 112
0001000
8, 24,... 104, 120
0010000
4, 12,... 116, 124
0100000
2, 6,... 122, 126
1000000
1, 3,... 125, 127
The BRM values shown may be combined together to provide a summation of the incremental pulse
intervals specified.
The pulse increment corresponds to the PWM resolution.
Figure 101. Simplified Filtered Voltage Output Schematic with BRM added
=
=
=
VDD
PWMOUT
0V
VDD
BRM = 1
OUTPUT
BRM = 0
VOLTAGE
0V
TINTCLK/4
BRM
EXTENDED PULSE
159/178
ST92185B - VOLTAGE SYNTHESIS TUNING CONVERTER (VS)
VOLTAGE SYNTHESIS (Cont’d)
7.8.3 Register Description
VS DATA AND CONTROL REGISTER
(VSDR1)
R254 - Read/Write
Register Page: 59
Reset Value: 0000 0000 (00h)
7
VSE
6
5
VSWP VD13
1
4
3
2
1
0
7
VD12
VD11
VD10
VD9
VD8
VD7
Bit 7 = VSE: VS enable bit.
0: VS Tuning Converter disabled (i.e. the clock is
not forwarded to the VS counter and the 2 outputs are set to 1 (idle state)
1: VS Tuning Converter enabled.
Bit 6 = VSWP: VS Output Select
This bit controls which VS output is enabled to output the VS signal.
0: VSO1 output selected
1: VSO2 output selected
Bit 5:0 = VD[13:8] Tuning word bits.
These bits are the 6 most significant bits of the
Tuning word forming the PWM selection. The
VD13 bit is the MSB.
160/178
VS DATA AND CONTROL
(VSDR2)
R255 - Read/Write
Register Page: 59
Reset Value: 0000 0000 (00h)
REGISTER
2
0
VD6
VD5
VD4
VD3
VD2
VD1
VD0
Bit 7:0 = VD[7:0] Tuning word bits.
These bits are the 8 least significant data bits of
the VS Tuning word. All bits are accessible. Bits
VD6 - VD0 form the BRM pulse selection. VD7 is
the LSB of the 7 bits forming the PWM selection.
ST92185B - PWM GENERATOR
7.9 PWM GENERATOR
7.9.1 Introduction
The PWM (Pulse Width Modulated) signal generator allows the digital generation of up to 8 analog
outputs when used with an external filtering network.
The unit is based around an 8-bit counter which is
driven by a programmable 4-bit prescaler, with an
input clock signal equal to the internal clock
INTCLK divided by 2. For example, with a 12 MHz
Internal clock, using the full 8-bit resolution, a fre-
quency range from 1465 Hz up to 23437 Hz can
be achieved.
Higher frequencies, with lower resolution, can be
achieved by using the autoclear register. As an example, with a 12 MHz Internal clock, a maximum
PWM repetition rate of 93750 Hz can be reached
with 6-bit resolution.
Note: The number of output pins is device dependant. Refer to the device pinout description.
Figure 102. PWM Block Diagram.
Control Logic
Autoclear
8 Bit Counter
INTCLK/2
4 Bit Presc.
Compare 7
PWM7
Compare 5
Compare 4
Compare 3
Compare 2
OUTPUT LOGIC
ST9 Register Bus
Compare 6
Compare 1
Compare 0
PWM0
VR01765
161/178
ST92185B - PWM GENERATOR
PWM GENERATOR (Cont’d)
Up to 8 PWM outputs can be selected as Alternate
Functions of an I/O port. Each output bit is independently controlled by a separate Compare Register. When the value programmed into the Compare Register and the counter value are equal, the
corresponding output bit is set. The output bit is reset by a counter clear (by overflow or autoclear),
generating the variable PWM signal.
Each output bit can also be complemented or disabled under software control.
7.9.2 Register Mapping
The ST9 can have one or two PWM Generators.
Each has 13 registers mapped in page 59 (PWM0)
or page 58 (PWM1). In the register description on
the following pages, the register page refers to
PWM0 only.
Register
Address
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253- R255
Register
CM0
CM1
CM2
CM3
CM4
CM5
CM6
CM7
ACR
CRR
PCTLR
OCPLR
OER
—
Function
Ch. 0 Compare Register
Ch. 1 Compare Register
Ch. 2 Compare Register
Ch. 3 Compare Register
Ch. 4 Compare Register
Ch. 5 Compare Register
Ch. 6 Compare Register
Ch. 7 Compare Register
Autoclear Register
Counter Read Register
Prescaler/ Reload Reg.
Output Complement Reg.
Output Enable Register
Reserved
Figure 103. PWM Action When Compare Register = 0 (no complement)
PWM
CLOCK
Counter=Autoclear value
Counter=0
Counter=1
PWM
OUTPUT
VR0A1814
Figure 104. PWM Action When Compare Register = 3 (no complement)
PWM
CLOCK
Counter=Autoclear value
Counter=0
Counter=3
PWM
OUTPUT
VR001814
162/178
ST92185B - PWM GENERATOR
PWM GENERATOR (Cont’d)
7.9.2.1 Register Description
COMPARE REGISTER 0 (CM0)
R240 - Read/Write
Register Page: 59
Reset Value: 0000 0000 (00h)
7
COMPARE REGISTER 4 (CM4)
R244 - Read/Write
Register Page: 59
Reset Value: 0000 0000 (00h)
7
0
0
CM4.7 CM4.6 CM4.5 CM4.4 CM4.3 CM4.2 CM4.1 CM4.0
CM0.7 CM0.6 CM0.5 CM0.4 CM0.3 CM0.2 CM0.1 CM0.0
This is the compare register controlling PWM output 0. When the programmed content is equal to
the counter content, a SET operation is performed
on PWM output 0 (if the output has not been complemented or disabled).
Bit 7:0 = CM0.[7:0]: PWM Compare value Channel 0.
7
0
This is the compare register controlling PWM output 5.
0
CM1.7 CM1.6 CM1.5 CM1.4 CM1.3 CM1.2 CM1.1 CM1.0
This is the compare register controlling PWM output 1.
COMPARE REGISTER 6 (CM6)
R246 - Read/Write
Register Page: 59
Reset Value: 0000 0000 (00h)
7
0
CM6.7 CM6.6 CM6.5 CM6.4 CM6.3 CM6.2 CM6.1 CM6.0
COMPARE REGISTER 2 (CM2)
R242 - Read/Write
Register Page: 59
Reset Value: 0000 0000 (00h)
7
COMPARE REGISTER 5 (CM5)
R245 - Read/Write
Register Page: 59
Reset Value: 0000 0000 (00h)
CM5.7 CM5.6 CM5.5 CM5.4 CM5.3 CM5.2 CM5.1 CM5.0
COMPARE REGISTER 1 (CM1)
R241 - Read/Write
Register Page: 59
Reset Value: 0000 0000 (00h)
7
This is the compare register controlling PWM output 4.
This is the compare register controlling PWM output 6.
0
CM2.7 CM2.6 CM2.5 CM2.4 CM2.3 CM2.2 CM2.1 CM2.0
This is the compare register controlling PWM output 2.
7
COMPARE REGISTER 3 (CM3)
R243 - Read/Write
Register Page: 59
Reset Value: 0000 0000 (00h)
7
COMPARE REGISTER 7 (CM7)
R247 - Read/Write
Register Page: 59
Reset Value: 0000 0000 (00h)
0
CM7.7 CM7.6 CM7.5 CM7.4 CM7.3 CM7.2 CM7.1 CM7.0
0
This is the compare register controlling PWM output 7.
CM3.7 CM3.6 CM3.5 CM3.4 CM3.3 CM3.2 CM3.1 CM3.0
This is the compare register controlling PWM output 3.
163/178
ST92185B - PWM GENERATOR
PWM GENERATOR (Cont’d)
AUTOCLEAR REGISTER (ACR)
R248 - Read/Write
Register Page: 59
Reset Value: 1111 1111 (FFh)
7
AC7
0
AC6
AC5
AC4
AC3
AC2
AC1
AC0
PRESCALER AND CONTROL
(PCTL)
R250 - Read/Write
Register Page: 59
Reset Value: 0000 1100 (0Ch)
7
0
PR3
This register behaves exactly as a 9th compare
Register, but its effect is to clear the CRR counter
register, so causing the desired PWM repetition
rate.
The reset condition generates the free running
mode. So, FFh means count by 256.
Bit 7:0 = AC[7:0]: Autoclear Count Value.
When 00 is written to the Compare Register, if the
ACR register = FFh, the PWM output bit is always
set except for the last clock count (255 set and 1
reset; the converse when the output is complemented). If the ACR content is less than FFh, the
PWM output bit is set for a number of clock counts
equal to that content (see Figure 2).
Writing the Compare register constant equal to the
ACR register value causes the output bit to be always reset (or set if complemented).
Example: If 03h is written to the Compare Register, the output bit is reset when the CRR counter
reaches the ACR register value and set when it
reaches the Compare register value (after 4 clock
counts, see Figure 3). The action will be reversed
if the output is complemented. The PWM mark/
space ratio will remain constant until changed by
software writing a new value in the ACR register.
COUNTER REGISTER (CRR)
R249 - Read Only
Register Page: 59
Reset Value: 0000 0000 (00h)
7
CR7
0
CR6
CR5
CR4
CR3
CR2
CR1
CR0
This read-only register returns the current counter
value when read.
The 8 bit Counter is initialized to 00h at reset, and
is a free running UP counter.
Bit 7:0 = CR[7:0]: Current Counter Value.
164/178
REGISTER
PR2
PR1
PR0
1
1
CLR
CE
Bit 7:4 = PR[3:0] PWM Prescaler value.
These bits hold the Prescaler preset value. This is
reloaded into the 4-bit prescaler whenever the
prescaler (DOWN Counter) reaches the value 0,
so determining the 8-bit Counter count frequency.
The value 0 corresponds to the maximum counter
frequency which is INTCLK/2. The value Fh corresponds to the maximum frequency divided by 16
(INTCLK/32).
The reset condition initializes the Prescaler to the
Maximum Counter frequency.
PR[3:0]
Divider Factor
Frequency
0
1
INTCLK/2 (Max.)
1
2
INTCLK/4
2
3
INTCLK/6
..
..
..
Fh
16
INTCLK/32 (Min.)
Bit 3:2 = Reserved. Forced by hardware to “1”
Bit 1 = CLR: Counter Clear.
This bit when set, allows both to clear the counter,
and to reload the prescaler. The effect is also to
clear the PWM output. It returns “0” if read.
Bit 0 = CE: Counter Enable.
This bit enables the counter and the prescaler
when set to “1”. It stops both when reset without
affecting their current value, allowing the count to
be suspended and then restarted by software “on
fly”.
ST92185B - PWM GENERATOR
PWM GENERATOR (Cont’d)
OUTPUT COMPLEMENT REGISTER (OCPL)
R251- Read/Write
Register Page 59
Reset Value: 0000 0000 (00h)
7
0
OCPL.7 OCPL.6OCPL.5 OCPL.4OCPL.3 OCPL.2 OCPL.1OCPL.0
This register allows the PWM output level to be
complemented on an individual bit basis.
In default mode (reset configuration), each comparison true between a Compare register and the
counter has the effect of setting the corresponding
output.
At counter clear (either by autoclear comparison
true, software clear or overflow when in free running mode), all the outputs are cleared.
By setting each individual bit (OCPL.x) in this register, the logic value of the corresponding output
will be inverted (i.e. reset on comparison true and
set on counter clear).
Example: When set to “1”, the OCPL.1 bit complements the PWM output 1.
Bit 7 = OCPL.7: Complement PWM Output 7.
Bit 6 = OCPL.6: Complement PWM Output 6.
Bit 5 = OCPL.5: Complement PWM Output 5.
Bit 4 = OCPL.4: Complement PWM Output 4.
Bit 3 = OCPL.3: Complement PWM Output 3.
Bit 2 = OCPL.2: Complement PWM Output 2.
Bit 1 = OCPL.1: Complement PWM Output 1.
Bit 0 = OCPL.0: Complement PWM Output 0.
OUTPUT ENABLE REGISTER (OER)
R252 - Read/Write
Register Page: 59
Reset Value: 0000 0000 (00h)
7
0
OE.7 OE.6 OE.5 OE.4 OE.3 OE.2 OE.1 OE.0
These bits are set and cleared by software.
0: Force the corresponding PWM output to logic
level 1. This allows the port pins to be used for
normal I/O functions or other alternate functions
(if available).
1: Enable the corresponding PWM output.
Example: Writing 03h into the OE Register will enable only PWM outputs 0 and 1, while outputs 2, 3,
4, 5, 6 and 7 will be forced to logic level “1”.
Bit 7 = OE.7: Output Enable PWM Output 7.
Bit 6 = OE.6: Output Enable PWM Output 6.
Bit 5 = OE.5: Output Enable PWM Output 5.
Bit 4 = OE.4: Output Enable PWM Output 4.
Bit 3 = OE.3: Output Enable PWM Output 3.
Bit 2 = OE.2: Output Enable PWM Output 2.
Bit 1 = OE.1: Output Enable PWM Output 1.
Bit 0 = OE.0: Output Enable PWM Output 0.
165/178
ST92185B - ELECTRICAL CHARACTERISTICS
8 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDD
Supply Voltage
VSSA
Analog Ground
VDDA
Analog Supply Voltage
VI
Input Voltage
Value
Unit
VSS - 0.3 to VSS + 6.5
VSS - 0.3 to VSS + 0.3
V
VDD -0.3 to VDD +0.3
VSS - 0.3 to VDD +0.3
V
V
V
VSS - 0.3 to VDD +0.3
VSSA - 0.3 to VDDA +0.3
VAI
Analog Input Voltage (A/D Converter)
VO
Output Voltage
VSS - 0.3 to VDD + 0.3
V
TSTG
Storage Temperature
- 55 to + 150
°C
Pin Injected Current
- 5 to + 5
mA
- 50 to +5 0
mA
IINJ
V
Maximum Accumulated Pin
Injected Current In Device
Note: Stress above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
Min.
Max.
0
70
°C
TA
Operating Temperature
VDD
Supply Voltage
4.5
5.5
V
VDDA
Analog Supply Voltage (PLL)
4.5
5.5
V
fOSCE
External Oscillator Frequency
3.3
8.7
MHz
fOSCI
Internal Clock Frequency (INTCLK)
24
MHz
166/178
ST92185B - ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
(VDD= 5V +/-10%; TA= 0 to 70°C; unless otherwise specified)
Symbol
Parameter
Test Conditions
VIHCK
Clock In high level
External clock
VILCK
Clock in low level
External clock
VIH
Input high level
TTL
VIL
Input low level
TTL
VIH
Input high level
CMOS
VIL
Input low level
CMOS
VIHRS
Reset in high level
VILRS
Reset in low level
VHYRS
Reset in hysteresis
VIHY
P2.(1:0) input hysteresis
VIHVH
HSYNC/VSYNC input high level
VILVH
HSYNC/VSYNC input low level
VHYHV
HSYNC/VSYNC input hysteresis
VOH
Output high level
VOL
Output low level
Value
Min.
Max.
0.7 VDD
V
0.3 VDD
2.0
V
V
0.8
0.8 VDD
V
V
0.2 VDD
0.7 VDD
V
V
0.3 VDD
0.3
V
V
0.9
V
0.7 VDD
V
0.3 VDD
Push-pull Ild=-0.8mA
Unit
V
0.5
V
VDD-0.8
V
Push-pull ld=+1.6mA
0.4
V
bidir. state
IWPU
Weak pull-up current
VOL= 3V
50
VOL= 7V
µA
350
ILKIO
I/O pin input leakage current
0<VIN<VDD
-10
+10
µA
ILKRS
Reset pin input
0<VIN<VDD
-10
+10
µA
ILKAD
A/D pin input leakage current
alternate funct. op. drain
-10
+10
µA
ILKOS
OSCIN pin input leakage current
0<VIN<VDD
-10
+10
µA
167/178
ST92185B - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
PIN CAPACITANCE
(VDD= 5V +/-10%; TA= 0 to 70°C; unless otherwise specified))
Symbol
CIO
Parameter
Value
Conditions
min
Pin Capacitance Digital Input/Output
max
10
Unit
pF
CURRENT CONSUMPTION
(VDD= 5V +/-10%; TA= 0 to 70°C; unless otherwise specified)
Symbol
Parameter
Value
Conditions
min
typ.
max
Unit
IDD1
Run Mode Current
notes 1,2; all On
70
100
mA
IDDA1
Run Mode Analog Current
(pin VDDA)
Timing Controller On
35
50
mA
IDD2
HALT Mode Current
notes 1,4
10
100
µA
IDDA2
HALT Mode Analog Current
(pin VDDA)
notes 1,4
40
100
µA
Notes:
1. Port 0 is configured in push-pull output mode (output is high). Ports 2, 3, 4 and 5 are configured in bi-directional weak pull-up mode resistor.
The external CLOCK pin (OSCIN) is driven by a square wave external clock at 8 MHz. The internal clock prescaler is in divide-by-1 mode.
2. The CPU is fed by a 24 MHz frequency issued by the Main Clock Controller. VSYNC is tied to VSS, HSYNC is driven by a 15625Hz clock.
All peripherals working including Display.
3. The CPU is fed by a 24 MHz frequency issued by the Main Clock Controller. VSYNC is tied to VSS, HSYNC is driven by a 15625Hz clock.
The TDSRAM interface and the Slicers are working; the Display controller is not working.
4. VSYNC and HSYNC tied to VSS. External CLOCK pin (OSCIN) is hold low. All peripherals are disabled.
EXTERNAL INTERRUPT TIMING TABLE (rising or falling edge mode)
(VDD= 5V +/-10%; TA= 0 to 70°C; unless otherwise specified))
Symbol
Parameter
Conditions
INTCLK=24 MHz.
Value
min
Unit
max
TwLR
low level pulse width
TpC+12
95
ns
TwHR
high level pulse width
TpC+12
95
ns
TpC is the INTCLK clock period.
168/178
ST92185B - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS (Cont’d)
SPI TIMING TABLE
(VDD= 5V +/-10%; TA= 0 to 70°C; Cload= 50pF)
Symbol
Parameter
Condition
Value
min
max
tbd
Unit
TsDI
Input Data Set-up Time
ThDI
Input Data Hold Time
TdOV
SCK to Output Data Valid
ThDO
Output Data Hold Time
tbd
ns
TwSKL
SCK Low Pulse Width
tbd
ns
TwSKH
SCK High Pulse Width
tbd
ns
(1)
OSCIN/2 as internal Clock
1INTCLK
ns
+100ns
ns
tbd
ns
(1) TpC is the OSCIN clock period; TpMC is the “Main Clock Frequency” period.
SKEW CORRECTOR TIMING TABLE
(VDD= 5V +/-10%, TA= 0 to 70°C, unless otherwise specified)
Symbol
Tjskw
Parameter
Jitter on RGB output
Conditions
36 MHz Skew corrector clock frequency
max
Value
Unit
5*
ns
(*) The OSD jitter is measured from leading edge to leading edge of a single character row on consecutive TV lines. The value is an envelope
of 100 fields
169/178
ST92185B - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS (Cont’d)
OSD DAC CHARACTERISTICS (ROM DEVICES ONLY)
(VDD= 5V +/-10%, TA= 0 to 70°C, unless otherwise specified).
Symbol
Parameter
Conditions
Output impedance: FB,R,G,B
Output voltage: FB,R,G,B
Value
min
typical
max
300
500
700
Unit
Ohm
Cload= 20pF
RL = 100K
code= 111
1.000
1.250
V
code= 011
0.450
0.500
V
code= 000
0.025
0.080
V
FB= 1
2.4
2.7
3.4
V
FB= 0
0
0.025
0.080
V
+/-5
%
Global voltage accuracy
OSD DAC CHARACTERISTICS (EPROM AND OTP DEVICES ONLY)
(VDD= 5V +/-10%, TA= 0 to 70°C, unless otherwise specified).
Symbol
Parameter
Conditions
Unit
min
typical
max
300
500
700
Ohm
code= 111
1.100
1.400
V
code= 011
0.600
0.800
V
code= 000
0.200
0.350
V
0.400
V
+/-5
%
Output impedance: FB,R,G,B
Output voltage: FB,R,G,B
FB= 1
FB= 0
Global voltage accuracy
170/178
Value
Cload= 20pF
RL = 100K
VDD-0.8
V
ST92185B - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS (Cont’d)
A/D CONVERTER, EXTERNAL TRIGGER TIMING TABLE
(VDD= 5V +/-10%; TA= 0 to 70°C; unless otherwise specified
Symbol
Parameter
Tlow
Pulse Width
Thigh
Pulse Distance
Text
Period/fast Mode
Tstr
Start Conversion Delay
OSCIN divide by
2;min/max
Value
OSCIN divide
by 1; min/max
min
max
1.5
INTCLK
Unit
ns
ns
78+1
INTCLK
µs
0.5
1.5
INTCLK
Core Clock issued by Timing Controller
Tlow
Pulse Width
ns
Thigh
Pulse Distance
ns
Text
Period/fast Mode
µs
Tstr
Start Conversion Delay
ns
A/D CONVERTER. ANALOG PARAMETERS TABLE
(VDD= 5V +/-10%; TA= 0 to 70°C; unless otherwise specified))
Parameter
Value
typ (*)
Analog Input Range
Conversion Time Fast/Slow
Sample Time Fast/Slow
Power-up Time
Unit
min
max
(**)
VSS
VDD
V
Note
78/138
INTCLK
(1,2)
51.5/87.5
INTCLK
(1)
60
µs
Resolution
8
Differential Non Linearity
3
5
LSBs
(4)
Integral Non Linearity
4
5
LSBs
(4)
Absolute Accuracy
2
3
LSBs
(4)
Input Resistance
1.5
Kohm
(3)
Hold Capacitance
1.92
pF
Notes: (*)
(**)
(1)
(2)
(3)
(4)
bits
The values are expected at 25 Celsius degrees with VDD= 5V
’LSBs’ , as used here, as a value of VDD/256
@ 24 MHz external clock
including Sample time
it must be considered as the on-chip series resistance before the sampling capacitor
DNL ERROR= max {[V(i) -V(i-1)] / LSB-1}
INL ERROR= max {[V(i) -V(0)] / LSB-i}
ABSOLUTE ACCURACY= overall max conversion error
171/178
ST92185B - GENERAL INFORMATION
9 GENERAL INFORMATION
9.1 PACKAGE MECHANICAL DATA
Figure 105. 56-Pin Shrink Plastic Dual In Line Package, 600-mil Width
mm
Dim.
Min
Typ
A
inches
Max
Min
0.38
0.015
A2
3.18
4.95 0.125
b
0.41
b2
0.20
D
50.29
E
0.035
0.38 0.008
12.32
2.095
0.591
14.73 0.485
1.78
eA
15.24
eB
2.92
PDIP56S
0.015
53.21 1.980
15.01
e
L
0.195
0.016
0.89
C
Max
0.250
A1
E1
Typ
6.35
0.580
0.070
0.600
17.78
0.700
5.08 0.115
0.200
Number of Pins
N
56
Figure 106. 42-Pin Shrink Plastic Dual In-Line Package, 600-mil Width
Dim.
mm
Min
Typ
A
Min
Typ
5.08
0.51
0.020
A2
3.05
3.81 4.57 0.120 0.150 0.180
b
0.46 0.56
0.018 0.022
b2
1.02 1.14
0.040 0.045
C
0.23
D
36.58 36.83 37.08 1.440 1.450 1.460
E
15.24
E1
12.70 13.72 14.48 0.500 0.540 0.570
0.25 0.38 0.009 0.010 0.015
16.00 0.600
0.630
e
1.78
0.070
eA
15.24
0.600
eC
0.00
L
2.54
18.54
0.730
1.52 0.000
0.060
3.30 3.56 0.100 0.130 0.140
Number of Pins
N
172/178
Max
0.200
A1
eB
PDIP42S
inches
Max
42
ST92185B - GENERAL INFORMATION
PACKAGE MECHANICAL DATA (Cont’d)
Figure 107. 64-Pin Thin Quad Flat Package
Dim
mm
Min
Typ
A
Min
Typ
Max
1.60
0.063
0.15 0.002
0.006
A1
0.05
A2
1.35 1.40 1.45 0.053 0.055 0.057
B
0.30 0.37 0.45 0.012 0.015 0.018
C
0.09
0.20 0.004
0.008
D
16.00
0.630
D1
14.00
0.551
D3
12.00
0.472
E
16.00
0.630
E1
14.00
0.551
E3
12.00
0.472
e
0.80
K
L
L1
inches
Max
0°
3.5°
0.031
7°
0.45 0.60 0.75 0.018 0.024 0.030
L1
1.00
L
0.039
Number of Pins
N
64
ND
16
Max
Min
NE
16
K
Figure 108. 56-Pin Shrink Ceramic Dual In Line Package, 600-mil Width
Dim.
mm
Min
Typ
A
Typ
4.17
Max
0.164
A1
0.76
0.030
B
0.38
0.46 0.56 0.015 0.018 0.022
B1
0.76
0.89 1.02 0.030 0.035 0.040
C
0.23
0.25 0.38 0.009 0.010 0.015
D
50.04 50.80 51.56 1.970 2.000 2.030
D1
E1
48.01
1.890
14.48 14.99 15.49 0.570 0.590 0.610
e
1.78
0.070
G
14.12 14.38 14.63 0.556 0.566 0.576
G1
18.69 18.95 19.20 0.736 0.746 0.756
G2
CDIP56SW
inches
1.14
0.045
G3
11.05 11.30 11.56 0.435 0.445 0.455
G4
15.11 15.37 15.62 0.595 0.605 0.615
L
S
2.92
5.08 0.115
1.40
0.200
0.055
Number of Pins
N
56
173/178
ST92185B - GENERAL INFORMATION
Figure 109. 42-Pin Shrink Ceramic Dual In-Line Package, 600-mil Width
Dim.
mm
Min
Typ
A
Min
Typ
4.01
Max
0.158
A1
0.76
0.030
B
0.38
0.46 0.56 0.015 0.018 0.022
B1
0.76
0.89 1.02 0.030 0.035 0.040
C
0.23
0.25 0.38 0.009 0.010 0.015
D
36.68 37.34 38.00 1.444 1.470 1.496
D1
E1
35.56
1.400
14.48 14.99 15.49 0.570 0.590 0.610
e
1.78
0.070
G
14.12 14.38 14.63 0.556 0.566 0.576
G1
18.69 18.95 19.20 0.736 0.746 0.756
G2
CDIP42SW
inches
Max
1.14
0.045
G3
11.05 11.30 11.56 0.435 0.445 0.455
G4
15.11 15.37 15.62 0.595 0.605 0.615
L
2.92
S
5.08 0.115
0.89
0.200
0.035
Number of Pins
N
42
Figure 110. 64-Pin Ceramic Quad Flat Package
Dim
mm
Min
Typ
A
A1
B
inches
Max
Min
Typ
3.27
Max
0.129
0.50
0.020
0.30 0.35 0.45 0.012 0.014 0.018
C
0.13 0.15 0.23 0.005 0.006 0.009
D
16.65 17.20 17.75 0.656 0.677 0.699
D1 13.57 13.97 14.37 0.534 0.550 0.566
D3
12.00
e
0.80
0.031
G
12.70
0.500
G2
0.472
0.96
0.038
L
0.35 0.80
0.014 0.031
0
8.31
0.327
Number of Pins
CQFP064W
174/178
N
64
ST92185B - GENERAL INFORMATION
9.2 ORDERING INFORMATION
Each device is available for production in a user
programmable version (OTP) as well as in factory
coded version (ROM). OTP devices are shipped to
customer with a default blank content FFh, while
ROM factory coded parts contain the code sent by
customer. The common EPROM versions for debugging and prototyping features the maximum
memory size and peripherals of the family. Care
must be taken to only use resources available on
the target device.
9.2.1 Transfer Of Customer Code
Customer code is made up of the ROM contents
and the list of the selected options (if any). The
ROM contents are to be sent on diskette, or by
electronic means, with the hexadecimal file generated by the development tool. All unused bytes
must be set to FFh.
Figure 111. ROM Factory Coded Device Types
TEMP.
DEVICE PACKAGE RANGE / XXX
Code name (defined by STMicroelectronics)
1= standard 0 to +70 °C
BN= Plastic SDIP56
BJ= Plastic SDIP42
T= Plastic TQFP64
ST92185B1
ST92185B2
ST92185B3
175/178
ST92185B - GENERAL INFORMATION
STMicroelectronics OPTION LIST
ST92185B
Customer:
Address:
............................
............................
............................
Contact:
............................
Phone No: . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference/ROM Code* : . . . . . . . . . . . . . . . . . .
*The ROM code name assigned by ST.
STMicroelectronics reference:
Device:
[ ] ST92185B1B1
[ ] ST92185B2B1
[ ] ST92185B3B1
Package : [ ] SDIP42
[ ] SDIP56
[ ] TQFP64
Temperature Range : 0 to 70 C
Software Development:
[ ] STMicroelectronics
[ ] Customer
[ ] External laboratory
Special Marking:
[ ] No
[ ] Yes "_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _"
For marking, one line is possible with maximum 14 characters. Authorized characters are letters, digits, ’.’, ’-’, ’/’ and spaces only.
Please consult your local ST Microelectronics sales office for other marking details if required.
Notes
:
OSD Code
: [ ] OSD File Filename [........ .OSD]
Quantity forecast : [..................] k units per year
For a period of : [..................] years
Preferred Production start dates : [../../..] (YY/MM/DD)
Date
Customer Signature :
176/178
ST92185B - REVISION HISTORY
10 REVISION HISTORY
Rev.
1.0
1.1
1.2
1.3
Main Changes
First release on DMS
16K ROM added / TQFP64 added
p1, changed device summary; added one feature (pin-compatible with...) and changed one feature
(Pin-compatible EPROM, etc.). Added Option List.
Added Section 10 on page 177. Updated Figure 3 on page 10 and Figure 5 on page 12. Changed
Non-linearity values in A/D Converter Analog Parameters Table. Modified Table 9 on page 59.
Modified Section 4.2 on page 57.
Modification of the absolute maximum rating of the Supply Voltage value in Section 8 on page 166.
Date
01/11/00
03/15/00
11 Oct
2001
16 Jan
2002
177/178
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
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2003 STMicroelectronics - All Rights Reserved.
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I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
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