ETC STAC9708T

PRELIMINARY
SigmaTel, Inc.
Integrating Mixed-Signal Solutions
STAC9708/11
Multi-Channel AC'97 Codec
With Multi-Codec Option
GENERAL DESCRIPTION:
SigmaTel’s STAC9708/11 is a general purpose 18-bit, full duplex, audio codec that conforms to the analog
component specification of AC'97 (Audio Codec 97 Component Specification Rev. 2.1). The STAC9708/11
incorporates SigmaTel’s proprietary Sigma-Delta technology to achieve a DAC SNR in excess of 95dB. The
DACs, ADCs, and mixer are integrated with analog I/Os, which include four analog line-level stereo inputs, two
analog line-level mono inputs, two stereo outputs, and one mono output channel. Also included are two
additional high quality DACs, with independent volume control, for multi-channel applications. With
SigmaTel’s 3D stereo enhancement (SS3D), independently selectable on both LINE OUT and DAC OUT, the
multi-channel mode immerses the user in a richer and livelier listening experience. The STAC9708/11 may be
used as a secondary codec, with the STAC9704/07 as the primary, in a multiple codec configuration conforming
to the AC'97 Rev. 2.1 specification. This configuration can provide true six-channel, AC-3 playback required for
DVD applications. The STAC9708/11 communicates via the five-wire AC-Link to any digital component of
AC'97 providing flexibility in the audio system design. Packaged in an AC'97 compliant 48-pin TQFP, the
STAC9708/11 can be placed on the motherboard, daughter boards, add-on cards or PCMCIA cards.
FEATURES:
•
High performance Σ ∆ technology
•
Two additional high quality DAC’s
for multi-channel applications
•
18-bit full duplex stereo ADC, DACs
•
AC-Link protocol compliance
•
Multiple power supply options
•
Pin compatible with the STAC9704/07
1
•
SigmaTel Surround
Enhancement
•
Energy saving power down modes
•
Multi-Codec option (Intel AC'97 rev 2.1)
•
Six analog line-level inputs
•
48-pin TQFP
•
SNR > 95 dB through Mixer and DAC
(SS3D)
Stereo
10/02/98
ORDERING INFORMATION:
PART
NUMBER
PACKAGE
STAC9708T
48-pin TQFP 7mm x7mm x 1.4mm
0o C to +70o C
DVdd = 3.3V or 5V, AVdd = 5V
48-pin TQFP 7mmx7mm x 1.4mm
0o C to +70o C
DVdd = 3.3V, AVdd = 3.3V
STAC9711T
TEMPERATURE
RANGE
SUPPLY RANGE
SigmaTel reserves the right to change specifications without notice.
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Preliminary
3.1.2.2 Slot 2: Status Data Port
3.1.2.3 Slot 3: PCM Record Left
Channel
3.1.2.4 Slot 4: PCM Record Right
Channel
3.1.2.5 Slots 5-12: Reserved
Table of Contents
General Description
1
Ordering Information
2
1. PIN/SIGNAL Descriptions
1.1 Digital I/O
1.2 Analog I/O
1.3 Filter/References/GPIO
1.4 Power and Ground Signal
9
9
10
11
12
2. AC-Link
2.1 Clocking
2.2 Reset
12
13
13
3. Digital Interface
3.1 AC-Link Digital Serial Interface
Protocol
14
3.1.1 AC-Link Audio Output Frame
(SDATA_OUT)
3.1.1.1 Slot 1: Command Address Port
3.1.1.2 Slot 2: Command Data Port
3.1.1.3 Slot 3: PCM Playback Left
Channel
3.1.1.4 Slot 4: PCM Playback Right
Channel
3.1.1.5 Slot 5: Reserved
3.1.1.6 Slot 6: PCM Center Channel
3.1.1.7 Slot 7: PCM Left Surround
Channel
3.1.1.8 Slot 8: PCM Right Surround
Channel
3.1.1.9 Slot 9: PCM Low Frequency
Channel
3.1.1.10 Slot 10: PCM Alternate Left
3.1.1.11 Slot 11: PCM Alternate Right
3.1.1.12 Slot 12: Reserved
3.1.2 AC-Link Audio Input Frame
(SDATA_In)
3.1.2.1 Slot 1: Status Address Port
STAC9708/11
21
21
21
21
3.2 AC-Link Low Power Mode
21
3.2.1 Waking up the AC-Link
4. STAC9708/11 Mixer
4.1 Mixer Input.
4.2 Mixer Output
4.3 PC Beep Implementations
4.4 Programming Registers
4.4.1 Reset Register
4.4.2 Play Master Volume Registers
4.4.3 PC Beep Register
4.4.4 Analog Mixer Input Gain
4.4.5 Record Select Control
4.4.6 Record Gain Registers
4.4.7 General Purpose Register
4.4.8 3D Control Register
4.4.9 Multi-Channel Programming
4.4.10 Powerdown Control/Status
4.4.10.1 External Amplifier Power
Down (EAPD) Control
4.4.11 Extended Audio ID Register
4.4.12 Extended Audio Status Register
4.4.13 Analog Special Register
4.4.14 Vendor ID1 and ID2 Registers
14
15
16
17
17
17
17
17
22
23
25
25
25
26
27
27
27
28
28
30
30
30
31
32
33
33
33
33
33
18
5. Low Power Modes
34
18
6. Multiple Codec Support
6.1 Primary/Secondary Codec Selection
6.1.1 Primary Codec Operation
6.1.2 Secondary Codec Operation
6.2 Secondary Codec Register Access
Definitions
36
36
36
36
7. Testability
37
18
18
18
19
19
20
3
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Preliminary
8. Extended Codec Functionality
8.1 Anti-Pop Circuitry
38
38
9. AC Timing Characteristics
9.1 Cold Reset.
9.2 Warm Reset
9.3 Clocks
9.4 Data Setup and Hold
9.5 Signal Rise and Fall Times
9.6 AC-Link Low Power Mode Timing
9.7 ATE Test Mode
38
38
39
40
41
42
43
44
10. Electrical Specifications
10.1 Absolute Maximum Conditions
10.2 Recommended Operating Conditions
10.3 Power Consumption
10.4 AC-Link Static Digital Specifications
10.5 9708 Analog Performance
Characteristics
10.6 9711 Analog Performance
Characteristics
45
45
45
46
46
APPENDIX A
51
APPENDIX B
52
STAC9708/11
47
49
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Preliminary
Table of Contents – Tables
Table 1 – Package Dimensions
6
Table 2 – Pin Designation
6
Table 3 – Digital Signal List
9
Table 4 – Analog Signal List
10
Table 5 – Filtering and Voltage References
11
Table 6 – 9708/11 Power Signal List
11
Table 7 –Mixer Functional Connections
24
Table 8 – Programming Registers
25
Table 9 – Play Master Volume Register
26
Table 10 – PC Beep Register
27
Table 11 – Analog Mixer Input Gain Register
27
Table 12, 13 – Record Select Control Registers
28
Table 14 – Record Gain Registers
29
Table 15 – General Purpose Registers
29
Table 16, 17 – 3D Control Registers
30
Table 18– Multi-Channel Programming
Register
31
Table 19 – Powerdown Status Registers
31
Table 20 – Low Power Modes
32
Table 21 - Codec ID Selection
36
Table 22 - Secondary Codec Register Access
Slot 0 Bit Definitions
37
Table 23 – Cold Reset
36
Table 24 – Warm Reset
36
Table 25 – Clocks
37
Table 26 – Data Setup and Hold
38
Table 27 – Signal Rise and Fall Times
39
Table 28 – AC-Link Low Power Mode Timing
40
Table 29 – ATE Test Mode
40
5
STAC9708/11
Table 30 – Operating Conditions
44
Table 28 – Power Consumption
45
Table 29 – AC-Link Static Specifications
45
Table 30 – 9708 Analog Performance
Characteristics
Table 31 – 9711 Analog Performance
Characteristics
46
48
Table of Contents – Figures
Figure 1 – Package Outline
6
Figure 2 – STAC9708 Block Diagram
7
Figure 3 – Connection Diagram
8
Figure 4 – STAC9708 AC-Link
12
Figure 5 – AC'97 Standard Bi-directional
15
Figure 6 – AC-Link Audio Output Frame
15
Figure 7 – Start of an Audio Output Frame
16
Figure 8 – STAC9708 Audio Input Frame
19
Figure 9 – Start of an Audio Input Frame
20
Figure 10 – STAC9708 Powerdown Timing
22
Figure 11 – STAC9708 Mixer Functional Diagram
23
Figure 12 – Example of STAC9708 Powerdown/
Powerup flow
35
Figure 13 – STAC9708 Powerdown/Powerup
with analog still alive
35
Figure 14 – Cold Reset
38
Figure 15 – Warm Reset
39
Figure 16 – Clocks
39
Figure 17 – Data Setup and Hold
40
Figure 18 – Signal Rise and Fall Times
41
Figure 19 – AC-Link Low Power Mode Timing
42
Figure 20 – ATE Test Mode
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SigmaTel, Inc
Preliminary
Figure 1. Package Outline
STAC9708/11
Table 1. Package Dimensions
D
KEY
D1
D
D1
E
E1
a (lead width)
e (pitch)
thickness
a
26
38
SigmaTel
E
e
STAC9708/11
E1
48 pin TQFP
14
2
9708/11 DIMENSION
TQFP
9.00 mm
7.00 mm
9.00 mm
7.00 mm
0.20 mm
0.50 mm
1.4 mm
Table 2. Pin Designation
PIN
#
1
2
3
4
5
6
7
8
9
10
11
12
SIGNAL
NAME
DVdd1
XTL_IN
XTL_OUT
DVss1
SDATA_OUT
BIT_CLK
DVss2
SDATA_IN
DVdd2
SYNC
RESET#
PC_BEEP
PI
N#
13
14
15
16
17
18
19
20
21
22
23
24
SIGNAL
NAME
PHONE
AUX_L
AUX_R
VIDEO_L
VIDEO_R
CD_L
CD_GND
CD_R
MIC1
MIC2
LINE_IN_L
LINE_IN_R
PIN
#
25
26
27
28
29
30
31
32
33
34
35
36
SIGNAL
NAME
AVdd1
AVss1
Vref
Vrefout
AFILT1
AFILT2
CAP1
CAP2
CAP3
APOP
LINE_OUT_L
LINE_OUT_R
PIN
#
37
38
39
40
41
42
43
44
45
46
47
48
SIGNAL
NAME
MONO_OUT
AVdd2
DAC_OUT_L
NC
DAC_OUT_R
AVss2
NC
NC
CID0
CID1
EAPD
NC
# denotes active low
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Preliminary
STAC9708/11
Figure 2. STAC9708 Block Diagram
2 mono sources
4 stereo
sources
mono
Power
Management
stereo
PCM out DACs
48Kss
Digital
AC-link
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
RESET
Interface
DAC
DAC
Registers
64 x 16 bits
DAC_OUT
DAC
DAC
PCM in ADCs
ADC
M IXER
LINE_OUT
MONO_OUT
Analog mixing
and
Gain control
Mic
Boost
0/20 dB
M
U
X
M IC 1
M IC 2
ADC
Multi-Codec
48Kss
ID0
ID1
The STAC9708/11 block diagram, above, illustrates its primary functional blocks. It performs fixed 48K sample
rate D-A & A-D conversion, mixing, and analog processing. The digital interface communicates with the AC'97
controller via the five wire AC-Link and contains the 64 word by 16-bit registers. Four, fixed 48Ks/s DAC’s
support two stereo PCM-out channels for surround sound applications requiring four speakers. The digital mix of
all software sources, including the internal synthesizer and any other digital sources, is performed in the digital
controller. The Mixer block mixes the PCM_OUT with any analog sources, then outputs to LINE_OUT. The
surround DACs are output to DAC_OUT, and this stereo output has independent volume control. In addition, the
surround DACs can be input to the Mixer block and output to LINE_OUT. The MONO_OUT delivers either mic
only or a mono mix of sources from the mixer. The two fixed 48Ks/s ADC’s take any mix of mono or stereo
sources and convert it to a stereo PCM-in signal. All ADC's and DAC's operate at 18-bit resolution.
The STAC9708/11 is designed primarily to support multi-channel, 4-speaker PC audio. However, true AC-3
playback can be achieved for 6-speaker applications by taking advantage of the multi-codec option in the
STAC9708/11. Using this option with a STAC9704/07 as the primary codec, and the STAC9708 as the secondary
codec, 6-channel output can be achieved in an AC'97 architecture. Also, the STAC9708/11 provides for a stereo
enhancement feature, Sigmatel Surround 3D or SS3D. SS3D provides the listener with several options to
expand the soundstage beyond the normal 2-speaker arrangement.
Together with the logic component (controller or advanced core logic chip-set) of AC'97, STAC9708/11 can be
SoundBlaster and Windows Sound System compatible. SoundBlaster is a registered trademark of Creative
Labs. Windows is a registered trademark of Microsoft Corporation.
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Preliminary
STAC9708/11
Figure 3. Connection Diagram –
See Appendix A for an alternative connection diagram when using separate supplies.
See Appendix B for specific connection requirements prior to operation.
2 ohm *
Ferrite Bead *
* Suggested
10uF
0.1uF
0.1uF
1uF
25
AVdd1
3.3V or 5V ± 5%
0.1uF
0.1uF
38
1
AVdd2
DVdd1
9
2
DVdd2
33pF
XTL_IN
12
P C _ B EE P
24.576MHz
XTL_OUT
13
3
33pF
PHONE
5
SDATA_OUT
14
6
AUX_L
BIT_CLK
8
15
SDATA_IN
AUX_R
SigmaTel
16
10
SYNC
VIDEO_L
11
RESET
STAC9708/11
17
VIDEO_R
45
CID0
18
46
CD_L
CID1
19
CD_GND
27
20
Vref
CD_R
10uF
0.1uF
21
28
MIC1
Vrefout
32
22
CAP2
MIC2
CAP1
23
LINE_IN_L
CAP3
10uF
31
0.1uF
10uF
33
22uF
24
LINE_IN_R
APOP
45
CID0
EAPD
46
47
35
CID1
LINE_OUT_L
560 - 1000pF
29
34
LINE_OUT_R
36
AFILT1
37
560 - 1000pF
MONO_OUT
30
AFILT2
AVss1
26
AVss2
42
DVss1
DVss2
4
7
DAC_OUT_L
39
DAC_OUT_R
41
** Teminate ground
plane as close to power
supply as possible
NOTE: Pins 31, 33, 34, 40
43, 44, and 48 are No Connects
Brd Analog Gnd
8
Brd Digital Gnd
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SigmaTel, Inc.
Preliminary
STAC9708/11
1. PIN/SIGNAL DESCRIPTIONS
1.1 Digital I/O
These signals connect the STAC9708/11 to its AC'97 controller counterpart, an external crystal, multicodec selection and external audio amplifier.
Table 3. Digital Signal List
SIGNAL NAME
TYPE
DESCRIPTION
RESET #
I
AC'97 Master H/W Reset
XTL_IN
I
24.576 MHz Crystal
XTL_OUT
O
24.576 MHz Crystal
SYNC
I
48 kHz fixed rate sample sync
BIT_CLK
O
12.288 MHz serial data clock
SDATA_OUT
I
Serial, time division multiplexed, AC'97 input stream
SDATA__IN
O
Serial, time division multiplexed, AC'97 output stream
CID0
I
Multi-Codec ID select – bit 0
CID1
I
Multi-Codec ID select – bit 1
EAPD
O
External Amplifier Power Down
# denotes active low
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Preliminary
STAC9708/11
1.2 Analog I/O
These signals connect the STAC9708/11 to analog sources and sinks, including microphones and
speakers.
Table 4. Analog Signal List
SIGNAL NAME
TYPE
DESCRIPTION
PC-BEEP
I
PC Speaker beep pass-through
PHONE
I
From telephony subsystem speakerphone (or DLP - Down Line Phone)
MIC1
I
Desktop Microphone Input
MIC2
I
Second Microphone Input
LINE-IN-L
I
Line In Left Channel
LINE-IN-R
I
Line In Right Channel
CD-L
I
CD Audio Left Channel
CD-GND
I
CD Audio analog ground
CD-R
I
CD Audio Right Channel
VIDEO-L
I
Video Audio Left Channel
VIDEO-R
I
Video Audio Right Channel
AUX-L
I
Aux Left Channel
AUX-R
I
Aux Right Channel
LINE-OUT-L
O
Line Out Left Channel
LINE-OUT-R
O
Line Out Right Channel
MONO-OUT
O
To telephony subsystem speakerphone (or DLP – Down Line Phone)
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STAC9708/11
DAC_OUT_L
O
Surround DAC Out Left Channel
DAC_OUT_R
O
Surround DAC Out Right Channel
* Note: any unused input pins should have a capacitor (1 uF suggested) to ground.
1.3 Filter/References/GPIO
These signals are connected to resistors, capacitors, specific voltages, or provide general purpose I/O.
Table 5. Filtering and Voltage References
SIGNAL NAME
TYPE
DESCRIPTION
Vref
O
Reference Voltage
Vrefout
O
Reference Voltage out 5mA drive (intended for mic bias)
AFILT1
O
Anti-Aliasing Filter Cap - ADC channel
AFILT2
O
Anti-Aliasing Filter Cap - ADC channel
CAP1
O
Analog Output Hold-Off Delay
CAP2
O
ADC reference Cap
CAP3
O
Anti-Pop Power Sustain Delay
APOP
O
Anti-Pop Output Ground Shunt Control
EAPD
O
External Amplifier Power Down Control
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Preliminary
STAC9708/11
1.4 Power and Ground Signals
Table 6. Power Signal List STAC9708/11
SIGNAL NAME
AVdd1
AVdd2
AVss1
AVss2
DVdd1
DVdd2
DVss1
DVss2
TYPE
I
I
I
I
I
I
I
I
STAC9708
Analog Vdd = 5.0V
Analog Vdd = 5.0V
Analog Gnd
Analog Gnd
Digital Vdd = 5.0V or 3.3V
Digital Vdd = 5.0V or 3.3V
Digital Gnd
Digital Gnd
STAC9711
Analog Vdd = 3.3V
Analog Vdd = 3.3V
Analog Gnd
Analog Gnd
Digital Vdd = 3.3V
Digital Vdd = 3.3V
Digital Gnd
Digital Gnd
2. AC-LINK
Below is the figure of the AC-Link point to point serial interconnect between the STAC9708/11 and its
companion controller. All digital audio streams and command/status information are communicated over this
AC-Link. Please refer to the “Digital Interface” section 3 for details.
Figure 4. STAC9708/11’s AC-Link to its companion controller
XTAL_IN
SYNC
Digital
DC’97
Controller
BIT_CLK
SDATA_OUT
STAC9708/11
SDATA_IN
XTAL_OUT
RESET
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Preliminary
STAC9708/11
2.1 Clocking
STAC9708/11 derives its clock internally from an externally connected 24.576 MHz crystal or an
oscillator through the XTAL_IN pin. Synchronization with the AC'97 controller is achieved through the
BIT_CLK pin at 12.288 MHz (half of crystal frequency).
The beginning of all audio sample packets, or “Audio Frames”, transferred over AC-Link is
synchronized to the rising edge of the “SYNC” signal driven by the AC'97 controller. Data is
transitioned on AC-Link on every rising edge of BIT_CLK, and subsequently sampled by the receiving
side on each immediately following falling edge of BIT_CLK.
2.2 Reset
There are 3 types of resets as detailed under “Timing Characteristics”.
1.
a “cold” reset where all STAC9708/11 logic and registers are initialized to their default state
2.
a “warm” reset where the contents of the STAC9708/11 register set are left unaltered
3.
a “register” reset which only initializes the STAC9708/11 registers to their default states
After signaling a reset to the STAC9708/11, the AC'97 controller should not attempt to play or capture
audio data until it has sampled a “Codec Ready” indication via register 26h from the STAC9708/11.
For proper reset operation SDATA_OUT should be “0” during “cold” reset.
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Preliminary
STAC9708/11
3. DIGITAL INTERFACE
3.1 AC-Link Digital Serial Interface Protocol
The STAC9708/11 communicates to the AC'97 controller via a 5-pin digital serial AC-Link interface,
which is a bi-directional, fixed rate, serial PCM digital stream. All digital audio streams, commands
and status information are communicated over this point-to-point serial interconnect. The AC-Link
handles multiple inputs, and output audio streams, as well as control register accesses using a time
division multiplexed (TDM) scheme. The AC'97 controller synchronizes all AC-Link data transaction.
The following data streams are available on the STAC9708/11:
•
PCM Playback
4 output slots
4 Channel composite PCM output stream
•
PCM Record data
2 input slots
2 Channel composite PCM input stream
•
Control
2 output slots
Control register write port
•
Status
2 input slots
Control register read port
Synchronization of all AC-Link data transactions is handled by the AC'97 controller.
The
STAC9708/11 drives the serial bit clock onto AC-Link. The AC'97 controller then qualifies with a
synchronization signal to construct audio frames.
SYNC, fixed at 48 kHz, is derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed
at 12.288 MHz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming
time slots. AC-Link serial data is transitioned on each rising edge of BIT_CLK. The receiver of ACLink data, STAC9708/11 for outgoing data and AC'97 controller for incoming data, samples each serial
bit on the falling edges of BIT_CLK.
The AC-Link protocol provides for a special 16-bit (13-bits defined, with 3 reserved trailing bit
positions) time slot (Slot 0) wherein each bit conveys a valid tag for its corresponding time slot within
the current audio frame. A “1” in a given bit position of slot 0 indicates that the corresponding time
slot within the current audio frame has been assigned to a data stream, and contains valid data. If a slot
is “tagged” invalid, it is the responsibility of the source of the data, (STAC9708/11 for the input
stream, AC'97 controller for the output stream), to stuff all bit positions with 0’s during that slot’s
active time.
SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The
portion of the audio frame where SYNC is high is defined as the “Tag Phase”. The remainder of the
audio frame where SYNC is low is defined as the “Data Phase”.
Additionally, for power savings, all clock, sync, and data signals can be halted.
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Preliminary
STAC9708/11
SYNC
TAG
OUTGOING STREAMS
CMD
ADR
INCOMING STREAMS
TAG
STATUS
ADR
CMD
DATA
PCM
LEFT
PCM
RT
NA
PCM
CTR
PCM
LSURR
PCM
RSURR
STATUS
PCM
LEFT
PCM
RT
NA
NA
RSVD
RSVD
DATA
TAG PHASE
PCM
LFE
PCM
LALT
PCM
RALT
RSVD
RSVD
RSVD
RSVD
RSVD
DATA PHASE
Figure 5. AC'97 Standard Bi-directional Audio Frame
3.1.1 AC-Link Audio Output Frame (SDATA_OUT)
The audio output frame data streams correspond to the multiplexed bundles of all digital output data
targeting the STAC9708/11 DAC inputs, and control registers. Each audio output frame supports up to
12 20-bit outgoing data time slots. Slot 0 is a special reserved time slot containing 16 bits that are used
for AC-Link protocol infrastructure.
Within slot 0, the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the
entire audio frame. If the “Valid Frame” bit is a 1, this indicates that the current audio frame contains
at least one slot time of valid data. The next 12 bit positions sampled by the STAC9708/11 indicate
which of the corresponding 12 times slots contain valid data. In this way data streams of differing
sample rates can be transmitted across AC-Link at its fixed 48kHz audio frame rate. The following
diagram illustrates the time slot based AC-Link protocol.
Figure 6. AC-Link Audio Output Frame
Data Phase
Tag Phase
SYNC
20.8 uS (48 kHZ)
12.288 MHz
BIT_CLK
SDATA_OUT
valid
Frame
slot1
slot2
slot(12) "0"
CID1 CID0
19
"0"
19
"0"
19
"0"
19
"0"
End of previous audio frame
Time Slot "Valid" Bits
("1" = time slot contains valid PCM data)
Slot 1
Slot 2
Slot 3
Slot 12
A new audio output frame begins with a low to high transition of SYNC. SYNC is synchronous to the
rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the STAC9708/11
samples the assertion of SYNC. This following edge marks the time when both sides of AC-Link are
aware of the start of a new audio frame. On the next rising edge of BIT_CLK, the AC'97 controller
transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is
presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the STAC9708/11 on
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Preliminary
STAC9708/11
the following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent
sample points for both incoming and outgoing data streams are time aligned.
Figure 7. Start of an Audio Output Frame
STAC9708 samples SYNC assertion here
SYNC
STAC9708 samples first SDATA_OUT bit of frame here
BIT_CLK
SDATA_OUT
valid
Frame
slot1
slot2
End of previous audio frame
SDATA_OUT’s composite stream is MSB justified (MSB first) with all non-valid slots’ bit positions
stuffed with 0’s by the AC'97 controller.
When mono audio sample streams are sent from the AC'97 controller, it is necessary that BOTH left
and right sample stream time slots be filled with the same data.
3.1.1.1 Slot 1: Command Address Port
The command port is used to control features, and monitor status (see Audio Input Frame
Slots 1 and 2) of the STAC9708/11 functions including, but not limited to, mixer settings,
and power management (refer to the control register section of this specification).
The control interface architecture supports up to 64 16-bit read/write registers, addressable on
even byte boundaries. Only the even registers (00h, 02h, etc.) are valid.
Audio output frame slot 1 communicates control register address, and write/read command
information to the STAC9708/11.
Command Address Port bit assignments:
Bit (19)
Read/Write command (1= read, 0=write)
Bit (18:12) Control Register Index (64 16-bit locations, addressed on even byte boundaries)
Bit (11:0) Reserved (Stuffed with 0's)
The first bit (MSB) sampled by STAC9708/11 indicates whether the current control
transaction is a read or a write operation. The following 7 bit positions communicate the
targeted control register address. The trailing 12 bit positions within the slot are reserved and
must he stuffed with 0's by the AC'97 controller.
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SigmaTel, Inc.
Preliminary
STAC9708/11
3.1.1.2 Slot 2: Command Data Port
The command data port is used to deliver 16-bit control register write data in the event that
the current command port operation is a write cycle. (as indicated by Slot 1, bit 19)
Bit (19:4)
Bit (3 :0)
Control Register Write Data (Stuffed with 0's if current operation is a read)
Reserved
(Stuffed with 0's)
If the current command port operation is a read then the entire slot time must be stuffed with
0's by the AC'97 controller.
3.1.1.3 Slot 3: PCM Playback Left Channel
Audio output frame slot 3 is the composite digital audio left playback stream. In a typical
“Games Compatible" PC this slot is composed of standard PCM (.wav) output samples
digitally mixed (on the AC'97 controller or host processor) with music synthesis output
samples. If a sample stream of resolution less than 20-bits is transferred, the AC'97 controller
must stuff all trailing non-valid bit positions within this time slot with 0's.
3.1.1.4 Slot 4: PCM Playback Right Channel
Audio output frame slot 4 is the composite digital audio right playback stream. In a typical
“Games Compatible" PC this slot is composed of standard PCM (.wav) output samples
digitally mixed (on the AC'97 controller or host processor) with music synthesis output
samples. If a sample stream of resolution less than 20-bits is transferred, the AC'97 controller
must stuff all trailing non-valid bit positions within this time slot with 0's.
3.1.1.5 Slot 5: Reserved
Audio output frame slot 5 is reserved for modem operation and is not used by the
STAC9708/11.
3.1.1.6 Slot 6: PCM Center Channel
Audio output frame slot 6 is the composite digital audio center stream used in a multi-channel
application where the STAC9708/11 is programmed to accept the primary DAC PCM data
from slots 6 and 9. As a programming option, PCM data from slots 6 and 9 may be used to
supply data to the surround DACs when slots 7 and 8 are used to drive the primary DACs.
Please refer to the register programming section for details on the multi-channel programming
options.
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SigmaTel, Inc.
Preliminary
STAC9708/11
3.1.1.7 Slot 7: PCM Left Surround Channel
Audio output frame slot 7 is the composite digital audio left surround stream. In the default
state, the STAC9708/11 accepts PCM data from slots 7 and 8 for the surround DACs, for
output to the DAC_OUT pins. As a programming option, PCM data from slots 7 and 8 may be
used to supply data to the primary DACs when slots 6 and 9 are used to drive the surround
DACs. Please refer to the register programming section for details on the multi-channel
programming options.
3.1.1.8 Slot 8: PCM Right Surround Channel
Audio output frame slot 8 is the composite digital audio right surround stream. In the default
state, the STAC9708/11 accepts PCM data from slots 7 and 8 for the surround DACs, for
output to the DAC_OUT pins. As a programming option, PCM data from slots 7 and 8 may be
used to supply data to the primary DACs when slots 6 and 9 are used to drive the surround
DACs. Please refer to the register programming section for details on the multi-channel
programming options.
3.1.1.9 Slot 9: PCM Low Frequency Channel
Audio output frame slot 9 is the composite digital audio low frequency stream used in a multichannel application where the STAC9708/11 is programmed to accept the primary DAC PCM
data from slots 6 and 9. As a programming option, PCM data from slots 6 and 9 may be used
to supply data to the surround DACs when slots 7 and 8 are used to drive the primary DACs.
Please refer to the register programming section for details on the multi-channel programming
options.
3.1.1.10 Slot 10: PCM Alternate Left
Audio output frame slot 10 is the composite digital audio alternate left stream used in a multichannel application where the STAC9708/11 is programmed to accept the primary DAC PCM
data from slots 6 and 9. Please refer to the register programming section for details on the
multi channel programming options.
3.1.1.11 Slot 11: PCM Alternate Right
Audio output frame slot 11 is the composite digital audio alternate right stream used in a
multi-channel application where the STAC9708/11 is programmed to accept the primary
DAC PCM data from slots 6 and 9. Please refer to the register programming section for
details on the multi channel programming options.
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Preliminary
STAC9708/11
3.1.1.12 Slot 12: Reserved
Audio output frame slot 12 is reserved for modem operations and is not used by the
STAC9708/11.
3.1.2 AC-Link Audio Input Frame (SDATA_IN)
The audio input frame data streams correspond to the multiplexed bundles of all digital input data
targeting the AC'97 controller. As is the case for audio output frame, each AC-Link audio input frame
consists of 12, 20-bit time slots. Slot 0 is a special reserved time slot containing 16 bits that are used for
AC-Link protocol infrastructure.
Within slot 0 the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the
STAC9708/11 is in the "Codec Ready" state or not. If the “Codec Ready” bit is a 0, this indicates that
STAC9708/11 is not ready for normal operation. This condition is normal following the de-assertion of
power on reset, for example, while STAC9708/11’s voltage references settle. When the AC-Link
"Codec Ready" indicator bit is a 1, it indicates that the AC-Link and STAC9708/11 control/status
registers are in a fully operational state. The AC'97 controller must further probe the Powerdown
Control Status Register (refer to Mixer Register section) to determine exactly which subsections, if any,
are ready.
Prior to any attempts at putting STAC9708/11 into operation the AC'97 controller should poll the first
bit in the audio input frame (SDATA_IN slot 0, bit 15) for an indication that STAC9708/11 has become
"Codec Ready". Once the STAC9708/11 is sampled "Codec Ready", the next 12 bit positions sampled
by the AC'97 controller indicate which of the corresponding 12 time slots are assigned to input data
streams, and that they contain valid data. The following diagram illustrates the time slot based AC-Link
protocol.
Figure 8. STAC9708/11 Audio Input Frame
Data Phase
Tag Phase
SYNC
20.8 uS (48 kHZ)
12.288 MHz
BIT_CLK
SDATA_IN
valid
Frame
slot1
slot2
slot(12) "0"
"0"
"0"
19
"0"
19
"0"
19
"0"
19
"0"
End of previous audio frame
Time Slot "Valid" Bits
Slot 1
Slot 2
Slot 3
Slot 12
("1" = time slot contains valid PCM data)
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Preliminary
STAC9708/11
A new audio input frame begins with a low to high transition of SYNC. SYNC is synchronous to the
rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, STAC9708/11
samples the assertion of SYNC. This falling edge marks the time when both sides of AC-Link are
aware of the start of a new audio frame. On the next rising of BIT_CLK, the STAC9708/11 transitions
SDATA_IN into the first bit position of slot 0 ("Codec Ready" bit). Each new bit position is presented
to AC-Link on a rising edge of BIT_CLK and subsequently sampled by the AC'97 controller on the
following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent
sample points for both incoming and outgoing data streams are time aligned.
Figure 9. Start of an Audio Input Frame
STAC9708 samples SYNC assertion here
SYNC
STAC9708 samples first SDATA_OUT bit of frame here
BIT_CLK
SDATA_IN
Codec
Ready
slot1
slot2
End of previous audio frame
SDATA_IN's composite stream is MSB justified (MSB first) with all non-valid bit positions (for
assigned and/or unassigned time slots) stuffed with 0's by STAC9708/11. SDATA_IN data is sampled
on the falling edges of BIT_CLK.
3.1.2.1 Slot 1: Status Address Port
The status port is used to monitor status for STAC9708/11 functions including, but not
limited to, mixer settings, and power management.
Audio input frame slot 1’s stream echoes the control register index, for historical reference,
for the data to be returned in slot 2. (Assuming that slots 1 and 2 had been tagged “valid” by
STAC9708/11 during slot 0)
Status Address Port hit assignments:
Bit (19)
RESERVED
(Stuffed with 0)
Bit (18;12) Control Register Index (Echo of register index for which data is being returned)
Bit (11:0) RESERVED
(Stuffed with 0's)
The first bit (MSB) generated by STAC9708/11 is always stuffed with a 0. The following 7
bit positions communicate the associated control register address, and the trailing 12 bit
positions are stuffed with 0's by STAC9708/11.
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Preliminary
STAC9708/11
3.1.2.2 Slot 2: Status Data Port
The status data port delivers 16-bit control register read data.
Bit (19:4)
Bit (3 :0)
Control Register Read Data
RESERVED
(Stuffed with 0's if tagged "invalid")
(Stuffed with 0's)
If Slot 2 is tagged "invalid" by STAC9708/11, then the entire slot will be stuffed with 0's.
3.1.2.3 Slot 3: PCM Record Left Channel
Audio input frame slot 3 is the left channel output of STAC9708/11 input MUX, post-ADC.
STAC9708/11 ADCs are implemented to support 18-bit resolution.
STAC9708/11 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit
positions with 0's to fill out its 20-bit time slot.
3.1.2.4 Slot 4: PCM Record Right Channel
Audio input frame slot 4 is the right channel output of STAC9708/11 input MUX, post-ADC.
STAC9708/11 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit
positions with 0's to fill out its 20-bit time slot.
3.1.2.5 Slots 5-12: Reserved
Audio input frame slots 5-12 are not used by the STAC97908/11 and are always stuffed with
0's.
3.2 AC-Link Low Power Mode
The STAC9708/11 AC-Link can be placed in the low power mode by programming register 26h to the
appropriate value. Both BIT_CLK and SDATA_IN will be brought to, and held at a logic low voltage
level. The AC'97 controller can wake up the STAC9708/11 by providing the appropriate reset signals.
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Preliminary
STAC9708/11
Figure 10. STAC9708/11 Powerdown Timing
SYNC
BIT_CLK
SDATA_OUT
slot2
per frame
TAG
SDATA_IN
slot2
per frame
TAG
Write to
0x20
Data
PR4
Note: BIT_CLK not to scale
BIT_CLK and SDATA_IN are transitioned low immediately (within the maximum specified time) following
the decode of the write to the Powerdown Register (26h) with PR4. When the AC'97 controller driver is at
the point where it is ready to program the AC-Link into its low power mode, slots (1 and 2) are assumed to
be the only valid stream in the audio output frame (all sources of audio input have been neutralized).
The AC'97 controller should also drive SYNC, and SDATA_OUT low after programming the STAC9708/11
to this low power mode.
3.2.1 Waking up the AC-Link
Once the STAC9708/11 has halted BIT_CLK, there are only two ways to “wake up” the AC-Link.
Both methods must be activated by the AC'97 controller. The AC-Link protocol provides for a “Cold
AC'97 Reset”, and a “Warm AC'97 Reset”. The current power down state would ultimately dictate
which form of reset is appropriate. Unless a “cold” or “register” reset (a write to the Reset register) is
performed, wherein the AC'97 registers are initialized to their default values, registers are required to
keep state during all power down modes. Once powered down, re-activation of the AC-Link via reassertion of the SYNC signal must not occur for a minimum of 4 audio frame times following the frame
in which the power down was triggered. When AC-Link powers up it indicates readiness via the Codec
Ready bit (input slot 0, bit 15).
Cold Reset - a cold reset is achieved by asserting RESET# for the minimum specified time. By driving
RESET# low, BIT_CLK, and SDATA_IN will be activated, or re-activated as the case may be, and all
STAC9708/11 control registers will be initialized to their default power on reset values.
Note: RESET# is an asynchronous input.
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Preliminary
STAC9708/11
Warm Reset - a warm reset will re-activate the AC-Link without altering the current STAC9708/11
register values. A warm reset is signaled by driving SYNC high for a minimum of 1us in the absence of
BIT_CLK.
Note: Within normal audio frames, SYNC is a synchronous input. However, in the absence
of BIT_CLK, SYNC is treated as an asynchronous input used in the generation of a warm
reset to the STAC9708/11.
4. STAC9708/11 MIXER
The STAC9708/11 mixer is designed to the AC'97 specification to manage the playback and record of all digital
and analog audio sources in the PC environment. These include:
•
•
•
•
•
•
System Audio: digital PCM input and output for business, games and multimedia
CD/DVD: analog CD/DVD-ROM Redbook audio with internal connections to Codec mixer
Mono microphone: choice of desktop mic, with programmable boost and gain
Speakerphone: use of system mic and speakers for telephone, DSVD, and video conferencing
Video: TV tuner or video capture card with internal connections to Codec mixer
AUX/synth: analog FM or wavetable synthesizer, or other internal source
Figure 11. STAC9708/11 Mixer Functional Diagram
PCM out
Surround
3D
D/A
vol
PCM out
Analog Audio
Sources
KEY
vol
mute
PC_BEEP
Phone
vol
mute
vol
mute
vol
mute
20dB
DAC OUT
mute
D/A
MIC1
MIC2
DAC
Volume
LINE IN
CD
vol
mute
vol
mute
Video
AUX
vol
mute
vol
mute -6 dB
Mono Analog
Stereo Analog
Digital
23
Σ
3D
-6 dB
M
Σ U
X
Σ
M
U
X
Master
Input
Volume
Master
Volume
LINE OUT
Mono
Volume
MONO OUT
A/D
A/D
PCM IN
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SigmaTel, Inc.
Preliminary
STAC9708/11
Table 7. Mixer Functional Connections
SOURCE
PC_Beep
PHONE
MIC1
MIC2
LINE_IN
CD
VIDEO
AUX
PCM out
LINE_OUT
DAC_OUT
MONO_OUT
PCM in
FUNCTION
PC beep pass thru
speakerphone or DLP in
desktop microphone
second microphone
external audio source
audio from CD-ROM
audio from TV tuner or video camera
upgrade synth or other external source
digital audio output from AC'97 Controller
stereo mix of all sources
surround stereo DAC output
mic or mix for speakerphone or DLP out
digital audio input to AC'97 Controller
24
CONNECTION
from PC beeper output
from telephony subsystem
from mic jack
from second mic jack
from line-in jack
cable from CD-ROM
cable from TV or VidCap card
internal connector
AC-Link
To output jack
To output jack
to telephony subsystem
AC-Link
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SigmaTel, Inc.
4.1
Preliminary
STAC9708/11
Mixer Input
The mixer provides recording and playback of any audio sources or output mix of all sources. The
STAC9708/11 supports the following input sources:
•
•
•
any mono or stereo source
mono or stereo mix of all sources
2-channel input w/mono output reference (mic + stereo mix)
Note: any unused input pins should have a capacitor (1 uF suggested) to ground.
4.2
Mixer Output
The mixer generates two distinct outputs:
•
a stereo mix of all sources for output to the LINE_OUT
•
a stereo mix of the surround DACs for output to the DAC_OUT
•
a mono, mic only or mix of all sources for MONO_OUT
* Note: Mono output of stereo mix is attenuated by -6 dB .
4.3 PC Beep Implementation
PC Beep is active on power up and defaults to an unmuted state. The user should mute this input
before using any other mixer input because the PC Beep input can contribute noise to the lineout during
normal operation.
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Preliminary
STAC9708/11
4.4 Programming Registers:
Table 8. Programming Registers
REG #
NAME
D15
D14
D13
00h
Reset
X
SE4
SE3
SE2
SE1
SE0
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
DE
FAULT
6940h
02h
Master Volume
Mute
X
X
ML4
ML3
ML2
ML1
ML0
X
X
X
MR4
MR3
MR2
MR1
MR0
8000h
Surround DAC Mute
Mixer Volume
06h
Master Volume Mute
Mono
0Ah PC_BEEP Volume Mute
X
X
GL4
GL3
GL2
GL1
GL0
X
X
X
GR4
GR3
GR2
GR1
GR0
8808h
X
X
X
X
X
X
X
X
X
X
MM4
MM3
MM2
MM1
MM0
8000h
0Ch
04h
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
X
X
PV3
PV2
PV1
PV0
X
0000h
Phone volume
Mute
X
X
X
X
X
X
X
X
X
X
GN4
GN3
GN2
GN1
GN0
8008h
0Eh
Mic Volume
Mute
X
X
X
X
X
X
X
X
20dB
X
GN4
GN3
GN2
GN1
GN0
8008h
10h
Line In Volume
Mute
X
X
GL4
GL3
GL2
GL1
GL0
X
X
X
GR4
GR3
GR2
GR1
GR0
8808h
12h
CD Volume
Mute
X
X
GL4
GL3
GL2
GL1
GL0
X
X
X
GR4
GR3
GR2
GR1
GR0
8808h
14h
Video Volume
Mute
X
X
GL4
GL3
GL2
GL1
GL0
X
X
X
GR4
GR3
GR2
GR1
GR0
8808h
AUX Volume
Mute
X
X
GL4
GL3
GL2
GL1
GL0
X
X
X
GR4
GR3
GR2
GR1
GR0
8808h
PCM Out Volume Mute
X
X
GL4
GL3
GL2
GL1
GL0
X
X
X
GR4
GR3
GR2
GR1
GR0
8808h
16h
18h
1Ah
Record Select
X
X
X
X
X
SL2
SL1
SL0
X
X
X
X
X
SR2
SR1
SR0
0000h
1Ch
Record Gain
Mute
X
X
X
GL3
GL2
GL1
GL0
X
X
X
X
GR3
GR2
GR1
GR0
8000h
20h
General Purpose
X
X
3D
X
X
X
MIX
MS
LPBK
X
X
X
X
X
X
X
0000h
22h
3D Control
X
X
X
X
X
X
X
X
X
X
X
X
DPR1 DPR0
DP1
DP0
0000h
26h
Powerdown
Ctrl/Stat
Extended Audio
ID
Extended Audio
Status Control
Surround DAC
Master Volume
Analog Special
EAPD
PR6
PR5
PR4
PR3
PR2
PR1
PR0
X
X
X
X
REF
ANL
DAC
ADC
000Fh
ID1
ID0
X
X
X
X
X
X
SDAC
X
X
X
X
X
X
X
0000h
X
X
X
X
X
X
X
X
X
X
X
X
X
0000h
Mute
Left
X
X
X
ML2
ML1
X
X
MR4
MR3
MR2
MR1
MR0
8080h
X
X
X
X
X
X
SDAC
Ready
ML0 Mute
Right
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ADC
-6dB
MC0
0000h
7Ch
Multi-Channel
Selection
Vendor ID1
DAC
-6dB
MC1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
8384h
7Eh
Vendor ID2
0
1
1
1
0
1
1
0
0
0
0
0
1
0
0
0
7608h
28h
2Ah
38h
6Ch
74h
PWD
X
SDAC
ML4 ML3
0000h
Notes:
1. All registers not shown and bits containing an X are reserved.
2. Any reserved bits, marked X, can be written to but are don’t care upon read back.
3. PC_BEEP default to 0000h, mute off.
4. If optional bits D13, D5 of register 02h or D5 of register 06h are set to 1, then the corresponding attenuation
is set to 46dB and the register reads will produce 1Fh as a value for this attenuation/gain block.
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Preliminary
STAC9708/11
4.4.1 Reset Register (Index 00h)
Writing any value to this register performs a register reset, which causes all registers to revert to their
default values. Reading this register returns the ID code of the part.
4.4.2 Play Master Volume Registers (Index 02h, 38h, and 06h)
These registers manage the output signal volumes. Register 02h controls the stereo LINE_OUT master
volume (both right and left channels), register 04h controls the surround stereo DAC_OUT volume, and
register 06h controls the mono volume output. Each step corresponds to 1.5 dB. The MSB of the
register is the mute bit. When this bit is set to 1 the level for that channel is set at -∞ dB. ML5
through ML0 is for left channel level, MR5 through MR0 is for the right channel and MM5 through
MM0 is for the mono out channel.
The default value is 8000h for registers 02h and 06h(8080h for register 38h), which corresponds to 0
dB attenuation with mute on.
Table 9. Play Master Volume Register
MUTE
Mx5…Mx0
FUNCTION
RANGE
0
00 0000
0dB Attenuation
Req.
0
01 1111
46.5 Attenuation
Req.
1
xx xxxx
∞ dB Attenuation
Req.
4.4.3 PC Beep Register (Index 0Ah)
This register controls the level for the PC Beep input. Each step corresponds to approximately 3 dB of
attenuation. The MSB of the register is the mute bit. When this bit is set to 1 the level for that
channel is set at -∞ dB. PC_BEEP supports motherboard implementations. The intention of routing
PC_BEEP through the STAC9708/11 mixer is to eliminate the requirement for an onboard speaker by
guaranteeing a connection to speakers connected via the output jack. In order for this to be viable the
PC_BEEP signal needs to reach the output jack at all times. NOTE: the PC_BEEP is recommended to
be routed to L & R Line outputs even when the STAC9708/11 is in a RESET state. This is so that
Power On Self Test (POST) codes can be heard by the user in case of a hardware problem with the PC.
For further PC_BEEP implementation details please refer to the AC'97 Technical FAQ sheet. The
default value can be 0000h or 8000h, which corresponds to 0 dB attenuation with mute off or on.
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Preliminary
STAC9708/11
Table 10. PC_BEEP Register
MUTE
PV3…PV0
FUNCTION
0
0000
0 dB Attenuation
0
1111
45 dB Attenuation
1
xxxx
∞ dB Attenuation
4.4.4 Analog Mixer Input Gain Registers (Index 0Ch - 18h, 04h)
These registers control the gain/attenuation for each of the analog inputs. Each step corresponds to
approximately 1.5 dB. The MSB of the register is the mute bit. When this bit is set to 1 the level for
that channel is set at -∞ dB. Register 0Eh (Mic Volume Register) has an extra bit that is for a 20dB
boost. When bit 6 is set to 1, the 20 dB boost is on. The default value is 8008, which corresponds to 0
dB gain with mute on. The default value for the mono registers is 8008h, which corresponds to 0dB
gain with mute on. The default value for stereo registers is 8808h, which corresponds to 0 dB gain with
mute on.
Table 11. Analog Mixer Input Gain Register
MUTE
Gx4…Gx0
FUNCTION
0
00000
+12 dB gain
0
01000
0 dB gain
0
11111
-34.5 dB gain
1
xxxxx
-∞ dB gain
4.4.5 Record Select Control Register (Index 1Ah)
Used to select the record source independently for right and left. The default value is 0000h, which
corresponds to Mic in.
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Preliminary
STAC9708/11
Table 12, 13. Record Select Control Registers
SR2…SR0
RIGHT RECORD SOURCE
0
Mic
1
CD In (right)
2
Video In (right)
3
Aux In (right)
4
Line In (right)
5
Stereo Mix (right)
6
Mono Mix
7
Phone
SL2…SL0
LEFT RECORD SOURCE
0
Mic
1
CD In (L)
2
Video In (L)
3
Aux In (L)
4
Line In (L)
5
Stereo Mix (L)
6
Mono Mix
7
Phone
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Preliminary
STAC9708/11
4.4.6 Record Gain Registers (Index 1Ch)
The 1Ch register adjusts the stereo input record gain. Each step corresponds to 1.5 dB. 22.5 dB
corresponds to 0F0Fh and 000Fh respectively. The MSB of the register is the mute bit. When this bit
is set to 1, the level for that channel(s) is set at -∞ dB.
The default value is 8000h, which corresponds to 0 dB gain with mute on.
Table 14. Record Gain Registers
MUTE
Gx3… Gx0
FUNCTION
0
1111
+22.5 dB gain
0
0000
0 dB gain
1
xxxx
-∞ gain
4.4.7 General Purpose Register (Index 20h)
This register is used to control some miscellaneous functions. Below is a summary of each bit and its
function. The MS bit controls the mic selector. The LPBK bit enables loopback of the ADC output to
the DAC input without involving the AC-Link, allowing for full system performance measurements.
Table 15. General Purpose Register
BIT
FUNCTION
3D
3D Stereo Enhancement on/off 1 = on
MIX
Mono output select 0 = Mix, 1= Mic
MS
Mic select 0 = Mic1, 1 = Mic2
LPBK
ADC/DAC loopback mode
4.4.8 3D Control Register (Index 22h)
This register is used to control the 3D stereo enhancement function, Sigmatel Surround 3D (SS3D),
built into the AC'97 component. Note that register bits, DP1-DP0 and DPR1-DPR0 are used to control
the separation ratios in the 3D control for both LINE_OUT and DAC_OUT respectively. This allows
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for independent control of the stereo enhancement between LINE_OUT and DAC_OUT. SS3D provides
for a wider soundstage extending beyond the normal 2-speaker arrangement. Note that the 3D bit in the
general purpose register (20h) must be set to 1 to enable SS3D functionality and for the bits in 22h to
take effect.
Table 16, 17. 3D Control Registers
DP1, DP0
LINE_OUT
SEPARATION
RATIO
00
0 (Off)
01
3 (Low)
10
4.5 (Med)
11
6 (High)
DPR1, DPR0
DAC_OUT
SEPARATION
RATIO
00
0 (Off)
01
3 (Low)
10
4.5 (Med)
11
6 (High)
The three separation ratios are implemented as shown above. The separation ratio defines a series of
equations that determine the amount of depth difference (High, Medium, and Low) perceived during
two-channel playback. The ratios provide for options to narrow or widen the soundstage.
4.4.9 Multi-Channel Programming Register (Index 74h)
This read/write register is used to program the various options for multi-channel configurations. Only
the two LSBs are used (MC0 and MC1), and they define which AC-Link slot data is supplied to the
four audio DACs on the STAC9708/11. PCM2 in the table below is the surround stereo DAC, which
drives the DAC_OUT pins. The purpose of using slot 10 and 11 in the final configuration is to allow the
possibility of an eight channel architecture using two STAC9708 devices in the multi-codec
configuration. Also see “Multiple Codec Support” discussion for information on the use of external pins
CID1 and CID0.
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Table 18. Multi-Channel Programming Register
MC1, MC0
PCM OUT
PCM OUT
PCM2
PCM2
LEFT
RIGHT
LEFT
RIGHT
0, 0
Slot 3
Slot 4
Slot 7
Slot 8
0, 1
Slot 7
Slot 8
Slot 6
Slot 9
1, 0
Slot 6
Slot 9
Slot 7
Slot 8
1, 1
Slot 6
Slot 9
Slot 10
Slot 11
4.4.10 Powerdown Control/Status Register (Index 26h)
This read/write register is used to program powerdown states and monitor subsystem readiness. The
lower half of this register is read only status, a “1” indicating that the subsection is “ready”. Ready is
defined as the subsection’s ability to perform in its nominal state. When this register is written, the bit
values that come in on AC-Link will have no effect on read only bits 0-7. Bit 15,
When the AC-Link “Codec Ready” indicator bit (SDATA_IN slot 0, bit 15) is a 1, it indicates that the
AC-Link and AC'97 control and status registers are in a fully operational state. The AC'97 controller
must further probe this Powerdown Control/Status Register to determine exactly which subsections, if
any are ready.
Table 19. Powerdown Status Registers
BIT
FUNCTION
EAPD
External Amplifier Power Down
REF
VREF’s up to nominal level
ANL
Analog mixers, etc. ready
DAC
DAC section ready to playback data
ADC
ADC section ready to playback data
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4.4.10.1 External Amplifier Power Down Control
The EAPD bit 15 of the Powerdown Control/Status Register (Index 26h) directly controls the output of
the EAPD output, pin 45, and produces a logical “1” when this bit is set to logic high. This function is
used to control an external audio amplifier power down. EAPD = 0 places approximately 0V on the
output pin, enabling an external audio amplifier. EAPD = 1 places approximately DVdd on the output
pin, disabling the external audio amplifier. Audio amplifiers that operate with reverse polarity will
likely require an external inverter to maintain software driver compatibility.
4.4.11 Extended Audio ID Register (Index 28)
The Extended Audio ID register is a read only register used to communicate information to the digital
controller on two functions. ID1 and ID0 echo the configuration of the codec as defined by the
programming of pins 47 and 48 externally. “00” returned defines the codec as the primary codec, while
any other code identifies the codec as one of three secondary codec possibilities. SDAC=1 tells the
controller that the STAC9708 is a multi-channel codec as defined by the Intel spec.
4.4.12 Extended Audio Status Register (Index 2Ah)
The Extended Audio Status Control register contains two active bits for powerdown and status of the
surround DACs. PWD is a read/write bit which is used to powerdown the surround DACs, and SDAC a
read only bit to tell the controller when the surround DACs are ready to receive data.
4.4.13 Analog Special Register (Index 6Ch)
The Analog Special Register has two read/write bits used to control two functions specific to the
STAC9708. DAC –6dB is used to program the DAC outputs to a –6dB signal level relative to the value
of gain already programmed. Similarly, ADC –6dB attenuates any signal input to the ADC by 6dB. This
second function is very useful in applications with greater than 1Vrms input levels, as is the case with
many CDROMs.
4.4.14 Vendor ID1 and ID2 (Index 7Ch and 7Eh)
These two registers contain four 8-bit ID codes. The first three codes have been assigned by Microsoft
using their Plug and Play Vendor ID methodology. The fourth code is a SigmaTel, Inc. assigned code
identifying the STAC9708/11. The ID1 register (index 7Ch) contains the value 8384h, which is the
first (83h) and second (84h) characters of the Microsoft ID code. The ID2 register (index 7Eh)
contains the value 7608h, which is the third (76h) of the Microsoft ID code, and 08h which is the
STAC9708/11 ID code.
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NOTE: The lower half of the Vendor ID2 register (index 7Eh) currently contains the value 08h
identifying the STAC9708/11. This value can be used by the audio driver, or miniport driver in the
case of WIN98, to adjust software functionality to match the feature-set of the STAC9708/11. This
portion of the register will likely contain different values if the software profile of the STAC9708/11
changes, as in the case of silicon level device modifications. This will allow the software driver to
identify any required operational differences between the existing STAC9708/11 and any future
versions.
5. LOW POWER MODES
The STAC9708/11 is capable of operating at reduced power when no activity is required. The state of power
down is controlled by the Powerdown Register (26h). There are 7 commands of separate power down. The
power down options are listed in Table 18. The first three bits , PR0..PR2, can be used individually or in
combination with each other, and control power distribution to the ADC’s, DAC’s and Mixer. The last analog
power control bit, PR3, affects analog bias and reference voltages, and can only be used in combination with PR1,
PR2, and PR3. PR3 essentially removes power from all analog sections of the codec, and is generally only
asserted when the codec will not be needed for long periods. PR0 and PR1 control the PCM ADC’s and DAC’s
only. PR2 and PR3 do not need to be "set" before a PR4, but PR0 and PR1 must be "set" before PR4.
Table 20. Low Power Modes
GRP BITS
FUNCTION
PR0
PCM in ADC’s & Input Mux Powerdown
PR1
PCM out DACs Powerdown
PR2
Analog Mixer powerdown (Vref still on)
PR3
Analog Mixer powerdown (Vref off)
PR4
Digital Interface (AC-Link) powerdown (extnl clk off)
PR5
Internal Clk disable
PR6
Not implemented
PRJ
Powerdown Surround DACs
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Figure 12. Example of STAC9708/11 Powerdown/Powerup flow
PR0=1
PR1=1
ADCs off
PR0
Normal
PR2=1
DACs off
PR1
Analog off
PR2 or PR3
PR2=0
&
ANL=1
PR1=0
&
DAC=1
PR0=0
&
ADC=1
Ready =1
PR4=1
Digital I/F off
PR4
Shut off
Coda-link
Warm Reset
Default
Cold Reset
The above figure illustrates one example procedure to do a complete powerdown of STAC9708/11. From normal
operation, sequential writes to the Powerdown Register are performed to power down STAC9708/11 a piece at a
time. After everything has been shut off, a final write (of PR4) can be executed to shut down the AC-Link. The
part will remain in sleep mode with all its registers holding their static values. To wake up, the AC'97 controller
will send an extended pulse on the sync line, issuing a warm reset. This will restart the AC-Link (resetting PR4
to zero). The STAC9708/11 can also be woken up with a cold reset. A cold reset will reset all of the registers to
their default states. When a section is powered back on, the Powerdown Control/Status register (index 26h)
should be read to verify that the section is ready (stable) before attempting any operation that requires it.
Figure 13. STAC9708/11 Powerdown/Powerup flow with analog still alive
PR0=1
PR1=1
ADCs off
PR0
Normal
PR0=0
&
ADC=1
PR4=1
DACs off
PR1
PR1=0
&
DAC=1
Digital I/F
off PR4
Shut off
Coda-link
Warm Reset
The above figure illustrates a state when all the mixers should work with the static volume settings that are
contained in their associated registers. This configuration can be used when playing a CD (or external LINE_IN
source) through STAC9708/11 to the speakers, while most of the system in low power mode. The procedure for
this follows the previous except that the analog mixer is never shut down.
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6. MULTIPLE CODEC SUPPORT
The STAC9708/11 provides support for the multi-codec option according to the Intel AC'97, rev 2.1 specification.
By definition there can be only one Primary Codec (Codec ID 00) and up to three Secondary Codecs (Codec IDs
01,10, and 11). The Codec ID functions as a chip select. Secondary devices therefore have completely
orthogonal register sets; each is individually accessible and they do not share registers.
6.1
Primary/Secondary Codec Selection
In a multi-codec environment the codec ID is provided by external programming of pins 45 and 46 (CID0 and
CID1). The CID pin electrical function is logically inverted from the codec ID designation. The corresponding
pin state and its associated codec ID are listed in the "Codec ID Selection" table. Also see slot assignment
discussion, “Multi-Channel Programming Register (Index 74)”.
Table 21. Codec ID Selection
CID1 STATE
+5V or floating
+5V or floating
0V
0V
CID0 STATE
+5V or floating
0V
+5V or floating
0V
CODEC ID
00
01
10
11
CODEC STATUS
Primary
Secondary
Secondary
Secondary
6.1.1
Primary Codec Operation
As a Primary device the STAC9708/11 is completely compatible with existing AC'97 definitions and
extensions. Primary Codec registers are accessed exactly as defined in the AC'97 Component Specification
and AC'97 Extensions. The STAC9708/11 operates as Primary by default, and the external ID pins (47 and
48), have internal pull-ups so that these pins may be left as no-connects for primary operation.
When used as the Primary Codec, the STAC9708/11 generates the master AC-Link BIT_CLK for both the
AC'97 Digital Controller and any Secondary Codecs. The STAC9708/11 can support up to 4, 10 KΩ 50 pF
loads on the BIT_CLK. This is to insure that up to 4 Codec implementations will not load down the clock
output.
6.1.2 Secondary Codec Operation
When the STAC9708/11 is configured as a Secondary device the BIT_CLK pin is configured as an input at
power up. Using the BIT_CLK provided by the Primary Codec insures that everything on the AC-Link will
be synchronous. As a Secondary device it can be defined as Codec ID 01, 10, or 11 in the two-bit field(s) of
the Extended Audio and/or Extended Modem ID Register(s).
6.2
Secondary Codec Register Access Definitions
The AC'97 Digital Controller can independently access Primary and Secondary Codec registers by using a 2-bit
Codec ID field (chip select) which is defined as the LSBs of Output Slot 0. For Secondary Codec access, the
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AC'97 Digital Controller must invalidate the tag bits for Slot 1 and 2 Command Address and Data (Slot 0, bits 14
and 13) and place a non-zero value (01, 10, or 11) into the Codec ID field (Slot 0, bits 1 and 0).
As a Secondary Codec, the STAC9708/11 will disregard the Command Address and Command Data (Slot 0, bits
14 and 13) tag bits when it sees a 2-bit Codec ID value (Slot 0, bits 1 and 0) that matches its configuration. In a
sense the Secondary Codec ID field functions as an alternative Valid Command Address (for Secondary reads and
writes) and Command Data (for Secondary writes) tag indicator.
Secondary Codecs must monitor the Frame Valid bit, and ignore the frame (regardless of the state of the
Secondary Codec ID bits) if it is not valid. AC'97 Digital Controllers should set the frame valid bit for a frame
with a secondary register access, even if no other bits in the output tag slot except the Secondary Codec ID bits
are set.
This method is designed to be backward compatible with existing AC'97 controllers and Codecs. There is no
change to output Slot 1 or 2 definitions.
Table 22. Secondary Codec Register Access Slot 0 Bit Definitions
Output Tag Slot (16-bits)
Bit
Description
15
Frame Valid
14
Slot 1 Valid Command Address bit (†Primary Codec only)
13
Slot 2 Valid Command Data bit (†Primary Codec only)
12-3
Slot 3-12 Valid bits as defined by AC'97
2
Reserved
(Set to “0”)
†1-0
2-bit Codec ID field
(00 reserved for Primary; 01, 10, 11 indicate Secondary)
† New definitions for Secondary Codec Register Access
7. TESTABILITY
The STAC9708/11 has two test modes. One is for ATE in-circuit test and the other is restricted for SigmaTel’s
internal use. STAC9708/11 enters the ATE in circuit test mode if SDATA_OUT is sampled high at the trailing
edge of RESET#. Once in the ATE test mode, the digital AC-Link outputs (BIT_CLK and SDATA_IN) are
driven to a high impedance state. This allows ATE in-circuit testing of the AC'97 controller. This case will
never occur during standard operating conditions. Once either of the two test modes have been entered, the
STAC9704/7 must be issued another rest with all AC-link signals held low to return to the normal operating
mode.
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8. EXTENDED CODEC FUNCTIONALITY
8.1 Anti-Pop Circuitry
The STAC9708/11 provides an integrated output signal (APOP on pin 34) to aid in low-component-count antipop implementations. An audible speaker "pop" can occur when the main power is applied to, or removed from,
the codec or audio output amplifier. In ac coupled systems, the speaker sided of the ac coupling capacitor is
shunted to ground through a transistor or FET; this prevents audible pops when the system is powering on and
off. A +10 uF capacitor on CAP1 provides a delay to hold-off power to the output stages on power up. A +22 uF
capacitor provides reserve power to sustain the output shunting action until the power has been fully removed on
power down. APOP is active logic high during shunting operations; APOP is at logic low during normal
operations.
9. AC TIMING CHARACTERISTICS
(Tambient = 25 °C, AVdd = DVdd = 5.0V or 3.3V ± 5%, AVss=DVss+0V; 50pF external load)
9.1 Cold Reset
Figure 14. Cold Reset
Trst2clk
Tres_low
RESET#
BIT_CLK
Table 23. Cold Reset
PARAMETER
RESET# active low pulse width
RESET# inactive to BIT_CLK startup delay
SYMBOL
Tres_low
Trst2clk
MIN
1.0
162.8
TYP
-
MAX
-
UNITS
us
ns
# denotes active low.
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9.2 Warm Reset
Figure 15. Warm Reset
Tsync_high
Tsync_2clk
SYNC
BIT_CLK
Table 24. Warm Reset
PARAMETER
SYNC active high pulse width
SYNC inactive to BIT_CLK startup delay
SYMBOL
Tsync_high
Tsync2clk
39
MIN
162.8
TYP
1.3
-
MAX
-
UNITS
us
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9.3 Clocks
Figure 16. Clocks
Tclk_low
BIT_CLK
Tclk_high
Tclk_period
Tsync_low
SYNC
Tsync_high
Tsync_period
Table 25. Clocks
PARAMETER
BIT_CLK frequency
BIT_CLK period
BIT_CLK output jitter
BLT_CLK high pulsewidth (note 1)
BIT_CLK low pulse width (note 1)
SYNC frequency
SYNC period
SYNC high pulse width
SYNC low_pulse width
SYMBOL
Tclk_period
Tclk_high
Tclk_low
Tsync_period
Tsync_high
Tsync_low
MIN
32.56
32.56
-
TYP
12.288
81.4
40.7
40.7
48.0
20.8
1.3
19.5
MAX
750
48.84
48.84
-
UNITS
MHz
ns
ps
ns
ns
kHz
us
us
us
Notes: 1) Worst case duty cycle restricted to 40/60.
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9.4 Data Setup and Hold
STAC9708/11
(50pF external load)
Figure 17. Data Setup and Hold
Tsetup
BIT_CLK
SDATA_IN
SDATA_OUT
Thold
SYNC
Thold
Tsetup
Table 26. Data Setup and Hold
PARAMETER
Setup to falling edge of BIT_CLK
Hold from falling edge of BIT_CLK
SYMBOL
Tsetup
Thold
MIN
15.0
5.0
TYP
-
MAX
-
UNITS
ns
ns
Note 1: Setup and hold time parameters for SDATA_IN are with respect to the AC'97 controller.
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9.5 Signal Rise and Fall Times - (50pF external load; from 10% to 90% of Vdd)
Figure 18. Signal Rise and Fall Times
BIT_CLK
Triseclk
Tfallclk
Trisedin
Tfalldin
SDATA_IN
Table 27. Signal Rise and Fall Times
PARAMETER
BIT_CLK rise time
BIT_CLK fall time
SDATA_IN rise time
SDATA_IN fall time
SYMBOL
Triseclk
Tfallclk
Trisedin
Tfalldin
42
MIN
2
2
2
2
TYP
-
MAX
6
6
6
6
UNITS
ns
ns
ns
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9.6 AC-Link Low Power Mode Timing
Figure 19. AC-Link Low Power Mode Timing
Slot 1
Slot 2
Write to
0x20
Data
PR4
SYNC
BIT_CLK
SDATA_OUT
Don't care
Ts2_pdown
SDATA_IN
Note: BIT_CLK not to scale
Table 28. AC-Link Low Power Mode Timing
PARAMETER
End of Slot 2 to BIT_CLK, SDATA_IN low
SYMBOL
Ts2_pdown
43
MIN
-
TYP
-
MAX
1.0
UNITS
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9.7 ATE Test Mode
Figure 20. ATE Test Mode
RESET#
SDATA_OUT
Tsetup2rst
Hi-Z
SDATA_IN, BIT_CLK
Toff
Table 29. ATE Test Mode
PARAMETER
Setup to trailing edge of RESET#
(also applies to SYNC)
Rising edge of RESET# to Hi-Z delay
SYMBOL
Tsetup2rst
MIN
15.0
TYP
-
MAX
-
UNITS
ns
Toff
-
-
25.0
ns
Notes:
1.
2.
All AC-Link signals are normally low through the trailing edge of RESET#.
Bringing
SDATA_OUT high for the trailing edge of RESET# causes STAC9708/11’s AC-Link outputs to go
high impedance which is suitable for ATE in circuit testing.
Once either of the two test modes have been entered, the STAC9708/11 must be issued another
RESET# with all AC-Link signals low to return to the normal operating mode.
# denotes active low.
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10. ELECTRICAL SPECIFICATIONS:
10.1 Absolute Maximum Ratings:
Voltage on any pin relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
Output Current per Pin
Vss - 0.3V TO Vdd + 0.3V
0 oC TO 70 o C
-55 oC TO +125 o C
o
260 C FOR 10 SECONDS
± 4 mA except Vrefout = ± 5mA
10.2 Recommended Operating Conditions
Table 30. Operating Conditions
PARAMETER
Power Supplies
+ 3.3V Digital
+ 5V Digital
+ 5V Analog
+ 3.3V Analog
Ambient Temperature
MIN
TYP
MAX UNITS
3.135
4.75
4.75
3.135
3.3
5
5
3.3
3.435
5.25
5.25
3.435
V
V
V
V
0
-
70
oC
SigmaTel reserves the right to change specifications without notice.
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10.3 Power Consumption
Table 31. Power Consumption
PARAMETER
Digital Supply Current
MIN
TYP
+ 5V Digital
+ 3.3V Digital
+ 5V Analog
+ 3.3V Analog
Analog Supply Current
Power Down Status
PR0 +5V Analog Supply Current
PR1 +5V Analog Supply Current
PRJ +5V Analog Supply Current
PR2 +5V Analog Supply Current
PR3 +5V Analog Supply Current
PR4 +3.3V Digital Supply Current
PR4 +5V Digital Supply Current
PR5 No effect
MAX
UNITS
55
35
80
70
mA
mA
mA
mA
68
54
40
30
0.1
0.1
0.1
mA
mA
mA
mA
mA
mA
mA
(Tambient = 25 oC, DVdd = 5.0V or 3.3V ± 5%,
10.4 AC-Link Static Digital Specifications
AVss=DVss=0V; 50pF external load)
Table 32. AC-Link Static Specifications
PARAMETER
SYMBOL
MIN
Input Voltage Range
Vin
-0.30
Low level input range
Vil
-
High level input voltage
Vih
High level output voltage
Low level output voltage
MAX
UNITS
DVdd + 0.30
V
-
0.30xDVdd
V
0.40xDVdd
-
-
V
Voh
0.50xDVdd
-
-
V
Vol
-
-
Input Leakage Current (AC-Link inputs)
-
-10
-
10
uA
Output Leakage Current (Hi-Z’d AC-Link outputs)
-
-10
-
10
uA
Output buffer drive current
-
-
4
46
TYP
0.2xDVdd
V
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10.5 STAC9708 Analog Performance Characteristics (Tambient = 25 oC, AVdd = 5.0V ± 5%,
DVdd = 3.3V ± 5%, AVss=DVss=0V; 1 kHz input sine wave; Sample Frequency = 48 kHz; 0 dB = 1 Vrms,
10KΩ/50pF load, Testbench Characterization BW: 20 Hz – 20 kHz, 0 dB settings on all gain stages)
Table 33. Analog Performance Characteristics
PARAMETER
MIN
TYP
MAX
UNITS
-
1.0
0.1
-
Vrms
-
1.0
-
Vrms
Analog S/N:
CD to LINE_OUT 5V
Other to LINE_OUT 5V
90
-
98
98
-
dB
Analog Frequency Response2
20
-
20,000
Hz
85
75
96
86
-
dB
20
-
0.02
19,200
%
Hz
19,200
-
28,800
Hz
28,800
-
∞
Hz
+85
-
−
dB
Out-of-Band Rejection
-
+40
−
dB
Group Delay
-
-
1
ms
Power Supply Rejection Ratio (1kHz)
-
+40
−
dB
Crosstalk between Input channels
-
-
-70
dB
Spurious Tone Rejection
-
+100
−
dB
Attenuation, Gain Step Size
-
1.5
−
dB
Input Impedance
10
-
−
KΩ
Input Capacitance
-
15
−
pF
Vrefout
-
0.41 x AVdd
−
V
Full Scale Input Voltage:
Line Inputs
Mic Inputs1
Full Scale Output Voltage:
Line Output 5V
3
Digital S/N
D/A 5V
A/D 5V
Total Harmonic Distortion:
Line Output4
D/A & A/D Frequency Response5
Transition Band
Stop Band
6
Stop Band Rejection
7
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Interchannel Gain Mismatch ADC
Interchannel Gain Mismatch DAC
-
Gain Drift
100
DAC Offset Voltage
10
Deviation from Linear Phase
External Load Impedance
10
Mute Attenuation (Vrms input)
90
STAC9708/11
0.5
dB
0.5
dB
ppm/deg. C
50
mV
1
degree
K ohm
96
dB
Notes:
1. With +20 dB Boost on, 1.0Vrms with Boost off
2. ± 1 dB limits
3. The ratio of the rms output level with 1 kHz full scale input to the rms
output level with all zeros into the digital input. Measured “A weighted”
over a 20 Hz to a 20 kHz bandwidth. (AES17-1991 Idle Channel Noise or
EIAJ CP-307 Signal-to-noise Ratio).
4. 0 dB gain, 20 kHz BW, 48 kHz Sample Frequency
5. ± 0.25dB limits
6. Stop Band rejection determines filter requirements. Out-of-Band rejection
determines audible noise.
7. The integrated Out-of-Band noise generated by the DAC process, during
normal PCM audio playback, over a bandwidth 28.8 to 100 kHz, with
respect to a 1 Vrms DAC output.
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(Tambient = 25 oC, AVdd = DVdd =
3.3V ± 5%, AVss=DVss=0V; 1 kHz input sine wave; Sample Frequency = 48 kHz; 0 dB = 1 Vrms, 10KΩ/50pF
load, Testbench Characterization BW: 20 Hz – 20 kHz, 0 dB settings on all gain stages)
10.6 STAC9711 Analog Performance Characteristics
Table 34. Analog Performance Characteristics
PARAMETER
Full Scale Output Voltage:
Line Inputs to line output 3.3V
Line Inputs to LINE_OUT 3.3V @ Line In =
1 Vrms and @ Gain setting of -6 dB
Line Inputs to LINE_OUT 3.3V @ Line In =
0.5 Vrms and @ gain setting of 0dB
PCM to LINE_OUT 3.3V @ full scale PCM input
@PCM gain setting of 0dB
PCM to Line Output 3.3V
MIC Inputs to LINE_OUT 3.3V @ MIC In
= 1 Vrms and @ gain setting of 0dB
Analog S/N:
CD to LINE_OUT 3.3V
Other to LINE_OUT 3.3V
Analog Frequency Response2
MIN
TYP
MAX
UNITS
-
0.5
-
Vrms
-
0.5
Vrms
0.5
Vrms
0.5
Vrms
0.5
Vrms
20
90
90
-
20,000
85
75
90
85
-
20
-
0.02
19,200
%
Hz
19,200
-
28,800
Hz
28,800
-
∞
Hz
+85
-
−
dB
Out-of-Band Rejection
-
+40
−
dB
Group Delay
-
-
1
ms
Power Supply Rejection Ratio (1kHz)
-
+40
−
dB
Crosstalk between Input channels
-
-
-70
dB
Hz
3
Digital S/N
D/A 3.3V
A/D 3.3V
Total Harmonic Distortion:
Line Output4
D/A & A/D Frequency Response5
Transition Band
Stop Band
6
Stop Band Rejection
7
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Spurious Tone Rejection
-
+100
−
dB
Attenuation, Gain Step Size
-
1.5
−
dB
Input Impedance
10
-
−
KΩ
Input Capacitance
-
15
−
pF
Vrefout
-
0.41 x
AVdd
−
V
0.5
dB
0.5
dB
Interchannel Gain Mismatch ADC
Interchannel Gain Mismatch DAC
-
Gain Drift
100
DAC Offset Voltage
10
Deviation from Linear Phase
External Load Impedance
10
Mute Attenuation (0 dB)
90
ppm/ oC
50
mV
1
degree
KΩ
96
dB
Notes:
1. With +20 dB Boost on, 1.0Vrms with Boost off
2. ± 1 dB limits
3. The ratio of the rms output level with 1 kHz full scale input to the rms
output level with all zeros into the digital input. Measured “A weighted”
over a 20 Hz to a 20 kHz bandwidth. (AES17-1991 Idle Channel Noise or
EIAJ CP-307 Signal-to-noise Ratio).
4. 0 dB gain, 20 kHz BW, 48 kHz Sample Frequency
5. ± 0.25dB limits
6. Stop Band rejection determines filter requirements. Out-of-Band rejection
determines audible noise.
7. The integrated Out-of-Band noise generated by the DAC process, during
normal PCM audio playback, over a bandwidth 28.8 to 100 kHz, with
respect to a 1 Vrms DAC output.
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Appendix A
SPLIT INDEPENDENT POWER SUPPLY OPERATION
In PC applications, one power supply input to the STAC9708/11 may be derived from a supply regulator (as
shown in Figure 3) and the other directly from the PCI power supply bus. When power is applied to the PC, the
regulated supply input to the IC will be applied some time delay after the PCI power supply. Without proper onchip partitioning of the analog and digital circuitry, some manufacturer's codecs would be subject to on-chip SCR
type latch-up.
SigmaTel’s STAC9708/11 specifically allows power-up sequencing delays between the analog (AVddx) and
digital (VDddx) supply pins. These two power supplies can power-up independently and at different rates with
no adverse effects to the codec. The IC is designed with independent analog and digital circuitry that prevents
on-chip SCR type latch-up.
3.3V or 5V ± 5%
* AVdd must always be >= DVdd
REG
3.3V or 5V ± 5%
10uF
0.1uF
0.1uF
1uF
25
AVdd1
0.1uF
0.1uF
38
1
AVdd2
DVdd1
9
DVdd2
33pF
2
XTL_IN
12
P C _B E E P
24.576MHz
XTL_OUT
13
3
PHONE
33pF
5
SDATA_OUT
14
6
AUX_L
BIT_CLK
8
15
SDATA_IN
AUX_R
S igm a T e l
16
10
SYNC
VIDEO_L
11
RESET
S T A C 9 7 0 8 /11
17
VIDEO_R
45
CID0
18
46
CD_L
CID1
19
CD_GND
27
20
Vref
CD_R
10uF
0.1uF
21
28
MIC1
Vrefout
32
22
CAP2
MIC2
10uF
31
0.1uF
CAP1
23
LINE_IN_L
CAP3
10uF
33
22uF
24
LINE_IN_R
APOP
45
CID0
34
47
EAPD
46
35
CID1
LINE_OUT_L
560 - 1000pF
29
LINE_OUT_R
36
AFILT1
37
560 - 1000pF
MONO_OUT
30
AFILT2
AVss1
26
AVss2
42
DVss1
4
DVss2
7
DAC_OUT_L
39
DAC_OUT_R
41
** Teminate ground
plane as close to power
supply as possible
NOTE: Pins 31, 33, 34, 40
43, 44, and 48 are No Connects
Brd Analog Gnd
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Appendix B
+5.0V/+3.3V POWER SUPPLY OPERATION NOTES
The STAC9708 is capable of operating from a single 5V supply connected to both DVdd and AVdd. Even though
the STAC9708 has digital switching levels of 0.2Vdd to 0.5Vdd (See AC Link Electrical Characteristics in this
data book), we recommend that all digital interface signals to the AC-Link be 5V. If digital interface signals
below 5V are used, then appropriate level shifting circuitry must be provided to ensure adequate digital noise
immunity.
The STAC9708 can also operate from a 3.3V digital supply connected to DVdd while maintaining a 5V analog
supply on AVdd. On-chip level shifters ensure accurate logic transfers between the analog and digital portions of
the STAC9708. If digital interface signals above 3.3V are used (i.e. a +5V AC-Link interface), then appropriate
level shifting circuitry must be provided to ensure adequate digital noise immunity and to prevent on-chip ESD
protection diodes from turning on. (See Appendixes A concerning SPLIT INDEPENDENT POWER SUPPLY
OPERATION).
The STAC9711 must be run from a 3.3V supply connected to both DVdd and AVdd. If digital interface signals
above 3.3V are used (i.e. a +5V AC-Link interface), then appropriate level shifting circuitry must be provided to
ensure adequate digital noise immunity and to prevent on-ship ESD protection diodes from turning on.
*Always operate the STAC97xx digital supply from the same supply voltage as the digital controller
supply.
*All the analog inputs must be ac-coupled with a capacitor of 3.3 uF or greater. It is recommended that a
resistor of about 47KΩ
Ω be connected from the signal side of the capacitor to analog GND as shown below.
> 3.3 uF
SIGNAL
Analog Input
47K
*All the analog outputs must be ac-coupled. If an external amplifier is used, make sure that the input
impedance of the amplifier is at least 10KΩ
Ω and use an ac-coupling capacitor of 3.3 uF.
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- NOTES -
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- NOTES -
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- NOTES -
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For more information, please contact:
SigmaTel, Inc.
6101 W. Courtyard Dr., Bldg. 1, Suite 100
Austin, Texas 78730
Tel (512) 343-6636, Fax (512) 343-6199
email: [email protected]
Homepage: www.sigmatel.com
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