ATMEL T5750-6AQ

Features
• Integrated PLL Loop Filter
• ESD Protection also at ANT1/ANT2
(4 kV HBM/200 V MM; Except Pin 2: 4 kV HBM/100 V MM)
• High Output Power (5.5 dBm) with Low Supply Current (8.5 mA)
• Modulation Scheme ASK/FSK
•
•
•
•
•
•
•
•
– FSK Modulation is Achieved by Connecting an Additional Capacitor Between the
XTAL Load Capacitor and the Open Drain Output of the Modulating Microcontroller
Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply
Single Li-cell for Power Supply
Supply Voltage 2.0 V to 4.0 V in the Temperature Range of -40° C to 85° C/125° C
Package TSSOP8L
Single-ended Antenna Output with High Efficient Power Amplifier
CLK Output for Clocking the Microcontroller
One-chip Solution with Minimum External Circuitry
125° C Operation for Tire Pressure Systems
UHF ASK/FSK
Transmitter
T5750
Description
Preliminary
The T5750 is a PLL transmitter IC which has been developed for the demands of RF
low-cost transmission systems at data rates up to 32 kBaud. The transmitting
frequency range is 868 MHz to 928 MHz. It can be used in both FSK and ASK
systems.
Figure 1. System Block Diagram
UHF ASK/FSK
Remote control transmitter
1 Li cell
Keys
UHF ASK/FSK
Remote control receiver
T5750
Encoder
M44Cx9x
T5760/
T5761
Demod.
Control
1...3
µC
PLL
IF Amp
Antenna Antenna
XTO
VCO
Power
amp.
PLL
LNA
XTO
VCO
Rev. 4546B–RKE–07/04
Pin Configuration
Figure 2. Pinning TSSOP8L
CLK
PA_ENABLE
1
8
ENABLE
2
7
GND
T5750
ANT2
3
6
VS
ANT1
4
5
XTAL
Pin Description
Pin
Symbol
Function
Configuration
VS
1
CLK
Clock output signal for micro con roller
The clock output frequency is set by the
crystal to fXTAL/4
100
100
PA_ENABLE
2
PA_ENABLE
CLK
50k
Uref=1.1V
Switches on power amplifier, used for
ASK modulation
20 µA
ANT1
3
ANT2
Emitter of antenna output stage
4
ANT1
Open collector antenna output
ANT2
VS
1.5k
5
XTAL
Connection for crystal
VS
1.2k
XTAL
182 mA
6
7
VS
GND
8
ENABLE
Supply voltage
Ground
See ESD protection circuitry (see Figure 8 on page 8)
See ESD protection circuitry (see Figure 8 on page 8)
ENABLE
2
200k
Enable input
T5750 [Preliminary]
4546B–RKE–07/04
T5750 [Preliminary]
Figure 3. Block Diagram
T5750
Power up / down
CLK
1
ENABLE
f
8
4
f
64
PA_ENABLE
GND
7
2
PFD
CP
ANT2
VS
3
6
LF
ANT1
4
XTAL
VCO
PA
XTO
5
PLL
General Description
This fully integrated PLL transmitter allows particularly simple, low-cost RF miniature
transmitters to be assembled. The VCO is locked to 64 × fXTAL hence a 13.5672 MHz
crystal is needed for a 868.3 MHz transmitter and a 14.2969 MHz crystal for a 915 MHz
transmitter. All other PLL and VCO peripheral elements are integrated.
The XTO is a series resonance oscillator so that only one capacitor together with a
crystal connected in series to GND are needed as external elements.
The crystal oscillator together with the PLL needs typically <1 ms until the PLL is locked
and the CLK output is stable. There is a wait time of ≥ 4 ms must be used until the CLK
is used for the microcontroller and the PA is switched on.
The power amplifier is an open-collector output delivering a current pulse which is nearly
independent from the load impedance. The delivered output power is hence controllable
via the connected load impedance.
This output configuration enables a simple matching to any kind of antenna or to 50 Ω. A
high power efficiency of η= Pout/(IS,PA × VS) of 24% for the power amplifier at 868.3 MHz
results when an optimized load impedance of ZLoad = (166 + j226) Ω is used at 3 V supply voltage.
3
4546B–RKE–07/04
Functional
Description
If ENABLE = L and the PA_ENABLE = L, the circuit is in standby mode consuming only
a very small amount of current, so that a lithium cell used as power supply can work for
several years.
With ENABLE = H the XTO, PLL and the CLK driver are switched on. If PA_ENABLE
remains L only the PLL and the XTO is running and the CLK signal is delivered to the
microcontroller. The VCO locks to 64 times the XTO frequency.
With ENABLE = H and PA_ENABLE = H the PLL, XTO, CLK driver and the power
amplifier are on. With PA_ENABLE the power amplifier can be switched on and off,
which is used to perform the ASK modulation.
ASK Transmission
The T5750 is activated by ENABLE = H. PA_ENABLE must remain L for t ≥ 4 ms, then
the CLK signal can be taken to clock the microcontroller and the output power can be
modulated by means of Pin PA_ENABLE. After transmission PA_ENABLE is switched
to L and the microcontroller switches back to internal clocking. The T5750 is switched
back to standby mode with ENABLE = L.
FSK Transmission
The T5750 is activated by ENABLE = H. PA_ENABLE must remain L for t ≥ 4 ms, then
the CLK signal can be taken to clock the microcontroller and the power amplifier is
switched on with PA_ENABLE = H. The chip is then ready for FSK modulation. The
microcontroller starts to switch on and off the capacitor between the XTAL load capacitor and GND with an open-drain output port, thus changing the reference frequency of
the PLL. If the switch is closed, the output frequency is lower than if the switch is open.
After transmission PA_ENABLE is switched to L and the microcontroller switches back
to internal clocking. The T5750 is switched back to standby mode with ENABLE = L.
The accuracy of the frequency deviation with XTAL pulling method is about ±25% when
the following tolerances are considered.
Figure 4. Tolerances of Frequency Modulation
~
VS
CStray2
CStray1
XTAL
~
CM
LM
RS
C0
Crystal equivalent circuit
C4
C5
CSwitch
Using C4 = 9.2 pF ±2%, C5 = 6.8 pF ±5%, a switch port with CSwitch = 3 pF ±10%, stray
capacitances on each side of the crystal of C Stray1 = C Stray2 = 1 pF ±10%, a parallel
capacitance of the crystal of C0 = 3.2 pF ±10% and a crystal with CM = 13 fF ±10%, an
FSK deviation of ±21.5 kHz typical with worst case tolerances of ±16.8 kHz to
±28.0 kHz results.
CLK Output
An output CLK signal is provided for a connected microcontroller, the delivered signal is
CMOS compatible if the load capacitance is lower than 10 pF.
Clock Pulse Take-over
The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel’s
M4xCx9x has the special feature of starting with an integrated RC-oscillator to switch on
the T5750 with ENABLE = H, and after 4 ms to assume the clock signal of the transmission IC, so that the message can be sent with crystal accuracy.
4
T5750 [Preliminary]
4546B–RKE–07/04
T5750 [Preliminary]
Output Matching and Power
Setting
The output power is set by the load impedance of the antenna. The maximum output
power is achieved with a load impedance of ZLoad,opt = (166 + j226) Ω at 868.3 MHz.
There must be a low resistive path to VS to deliver the DC current.
The delivered current pulse of the power amplifier is 7.7 mA and the maximum output
power is delivered to a resistive load of 475 Ω if the 0.53 pF output capacitance of the
power amplifier is compensated by the load impedance.
An optimum load impedance of:
ZLoad = 475 Ω || j/(2 × π × f × 0.53 pF) = (166 + j226) Ω thus results for the maximum output power of 5.5 dBm.
The load impedance is defined as the impedance seen from the T5750’s ANT1, ANT2
into the matching network. Do not confuse this large signal load impedance with a small
signal input impedance delivered as input characteristic of RF amplifiers and measured
from the application into the IC instead of from the IC into the application for a power
amplifier.
Less output power is achieved by lowering the real parallel part of 475 Ω where the
parallel imaginary part should be kept constant.
Output power measurement can be done with the circuit of Figure 5. Note that the component values must be changed to compensate the individual board parasitics until the
T5750 has the right load impedance ZLoad,opt = (166 + j226) Ω at 868.3 MHz. Also the
damping of the cable used to measure the output power must be calibrated out.
Figure 5. Output Power Measurement
VS
C1 = 1n
L1 = 10n
~
Power
meter
Z = 50 Ω
ANT1
ZLopt
C2 = 1.5p
Rin
C3 = 2.7p
ANT2
50 Ω
~
Application Circuit
For the supply-voltage blocking capacitor C3 a value of 68 nF/X7R is recommended
(see Figure 6 on page 6 and Figure 7 on page 7). C1 and C2 are used to match the loop
antenna to the power amplifier where C1 typically is 3.9 pF/NP0 and C2 is 1 pF/NP0; for
C2 two capacitors in series should be used to achieve a better tolerance value and to
have the possibility to realize the ZLoad,opt by using standard valued capacitors.
C1 forms together with the pins of T5750 and the PCB board wires a series resonance
loop that suppresses the 1st harmonic, hence the position of C1 on the PCB is important.
Normally the best suppression is achieved when C1 is placed as close as possible to the
Pins ANT1 and ANT2.
The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the
loop antenna is too high.
L1 (≈ 50 nH to 100 nH) can be printed on PCB. C4 should be selected so that the XTO
runs on the load resonance frequency of the crystal. Normally, a value of 12 pF results
for a 15 pF load-capacitance crystal.
5
4546B–RKE–07/04
Figure 6. ASK Application Circuit
BPXY
S1
S2
VDD
M4xCx9x
1
VS
VSS
BPXY
20
BPXY
OSC1
BPXY
7
T5750
Power up / down
CLK
1
f
ENABLE
8
4
f
64
PA_ENABLE
GND
7
2
PFD
C3
CP
C2
ANT2
VS
3
Loop
Antenna
6
VS
LF
C1
XTAL
ANT1
4
L1
XTAL
VCO
PA
PLL
XTO
5
C4
VS
6
T5750 [Preliminary]
4546B–RKE–07/04
T5750 [Preliminary]
Figure 7. FSK Application Circuit
M4xCx9x
BPXY
S1
VDD
1
S2
VS
VSS
BPXY
20
BPXY
BP42/T2O
18
OSC1
BPXY
7
T5750
Power up / down
CLK
1
f
ENABLE
8
4
f
64
PA_ENABLE
GND
7
2
PFD
C3
CP
C2
ANT2
VS
3
Loop
Antenna
6
VS
LF
C1
XTAL
ANT1
4
C5
XTAL
VCO
PA
XTO
5
C4
L1
PLL
VS
7
4546B–RKE–07/04
Figure 8. ESD Protection Circuit
VS
ANT1
CLK
PA_ENABLE
ANT2
XTAL
ENABLE
GND
Absolute Maximum Ratings
Parameters
Symbol
Minimum
Maximum
Unit
Supply voltage
VS
5
V
Power dissipation
Ptot
100
mW
Junction temperature
Tj
150
°C
Storage temperature
Tstg
-55
125
°C
Ambient temperature
Tamb
-55
125
Input voltage
Note:
VmaxPA_ENABLE
-0.3
°C
(VS + 0.3)
(1)
V
1. If VS + 0.3 is higher than 3.7 V, the maximum voltage will be reduced to 3.7 V.
Thermal Resistance
Parameters
Junction ambient
Symbol
Value
Unit
RthJA
170
K/W
Electrical Characteristics
VS = 2.0 V to 4.0 V, Tamb = -40°C to 125°C unless otherwise specified.
Typical values are given at VS = 3.0 V and Tamb = 25°C. All parameters are referred to GND (Pin 7).
Parameters
Test Conditions
Supply current
Power down,
VENABLE < 0.25 V, -40°C to 85°C
VPA_ENABLE < 0.25 V, -85°C to +125° C
VPA_ENABLE < 0.25 V, 25°C
(100% correlation tested)
IS_Off
Power up, PA off, VS = 3 V,
VENABLE > 1.7 V, VPA_ENABLE < 0.25 V
IS
Power up, VS = 3.0 V,
VENABLE > 1.7 V, VPA_ENABLE > 1.7 V
IS_Transmit
Supply current
Output power
Note:
8
VS = 3.0 V, Tamb = 25° C,
f = 868.3 MHz, ZLoad = (166 + j226) Ω
Symbol
Min.
Typ.
Max.
Unit
350
7
nA
µA
nA
3.6
4.6
mA
8.5
11
mA
5.5
8
dBm
<10
PRef
3.5
1. If VS is higher than 3.6 V, the maximum voltage will be reduced to 3.6 V.
T5750 [Preliminary]
4546B–RKE–07/04
T5750 [Preliminary]
Electrical Characteristics (Continued)
VS = 2.0 V to 4.0 V, Tamb = -40°C to 125°C unless otherwise specified.
Typical values are given at VS = 3.0 V and Tamb = 25°C. All parameters are referred to GND (Pin 7).
Parameters
Test Conditions
Output power variation for the full
temperature range
Tamb = -40°C to +85° C,
VS = 3.0 V
VS = 2.0 V
Output power variation for the full
temperature range
Tamb = -40°C to +125° C,
VS = 3.0 V
VS = 2.0 V,
POut = PRef + ∆PRef
Achievable output-power range
Selectable by load impedance
Spurious emission
fCLK = f0/128
Load capacitance at Pin CLK = 10 pF
fO ±1× fCLK
fO ± 4 × fCLK
other spurious are lower
Oscillator frequency XTO
(= phase comparator frequency)
fXTO = f0/32
fXTAL = resonant frequency of the
XTAL, CM ≤10 fF, load capacitance
selected accordingly
Tamb = -40°C to +85°C,
Tamb = -40°C to +125°C
Symbol
Max.
Unit
∆PRef
∆PRef
-1.5
-4.0
dB
dB
∆PRef
∆PRef
-2.0
-4.5
dB
dB
+5.5
dBm
POut_typ
Min.
Typ.
-3
-52
-52
dBc
dBc
fXTO
-30
-40
PLL loop bandwidth
fXTAL
+30
+40
250
ppm
ppm
kHz
Phase noise of phase
comparator
Referred to fPC = fXT0,
25 kHz distance to carrier
-116
-110
dBc/Hz
In loop phase noise PLL
25 kHz distance to carrier
-80
-74
dBc/Hz
Phase noise VCO
at 1 MHz
at 36 MHz
-89
-120
-86
-117
dBc/Hz
dBc/Hz
928
MHz
Frequency range of VCO
fVCO
868
Clock output frequency (CMOS
microcontroller compatible)
Voltage swing at Pin CLK
f0/256
CLoad ≤10 pF
Series resonance R of the crystal
V0h
V0l
VS × 0.
8
Rs
Capacitive load at Pin XT0
MHz
VS × 0.
2
V
V
110
Ω
7
pF
FSK modulation frequency rate
Duty cycle of the modulation signal =
50%
0
32
kHz
ASK modulation frequency rate
Duty cycle of the modulation signal =
50%
0
32
kHz
Low level input voltage
High level input voltage
Input current high
VIl
VIh
IIn
0.25
ENABLE input
20
V
V
µA
PA_ENABLE input
Low level input voltage
High level input voltage
Input current high
VIl
VIh
IIn
0.25
VS(1)
5
V
V
µA
Note:
1.7
1.7
1. If VS is higher than 3.6 V, the maximum voltage will be reduced to 3.6 V.
9
4546B–RKE–07/04
Ordering Information
Extended Type Number
Package
Remarks
T5750-6AQ
TSSOP8L
Taped and reeled, Marking: T570
Package Information
10
T5750 [Preliminary]
4546B–RKE–07/04
T5750 [Preliminary]
Revision History
Please note that the following page numbers referred to in this section refer to the
specific revision mentioned, not to this document.
Changes from Rev.
4546A-RKE-05/02
to Rev.
4546B-RKE-07/04
1. Abs. Max. Ratings table (page 8): row “Input voltage” added
2. Abs. Max. Ratings table (page 8): table note 1 added
3. El. Char. table (page 9): row “PA_ENABLE input“ changed
4. El. Char. table (page 9): table note 1 added
5. Ordering Information table (page 10): Remarks changed
11
4546B–RKE–07/04
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4546B–RKE–07/04