PHILIPS TFA9879

TFA9879
Mono BTL class-D audio amplifier for portable applications
with digital input
Rev. 02 — 15 October 2010
Product data sheet
1. Introduction
The TFA9879 is a high-efficiency filter-free mono class-D audio amplifier with two
separate digital inputs for mobile applications.
2. General description
The TFA9879 contains a processor that supports a range of sound processing features
including a 5-band parametric equalizer, separate bass and treble control, a dynamic
range compressor, soft clip control and volume control. Excellent audio performance
combined with high Power Supply Rejection Ratio (PSRR) is achieved through the use of
a closed loop configuration.
Two independent digital audio inputs (I2S-bus / PCM / IOM2) are available for connecting
both a baseband and a multimedia processor.
The TFA9879 is available in a HVQFN24 package.
3. Features and benefits
3.1 General features
Closed loop amplifier for:
High power supply rejection ratio
Excellent audio performance
Digital input for high RF immunity
High efficiency for maximizing battery life
Wide supply voltage range (fully operational from 2.5 V to 5.5 V)
Delivers high output power into 4 Ω and 8 Ω load impedances
Phase-Locked Loop (PLL); no system clock required
Protection including diagnostics via I2C-bus:
OverCurrent Protection (OCP) to protect against short circuits across the speaker,
to the supply line or to ground
OverTemperature Protection (OTP)
Digital inputs protected with UnderFrequency Protection (UFP), OverFrequency
Protection (OFP) and Invalid Bit-clock Protection (IBP)
‘Pop noise’ free at power-up/power down, during sample rate switching and when
switching between digital inputs
Four separate I2C-bus addresses for multi-channel applications
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
1.8 V / 3.3 V tolerant digital inputs
Only three external components required
3.2 Programmable Digital Sound Processor (DSP)

Digital volume control (−70 dB to +24 dB)
Digital parametric 5-band equalizer
Bass and treble control (−18 dB to +18 dB)
Dynamic range compressor:
Programmable attack and release levels
Programmable attack and release rates
Soft and hard mute control
Programmable DC blocking via high-pass filter
Power limiter (0 dB to −124 dB in 0.5 dB steps)
Zero crossing volume control
Stereo-to-mono down-mix function
3.3 Interface format support for digital audio inputs
I2S formats (fs = 8 kHz to 96 kHz):
Philips standard I2S-bus
Japanese I2S-bus MSB-justified
Sony I2S-bus LSB-justified
PCM / IOM2 formats (fs = 8 kHz or fs = 16 kHz):
Long frame sync
Short frame sync
4. Applications

TFA9879
Product data sheet
Mobile phones
Portable Navigation Devices (PND)
PDAs
Notebooks
Portable gaming devices
MP3 and MP4 players
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Rev. 02 — 15 October 2010
© NXP B.V. 2010. All rights reserved.
2 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
5. Quick reference data
Table 1.
Quick reference data
All parameters are guaranteed for VDDD = 1.8 V; VDDP = 3.7 V; RL = 8 Ω; LL = 44 μH; fi = 1 kHz; fs = 48 kHz; clip control off;
Tamb = 25 °C unless otherwise specified.
Symbol
Parameter
Conditions
Min
VDDP
power supply voltage
on pin VDDP
2.5
-
5.5
V
VDDD
digital supply voltage
on pin VDDD
1.65
1.8
1.95
V
IP
supply current
on pin VDDP; Amplifier mode with load; soft
mute on
-
5.7
-
mA
on pin VDDP; Power-down mode
-
-
20
μA
IDDD
digital supply current
on pin VDDD; Amplifier mode
-
1.2
-
mA
-
5
15
μA
THD + N = 1 %
0.65
0.7
-
W
THD + N = 10 %
-
0.85
-
W
THD + N = 1 %
-
1.2
-
W
THD + N = 10 %
-
1.5
-
W
THD + N = 1 %
-
0.9
-
W
THD + N = 10 %
-
1.1
-
W
THD + N = 1 %
-
1.6
-
W
THD + N = 10 %
-
1.95
-
W
on pin VDDD; Power-down mode
Po(RMS)
[1]
Typ
Max
Unit
RL = 8 Ω
RMS output power
RL = 4 Ω
RL = 8 Ω; VDDP = 4.2 V
RL = 4 Ω; VDDP = 4.2 V
RL = 8 Ω; VDDP = 5.0 V
THD + N = 1 %
-
1.35
-
W
THD + N = 10 %
-
1.6
-
W
-
2.35
-
W
RL = 4 Ω; VDDP = 5.0 V
THD + N = 1 %
ηpo
[1]
output power efficiency
THD + N = 10 %
-
2.75
-
W
Po(RMS) = 850 mW
-
92
-
%
After switching from Off/Amplifier mode to Power-down mode.
6. Ordering information
Table 2.
Ordering information
Type number
TFA9879HN
TFA9879
Product data sheet
Package
Name
Description
Version
HVQFN24
plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.85 mm
SOT616_3
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TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
7. Block diagram
SDA
1
SCL
2
I2C
CONTROL
VDDD
n.c.
STABA
TEST1
TEST2
TEST3
23
6, 14
13
3
15
5
PROTECTION
CIRCUITS:
OCP
OTP
OFP
UFP
IBP
TFA9879
SDI1 20
SCK1 21
LRCK1 22
MUX
SDI2 17
DIGITAL
AUDIO
RECEIVER
SCK2 18
PLL
7, 8 VDDP
LRCK2 19
2nd
ORDER
LOOP
HIGH
PASS
FILTER
VOLUME
CONTROL
5
BAND
EQUALIZER
BASS
TREBLE
BOOST
POWER
LIMITER
PWM
10 OUTA
H-BRIDGE
DRC
DSP
2nd
ORDER
LOOP
9 OUTB
ADSEL1 16
11, 12 GNDP
ADSEL2 4
24
GNDD
Fig 1.
DAP
010aaa542
Block diagram
TFA9879
Product data sheet
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TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
8. Pinning information
19 LRCK2
20 SDI1
21 SCK1
22 LRCK1
terminal 1
index area
23 VDDD
24 GNDD
8.1 Pinning
SDA
1
18 SCK2
SCL
2
17 SDI2
TEST1
3
ADSEL2
4
TEST3
5
n.c.
6
16 ADSEL1
TFA9879
15 TEST2
14 n.c.
GNDP 12
9
OUTB
GNDP 11
8
VDDP
13 STABA
OUTA 10
7
VDDP
DAP(1)
010aaa582
Transparent top view
(1) Exposed Die Attach Paddle (DAP)
Fig 2.
Pin configuration
8.2 Pin description
TFA9879
Product data sheet
Table 3.
Pin description
Symbol
Pin
Pin Type Description
SDA
1
IO
I2C-bus data input/output
SCL
2
I
I2C-bus bit clock input
TEST1
3
I
test signal input 1; for test purposes only; connect to PCB ground
ADSEL2
4
I
address selection input 2
TEST3
5
I
test signal input 3; for test purposes only; connect to PCB ground
n.c.
6
-
not connected; connect to PCB ground
VDDP
7, 8
P
analog supply voltage (2.5 V to 5.5 V)
OUTB
9
O
output B (negative)
OUTA
10
O
output A (positive)
GNDP
11, 12
P
analog ground, PCB ground reference
STABA
13
O
1.8 V analog stabilizer output
n.c
14
-
not connected; connect to PCB ground
TEST2
15
I
test signal input 2; for test purposes only; connect to PCB ground
ADSEL1
16
I
address selection input 1
SDI2
17
I
digital audio data input 2
SCK2
18
I
digital audio bit clock input 2
LRCK2
19
I
digital audio word select input 2
SDI1
20
I
digital audio data input 1
SCK1
21
I
digital audio bit clock input 1
LRCK1
22
I
digital audio word select input 1
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Rev. 02 — 15 October 2010
© NXP B.V. 2010. All rights reserved.
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TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
Table 3.
Pin description …continued
Symbol
Pin
Pin Type Description
VDDD
23
P
digital supply voltage (1.8 V)
GNDD
24
P
digital ground, PCB ground reference
DAP
-
P
exposed Die Attached Paddle (DAP); connect to PCB ground
9. Functional description
The TFA9879 is a high-efficiency mono Bridge Tied Load (BTL) class-D amplifier with
digital audio inputs. It supports all commonly used formats.
The key functional blocks of the TFA9879 are shown in Figure 1. In the digital domain, the
audio signal is processed and converted into a Pulse Width Modulated (PWM) signal
using a 3-level modulation. In the analog domain, the PWM signal is amplified using a
second order feedback loop.
The audio signal-processing path is described below:
1. The MUX selects the serial interface input to be used.
2. The digital audio receiver translates the serial input signal into a standard internal
mono audio stream.
3. The programmable high-pass filter blocks DC signals and low frequency signals.
4. The volume control provides both gain and attenuation functionality and can be
adjusted by the user or dynamically via the Dynamic Range Compressor (DRC). The
volume control can be used to adjust the signal level between −70 dB and +24 dB.
5. The 5-band parametric equalizer can be used to equalize the mono audio stream. It
can be used for speaker transfer curve compensation to optimize the audio
performance of the speakers.
6. The bass and treble boost function provides another way to adjust the sound.
7. The power limiter limits the maximum output signal of the TFA9879. The power limiter
settings are 0 dB to −124 dB in steps of 0.5 dB. This function can be used to limit the
maximum output power delivered to the speakers at a fixed supply voltage and
speaker impedance.
8. The PWM controller block converts the audio signal into a 3-level modulated PWM
signal. The 3-level modulation provides a high signal-to-noise performance and
eliminates clock jitter noise.
9. The second order feedback loop ensures excellent audio performance and high
power supply rejection ratio.
10. The H-BRIDGE allows the TFA9879 to deliver the required output power between
terminals OUTA and OUTB.
The internal clocks of the TFA9879 are derived from the digital audio interface (SCK1 and
SCK2) using a PLL. The reference input for the PLL is selected via the digital input MUX.
The audio signal path can be selected via the I2C-bus interface.
The PLL block generates the system clock.
TFA9879
Product data sheet
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Rev. 02 — 15 October 2010
© NXP B.V. 2010. All rights reserved.
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TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
The following protection circuits are built into the TFA9879:
•
•
•
•
•
•
OverTemperature Protection (OTP)
OverCurrent Protection (OCP)
UnderFrequency Protection (UFP)
OverFrequency Protection (OFP)
Invalid Bit-clock Protection (IBP)
DC-blocking
9.1 Operating modes
The TFA9879 supports the following operating modes, which are controlled via the
I2C-bus interface:
• Power-down mode, used to switch off the device; current consumption is reduced to
a minimum; the I2C-bus remains operational; the PWM outputs are disabled.
• Off mode, in which the class-D amplifier is switched off; the TFA9879 is completely
biased and the PWM outputs are disabled.
• Amplifier mode, in which the digital inputs are used to generate a signal between
OUTA and OUTB.
The TFA9879 device control settings are detailed in Table 21.
9.1.1 Power-up/power-down
The power-up and power-down timing of the TFA9879 is illustrated in Figure 3. The
external power supply levels, VDDP and VDDD, should be within the specified operating
ranges before the operating mode is selected. Bit POWERUP in the Device control
register (Table 21) must be set to 1 before the operating mode can be selected via bits
OPMODE. After the turn-on delay (td(on)), the device automatically generates a soft
un-mute function. A soft mute function is generated when OPMODE is set to 0. The
TFA9879 should be set to Power-down mode before the power supplies are disconnected
or turned off.
TFA9879
Product data sheet
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Rev. 02 — 15 October 2010
© NXP B.V. 2010. All rights reserved.
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TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
VDDP, VDDD
I2C POWERUP
(00h, bit 0)
I2C OPMODE
(00h, bit 3)
serial interface
input signals
OUTA, OUTB
filtered BTL
output signal
td(on)
operating
td(mute_off)
td(soft_mute)
010aaa653
Fig 3.
Power-up/power-down timing
9.1.2 Supported Digital audio data formats
The TFA9879 supports a commonly used range of I2S, PCM and IOM2 digital audio data
formats. The I2S formats, selected via bits I2S_SET in the Serial interface control register
(Table 22), are listed in Table 4. The PCM/IOM2 formats are listed in Table 5. The
TFA9879 automatically detects the number of slots by measuring the ratio between the
sync frequency (8 kHz) and the data clock. Table 24 details the I2C settings for the
PCM/IOM2 formats.
TFA9879
Product data sheet
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© NXP B.V. 2010. All rights reserved.
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TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
I2S-supported digital audio data formats
Table 4.
SCK frequency
Interface format (MSB first)
Supported data format
32 fs
I2S
up to 16-bit data
32 fs
MSB-justified
up to 16-bit data
32 fs
LSB-justified - 16 bits
16-bit data
64 fs
I2S (Philips) standard
up to 24-bit data
64 fs
MSB-justified
up to 24-bit data
64 fs
LSB-justified - 16 bits
16-bit data
64 fs
LSB-justified - 18 bits
18-bit data
64 fs
LSB-justified - 20 bits
20-bit data
64 fs
LSB-justified - 24 bits
24-bit data
RIGHT
LEFT
WS
1
2
(Philips) standard
3
2
3
MSB
B2
1
BCK
MSB
DATA
B2
MSB
I2S-BUS FORMAT
LEFT
WS
1
2
RIGHT
3
1
2
3
BCK
DATA
MSB
B2
LSB
MSB
B2
LSB
MSB
B2
MSB-JUSTIFIED FORMAT
WS
LEFT
RIGHT
16
15
2
1
16
B15 LSB
MSB
15
2
1
BCK
DATA
MSB
B2
B2
B15 LSB
LSB-JUSTIFIED FORMAT 16 BITS
WS
LEFT
RIGHT
18
17
16
15
2
1
18
B17 LSB
MSB
17
16
15
2
1
BCK
DATA
MSB
B2
B3
B4
B2
B3
B4
B17 LSB
LSB-JUSTIFIED FORMAT 18 BITS
WS
LEFT
20
RIGHT
19
18
17
16
15
2
1
20
B19 LSB
MSB
19
18
17
16
15
2
1
BCK
DATA
MSB
B2
B3
B4
B5
B6
B2
B3
B4
B5
B6
B19 LSB
LSB-JUSTIFIED FORMAT 20 BITS
WS
LEFT
24
23
22
21
20
RIGHT
19
18
17
16
15
2
1
24
B23 LSB
MSB
23
22
21
20
19
18
17
16
15
2
1
BCK
DATA
MSB
B2
B3
B4
B5
B6
B7
B8
B9
B10
B2
B3
B4
B5
B6
B7
B8
B9
B10
B23 LSB
010aaa458
LSB-JUSTIFIED FORMAT 24 BITS
Fig 4.
I2S-supported digital audio data formats
TFA9879
Product data sheet
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TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
Table 5.
PCM/IOM2-supported audio data formats
Number of slots
fs (kHz)
Sync frequency
(kHz) on LRCK
pin
Supported data
formats
Data clock (kHz)
on SCK pin
2
8 or 16
8
8-bit data
128
2
8 or 16
8
8-bit data
128
4
8 or 16
8
8-bit data
256
4
8 or 16
8
8-bit data
256
6
8 or 16
8
8-bit data
384
8
8 or 16
8
8-bit data
512
12
8 or 16
8
8-bit data
768
16
8 or 16
8
8-bit data
1024
2
8 or 16
8
16-bit data
256
3
8 or 16
8
16-bit data
384
4
8 or 16
8
16-bit data
512
6
8 or 16
8
16-bit data
768
8
8 or 16
8
16-bit data
1024
12
8 or 16
8
16-bit data
1536
12
8 or 16
8
16-bit data
1536
reserved
LRCK
SCK
SDI
MSB
B2
LSB
MSB
B2
Slot 0
LSB
MSB
B2
Slot 1
LSB
Slot 2
MSB
B2
Slot N − 1
LSB
Slot N
SHORT SYNC PCM/IOM2 FORMAT
LRCK
SCK
SDI
MSB
B2
LSB
Slot 0
MSB
B2
LSB
Slot 1
MSB
B2
LSB
Slot 2
Slot N − 1
LONG SYNC PCM/IOM2 FORMAT
Fig 5.
MSB
B2
LSB
Slot N
010aaa652
PCM/IOM2-supported digital audio data formats
TFA9879
Product data sheet
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Rev. 02 — 15 October 2010
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TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
9.2 Digital Signal Processor (DSP) features
9.2.1 Serial interface selection
The TFA9879 contains two serial interfaces. The active interface is selected via bit
INPUT_SEL in the Device control register (see Table 21). When this bit is toggled, the
following sequence is initiated:
• Soft mute is activated for 128/fs seconds
• The TFA9879 switches to Off mode and the serial interface input is toggled
• The TFA9879 switches back to Operating mode and soft mute is released
9.2.2 Mono selection
Mono selection is used to select the digital audio input channel to be amplified. The
options are:
• Left channel
• Right channel
• Left + right channels (sum divided by two)
Separate Mono selection is provided for the two serial interfaces via bits MONO_SEL in
the Serial interface control registers (addresses 01h and 03h; see Table 22).
9.2.3 Programmable high-pass filter
The TFA9879 features a first-order high-pass filter on the digital audio input to block DC
and low frequency signals. DC values at the output can damage the speaker.
The high-pass filter cut-off frequency is determined by:
• The high-pass filter control setting (bits HP_CTRL, see Table 30)
• The sample frequency, fs
The relationship between these parameters and the cut-off frequency is defined in
Equation 1:
f high ( –3dB )
4096 – HP_CTRL
– f s × ln ⎛⎝ ---------------------------------------------⎞⎠
4096
= ---------------------------------------------------------------------2π
(1)
HP_CTRL can be programmed to any integer value between 0 and 511 (see Table 30).
The high-pass filter is bypassed if HP_CTRL = 0 or bit HPF_BP in the Bypass control
register is set to 1 (see Table 27).
9.2.4 De-emphasis
Digital de-emphasis is sometimes needed, especially with older recordings. Emphasis
and de-emphasis originate in the FM transmission, in which the Signal-to-Noise Ratio
(SNR) is not flat over the signal band (in fact the SNR gets worse as the signal frequency
increases). To achieve good SNR over the complete audio band, the high frequency
components of the audio signal were amplified prior to transmission (this is called
Emphasis).
TFA9879
Product data sheet
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TFA9879
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Mono BTL class-D audio amplifier with digital input
The de-emphasis filter is a simple first order filter. The cut-off frequency of the
de-emphasis low-pass filter is approximately 3.5 kHz. The TFA9879 de-emphasis filter is
supported for four sample frequencies, as detailed in Table 6.
Table 6.
De-emphasis control
[1:0] Control value[1]
fs (kHz)
00[2]
de-emphasis inactive
01
32
10
44.1
11
48
[1]
Value selected via bits DE_PHAS in the De-emphasis, soft/hard mute and power limiter control register
(see Table 32).
[2]
Default value.
9.2.5 Equalizer
The equalizer can be used for speaker curve compensation or for customer equalizer
settings, such as jazz, pop, rock or classical music. The equalizer function can be
bypassed or configured as 5-band.
9.2.5.1
Equalizer band function
The shape of each parametric equalizer band is determined by the following three filter
parameters:
• (Relative) center frequency ω = 2π ( fc ⁄ f s )
• Quality factor Q
• Gain factor G
In the above equation, fc is the center frequency and fs is the sample frequency.
The definition of the quality factor is the center frequency divided by the 3 dB bandwidth
(see Equation 2). In parametric equalizers this is only valid when the gain is set very low
(−30 dB).
f1 :
⎛ Af ⎞
20 log ⎜ -------1⎟
⎝ A f c⎠
10
= 3dB f c > f 1
f2 :
⎛ Af ⎞
20 log ⎜ -------2⎟
⎝ A f c⎠
10
= 3dB ,f 2 > f c
fc
Q = -------------- ;
f2 – f1
(2)
Each band filter can be programmed to perform a band-suppression (G < 1) or a
band-amplification (G > 1) function around the center frequency.
Each band of the TFA9879 equalizer has a second order Regalia-Mitra all-pass filter
structure. The structure is shown in Figure 6.
TFA9879
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TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
+
½
+
Y(z)
+
X(z)
s
−
K0/2
A(z)
010aaa406
Fig 6.
Regalia-Mitra filter flow diagram
The transfer function of this all-pass filter is given in Equation 3:
H ( z ) = 1 ⁄ 2 ⋅ ( 1 + A ( z ) ) + K0 ⁄ 2 ⋅ ( 1 – A ( z ) )
(3)
A(z) is the second order filter structure. The transfer function of A(z) is given in
Equation 4:
–1
–2
K1 + K2 ⋅ ( 1 + K1 ) ⋅ Z + Z
A ( z ) = -----------------------------------------------------------------------------–1
–2
1 + K2 ⋅ ( 1 + K1 ) ⋅ Z + K1 ⋅ Z
(4)
Z−1 equals one fs delay period. The relationship between the programmable parameters
K0, K1 and K2 and the filter parameters G, ω and Q is shown in Equation 5 and Equation 6.
Equation 5 can be used to calculate band suppression (G < 1) functions.
K0 = G
K 1 = – cos ω
(5)
K 2 = ( 2Q ⋅ G – sin ω ) ⁄ ( 2Q ⋅ G + sin ω )
G<1
Equation 6 can be used to calculate band amplification (G ≥ 1) functions.
K0 = G
K 1 = – cos ω
(6)
K 2 = ( 2Q – sin ω ) ⁄ ( 2Q + sin ω )
G≥1
The ranges of the parametric equalizer settings for each band are:
• The gain, G, is from −30 dB to +12 dB.
• The center frequency, fc, is from 0.0004 ´ fs to 0.49 ´ fs.
• The quality factor, Q, is from 0.001 to 8.
Filter coefficients need to be entered for each filter stage via the I2C-bus interface to
configure the filters (see Section 10.4.3).
Figure 7, Figure 8 and Figure 9 illustrate some possible equalizer band transfer functions.
The relationships are symmetrical for the suppression and amplification functions. A
skewing effect can be observed at higher frequencies.
TFA9879
Product data sheet
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TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
For optimum numerical noise performance, different configurations are available for a
given filter transfer function. The binary filter configuration parameters t1 and t2 control the
actual configuration and should be chosen according to Equation 7.
K1 ≤ 0
K1 > 0
⎛0
t 1 = ⎜1
⎝
⎛0
t 2 = ⎜1
⎝
(7)
K2 ≥ 0
K2 < 0
A maximum of 12 dB amplification, with respect to the input signal, can be achieved per
equalizer stage. The equalizer band signals are processed in sequence, from the highest
(Band A) to the lowest (Band E). Each band can attenuate the signal by 6 dB so, in order
to prevent numerical clipping at filter settings of over 6 dB amplification, band filters can
be scaled by 0 dB or −6 dB. For optimum numerical noise performance, steps of −6 dB
amplification should be applied to the bands in sequence, starting with B and A, as long as
they are able to amplify the signal without clipping.
A filter scale factor, s, is associated with each of the equalizer bands and is set via the
relevant EQx_s control bit (see Table 25).
Table 7.
9.2.5.2
Equalizer filter scale factor settings
s
scale factor (dB)
0
0
1
−6
Equalizer band control
For compact representation with positive signed parameters, parameters k1’ and k2’ are
introduced in Equation 8.
k0 ′ = K0
⎛ 1 – K1
k1 ′ = ⎜
⎝ 1 + K1
t1 = 0
⎛ 1 – K2
k2′ = ⎜
⎝ 1 + K2
t2 = 0
t1 = 1
(8)
t2 = 1
Parameters K0, k1', k2', t1, t2 and s must be combined in two 16-bit control words, word1
and word2 (see Table 24 and Table 25), using the format shown in Table 8. Parameters k1'
and k2' are unsigned floating-point representations in Equation 8.
kx′ = M ⋅ 2
–E
(9)
M<1
In Equation 9, M is the unsigned mantissa and E the negative signed exponent. For
example, in word2 bits [14:8] = [0111 010] represent k2' = (7/24) × 2−2 = 1.09375 × 10−1.
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Mono BTL class-D audio amplifier with digital input
Table 8.
Equalizer control word construction
Word
Section
Data
word1
15
t1
word1
[14:4]
11 mantissa bits of k1’
word1
[3:0]
four exponent bits of k1’
word2
15
t2
word2
[14:11]
four mantissa bits of k2’
word2
[10:8]
three exponent bits of k2’
word2
[7:1]
k0 ’
word2
0
s
010aaa222
12
Q1 = 0.27
G
(dB)
Q2 = 0.61
8
Q3 = 1.65
4
0
10
102
103
104
105
f (Hz)
Fig 7.
Transfer functions for selected values of Q, the quality factor
010aaa223
12
G
(dB)
8
4
0
10
102
103
104
105
f (Hz)
Fig 8.
TFA9879
Product data sheet
Transfer functions for selected values of fc, the center frequency
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Mono BTL class-D audio amplifier with digital input
010aaa224
12
G
(dB)
6
0
-6
-12
10
102
103
104
105
f (Hz)
Fig 9.
Transfer functions for selected values of G, the gain factor
9.2.6 Bass and treble control
The TFA9879 contains first order shelving filters for bass and treble control. The device
can attenuate or boost the bass and high frequency signals independently in 2 dB steps
within a −18 dB to +18 dB range. Attenuation and boosting are dependent on the audio
signal zero crossing settings (see Section 9.2.9 for further details). The bass and treble
corner frequencies are adjustable.
The bass and treble corner frequencies, as a function of the I2C control settings and the
sample rate, are given in Table 9.
Table 9.
Corner frequency settings for bass and treble control
Control value
00
01[3]
10
11
[1]
TFA9879
Product data sheet
fs (kHz)
Corner frequency (Hz)
Bass[1]
Treble[2]
8, 16, 32, 64
181
1090
11.025, 22.05, 44.1, 88.2
250
1500
12, 24, 48, 96
272
1630
8, 16, 32, 64
218
2180
11.025, 22.05, 44.1, 88.2
300
3000
12, 24, 48, 96
326
3260
8, 16, 32, 64
300
3000
11.025, 22.05, 44.1, 88.2
413
4130
12, 24, 48, 96
450
4500
reserved
Value selected via bits F_BASS in the Bass and treble control register (see Table 29).
[2]
Value selected via bits F_TREBLE in the Bass and treble control register (see Table 29).
[3]
Default value.
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Figure 10 shows the bass function for a range of attenuation and boost settings with a
sample rate of 48 kHz and a corner frequency of 272 Hz.
010aaa650
20
dB
10
0
−10
−20
102
10
103
104
105
f (Hz)
VDDP = 3.7 V, 2 × 8 Ω BTL configuration, treble control = 0 dB, clip control on
Fig 10. Bass function in 2 dB steps; the treble control is set to flat
Figure 11 shows the treble function for a range of attenuation and boost settings with a
sample rate of 48 kHz and a corner frequency of 1630 Hz.
010aaa649
20
dB
10
0
−10
−20
102
10
103
104
105
f (Hz)
VDDP = 3.7 V, 2 × 8 Ω BTL configuration, bass control = 0 dB, clip control on
Fig 11. Treble function in 2 dB steps; the bass control is set to flat
9.2.7 Muting
The TFA9879 support two muting options, which are controlled via the I2C-bus interface:
• Soft muting
• Hard muting
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Mono BTL class-D audio amplifier with digital input
Soft muting prevents audible pops. The function smoothly reduces the gain setting of the
audio channel to the mute level according to a raised cosine shape. Soft muting is
performed in 128 / fs steps. Soft de-mute results in a similar gain increase. Bit S_MUTE in
Table 32 enables and disables the soft mute function.
The hard mute function immediately switches the outputs to 50 % duty-cycle pulses. As a
result, the input signals are abruptly blocked. Hard mute takes priority over soft mute.
Hard mute is enabled and disabled via bit H_MUTE in Table 32.
9.2.8 Digital volume control
The digital volume control has a range of −70 dB to + 24 dB, programmable in 0.5 dB
steps. The default setting is mute (0 × BD). Attenuation and boosting behavior is affected
by the zero crossing volume setting (see Section 9.2.9 for further details).
The volume control settings, and the resulting amplification or suppression factors, are
detailed in Table 10.
Table 10.
Volume control amplification and suppression
Control value[1]
Gain (dB)
00h
+24
01h
+23.5
..
steps of 0.5 dB
....
BBh
−69.5
BCh
−70
BDh[2]
mute
..
mute
....
FFh
mute
[1]
Control value is selected via bits VOL in the Volume control register (see Table 31).
[2]
Default value.
9.2.9 Zero-crossing volume control
The TFA9879 employs zero-crossing volume control to minimize pop noise when the
volume or bass/treble control is changing.
When zero-crossing volume control is enabled (ZR_CRSS = 1; see Table 31), the
TFA9879 increases or decreases the gain only when the audio signal passes a zero
crossing.
9.2.10 Dynamic Range Compressor (DRC)
The TFA9879 provides a DRC to automatically adjust power levels according to
programmable attack and release levels. The attack level is related to the peak value of
the signal; the release level is related to the RMS value of the signal. The attack level is
programmable using 16 available levels in the range −12 dB to +10 dB. The release level
is programmable using 16 available levels in the range −29 dB to 0 dB relative to the
attack level. The signal level is measured after Equalizer, Bass and Treble processing, but
before it reaches the power limiter.
The DRC can be bypassed via bit DRC_BP in Table 27.
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Mono BTL class-D audio amplifier with digital input
9.2.10.1
Functional description
The DRC compresses the dynamic range of the audio stream. The volume control,
equalizer or bass/treble controls can be set so that the audio stream exceeds the 0 dBFs
clip level. The DRC can be programmed to compress the louder audio content when this
occurs, while quieter sounds remain unaffected, i.e. the DRC soft clips the audio stream.
This is useful when background noise overpowers quiet audio passages. Increasing the
volume using the volume control can make quiet audio passages audible but can cause
louder audio passages to be distorted by clipping. The DRC prevents this distortion
happening by reducing the volume during loud audio passages and increasing it again for
quiet passages.
The design of the DRC feedback loop, incorporating the equalizer and bass and treble
controls, is illustrated in Figure 12.
DRC
RMS
volume control
setting
audio in
DRC volume
LIMITER
PARAMETRIC
5-BAND
EQUALIZER
BASS AND
TREBLE
CONTROL
010aaa550
Fig 12. DRC feedback design
9.2.10.2
DRC control
The DRC has four programmable control settings:
•
•
•
•
Attack level
Attack rate
Release level
Release rate
The DRC reduces the volume when the audio signal level exceeds the attack level. The
attack level is based on the audio peak value. When the audio signal level drops below
the attack level, the DRC stops reducing the volume. The rate of decrease is
programmable via the attack rate. The DRC increases the audio signal level again when it
drops below the release level. This level is based on the audio RMS-value and is related
to the attack level. The rate of increase is programmable via the release level. The DRC
stops increasing the volume when the audio signal level reaches the release level or the
DRC volume falls to 0 dB.
Figure 13 shows the attack and release behavior of the DRC.
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Mono BTL class-D audio amplifier with digital input
audio in
audio out
RMS value
attack level (peak value)
release level (RMS-value)
attack level (peak value)
release rate (dB/ms)
attack rate (dB/ms)
010aaa654
Fig 13. DRC attack and release behavior
Table 11.
TFA9879
Product data sheet
DRC attack and release levels
Control value:
attack level[1]
Attack level based on
peak value; absolute
value (dBFS)
Control value:
release level[2]
Release level based on RMS
value (relative to the attack
level[3]) (dB)
0000
−12
0000
−29
0001
−10
0001
−26
0010
−8
0010
−23
0011
−6
0011
−20
0100
−5
0100
−18
0101
−4
0101
−16
0110
−3
0110
−14
0111
−2
0111
−12
1000
−1
1000
−10
1001[4]
0
1001
−8
1010
1
1010
−6
1011
2
1011[4]
−4
1100
4
1100
−3
1101
6
1101
−2
1110
8
1110
−1
1111
10
1111
0
[1]
The control value is selected via bits AT_LVL in the DRC control register (see Table 28).
[2]
The control value is selected via bits RL_LVL in the DRC control register (see Table 28).
[3]
0 dB (RMS) release level equals 0 dB (peak) attack level.
[4]
Default value.
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Table 12.
DRC attack and release rates
Control value:
attack rate[1]
Attack rate (dB/ms)
Control value:
release rate[2]
Release rate (dB/ms)
0000
3
0000
0.5
0001
2.7
0001
0.137
0010[3]
2.25
0010
0.075
0011
1.8
0011
0.05
0100
1.35
0100
0.036
0101
0.9
0101
0.03
0110
0.45
0110
0.026
0111
0.225
0111
0.021
1000
0.15
1000
0.020
1001
0.11
1001
0.017
1010
0.09
1010[3]
0.015
1011
0.075
1011
0.014
1100
0.065
1100
0.013
1101
0.06
1101
0.012
1110
0.055
1110
0.011
1111
0.05
1111
0.01
[1]
The control value is selected via bits AT_RATE in the DRC control register (see Table 28).
[2]
The control value is selected via bits RL_RATE in the DRC control register (see Table 28).
[3]
Default value.
9.2.11 Power limiter
The power limiter controls the maximum output voltage in Amplifier mode. This feature
makes it possible to limit the output voltage across a peripheral (speaker) when
necessary.
The TFA9879 output voltage is dependent on:
• The analog supply voltage on pin VDDP
• The gain of the power limiter (G)
• The power limiter input signal (Xi)
The bass/treble output signal is connected to the power limiter input and is relative to the
Fraction of Full Scale (FFS), from −1 to +1.
Equation 10 shows the relationship between these settings and the output voltage
between pins OUTA and OUTB in the audio bandwidth:
⎛ X i × G × 5.91
Vo = ⎜
⎝ V DDP
X i × G × 5.91 < V DDP
X I × G × 5.91 ≥ V DDP
(V)
(10)
Equation 10 only applies with no load and with clip control off (see Section 9.3). Clip
control and the RDSon of the power switches reduce the maximum clipped output signal.
The power limiter gain can be reduced in 249 steps of 0.5 dB in the range 0 dB to
−124 dB.
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Mono BTL class-D audio amplifier with digital input
The maximum peak output voltage for the first ten power limiter gain settings is given in
Table 13.
Table 13. Power limiter control settings
All parameters are guaranteed for VDDP = 5 V; no load; fi = 1 kHz; fs = 48 kHz; clip control off;
Tamb = 25 °C unless otherwise specified.
Control value[1]
Power limiter gain (dB)
Maximum peak output voltage (V)
00h[2]
0.0
VDDP
01h
−0.5
VDDP
02h
−1.0
VDDP
03h
−1.5
VDDP
04h
−2.0
4.7
05h
−2.5
4.4
06h
−3.0
4.2
07h
−3.5
4.0
08h
−4.0
3.7
09h
−4.5
3.5
[1]
The control value is selected via bits P_LIM in the De-emphasis, soft/hard mute and power limiter control
register (see Table 32).
[2]
Default value.
9.3 Class-D amplification and clip control
A fourth order sigma delta PWM converter converts the digital audio streams into 3-level
modulated PWM signals. The analog back end amplifies the two PWM signals in a BTL
configuration with complementary output stages.
One of two clip control configurations can be selected:
• Smooth clipping, clip control on
• Maximum power, clip control off
If smooth clipping is selected (CLIPCTRL = 0; see Table 27), the clipping behavior will
have no artefacts. To obtain the maximum possible output power, the device can be set to
maximum power.
The PWM frequency is related to the I2S input sample rate as detailed in Table 4.
Table 14.
Power limiter control settings
PWM frequency (kHz)
Sample rate (kHz)
SCK relative to sample rate
256
8, 16, 32, 64
32 ×, 64 ×
352.8
11.025, 22.05, 44.1, 88.2
32 ×, 64 ×
384
12, 24, 48, 96
32 ×, 64 ×
9.4 Protection
The TFA9879 incorporates a wide range of protection circuits to facilitate optimal and safe
application.
The following protection circuits are included in the TFA9879:
TFA9879
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Mono BTL class-D audio amplifier with digital input
•
•
•
•
•
•
OverTemperature Protection (OTP)
OverCurrent Protection (OCP)
UnderFrequency Protection (UFP)
OverFrequency Protection (OFP)
Invalid Bit-clock Protection (IBP)
DC-blocking via high-pass filter (see Section 9.2.3)
The reaction of the device to fault conditions differs depending on the protection circuit
involved.
9.4.1 OverTemperature Protection (OTP)
This is a ‘hard’ protection to prevent heat damage to the TFA9879. Overtemperature
protection is triggered when the junction temperature exceeds 130 °C. When this
happens, the output stages are set floating. OTP can be cleared automatically via a
programmable timer or via the I2C-bus interface, after which the output stages will start to
operate normally again. The programmable timer settings, selected via bits L_OTP in the
Bypass control register (Table 27), are:
• 4.5 μs
• 100 ms
• 1s
OTP can also be set to no recovery. Setting the TFA9879 to Off mode and subsequently
to Amplifier mode clears the OTP when no recovery is selected.
9.4.2 OverCurrent Protection (OCP)
The output current of the class-D amplifiers is current limited. When an output stage
exceeds a current in the range 1.3 A to 2.3 A, the output stages are set floating. OCP can
be cleared automatically via a programmable timer or via the I2C-bus interface, after
which the output stages will start to operate normally again. The programmable timer
settings, selected via bits L_OCP in the Bypass control register (Table 27), are:
• 4.5 μs
• 27.5 μs
• 10 ms
The OCP can also be set to no recovery. Setting the TFA9879 to Off mode and
subsequently to Amplifier mode clears the OCP when no recovery is selected.
9.4.3 UnderFrequency Protection (UFP)
UFP sets the output stages floating when the clock input source is too low (< fUFP). This
can happen if, for example, the selected sample frequency (bits I2S_FS in Table 22) is not
in line with the applied sample rate. The PWM switching frequency can become critically
low when the frequency of the input clock is lower than the selected sample frequency.
Without UFP, peripheral devices in an application might be damaged.
The UFP status can be monitored by polling the I2C status register (Table 33). The alarm
will be raised when the input sample rate is too low.
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9.4.4 OverFrequency Protection (OFP)
OFP sets the output stages floating when the clock input source is too high (>fOFP). This
can happen if, for example, the selected sample frequency (bits I2S_FS in Table 22) is not
in line with the applied sample rate. The PWM controller can become unstable when the
frequency of the input clock is higher than the selected sample frequency. Without OFP,
peripheral devices in an application might be damaged.
The OFP status can be monitored by polling the I2C status register (Table 33). The alarm
will be raised when the input sample rate is too high.
9.4.5 Invalid Bit-clock Protection (IBP)
If the SCK-to-LRCK ratio is not supported, the audio signal will be distorted. This occurs
because the sound processing blocks will be operating at frequencies out of
synchronization with the sample rate.
IBP prevents this happening by shutting down the TFA9879 if the IBP alarm is raised for
the selected channel. This will disconnect the digital audio path.
Valid SCK-to-LRCK ratios for PCM interface formats are 16, 32, 48, 64, 96, 128 and 192.
For I2S interface formats, valid SCK-to-LRCK ratios are 32 and 64.
9.4.6 Overview of protection circuits
Table 15 provides an overview of the protection circuits implemented.
Table 15.
Overview of protection circuits
Protection circuits
Symbol Conditions
I2C flag
Output
Recovery
OTP
Tj > 130 °C
OTP
floating
automatic when timer set to 4.5 μs, 100 ms or 1 s (via bits
L_OTP in Table 27) and Tj < 130 °C;
via I2C-bus when no recovery is selected
OCP
IO > IO(ocp)
OCP
floating
automatic when timer set to 4.5 μs, 27.5 μs or 10 μs (via
bits L_OCP in Table 27) and IO < IO(ocp);
via I2C-bus when no recovery is selected
UFP
PWM frequency <
96 kHz
UFP
floating
restart (fault to operating when PWM frequency > 96 kHz)
OFP
PWM frequency >
1031 kHz
OFP
floating
restart (fault to operating when PWM frequency <
1031 kHz)
IBP
SCK/WS is not 16 ± 1, 32 ± 1, IBP
48 ± 1, 64 ± 1 or 128 ± 1
floating
restart (fault to operating when SCK/WS is 16 ± 1, 32 ± 1,
48 ± 1, 64 ± 1 or 128 ± 1)
10. I2C-bus interface and register settings
10.1 I2C-bus interface
The TFA9879 supports the 400 kHz I2C-bus microcontroller interface mode standard. The
I2C-bus is used to control the TFA9879 and to transmit and receive data.
The TFA9879 can operate only in I2C slave mode, as a slave receiver or as a slave
transmitter.
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Mono BTL class-D audio amplifier with digital input
The TFA9879 is accessed via an 8-bit code (see Table 16). Bits 1 to 7 contain the device
address. Bit 0 (R/W) indicates whether a read (1) or a write (0) operation has been
requested. Four separate addresses are supported for multichannel applications.
Applying the appropriate voltage to pins ADSEL1 (A1) and ADSEL2 (A2) select the
required I2C address as detailed in Table 16.
Table 16.
I2C-bus device address
Bit 7 (MSB) Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
1
0
1
1
A2
A1
R/W
1
Table 17.
I2C pin voltages in I2C control mode
Logic value
Voltage on pins ADSEL1 and ADSEL2
0
< VIL
1
> VIH
10.2 I2C-bus write cycle
The sequence of events that needs to be followed when writing data to the TFA9879’s
I2C-bus registers is detailed in Table 18. One byte is transmitted at a time. Each register
stores two bytes of data. Data is always written in byte pairs. Data transfer is always MSB
first.
The write cycle sequence using SDA is as follows:
1. The microcontroller asserts a start condition (S).
2. The microcontroller transmits the 7-bit device address of the TFA9879, followed by
the R/W bit set to 0.
3. The TFA9879 asserts an acknowledge (A).
4. The microcontroller transmits the 8-bit TFA9879 register address to which the first
data byte will be written.
5. The TFA9879 asserts an acknowledge.
6. The microcontroller transmits the first byte (the most significant byte).
7. The TFA9879 asserts an acknowledge.
8. The microcontroller transmits the second byte (the least significant byte).
9. The TFA9879 asserts an acknowledge.
10. The microcontroller can either assert the stop condition (P) or continue transmitting
data by sending another pair of data bytes, repeating the sequence from step 6. In the
latter case, the targeted register address will have been auto-incremented by the
TFA9879.
Table 18.
I2C-bus write cycle
Start
TFA9879
Address
R/W
S
11011A2A1
0
TFA9879
Product data sheet
TFA9879 first
register address
A
ADDR
MSB
A
MS1
LSB
A
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LS1
A
More
data...
Stop
<....>
P
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Mono BTL class-D audio amplifier with digital input
10.3 I2C-bus read cycle
The sequence of events that needs to be followed when reading data from the TFA9879’s
I2C-bus registers is detailed in Table 19. One byte is transmitted at a time. Each of the
registers stores two bytes of data. Data is always written in byte pairs. Data transfer is
always MSB first.
The read cycle sequence using SDA is as follows:
1. The microcontroller asserts a start condition (S).
2. The microcontroller transmits the 7-bit device address of the TFA9879, followed by
the R/W bit set to 0.
3. The TFA9879 asserts an acknowledge (A).
4. The microcontroller transmits the 8-bit TFA9879 register address from which the first
data byte will be read.
5. The TFA9879 asserts an acknowledge.
6. The microcontroller asserts a repeated start (Sr).
7. The microcontroller re-transmits the device address followed by the R/W bit set to 1.
8. The TFA9879 asserts an acknowledge.
9. The TFA9879 transmits the first byte (the MSB).
10. The microcontroller asserts an acknowledge.
11. The TFA9879 transmits the second byte (the LSB).
12. The microcontroller asserts either an acknowledge or a negative acknowledge (NA).
– If the microcontroller asserts an acknowledge, the target register address is
auto-increased by the TFA9879 and steps 9 to 12 are repeated.
– If the microcontroller asserts a negative acknowledge, the TFA9879 frees the
I2C-bus and the microcontroller generates a stop condition (P).
Table 19.
I2C-bus read cycle
Start TFA9879
address
S
R/W
11011A2A1 0
First
register
address
A
ADDR
TFA9879
address
A
Sr
R/W
11011A2A1 1
MSB
A
MS1
LSB
A
LS1
More
data...
A
<....>
Stop
NA
P
10.4 Top-level register map
Table 20 describes the top-level assignment of register addresses to the functional control
and status areas. There are 21 control registers and 1 status register.
Table 20.
TFA9879
Product data sheet
Top-level register map
Register address (hex)
Default (hex)
Access Description
00h
0x0000
R/W
device control; see Table 21
01h
0x0A18
R/W
serial Interface input 1; see Table 22
02h
0x0007
R/W
PCM/IOM2 format input 1; see Table 23
03h
0x0A18
R/W
serial Interface input 2; see Table 22
04h
0x0007
R/W
PCM/IOM2 format input 2; see Table 23
05h
0x59DD
R/W
equalizer_A word_1; see Table 24
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Mono BTL class-D audio amplifier with digital input
Table 20.
Top-level register map …continued
Register address (hex)
Default (hex)
Access Description
06h
0xC63E
R/W
equalizer_A word_2; see Table 25
07h
0x651A
R/W
equalizer_B word_1; see Table 24
08h
0xE53E
R/W
equalizer_B word_2; see Table 25
09h
0x4616
R/W
equalizer_C word_1; see Table 24
0Ah
0xD33E
R/W
equalizer_C word_2; see Table 25
0Bh
0x4DF3
R/W
equalizer_D word_1; see Table 24
0Ch
0xEA3E
R/W
equalizer_D word_2; see Table 25
0Dh
0x5EE0
R/W
equalizer_E word_1; see Table 24
0Eh
0xF93E
R/W
equalizer_E word_2; see Table 25
0Fh
0x0093
R/W
bypass control; see Table 27
10h
0x92BA
R/W
dynamic range compressor; see Table 28
11h
0x12A5
R/W
bass and treble; see Table 29
12h
0x0004
R/W
high-pass filter; see Table 30
13h
0x10BD
R/W
volume control; see Table 31
14h
0x0000
R/W
de-emphasis, soft/hard mute and power
limiter; see Table 32
15h
-
R
miscellaneous status; see Table 33
The following subsections provide details of the of the bits in these registers and the
control and status functionality assigned to each.
10.4.1 Device control
Table 21.
Bit
Device control register (address 00h) bit description
Symbol
Access Default
15:5
reserved
4
INPUT_SEL
Description
0x000
R/W
0
serial interface input selection:
0: serial interface input 1
1: serial interface input 2
3
OPMODE
R/W
0
operating mode selection:
0: Off mode
1: Amplifier mode
2
reserved
1
RESET
0
R/W
0
I2C reset activation:
0: reset inactive
1: reset active; 1 is written to generate a reset, after
which the RESET bit is automatically reset to 0
0
POWERUP
R/W
0
Power-down mode selection:
0: Power-down mode
1: operating mode (dependent on OPMODE)
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Mono BTL class-D audio amplifier with digital input
10.4.2 Serial interface control
Table 22.
Bit
Serial interface control registers (addresses 01h and 03h[1]) bit description
Symbol
Access Default
15:12 reserved
Description
0000
11:10 MONO_SEL
R/W
10
mono selection:
00: left channel; left channel content is amplified in
Amplifier mode
01: right channel; right channel content is amplified in
Amplifier mode
10: left + right channels; sum of left and right
channels, divided by two, is amplified in Amplifier
mode
11: reserved
9:6
I2S_FS
R/W
1000
sample frequency (fs) of digital-in signal:
0000: 8 kHz
0001: 11.025 kHz
0010: 12 kHz
0011: 16 kHz
0100: 22.05 kHz
0101: 24 kHz
0110: 32 kHz
0111: 44.1 kHz
1000: 48 kHz
1001: 64 kHz
1010: 88.2 kHz
1011: 96 kHz
1100 to 1111: reserved
5:3
I2S_SET
R/W
011
I2S
format selection:
000: reserved
001: reserved
010: MSB-justified data up to 24 bits
011: I2S data up to 24 bits
100: LSB-justified 16-bit data
101: LSB-justified 18-bit data
110: LSB-justified 20-bit data
111: LSB-justified 24-bit data
2
SCK_POL
R/W
0
enable SCK signal polarity inversion:
0: no SCK signal polarity inversion
1: SCK signal polarity inversion enabled
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Mono BTL class-D audio amplifier with digital input
Table 22.
Serial interface control registers (addresses 01h and 03h[1]) bit description
Bit
Symbol
Access Default
Description
1:0
I_MODE
R/W
input audio mode selection:
00
00: I2S mode
01: PCM/IOM2 Short Frame Sync Format
10: PCM/IOM2 Long Frame Sync Format
11: reserved
[1]
Serial interface 1 settings are controlled via register 01h; serial interface 2 settings are controlled via
register 03h.
Table 23.
Bit
PCM/IOM2 format control registers (addresses 02h and 04h[1]) bit description
Symbol
Access Default
15:12 reserved
11
Description
0000
PCM_FS
R/W
0
PCM sample frequency:
0: 8 kHz
1: 16 kHz
10
A_LAW
R/W
0
U-LAW/A-LAW decoding selection (depending on
PCM_COMP):
0: U-law decoding; default value
1: A-law decoding
9
PCM_COMP R/W
0
companded PCM data:
0: linear
1: companded (U/A-law)
8
PCM_DL
R/W
0
PCM data length (number of bits per slot):
0: 8-bit; default value
1: 16-bit
7:4
D1_SLOT
R/W
0000
slot number position of the first sample (at 8 kHz and
16 kHz):
0000: slot 0
0001: slot 1
.. ..
1111: slot 15
3:0
D2_SLOT
R/W
0111
slot number position of the second sample (16 kHz):
0000: slot 0
0001: slot 1
.. ..
0111: slot 7
.. ..
1111: slot 15
[1]
TFA9879
Product data sheet
PCM/IOM2 format settings of serial interface 1 are controlled via register 02h; PCM/IOM2 format settings of
serial interface 2 are controlled via register 04h.
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Mono BTL class-D audio amplifier with digital input
10.4.3 Equalizer configuration
Table 24.
Equalizer word1 control registers (addresses 05h, 07h, 09h, 0Bh and 0Dh for
equalizer bands A, B, C, D and E respectively) bit description
‘x’ represents the equalizer band A, B, C, D or E
Default[1] Description
Bit
Symbol
Access
15
EQx_t1
R/W
filter configuration parameter t1; see section
Section 9.2.5.1
14:4
EQx_k1m
R/W
11 mantissa bits of filter parameter k1’; see
Section 9.2.5.1
3:0
EQx_k1e
R/W
four exponent bits of filter parameter k1’; see
Section 9.2.5.1
[1]
Default settings are given in Table 20. The corresponding equalizer configuration is shown in Table 26.
Table 25.
Equalizer word2 control register (addresses 06h, 08h, 0Ah, 0Ch and 0Eh for
equalizer bands A, B, C, D and E respectively) bit description
‘x’ represents the equalizer band A, B, C, D or E
Default[1] Description
Bit
Symbol
Access
15
EQx_t2
R/W
filter configuration parameter t2; see section
Section 9.2.5.1
14:11 EQx_k2m
R/W
four mantissa bits of filter parameter k2’; see
Section 9.2.5.1
10:8
EQx_k2e
R/W
three exponent bits of filter parameter k2’; see
Section 9.2.5.1
7:1
EQx_K0
R/W
seven-bit of filter gain parameter K0; see
Section 9.2.5.1
0
EQx_s
R/W
filter scale-factor (s); see Section 9.2.5.1
0: no scaling applied
1: −6 dB amplification enabled
[1]
Default settings are given in Table 20. The corresponding equalizer configuration is shown in Table 26.
Table 26.
Band
TFA9879
Product data sheet
Default equalizer configuration for fs = 48 kHz
A
B
C
D
E
Frequency (Hz) 100
300
1000
3000
10000
Q-factor
1.65
1.65
1.65
1.65
1.65
Gain (dB)
0
0
0
0
0
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Mono BTL class-D audio amplifier with digital input
10.4.4 Bypass control
Table 27.
Bypass control register (addresses 0Fh) bit description
Bit
Symbol
15:8
reserved
7:6
L_OCP
Access
Default
Description
0x00
R/W
10
overcurrent protection timer setting:
00: 4.5 μs floating when an overcurrent is detected
01: 27.5 μs floating when an overcurrent is detected
10: 10 ms floating when an overcurrent is detected
11: no recovery (stays floating) when an overcurrent
is detected
5:4
L_OTP
R/W
01
overtemperature protection timer setting:
00: 4.5 μs floating when an overtemperature is
detected
01: 100 ms floating when an overtemperature is
detected
10: 1 s floating when an overtemperature is detected
11: no recovery (stays floating) when an
overtemperature is detected
3
CLIPCTRL
R/W
0
clip control bypass setting, see Section 9.3:
0: clip control on (smooth clipping)
1: clip control off (maximum power)
2
HPF_BP
R/W
0
high-pass filter bypass setting:
0: high-pass filter active
1: high-pass filter bypassed
1
DRC_BP
R/W
1
dynamic range compressor bypass setting:
0: dynamic range compression active
1: dynamic range compression bypassed
0
EQ_BP
R/W
1
equalizer bypass setting:
0: equalizer active
1: equalizer bypassed
10.4.5 Dynamic range compressor
Table 28.
Bit
TFA9879
Product data sheet
DRC control register (addresses 10h) bit description
Access Default
Description
15:12 AT_LVL
Symbol
R/W
1001
dynamic range compressor attack level; see Table 11 for
the attack level as a function of the value of AT_LTV.
11:8
AT_RATE
R/W
0010
dynamic range compressor attack rate; see Table 12 for
the attack rate as a function of the value of AT_RATE
37:4
RL_LVL
R/W
1011
dynamic range compressor release level; see Table 11
for the release level as a function of the value of
RL_LTV.
3:0
RL_RATE
R/W
1010
dynamic range compressor release rate; see Table 12
for the release rate as a function of the value of
RL_RATE
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Mono BTL class-D audio amplifier with digital input
10.4.6 Bass and treble control
Table 29.
Bit
Bass and treble control register (addresses 11h) bit description
Symbol
Access
Default
Description
R/W
01001
treble gain (2 dB steps):
15:14 reserved
13:9
G_TRBLE
00000: −18 dB
00001: −16 dB
.. ..
01001: 0 dB
.. ..
10001: +16 dB
10010: +18 d8
10011 to 11111: reserved
8:7
F_TRBLE
R/W
01
treble control corner frequency, see Table 9 for the
corner frequency as a function of the value of
F_TREBLE
6:2
G_BASS
R/W
01001
bass gain (2 dB steps):
−18 dB
−16 dB
.. ..
01001: 0 dB
.. ..
+16 dB
+16 d8
reserved
1:0
F_BASS
R/W
01
bass control corner frequency, see Table 9 for the
corner frequency as a function of the value of F_BASS
10.4.7 High-pass filter
Table 30.
Symbol
15:9
reserved
8:0
HP_CTRL
[1]
TFA9879
Product data sheet
High-pass filter control register (addresses 12h) bit description
Bit
Access
Default
Description
R/W
0x04[1]
high-pass filter control, see Section 9.2.3 for a
discussion of the high pass corner frequency as a
function of the value of HP_CTRL
Default value is 04h. From Equation 1, this gives a high-pass cut-off frequency of approximately 1.6 × fs.
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Mono BTL class-D audio amplifier with digital input
10.4.8 Volume control
Table 31.
Bit
Volume control register (address 13h) bit description
Symbol
Access
Default
15:13 reserved
12
Description
000
ZR_CRSS
R/W
1
volume update at zero crossing audio stream:
0: zero-crossing volume control disabled
1: zero-crossing volume control enabled; default
value
11:8
reserved
R/W
0000
7:0
VOL
R/W
0xBD
volume control; see Table 10 for the amplification and
suppression factors as a function of the value of bits
VOL
10.4.9 De-emphasis, soft/hard mute and power limiter
Table 32.
Bit
De-emphasis, soft/hard mute and power limiter control register (address 14h) bit
description
Symbol
Access Default
15:12 reserved
Description
0000
11:10 DE_PHAS
R/W
00
de-emphasis settings, seeTable 6 for the de-emphasis
configuration for four sample rates as a function of the
value of DE_PHASE
9
R/W
0
hard mute:
H_MUTE
0: no hard mute; default value
1: hard mute enabled; implemented by PWM signal
with 50% duty-cycle
8
S_MUTE
R/W
0
soft mute; default value:
0: soft mute disabled using raised cosine
1: soft mute enabled using raised cosine
7:0
TFA9879
Product data sheet
P_LIM
R/W
0xBD
power limiter control settings; see Table 13 for
suppressions factors as a function of the value of P_LIM
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Mono BTL class-D audio amplifier with digital input
10.4.10 Miscellaneous status
Table 33.
Miscellaneous status register (address 15h) bit description
Bit
Symbol
15
reserved
14
PS
Access
Description
R
power stage status:
0: class-D audio amplifier power stage floating
1: class-D audio amplifier power stage switching; PWM signals
on pins OUTA and OUTB
13
PORA
R
analog 1V8 regulator status:
0: 1V8 analog regulator is off or output voltage level is too low
1: 1V8 analog regulator output is available and correct
12:11 reserved
10:9
AMP
R
Amplifier mode status:
00: amplifier is off
01: startup
10: startup
11: amplifier is functional
8
IBP(2)
R
invalid bit clock protection on serial interface input 2:
0: the ratio in frequency between the signal on pin SCK2 and
the signal on pin LRCK2 is valid for the selected interface
format
1: the ratio in frequency between the signal on pin SCK2 and
the signal on pin LRCK2 is invalid for the selected interface
format
7
OFP(2)
R
overfrequency protection on serial interface input 2:
0: the frequency of the signal on pin LRCK2 is in line with (or
lower than) the selected interface format
1: the frequency of the signal on pin LRCK2 is higher than the
selected interface format
6
UFP(2)
R
underfrequency protection on serial interface input 2:
0: the frequency of the signal on pin LRCK2 is in line with (or
higher than) the selected interface format
1: the frequency of the signal on pin LRCK2 is lower than the
selected interface format
5
IBP(1)
R
invalid bit clock protection on serial interface input 1:
0: the ratio in frequency between the signal on pin SCK1 and
the signal on pin LRCK1 is valid for the selected interface
format
1: the ratio in frequency between the signal on pin SCK1 and
the signal on pin LRCK1 is invalid for the selected interface
format
4
OFP(1)
R
overfrequency protection on serial interface input 1:
0: the frequency of the signal on pin LRCK1 is in line with (or
lower than) the selected interface format
1: the frequency of the signal on pin LRCK1 is higher than the
selected interface format
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Mono BTL class-D audio amplifier with digital input
Table 33.
Miscellaneous status register (address 15h) bit description …continued
Bit
Symbol
Access
Description
3
UFP(1)
R
underfrequency protection on serial interface input 1:
0: the frequency of the signal on pin LRCK1 is in line with (or
higher than) the selected interface format
1: the frequency of the signal on pin LRCK1 is lower than the
selected interface format
2
OCPOKA
R
overcurrent protection on pin OUTA:
0: overcurrent protection on pin OUTA active
1: overcurrent protection on pin OUTA inactive
1
OCPOKB
R
overcurrent protection on pin OUTB:
0: overcurrent protection on pin OUTB active
1: overcurrent protection on pin OUTB inactive
1
OTPOK
R
overtemperature protection:
0: overtemperature protection active
1: overtemperature protection inactive
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Mono BTL class-D audio amplifier with digital input
11. Internal circuitry
Table 34.
Internal circuitry
Pin
Symbol
1
SDA
Equivalent circuit
1
ESD
11, 12, 24
010aaa632
2
SCL
3
TEST1
4
ADSEL2
5
TEST3
16
ADSEL1
17
SDI2
18
SCK2
19
LRCK2
20
SDI1
21
SCK1
22
LRCK2
7,8
VDDP
2 to 5
16 to 22
ESD
11, 12, 24
010aaa633
7, 8
ESD
11, 12, 24
010aaa634
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Mono BTL class-D audio amplifier with digital input
Table 34.
Internal circuitry
Pin
Symbol
9
OUTB
10
OUTA
Equivalent circuit
7, 8
9, 10
11, 12, 24
010aaa635
13
STABA
7,8
13
ESD
11, 12, 24
010aaa636
15
TEST2
7, 8
15
ESD
11, 12, 24
010aaa637
12. Limiting values
Table 35. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDDA
analog supply voltage
on pin VDDP
−0.3
+5.5
V
VDDD
digital supply voltage
on pin VDDD
−0.3
+1.95
V
Tj
junction temperature
-
+150
°C
Tstg
storage temperature
−55
+150
°C
Tamb
ambient temperature
−20
+85
°C
Vx
voltage on pin x
pins LRCKx, SCKx, SDIx, SDA, SCL,
ADSEL1, ADSEL2, TEST1 and TEST3
−0.3
+3.6
V
pin TEST2
−0.3
VDDP + 0.3
V
pins OUTA and OUTB
−0.6
VDDP + 0.6
V
pin STABA
−0.3
+1.95
according to Human Body Model (HBM)
−2
+2
kV
according to Charge Device Model (CDM)
−500
+500
V
VESD
electrostatic discharge voltage
TFA9879
Product data sheet
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Mono BTL class-D audio amplifier with digital input
13. Thermal characteristics
Table 36.
Thermal characteristics
Symbol
Parameter
Conditions
Rth(j-a)
thermal resistance from junction to ambient
in free air with natural convection
JEDEC test board
[1]
2-layer application board
Ψj-lead
thermal characterization parameter from
junction to lead
Ψj-top
thermal characterization parameter from
junction to top of package
Rth(j-c)
thermal resistance from junction to case
[2]
in free air with natural convection
[1]
Measured on a JEDEC high K-factor test board (standard EIA/JESD 51-7).
[2]
Value depends on where measurement is taken on package.
TFA9879
Product data sheet
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Rev. 02 — 15 October 2010
Typ
Unit
49
K/W
67
K/W
23
K/W
6
K/W
5
K/W
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Mono BTL class-D audio amplifier with digital input
14. Characteristics
14.1 DC Characteristics
Table 37. DC characteristics
All parameters are guaranteed for VDDD = 1.8 V; VDDP = 3.7 V; RL = 8 Ω; LL = 44 μH; fi = 1 kHz; fs = 48 kHz; clip control off;
Tamb = 25 °C unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDP
power supply voltage
on pin VDDP
2.5
-
5.5
V
VDDD
digital supply voltage
on pin VDDD
1.65
1.8
1.95
V
IP
supply current
on pin VDDP; Amplifier mode with
load; soft mute on
-
5.7
-
mA
on pin VDDP; Power-down mode
-
-
20
μA
-
1.2
-
mA
-
5
15
μA
lower switch (NMOS)
-
190
-
mΩ
upper switch (PMOS)
-
260
-
mΩ
−15
0
+15
mV
1.65
-
1.95
V
V
IDDD
digital supply current
on pin VDDD; Amplifier mode
on pin VDDD; Power-down mode
[1]
Series resistance output power switches
RDSon
drain-source on-state resistance
Amplifier output pins; OUTA and OUTB
VO(offset)
output offset voltage
Regulator, pin STABA
VO(reg)
regulator output voltage
STABA to GNDP
LRCK1, SCK1, SDI1, LRCK2, SCK2, SDI2, SDA, SCL, ADSEL1 and ADSEL2
VIH
HIGH-level input voltage
0.7VDDD
-
-
VIL
LOW-level input voltage
-
-
0.3VDDD V
Ci
input capacitance
-
-
3
pF
VOL
LOW-level output voltage
-
-
400
mV
at IOL = 2.6 mA
Protection
Tact(th_prot)
thermal protection activation
temperature
130
-
-
°C
IO(ocp)
overcurrent protection output current
1.3
-
2.3
A
fOFP
overfrequency protection frequency
at PWM output frequency
-
710
1031
kHz
fUFP
underfrequency protection frequency
at PWM output frequency
96
175
-
kHz
[1]
After switching from Off/Amplifier mode to Power-down mode.
TFA9879
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Mono BTL class-D audio amplifier with digital input
14.2 AC characteristics
Table 38. AC characteristics
All parameters are guaranteed for VDDD = 1.8 V; VDDP = 3.7 V; RL = 8 Ω; LL = 44 μH; fi = 1 kHz; fs = 48 kHz; clip control off;
Tamb = 25 °C unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
THD+N = 1 %
0.65
0.7
-
W
THD+N = 10 %
-
0.85
-
W
THD+N = 1 %
-
1.2
-
W
THD+N = 10 %
-
1.5
-
W
THD+N = 1 %
-
0.9
-
W
THD+N = 10 %
-
1.1
-
W
THD+N = 1 %
-
1.6
-
W
THD+N = 10 %
-
1.95
-
W
THD+N = 1 %
-
1.35
-
W
THD+N = 10 %
-
1.6
-
W
THD+N = 1 %
-
2.35
-
W
THD+N = 10 %
-
2.75
-
W
-
92
-
%
Class D amplifier
Po(RMS)
RMS output power
RL = 8 Ω
RL = 4 Ω
RL = 8 Ω; VDDP = 4.2 V
RL = 4 Ω; VDDP = 4.2 V
RL = 8 Ω; VDDP = 5.0 V
RL = 4 Ω; VDDP = 5.0 V
ηpo
output power efficiency
Po(RMS) = 850 mW
THD+N
total harmonic distortion-plus-noise Po(RMS) = 100 mW
-
0.02
0.1
%
Vn(o)
output noise voltage
soft mute; A-weighted
-
60
-
μV
S/N
signal-to-noise ratio
VPVDD = 5 V; Po(RMS) = 1.3 W; A-weighted
-
94
-
dB
PSRR
power supply rejection ratio
Vripple = 200 mV; fripple = 217 Hz
65
80
-
dB
Vo(RMS)
RMS output voltage
At −9 dBFS (RMS) digital input
volume control = 0 dB
bass and treble control = 0 dB
equalizer bypassed and DRC bypassed
1.9
2.1
2.3
V
-
-
5.6
ms
-
-
2.67
ms
-
-
2.67
ms
-
600
-
μs
Power-up, power-down and propagation times
td(on)
turn-on delay time
td(mute_off)
mute off delay time
td(soft_mute)
soft mute delay time
tPD
propagation delay
TFA9879
Product data sheet
Off mode to Operating mode, soft de-mute
excluded
bass and treble control = 0 dB, equalizer
bypassed and DRC bypassed.
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TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
14.3 I2C timing characteristics
Table 39. I2C-bus interface characteristics; see Figure 14
All parameters are guaranteed for VDDP = 3.7 V, RL = 8 Ω, LL = 44 μH; fi = 1 kHz; fs = 48 kHz; clip control off; Tamb = 25 °C
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCL
tLOW
SCL clock frequency
-
-
400
kHz
LOW period of the SCL clock
1.3
-
-
μs
tHIGH
HIGH period of the SCL clock
rise time
tr
0.6
-
-
μs
SDA and SCL signals
[1]
20 + 0.1 Cb
-
-
ns
SDA and SCL signals
[1]
20 + 0.1 Cb
-
-
ns
[2]
0.6
-
-
μs
tf
fall time
tHD;STA
hold time (repeated) START
condition
tSU;STA
set-up time for a repeated START
condition
0.6
-
-
μs
tSU;STO
set-up time for STOP condition
0.6
-
-
μs
tBUF
bus free time between a STOP and
START condition
1.3
-
-
μs
tSU;DAT
data set-up time
100
-
-
ns
tHD;DAT
data hold time
0
-
-
μs
tSP
pulse width of spikes that must be
suppressed by the input filter
0
-
50
ns
Cb
capacitive load for each bus line
-
-
400
pF
[1]
Cb is the total capacitance of one bus line in pF. The maximum capacitive load for each bus line is 400 pF.
[2]
After this period, the first clock pulse is generated.
SDA
tLOW
tBUF
tr
tf
tHD;STA
tSP
SCL
tHD;STA
P
tHD;DAT
tHIGH
tSU;DAT
S
tSU;STA
Sr
tSU;STO
P
010aaa225
Fig 14. I2C timing
TFA9879
Product data sheet
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TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
14.4 I2S timing characteristics
Table 40. I2S bus interface characteristics; see Figure 15
All parameters are guaranteed for VDDD = 1.8 V; VDDP = 3.7 V, RL = 8 Ω[1], LL = 44 μH[1]; fi = 1 kHz; clip control off;
Tamb = 25 °C unless otherwise specified.
Symbol
Parameter
fs
sampling frequency
fclk
clock frequency
tsu
set-up time
hold time
th
[1]
Conditions
Min
Typ
Max
Unit
on LRCK1 or LRCK2 pins
8
-
96
kHz
on SCK1 or SCK2 pins
32fs
-
64fs
Hz
LRCK edge to SCK HIGH
10
-
-
ns
SDI edge to SCK HIGH
10
-
-
ns
SCK HIGH to LRCK edge
10
-
-
ns
SCK HIGH to SDI edge
10
-
-
ns
RL = load resistance; LL = load inductance.
SCK
th
tsu
LRCK
SDI
010aaa624
Fig 15. I2S timing
TFA9879
Product data sheet
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42 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
14.5 PCM/IOM2 timing characteristics
Table 41. PCM/IOM2 characteristics; see Figure 16
All parameters are guaranteed for VDDD = 1.8 V; VDDP = 3.7 V, RL = 8 Ω[1], LL = 44 μH[1]; fi = 1 kHz; clip control off;
Tamb = 25 °C unless otherwise specified.
Symbol
Parameter
fp
pulse frequency
fclk
clock frequency
tsu
set-up time
hold time
th
pulse duration
tp
[1]
Conditions
Min
Typ
Max
Unit
on LRCK1 or LRCK2 pins
-
-
8
kHz
on SCK1 or SCK2 pin
16fp
-
192fp
Hz
SCK HIGH to LRCK edge
10
-
-
ns
SCK HIGH to SDI edge
10
-
-
ns
LRCK edge to SCK HIGH
10
-
-
ns
SDI edge to SCK HIGH
10
-
-
ns
pulse on LRCK1 pin or LRCK2 pin
1/fclk
-
-
s
RL = load resistance; LL = load inductance.
SCK
th
tsu
LRCK, FSC (long)
tp
LRCK, FSC (short)
SDI
010aaa625
Fig 16. PCM/IOM2 timing
TFA9879
Product data sheet
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TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
15. Application information
The TFA9879 is a filter-free BTL class-D amplifier that uses a fixed frequency PWM
modulation scheme (see the simplified application schematic in Figure 18). When the
TFA9879 is idle (no audio input signal), the voltage across the speaker is 0 V, generating
no additional current. Even when the PWM output is modulated by the audio input signal,
the out-of-band AC ripple current in the voice coil is very small compared to the audio
current. This is due to the inductive behavior of the voice coil at the PWM switching
frequency. A typical voice coil inductance is in the range 30 μH to 80 μH.
15.1 Power capability
15.1.1 Estimating the RMS output power (Po(RMS))
The RMS output power, Po(RMS), at THD + N = 1 % just before clipping can be estimated
using Equation 11, with clip-control off, or using Equation 12, with clip-control on.
Clip control off:
P o ( RMS )1%
2
RL
⎛ ⎛ -----------------------------------------------------⎞ × V DDP⎞
⎝ ⎝ R L + R S + ( 2 × R DSon )⎠
⎠
= ---------------------------------------------------------------------------------------2 × RL
(11)
Clip control on:
P o ( RMS )1%
2
RL
⎛ ⎛ -----------------------------------------------------⎞ × M max × V DDP⎞
⎝ ⎝ R L + R S + ( 2 × R DSon )⎠
⎠
= ----------------------------------------------------------------------------------------------------------2 × RL
(12)
where:
RL = load resistance (Ω)
RS = total series resistance of application
RDSon = on-resistance of power switch (typically 230 mΩ)
VDDP = power supply voltage (V)
Mmax = maximum modulation depth (clip control on); typically 0.9
Example (clip control off):
With VDDP = 5 V, RDSon = 0.23 Ω (at Tj = 25 °C), RS = 0.14 Ω:
Po(RMS)1% = 1.35 W in an 8 Ω load or
Po(RMS)1% = 2.35 W in a 4 Ω load
The RMS output power at THD + N = 10 % can be estimated using Equation 13:
P 0 ( RMS )10% = 1.25 × P 0 ( RMS )1%
TFA9879
Product data sheet
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(13)
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TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
15.1.2 Output current limiting
The peak output current IO(max) is limited internally by OCP. The minimum OCP trigger
level is 1.3 A. During normal operation, the output current should not exceed this
threshold level, otherwise the audio signal will be distorted. The peak output current in
BTL configuration can be calculated using Equation 14:
V DDP
I O ( max ) ≤ I O ( OCP ) ≤ ------------------------------------- ≤ 1.3A
2 × R DSon + R L
(14)
where:
VDDP = power supply voltage (V)
RL = load resistance (Ω)
RDSon = drain-source on-state resistance (Ω)
Example:
A 4 Ω speaker can be used with a 5 V supply without triggering OCP.
15.2 PWM output filtering
The TFA9879 PWM power stage is optimized to meet the legal limits (FCC) for radiated
emissions without requiring an external filter (speaker cable < 5 cm). But a low-pass LC
filter is recommended if a long speaker cable can’t be avoided or other components in the
application are sensitive to frequencies in the 10 MHz to 150 MHz range (e.g. an FM
tuner). The suggested differential low-pass filter consists of a ferrite bead inductor (Z >
80 Ω at 100 MHz) and a small ceramic capacitor of about 1 nF (see Figure 17).
TFA9879
CLASS-D AMPLIFIER
speaker cables > 5 cm
OUTA
OUTB
ferrite bead
1 nF
1 nF
010aaa626
Fig 17. Optional low-pass LC filter
15.3 Supply decoupling and filtering
A ceramic decoupling capacitor of between 1 μF and 10 μF should be placed close to the
TFA9879 to minimize the size of the high-frequency current loop, thereby optimizing EMC
performance. Optionally, a small 1 nF ceramic capacitor can be connected in parallel to
further reduce the impedance.
TFA9879
Product data sheet
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45 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
15.4 PCB layout considerations
Great care should be taken when designing the PCB layout for a Class-D amplifier circuit
as the layout can affect the audio performance, the EMC performance and/or the thermal
performance, and can even affect the functionality of the TFA9879.
15.4.1 EMC considerations
The decoupling capacitors on pins VDDD, VDDP and STABA should be placed close to the
TFA9879, referenced to a solid ground plane. The exposed DAP should also be
connected to this ground plane.
15.4.2 Thermal considerations
The TFA9879 is available in a thermally enhanced HVQFN24 (SOT616-3) package for
reflow soldering. The HVQFN24 has an exposed DAP that significantly reduces the
thermal resistance, Rth(j-a). To achieve a lower overall thermal resistance, the exposed
DAP should be soldered to a thermal copper plane. Increasing the area of the thermal
plane, the number of planes or the copper thickness can further reduce the thermal
resistance. The typical thermal resistance (free air and natural convection) of a practical
PCB implementation is:
Rth(j-a) = 67 K/W for a two-layer application board (18 mm × 22 mm, 35 μm copper, FR4
base material).
Equation 15 describes the relationship between the maximum allowable power dissipation
(P) and the thermal resistance from junction to ambient.
T j ( max ) – T amb
R th ( j-a ) = ---------------------------------P
(15)
where:
Rth(j-a) = thermal resistance from junction to ambient
Tj(max) = maximum junction temperature (125 °C)
Tamb = ambient temperature
P = power dissipated in the TFA9879
OTP will limit the maximum junction temperature to 130 °C to avoid thermal damage.
TFA9879
Product data sheet
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TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
15.5 Typical application diagram (simplified)
BASEBAND
PROCESSOR
battery
LRCK1
SCK1
I2S output
SDI1
22
7
21
8
VDDP
VDDP
20
10
OUTA
LRCK2
19
SDA
SDA
ADSEL1
address select 1
ADSEL2
address select 2
VDDD
1.8 V
GNDD
CVDDD
12
1
CVDDP
10 μF
GNDP
16
4
13
23
24
3
TEST1
100 nF
11
2
GNDP
5
6, 14
STABA
CSTABA
100 nF
15
DAP
SCL
SCL
TEST2
MULTIMEDIA
PROCESSOR
OUTB
17
n.c.
SDI2
9
18
TEST3
SCK2
I2S output
speaker
4 Ω or 8 Ω
TFA8979HN
010aaa545
Fig 18. Typical application (simplified)
TFA9879
Product data sheet
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© NXP B.V. 2010. All rights reserved.
47 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
15.6 Curves measured in reference design (demonstration board)
All measurements were taken with VDDD = 1.8 V, fs = 48 kHz, clip control on and the
high-pass filter off, unless otherwise specified.
010aaa675
102
THD+N
(%)
THD+N
(%)
10
10
1
1
10−1
010aaa676
102
10−1
(1)
(1)
(3)
10−2
10−3
10−2
10−1
(2)
10−2
(2)
(3)
1
10
10−3
10−2
10−1
1
Po (W)
(1) fi = 6 kHz.
(1) fi = 6 kHz.
(2) fi = 1 kHz.
(2) fi = 1 kHz.
(3) fi = 100 Hz.
(3) fi = 100 Hz.
a. VDDP = 3.7 V, RL = 8 Ω
b. VDDP = 5 V, RL = 8 Ω
010aaa677
102
010aaa678
102
THD+N
(%)
THD+N
(%)
10
10
1
1
10−1
10
Po (W)
10−1
(1)
(1)
(2)
10−2
10−3
10−2
(2)
(3)
10−1
10−2
1
10
10−3
10−2
(3)
10−1
Po (W)
10
Po (W)
(1) fi = 6 kHz.
(1) fi = 6 kHz.
(2) fi = 1 kHz.
(2) fi = 1 kHz.
(3) fi = 100 Hz.
(3) fi = 100 Hz.
c. VDDP = 3.7 V, RL = 4 Ω
1
d. VDDP = 5 V, RL = 4 Ω
Fig 19. Total harmonic distortion-plus-noise as a function of output power
TFA9879
Product data sheet
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Rev. 02 — 15 October 2010
© NXP B.V. 2010. All rights reserved.
48 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
010aaa679
102
THD+N
(%)
THD+N
(%)
10
10
1
1
10−1
010aaa680
102
10−1
(2)
(1)
10−2
10−2
(1)
(2)
10−3
10
102
103
104
105
10−3
10
102
103
104
f (Hz)
(1) Po = 100 mW
(1) Po = 100 mW
(2) Po = 500 mW
(2) Po = 500 mW
a. VDDP = 3.7 V, RL = 8 Ω
b. VDDP = 5 V, RL = 8 Ω
010aaa681
102
010aaa682
102
THD+N
(%)
THD+N
(%)
10
10
1
1
10−1
10−1
(1)
10−2
(1)
10−2
(2)
10−3
10
102
105
f (Hz)
103
104
105
(2)
10−3
10
102
103
f (Hz)
105
f (Hz)
(1) Po = 100 mW
(1) Po = 100 mW
(2) Po = 500 mW
(2) Po = 1 W
c. VDDP = 3.7 V, RL = 4 Ω
104
d. VDDP = 5 V, RL = 4 Ω
Fig 20. Total harmonic distortion-plus-noise as a function of frequency
TFA9879
Product data sheet
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49 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
010aaa683
102
THD+N
(%)
010aaa684
102
THD+N
(%)
10
10
1
1
(4)
(4)
10−1
10−1
(2)
(3)
10−2
(3)
10−2
(1)
(2)
(1)
10−3
10
102
103
104
105
10−3
10
102
103
f (Hz)
104
105
f (Hz)
(1) Vripple = 0 V (fripple = 0 Hz)
(1) Vripple = 0 V (fripple = 0 Hz)
(2) fripple = 217 Hz
(2) fripple = 217 Hz
(3) fripple = 1 kHz
(3) fripple = 1 kHz
(4) fripple = 6 kHz
(4) fripple = 6 kHz
a. VDDP = 3.7 V, RL = 8 Ω, Po = 100 mW,
Vripple = 200 mV (RMS)
b. VDDP = 5 V, RL = 8 Ω, Po = 100 mW,
Vripple = 200 mV (RMS)
Fig 21. Total harmonic distortion-plus-noise and power supply intermodulation distortion as a function of
frequency
010aaa685
10
G
dB
010aaa686
0
PSRR
(dB)
(1)
−20
0
(2)
(3)
−10
−40
−20
−60
−30
−80
(1)
(2)
−40
10
102
103
104
105
−100
10
102
f (Hz)
VDDP = 3.7 V, RL = 8 Ω, Po = 500 mW
103
105
104
fripple (Hz)
VDDP = 5 V, RL = 8 Ω, ripple = 200 mV (RMS)
(1) high-pass filter off
(1) VDDP = 3.7 V
(2) high-pass filter cut-off frequency: 100 Hz
(2) VDDP = 5 V
(3) high-pass filter cut-off frequency: 500 Hz
Fig 22. Normalized gain as a function of frequency
TFA9879
Product data sheet
Fig 23. Power supply rejection ration as a function of
ripple frequency
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TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
010aaa687
120
S/N
(dB)
100
(1)
80
(2)
60
40
20
10−2
10−1
1
10
Po (W)
VDDP = 5 V, RL = 8 Ω, reference signal: 3.5 V (RMS)
(1) A-weighted
(2) 20 kHz brickwall filter
Fig 24. Signal-to-noise ratio as a function of output power
010aaa688
4
Po
(W)
010aaa689
4
Po
(W)
3
3
(4)
(3)
(4)
2
2
(3)
(2)
(2)
1
(1)
1
(1)
0
0
2
3
4
5
6
2
3
4
VDDP (V)
5
6
VDDP (V)
(1) THD+N = 1 %, RL = 8 Ω
(1) THD+N = 1 %, RL = 8 Ω
(2) THD+N = 10 %, RL = 8 Ω
(2) THD+N = 10 %, RL = 8 Ω
(3) THD+N = 1 %, RL = 4 Ω
(3) THD+N = 1 %, RL = 4 Ω
(4) THD+N = 10 %, RL = 4 Ω
(4) THD+N = 10 %, RL = 4 Ω
a. fi = 100 Hz, clip control on
b. fi = 100 Hz, clip control off
Fig 25. Output power as a function of supply voltage
TFA9879
Product data sheet
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51 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
010aaa694
0.20
010aaa696
0.5
P
(W)
P
(W)
0.4
0.15
0.3
0.10
0.2
0.05
(2)
0.1
(2)
(1)
0.00
10−3
10−2
10−1
1
10
0.0
10−3
(1)
10−2
10−1
1
Po (W)
10
Po (W)
(1) VDDP = 3.7 V
(1) VDDP = 3.7 V
(2) VDDP = 5 V
(2) VDDP = 5 V
a. RL = 8 Ω, fi = 1 kHz, clip control off
b. RL = 4 Ω, fi = 1 kHz, clip control off
Fig 26. Power dissipation as a function of output power
010aaa695
100
(1)
η
(%)
010aaa697
100
(1)
η
(%)
(2)
(2)
80
80
60
60
40
40
20
20
0
0
0
0.5
1
1.5
2
0
Po (W)
1
2
3
Po (W)
(1) VDDP = 3.7 V
(1) VDDP = 3.7 V
(2) VDDP = 5 V
(2) VDDP = 5 V
a. RL = 8 Ω, fi = 1 kHz, clip control off
b. RL = 4 Ω, fi = 1 kHz, clip control off
Fig 27. Efficiency as a function of output power
TFA9879
Product data sheet
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52 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
16. Package outline
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.85 mm
A
B
D
SOT616-3
terminal 1
index area
A
A1
E
c
detail X
e1
C
1/2
e
e
7
12
y
y1 C
v M C A B
w M C
b
L
13
6
e
e2
Eh
1/2
e
1
18
terminal 1
index area
24
19
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
4.1
3.9
2.75
2.45
4.1
3.9
2.75
2.45
0.5
2.5
2.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT616-3
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
04-11-19
05-03-10
Fig 28. Package outline TFA9879 (HVQFN24)
TFA9879
Product data sheet
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TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
TFA9879
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 15 October 2010
© NXP B.V. 2010. All rights reserved.
54 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 29) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 42 and 43
Table 42.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 43.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 29.
TFA9879
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 15 October 2010
© NXP B.V. 2010. All rights reserved.
55 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 29. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
TFA9879
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 15 October 2010
© NXP B.V. 2010. All rights reserved.
56 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
18. Revision history
Table 44.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TFA9879 v.2
20101015
Product data sheet
-
TFA9879 v.1
Modifications:
TFA9879 v.1
TFA9879
Product data sheet
•
Specification status changed to Product data sheet
20100408
Preliminary data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 15 October 2010
-
© NXP B.V. 2010. All rights reserved.
57 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
TFA9879
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 15 October 2010
© NXP B.V. 2010. All rights reserved.
58 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
TFA9879
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 15 October 2010
© NXP B.V. 2010. All rights reserved.
59 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
21. Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
General description . . . . . . . . . . . . . . . . . . . . . . 1
3
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3.1
General features . . . . . . . . . . . . . . . . . . . . . . . . 1
3.2
Programmable Digital Sound Processor (DSP) 2
3.3
Interface format support for digital audio inputs 2
4
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5
Quick reference data . . . . . . . . . . . . . . . . . . . . . 3
6
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
8
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
8.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
8.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
9
Functional description . . . . . . . . . . . . . . . . . . . 6
9.1
Operating modes . . . . . . . . . . . . . . . . . . . . . . . 7
9.1.1
Power-up/power-down . . . . . . . . . . . . . . . . . . . 7
9.1.2
Supported Digital audio data formats . . . . . . . . 8
9.2
Digital Signal Processor (DSP) features. . . . . 11
9.2.1
Serial interface selection . . . . . . . . . . . . . . . . 11
9.2.2
Mono selection . . . . . . . . . . . . . . . . . . . . . . . . 11
9.2.3
Programmable high-pass filter . . . . . . . . . . . . 11
9.2.4
De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . 11
9.2.5
Equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
9.2.5.1
Equalizer band function . . . . . . . . . . . . . . . . . 12
9.2.5.2
Equalizer band control . . . . . . . . . . . . . . . . . . 14
9.2.6
Bass and treble control . . . . . . . . . . . . . . . . . . 16
9.2.7
Muting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9.2.8
Digital volume control . . . . . . . . . . . . . . . . . . . 18
9.2.9
Zero-crossing volume control . . . . . . . . . . . . . 18
9.2.10
Dynamic Range Compressor (DRC) . . . . . . . 18
9.2.10.1 Functional description. . . . . . . . . . . . . . . . . . . 19
9.2.10.2 DRC control . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9.2.11
Power limiter . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.3
Class-D amplification and clip control. . . . . . . 22
9.4
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.4.1
OverTemperature Protection (OTP) . . . . . . . . 23
9.4.2
OverCurrent Protection (OCP) . . . . . . . . . . . . 23
9.4.3
UnderFrequency Protection (UFP) . . . . . . . . . 23
9.4.4
OverFrequency Protection (OFP) . . . . . . . . . . 24
9.4.5
Invalid Bit-clock Protection (IBP) . . . . . . . . . . 24
9.4.6
Overview of protection circuits . . . . . . . . . . . . 24
10
I2C-bus interface and register settings . . . . . 24
10.1
I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 24
10.2
I2C-bus write cycle . . . . . . . . . . . . . . . . . . . . . 25
10.3
I2C-bus read cycle . . . . . . . . . . . . . . . . . . . . . 26
10.4
Top-level register map . . . . . . . . . . . . . . . . . . 26
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
10.4.6
10.4.7
10.4.8
10.4.9
Device control . . . . . . . . . . . . . . . . . . . . . . . .
Serial interface control . . . . . . . . . . . . . . . . . .
Equalizer configuration . . . . . . . . . . . . . . . . .
Bypass control . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic range compressor . . . . . . . . . . . . . .
Bass and treble control . . . . . . . . . . . . . . . . .
High-pass filter . . . . . . . . . . . . . . . . . . . . . . . .
Volume control . . . . . . . . . . . . . . . . . . . . . . . .
De-emphasis, soft/hard mute and power
limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.4.10 Miscellaneous status . . . . . . . . . . . . . . . . . . .
11
Internal circuitry . . . . . . . . . . . . . . . . . . . . . . .
12
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
13
Thermal characteristics . . . . . . . . . . . . . . . . .
14
Characteristics . . . . . . . . . . . . . . . . . . . . . . . .
14.1
DC Characteristics . . . . . . . . . . . . . . . . . . . . .
14.2
AC characteristics . . . . . . . . . . . . . . . . . . . . .
14.3
I2C timing characteristics . . . . . . . . . . . . . . . .
14.4
I2S timing characteristics . . . . . . . . . . . . . . . .
14.5
PCM/IOM2 timing characteristics. . . . . . . . . .
15
Application information . . . . . . . . . . . . . . . . .
15.1
Power capability . . . . . . . . . . . . . . . . . . . . . . .
15.1.1
Estimating the RMS output power (Po(RMS)) .
15.1.2
Output current limiting . . . . . . . . . . . . . . . . . .
15.2
PWM output filtering. . . . . . . . . . . . . . . . . . . .
15.3
Supply decoupling and filtering . . . . . . . . . . .
15.4
PCB layout considerations. . . . . . . . . . . . . . .
15.4.1
EMC considerations. . . . . . . . . . . . . . . . . . . .
15.4.2
Thermal considerations . . . . . . . . . . . . . . . . .
15.5
Typical application diagram (simplified) . . . . .
15.6
Curves measured in reference design
(demonstration board) . . . . . . . . . . . . . . . . . .
16
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
17
Soldering of SMD packages . . . . . . . . . . . . . .
17.1
Introduction to soldering. . . . . . . . . . . . . . . . .
17.2
Wave and reflow soldering. . . . . . . . . . . . . . .
17.3
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
17.4
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
18
Revision history . . . . . . . . . . . . . . . . . . . . . . .
19
Legal information . . . . . . . . . . . . . . . . . . . . . .
19.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
19.2
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.3
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
19.4
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
20
Contact information . . . . . . . . . . . . . . . . . . . .
21
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
28
30
31
31
32
32
33
33
34
36
37
38
39
39
40
41
42
43
44
44
44
45
45
45
46
46
46
47
48
53
54
54
54
54
55
57
58
58
58
58
59
59
60
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 15 October 2010
Document identifier: TFA9879

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