TI TL16C554FN

TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
D
D
D
D
D
D
D
D
Integrated Asynchronous Communications
Element
Consists of Four Improved TL16C550 ACEs
Plus Steering Logic
In FIFO Mode, Each ACE Transmitter and
Receiver Is Buffered With 16-Byte FIFO to
Reduce the Number of Interrupts to CPU
In TL16C450 Mode, Hold and Shift
Registers Eliminate Need for Precise
Synchronization Between the CPU and
Serial Data
Up to 16-MHz Clock Rate for up to 1-Mbaud
Operation
Programmable Baud Rate Generators
Which Allow Division of Any Input
Reference Clock by 1 to (216 – 1) and
Generate an Internal 16 × Clock
Adds or Deletes Standard Asynchronous
Communication Bits (Start, Stop, and
Parity) to or From the Serial Data Stream
Independently Controlled Transmit,
Receive, Line Status, and Data Set
Interrupts
D
D
D
D
D
D
D
D
Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (DC to 1-Mbit Per
Second)
False Start Bit Detection
Complete Status Reporting Capabilities
Line Break Generation and Detection
Internal Diagnostic Capabilities:
– Loopback Controls for Communications
Link Fault Isolation
– Break, Parity, Overrun, Framing Error
Simulation
Fully Prioritized Interrupt System Controls
Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
3-State Outputs Provide TTL Drive
Capabilities for Bidirectional Data Bus and
Control Bus
description
The TL16C554 and the TL16C554I are enhanced quadruple versions of the TL16C550B asynchronous
communications element (ACE). Each channel performs serial-to-parallel conversion on data characters
received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted
by the CPU. The complete status of each channel of the quadruple ACE can be read at any time during functional
operation by the CPU. The information obtained includes the type and condition of the operation performed and
any error conditions encountered.
The TL16C554 and the TL16C554I quadruple ACE can be placed in an alternate FIFO mode, which activates
the internal FIFOs to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in
both receive and transmit modes. To minimize system overhead and maximize system efficiency, all logic is on
the chip. Two terminal functions allow signaling of direct memory access (DMA) transfers. Each ACE includes
a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and
(216 – 1).
The TL16C554 and the TL16C554I are available in a 68-pin plastic-leaded chip-carrier (PLCC) FN package and
in an 80-pin (TQFP) PN package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
DCDA
RIA
RXA
GND
D7
D6
D5
D4
D3
D2
D1
D0
INTN
VCC
RXD
RID
DCDD
FN PACKAGE
(TOP VIEW)
9
10
8 7
6
5 4 3 2
1 68 67 66 65 64 63 62 61
60
11
59
12
58
13
57
14
56
15
55
16
54
17
53
18
52
19
51
20
50
21
49
22
48
23
47
24
46
25
45
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
DCDB
RIB
RXB
VCC
NC
A2
A1
A0
XTAL1
XTAL2
RESET
RXRDY
TXRDY
GND
RXC
RIC
DCDC
DSRA
CTSA
DTRA
VCC
RTSA
INTA
CSA
TXA
IOW
TXB
CSB
INTB
RTSB
GND
DTRB
CTSB
DSRB
NC – No internal connection
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
DSRD
CTSD
DTRD
GND
RTSD
INTD
CSD
TXD
IOR
TXC
CSC
INTC
RTSC
VCC
DTRC
CTSC
DSRC
TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
RIB
DCDB
NC
NC
DCDC
RIC
RXC
GND
TXRDY
RXRDY
RESET
NC
XTAL2
XTAL1
NC
A0
A1
A2
VCC
RXB
PN PACKAGE
(TOP VIEW)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
NC
DSRC
CTSC
DTRC
VCC
RTSC
INTC
CSC
TXC
IOR
NC
TXD
CSD
INTD
RTSD
GND
DTRD
CTSD
DSRD
NC
61
40
62
39
63
38
64
37
65
36
66
35
67
34
68
33
69
32
70
31
71
30
72
29
73
28
74
27
75
26
76
25
77
24
78
23
79
22
80
4 5
6
21
7 8 9 10 11 12 13 14 15 16 17 18 19 20
NC
DCDD
RID
RXD
VCC
INTN
D0
D1
D2
NC
D3
D4
D5
D6
D7
GND
RXA
RIA
DCDA
NC
1 2 3
NC
DSRB
CTSB
DTRB
GND
RTSB
INTB
CSB
TXB
IOW
NC
TXA
CSA
INTA
RTSA
VCC
DTRA
CTSA
DSRA
NC
NC – No internal connection
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• DALLAS, TEXAS 75265
3
TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
functional block diagram†
D7 – D0
A2 – A0
CSx
IOR, IOW
RESET
INTx
TXRDY, RXRDY
XTAL1
XTAL2
8
Data
Bus
TL16C550B
Circuitry
TL16C550B
Circuitry
Control
Logic
Receive
Control
Logic
RXx
Transmit
Control
Logic
TXx
Modem
Control
Logic
CTSx
RTSx
DSRx
DTRx
RIx
DCDx
TL16C550B
Circuitry
Interrupt
Logic
TL16C550B
Circuitry
Clock
Circuit
† For TL16C550 circuitry, refer to the TL16C550B data sheet.
Terminal Functions
TERMINAL
FN
NO.
PN
NO.
I/O
DESCRIPTION
34
33
32
48
47
46
I
Register select terminals. A0, A1, and A2 are three inputs used during read and write operations to
select the ACE register to read or write.
CSA, CSB,
CSC, CSD
16, 20,
50, 54
28, 33,
68, 73
I
Chip select. Each chip select (CSx) enables read and write operations to its respective channel.
CTSA, CTSB,
CTSC, CTSD
11, 25,
45, 59
23, 38,
63, 78
I
Clear to send. CTSx is a modem status signal. Its condition can be checked by reading bit 4 (CTS)
of the modem status register. CTS has no affect on the transmit or receive operation.
D7 – D0
66 – 68
1–5
15–11,
9–7
I/O
Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
information between the TL16C554 and the CPU. D0 is the least significant bit (LSB).
DCDA, DCDB,
DCDC, DCDD
9, 27,
43, 61
19,42,
59, 2
I
Data carrier detect. A low on DCDx indicates the carrier has been detected by the modem. The
condition of this signal is checked by reading bit 7 of the modem status register.
DSRA, DSRB,
DSRC, DSRD
10, 26,
44, 60
22, 39,
62, 79
DTRA, DTRB,
DTRC, DTRD
12, 24,
46, 58
24, 37,
64, 77
GND
6, 23,
40, 57
16, 36,
56, 76
INTN
65
6
NAME
A0
A1
A2
4
I
O
Data set ready. DSRx is a modem status signal. Its condition can be checked by reading bit 5 (DSR)
of the modem status register. DSR has no affect on the transmit or receive operation.
Data terminal ready. DTRx is an output that indicates to a modem or data set that the ACE is ready
to establish communications. It is placed in the active state by setting the DTR bit of the modem
control register. DTRx is placed in the inactive state (high) either as a result of the master reset during
loop mode operation or clearing bit 0 (DTR) of the modem control register.
Signal and power ground
I
Interrupt normal. INTN operates in conjunction with bit 3 of the modem status register and affects
operation of the interrupts (INTA, INTB, INTC, and INTD) for the four universal asynchronous
receiver/transceivers (UARTs) per the following table.
INTN
OPERATION OF INTERRUPTS
Brought low or
allowed to float
Interrupts are enabled according to the state of OUT2 (MCR bit 3). When the MCR
bit 3 is cleared, the 3-state interrupt output of that UART is in the high-impedance
state. When the MCR bit 3 is set, the interrupt output of the UART is enabled.
Brought high
Interrupts are always enabled, overriding the OUT2 enables.
POST OFFICE BOX 655303
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TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
Terminal Functions (Continued)
TERMINAL
FN
NO.
PN
NO.
I/O
DESCRIPTION
15, 21,
49, 55
27, 34,
67, 74
O
External interrupt output. The INTx outputs go high (when enabled by the interrupt register) and
inform the CPU that the ACE has an interrupt to be serviced. Four conditions that cause an interrupt
to be issued are: a receiver error, receiver data available or timeout (FIFO mode only), transmitter
holding register empty, and an enabled modem status interrupt. The interrupt is disabled when it is
serviced or as the result of a master reset.
IOR
52
70
I
Read strobe. A low level on IOR transfers the contents of the TL16C554 data bus to the external CPU
bus.
IOW
18
31
I
Write strobe. IOW allows the CPU to write into the selected address by the address register.
RESET
37
53
I
Master reset. When active, RESET clears most ACE registers and sets the state of various signals.
The transmitter output and the receiver input is disabled during reset time.
RIA, RIB,
RIC, RID
8, 28,
42, 62
18, 43,
58, 3
I
Ring detect indicator. A low on RIx indicates the modem has received a ring signal from the telephone
line. The condition of this signal can be checked by reading bit 6 of the modem status register.
RTSA, RTSB,
RTSC, RTSD
14, 22,
48, 56
26, 35,
66, 75
O
Request to send. When active, RTSx informs the modem or data set that the ACE is ready to receive
data. Writing a 1 in the modem control register sets this bit to a low state. After reset, this terminal
is set high. These terminals have no affect on the transmit or receive operation.
RXA, RXB
RXC, RXD
7, 29,
41, 63
17, 44,
57, 4
I
Serial input. RXx is a serial data input from a connected communications device. During loopback
mode, the RXx input is disabled from external connection and connected to the TXx output internally.
38
54
O
Receive ready. RXRDY goes low when the receive FIFO is full. It can be used as a single transfer
or multitransfer.
17, 19,
51, 53
29, 32,
69, 72
O
Transmit outputs. TXx is a composite serial data output that is connected to a communications
device. TXA, TXB, TXC, and TXD are set to the marking (high) state as a result of reset.
39
55
O
Transmit ready. TXRDY goes low when the transmit FIFO is full. It can be used as a single transfer
or multitransfer function.
13, 30,
47, 64
5, 25,
45, 65
XTAL1
35
50
I
Crystal input 1 or external clock input. A crystal can be connected to XTAL1 and XTAL2 to utilize the
internal oscillator circuit. An external clock can be connected to drive the internal clock circuits.
XTAL2
36
51
O
Crystal output 2 or buffered clock output (see XTAL1).
NAME
INTA, INTB,
INTC, INTD
RXRDY
TXA, TXB
TXC, TXD
TXRDY
VCC
Power supply
absolute maximum ratings over free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range at any input, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 3 V
Continuous total power dissipation at (or below) 70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
Operating free-air temperature range, TA: TL16C554 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0°C to 70°C
TL16C554I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage levels are with respect to GND.
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5
TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
recommended operating conditions
Supply voltage, VCC
Clock high-level input voltage at XTAL1, VIH(CLK)
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
VCC
0.8
V
VCC
0.8
V
2
Clock low-level input voltage at XTAL1, VIL(CLK)
– 0.5
High-level input voltage, VIH
2
Low-level input voltage, VIL
– 0.5
Clock frequency, fclock
Operating
O
erating free-air tem
temperature
erature, TA
V
V
16
MHz
TL16C554
0
70
°C
TL16C554I
–40
85
°C
electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage (unless otherwise noted)
PARAMETER
VOH‡
VOL‡
High-level output voltage
Low-level output voltage
TEST CONDITIONS
IOH = – 1 mA
IOL = 1.6 mA
IIkg
Input leakage current
IOZ
High-impedance output
current
VCC = 5.25 V,
GND = 0, VO = 0 to 5.25 V,
Chip selected in write mode or chip deselected
ICC
Supply current
VCC = 5.25 V,
TA = 25°C,
RX, DSR, DCD, CTS, and RI at 2 V,
All other inputs at 0.8 V, XTAL1 at 4 MHz,
No load on outputs,
Baud rate = 50 kilobits per second
Ci(XTAL1)
Clock input capacitance
Clock output capacitance
Ci
Input capacitance
TYP†
MAX
2.4
VCC = 5.25 V,
VI = 0 to 5.25 V,
Co(XTAL2)
MIN
V
0.4
V
± 10
µA
± 20
µA
50
mA
15
20
pF
20
30
pF
6
10
pF
10
20
pF
GND = 0,
All other terminals floating
VCC = 0,
VSS = 0,
All other terminals grounded
grounded,
TA = 25
25°C
C
MHz,
f = 1 MHz
Co
Output capacitance
† All typical values are at VCC = 5 V, TA = 25°C.
‡ These parameters apply for all outputs except XTAL2.
UNIT
clock timing requirements over recommended ranges of operating free-air temperature and supply
voltage (see Figure 1)
MIN
tw1
tw2
Pulse duration, clock high (external clock)
tw3
Pulse duration, RESET
6
Pulse duration, clock low (external clock)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
UNIT
31
ns
31
ns
1000
ns
TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
read cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 4)
MIN
MAX
UNIT
tw4
tsu1
Pulse duration, IOR low
75
ns
Setup time, CSx valid before IOR low (see Note 2)
10
ns
tsu2
th1
Setup time, A2 – A0 valid before IOR low (see Note 2)
15
ns
0
ns
th2
td1
Hold time, CSx valid after IOR high (see Note 2)
0
ns
140
ns
Hold time, A2 – A0 valid after IOR high (see Note 2)
Delay time, tsu2 + tw4 + td2 (see Note 3)
td2
Delay time, IOR high to IOR or IOW low
50
ns
NOTES: 2. The internal address strobe is always active.
3. In the FIFO mode, td1 = 425 ns (min) between reads of the receiver FIFO and the status registers (interrupt identification register
and line status register).
write cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 5)
MIN
MAX
UNIT
tw5
tsu3
Pulse duration, IOW↓
50
ns
Setup time, CSx valid before IOW↓ (see Note 2)
10
ns
tsu4
tsu5
Setup time, A2 – A0 valid before IOW↓ (see Note 2)
15
ns
Setup time, D7 – D0 valid before IOW↑
10
ns
th3
th4
Hold time, A2 – A0 valid after IOW↑ (see Note 2)
5
ns
Hold time, CSx valid after IOW↑ (see Note 2)
5
ns
th5
td3
Hold time, D7 – D0 valid after IOW↑
Delay time, tsu4 + tw5 + td4
td4
Delay time, IOW↑ to IOW or IOR↓
NOTE 2: The internal address strobe is always active.
25
ns
120
ns
55
ns
read cycle switching characteristics over recommended ranges of operating free-air temperature
and supply voltage, CL = 100 pF (see Note 4 and Figure 4)
PARAMETER
ten
tdis
MIN
Enable time, IOR↓ to D7 – D0 valid
Disable time, IOR↑ to D7 – D0 released
0
MAX
UNIT
30
ns
20
ns
NOTE 4: VOL and VOH (and the external loading) determine the charge and discharge time.
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7
TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
transmitter switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figures 6, 7, and 8)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
8
24
RCLK
cycles
td5
Delay time, INTx↓ to TXx↓ at start
td6
Delay time, TXx↓ at start to INTx↑
See Note 5
8
8
RCLK
cycles
td7
Delay time, IOW high or low (WR THR) to INTx↑
See Note 5
16
32
RCLK
cycles
td8
Delay time, TXx↓ at start to TXRDY↓
CL = 100 pF
8
RCLK
cycles
tpd1
Propagation delay time, IOW (WR THR)↓ to INTx↓
CL = 100 pF
35
ns
tpd2
Propagation delay time, IOR (RD IIR)↑ to INTx↓
CL = 100 pF
30
ns
tpd3
Propagation delay time, IOW (WR THR)↑ to TXRDY↑
CL = 100 pF
50
ns
NOTE 5: If the transmitter interrupt delay is active, this delay is lengthened by one character time minus the last stop bit time.
receiver switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figures 9 through 13)
PARAMETER
TEST CONDITIONS
td9
Delay time, stop bit to INTx↑ or stop bit to RXRDY↓ or read RBR to set interrupt
tpd4
Propagation delay time, Read RBR/LSR to INTx↓/LSR interrupt↓
tpd5
Propagation delay time, IOR RCLK↓ to RXRDY↑
MIN
MAX
UNIT
See Note 6
1
RCLK
cycle
CL = 100 pF,
See Note 7
40
ns
See Note 7
30
ns
NOTES: 6. The receiver data available indicator, the overrun error indicator, the trigger level interrupts, and the active RXRDY indicator are
delayed three RCLK (internal receiver timing clock) cycles in the FIFO mode (FCR0 = 1). After the first byte has been received, status
indicators (PE, FE, BI) are delayed three RCLK cycles. These indicators are updated immediately for any further bytes received after
IOR goes active for a read from the RBR register. There are eight RCLK cycle delays for trigger change level interrupts.
7. RCLK is an internal signal derived from divisor latch LSB (DLL) and divisor latch MSB (DLM) divisor latches.
modem control switching characteristics over recommended ranges of operating free-air
temperature and supply voltage, CL = 100 pF (see Figure 14)
PARAMETER
MIN
MAX
UNIT
tpd6
Propagation delay time, IOW (WR MCR)↑ to RTSx, DTRx↑
50
ns
tpd7
Propagation delay time, modem input CTSx, DSRx, and DCDx ↓↑ to INTx↑
30
ns
tpd8
Propagation delay time, IOR (RD MSR)↑ to interrupt↓
35
ns
tpd9
Propagation delay time, RIx↑ to INTx↑
30
ns
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
tw1
Clock
(XTAL1)
2V
2V
2V
0.8 V
0.8 V
0.8 V
tw2
fclock = 16 MHz MAX
(a) CLOCK INPUT VOLTAGE WAVEFORM
RESET
tw3
(b) RESET VOLTAGE WAVEFORM
Figure 1. Clock Input and RESET Voltage Waveforms
2.54 V
Device Under Test
680 Ω
TL16C554
82 pF
(see Note A)
NOTE A: This includes scope and jig capacitance.
Figure 2. Output Load Circuit
Data Bus
Serial
Channel 1
Buffers
9-Pin D Connector
Serial
Channel 2
Buffers
9-Pin D Connector
Serial
Channel 3
Buffers
9-Pin D Connector
Serial
Channel 4
Buffers
9-Pin D Connector
Address Bus
Control Bus
TL16C554
Quadruple
ACE
Figure 3. Basic Test Configuration
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
A2, A1, A0
Valid
50%
50%
th1
Valid
CSx
50%
50%
tsu1
th2
td1
tsu2
IOR
50%
Active
50%
50%
td2
tw4
or
50%
IOW
ten
Active
Active
tdis
D7 – D0
Valid Data
Figure 4. Read Cycle Timing Waveforms
A2, A1, A0
Valid
50%
50%
th3
Valid
CSx
50%
50%
th4
tsu3
td3
tsu4
IOW
50% Active
50%
tw5
50%
td4
or
50%
IOR
th5
tsu5
D7 – D0
Valid Data
Figure 5. Write Cycle Timing Waveforms
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Active
Active
TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
Start
Parity
td5
INTx
Start
50%
Stop (1 – 2)
Data (5 – 8)
50%
TXx
50%
50%
50%
td6
50%
50%
tpd1
td7
IOW
50%
(WR THR)
tpd1
50%
50%
tpd2
IOR
(RD IIR)
50%
Figure 6. Transmitter Timing Waveforms
IOW
(WR THR)
TXx
Byte #1
50%
Parity
Data
Stop
50%
Start
td8
tpd3
TXRDY
50%
FIFO Empty
50%
Figure 7. Transmitter Ready Mode 0 Timing Waveforms
IOW
(WR THR)
Byte #16
50%
Start
TXx
Data
Parity
Stop
Start
50%
tpd3
TXRDY
td8
50%
FIFO Full
50%
Figure 8. Transmitter Ready Mode 1 Timing Waveforms
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TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
TL16C450 Mode:
SIN
(receiver input data)
Start
Data Bits (5 – 8)
Parity
Stop
Sample Clock
td9
INTx
(data ready or
RCVR ERR)
50%
50%
tpd4
Active
50%
IOR
Figure 9. Receiver Timing Waveforms
RXx
Start
Data Bits (5 – 8)
Parity
Stop
Sample
Clock
INTx (trigger
interrupt)
(FCR6, 7 = 0, 0)
50%
50%
td9
tpd4
IOR
(RD RBR)
LSR
Interrupt
50%
50%
50%
tpd4
IOR
(RD LSR)
50%
Active
Figure 10. Receiver FIFO First Byte (Sets RDR) Waveforms
12
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Active
(FIFO at or
above trigger
level)
(FIFO below
trigger level)
TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
RXx
Stop
Sample
Clock
td9 (see Note A)
INTx
(time-out or
trigger level)
Interrupt
50%
(FIFO at or above
trigger level)
50%
(FIFO below
trigger level)
tpd4
INTx
Interrupt
50%
Top Byte of FIFO
td9
tpd4
IOR
(RD LSR)
Active
Active
IOR
(RD RBR)
50%
50%
50%
50%
Active
Previous BYTE
Read From FIFO
NOTE A: This is the reading of the last byte in the FIFO.
Figure 11. Receiver FIFO After First Byte (After RDR Set) Waveforms
IOR
(RD RBR)
50%
Active
(see Note A)
RXx
Stop
Sample
Clock
td9
(see Note B)
RXRDY
50%
50%
tpd5
NOTES: A. This is the reading of the last byte in the FIFO.
B. If FCR0 = 1, then td9 = 3 RCLK cycles. For a time-out interrupt, td9 = 8 RCLK cycles.
Figure 12. Receiver Ready Mode 0 Timing Waveforms
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TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
IOR
(RD RBR)
50%
Active
(see Note A)
SIN
(first byte that reaches
Stop
the trigger level)
Sample
Clock
td9
(see Note B)
50%
RXRDY
50%
tpd5
NOTES: A. This is the reading of the last byte in the FIFO.
B. If FCR0 = 1, td9 = 3 RCLK cycles. For a trigger change level interrupt, td9 = 8 RCLK.
Figure 13. Receiver Ready Mode 1 Timing Waveforms
IOW
(WR MCR)
50%
50%
tpd6
50%
50%
RTSx, DTRx
CTSx, DSRx,
DCDx
50%
50%
tpd7
INTx
tpd6
tpd7
50%
50%
50%
tpd8
IOR
(RD MSR)
50%
tpd9
50%
50%
RIx
Figure 14. Modem Control Timing Waveforms
14
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TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PRINCIPLES OF OPERATION
Three types of information are stored in the internal registers used in the ACE: control, status, and data. Mnemonic
abbreviations for the registers are shown in Table 1. Table 2 defines the address location of each register and whether
it is read only, write only, or read writable.
Table 1. Internal Register Mnemonic Abbreviations
CONTROL
MNEMONIC
Line control register
STATUS
MNEMONIC
DATA
MNEMONIC
LCR
Line status register
LSR
Receiver buffer register
RBR
FIFO control register
FCR
Modem status register
MSR
Transmitter holding register
THR
Modem control register
MCR
Divisor latch LSB
DLL
Divisor latch MSB
DLM
Interrupt enable register
IER
Table 2. Register Selection†
DLAB‡
A2§
A1§
A0§
0
0
0
0
0
0
0
1
X
0
1
0
X
0
1
1
X
1
0
0
X
1
0
1
Line status register
X
1
1
0
Modem status register
X
1
1
1
Scratchpad register
1
0
0
0
LSB divisor latch
1
0
0
1
MSB divisor latch
READ MODE
Receiver buffer register
WRITE MODE
Transmitter holding register
Interrupt enable register
Interrupt identification register
FIFO control register
Line control register
Modem control register
Scratchpad register
X = irrelevant, 0 = low level, 1 = high level
† The serial channel is accessed when either CSA or CSD is low.
‡ DLAB is the divisor latch access bit and bit 7 in the LCR.
§ A2 – A0 are device terminals.
Individual bits within the registers with the bit number in parenthesis are referred to by the register mnemonic. For
example, LCR7 refers to line control register bit 7. The transmitter buffer register and receiver buffer register are data
registers that hold from five to eight bits of data. If less than eight data bits are transmitted, data is right justified to
the LSB. Bit 0 of a data word is always the first serial data bit received and transmitted. The ACE data registers are
double buffered (TL16450 mode) or FIFO buffered (FIFO mode) so that read and write operations can be performed
when the ACE is performing the parallel-to-serial or serial-to-parallel conversion.
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TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PRINCIPLES OF OPERATION
accessible registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 1. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.
Table 3. Summary of Accessible Registers
REGISTER ADDRESS
REGISTER
MNEMONIC
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
RBR
(read only)
Data Bit 7
(MSB)
Data Bit 6
Data Bit 5
Data
Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0
(LSB)
0
THR
(write only)
Data BIt 7
Data BIt 6
Data BIt 5
Data
BIt 4
Data BIt 3
Data BIt 2
Data BIt 1
Data BIt 0
ADDRESS
0†
1†
DLL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DLM
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
IER
0
0
0
0
(EDSSI)
Enable
modem
status
interrupt
(ERLSI)
Enable
receiver
line status
interrupt
(ETBEI)
Enable
transmitter
holding
register
empty
interrupt
(ERBI)
Enable
received
data
available
interrupt
2
FCR
(write only)
Receiver
Trigger
(MSB)
Receiver
Trigger
(LSB)
Reserved
Reserved
DMA
mode
select
Transmit
FIFO reset
Receiver
FIFO reset
FIFO Enable
2
IIR
(read only)
FIFOs
Enabled‡
FIFOs
Enabled‡
0
0
Interrupt
ID Bit (3)‡
Interrupt ID
Bit (2)
Interrupt ID
Bit (1)
0 If interrupt
pending
3
LCR
(DLAB)
Divisor
latch
access bit
Set break
Stick parity
(EPS)
Even
parity
select
(PEN)
Parity
enable
(STB)
Number of
stop bits
(WLSB1)
Word length
select bit 1
(WLSB0)
Word length
select bit 0
4
MCR
0
0
0
Loop
OUT2
Enable
external
interrupt
(INT)
Reserved
(RTS)
Request to
send
(DTR) Data
terminal
ready
5
LSR
Error in
receiver
FIFO‡
(TEMT)
Transmitter
registers
empty
(THRE)
Transmitter
holding
register
empty
(BI)
Break
interrupt
(FE)
Framing
error
(PE)
Parity error
(OE)
Overrun
error
(DR)
Data ready
6
MSR
(DCD)
Data
carrier
detect
(RI)
Ring
indicator
(DSR)
Data set
ready
(CTS)
Clear to
send
(∆ DCD)
Delta data
carrier
detect
(TERI)
Trailing
edge ring
indicator
(∆ DSR)
Delta data
set ready
(∆ CTS)
Delta
clear to send
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
7
SCR
Bit 7
Bit 6
† DLAB = 1
‡ These bits are always 0 when FIFOs are disabled.
16
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TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PRINCIPLES OF OPERATION
FIFO control register (FCR)
The FCR is a write-only register at the same location as the IIR. It enables the FIFOs, sets the trigger level of
the receiver FIFO, and selects the type of DMA signalling.
D
D
D
D
D
D
Bit 0: FCR0 enables the transmit and receiver FIFOs. All bytes in both FIFOs can be cleared by clearing
FCR0. Data is cleared automatically from the FIFOs when changing from the FIFO mode to the TL16C450
mode (see FCR bit 0) and vice versa. Programming of other FCR bits is enabled by setting FCR0.
Bit 1: When set, FCR1 clears all bytes in the receiver FIFO and resets its counter. This does not clear the
shift register.
Bit 2: When set, FCR2 clears all bytes in the transmit FIFO and resets the counter. This does not clear the
shift register.
Bit 3: When set, FCR3 changes RXRDY and TXRDY from mode 0 to mode 1 if FCR0 is set.
Bits 4 and 5: FCR4 and FCR5 are reserved for future use.
Bits 6 and 7: FCR6 and FCR7 set the trigger level for the receiver FIFO interrupt (see Table 4).
Table 4. Receiver FIFO Trigger Level
BIT
7
6
RECEIVER FIFO
TRIGGER LEVEL (BYTES)
0
0
01
0
1
04
1
0
08
1
1
14
FIFO interrupt mode operation
The following receiver status occurs when the receiver FIFO and receiver interrupts are enabled.
1. LSR0 is set when a character is transferred from the shift register to the receiver FIFO. When the FIFO is
empty, it is reset.
2. IIR = 06 receiver line status interrupt has higher priority than the receive data available interrupt
IIR = 04.
3. Receive data available interrupt is issued to the CPU when the programmed trigger level is reached by the
FIFO. As soon as the FIFO drops below its programmed trigger level, it is cleared.
4. IIR = 04 (receive data available indicator) also occurs when the FIFO reaches its trigger level. It is cleared
when the FIFO drops below the programmed trigger level.
The following receiver FIFO character time-out status occurs when receiver FIFO and receiver interrupts are
enabled.
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TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PRINCIPLES OF OPERATION
FIFO interrupt mode operation (continued)
1. When the following conditions exist, a FIFO character time-out interrupt occurs:
a. Minimum of one character in FIFO
b. Last received serial character is longer than four continuous previous character times ago. (If two stop
bits are programmed, the second one is included in the time delay.)
c.
The last CPU of the FIFO read is more than four continuous character times earlier. At 300 baud and
12-bit characters, the FIFO time-out interrupt causes a latency of 160 ms maximum from received
character to interrupt issued.
2. By using the XTAL1 input for a clock signal, the character times can be calculated. The delay is proportional
to the baud rate.
3. The time-out timer is reset after the CPU reads the receiver FIFO or after a new character is received. This
occurs when there has been no time-out interrupt.
4. A time-out interrupt is cleared and the timer is reset when the CPU reads a character from the receiver FIFO.
Transmit interrupts occurs as follows when the transmitter and transmit FIFO interrupts are enabled
(FCR0 = 1, IER = 1).
1. When the transmitter FIFO is empty, the transmitter holding register interrupt (IIR = 02) occurs. The interrupt
is cleared when the transmitter holding register is written to or the IIR is read. One to sixteen characters can
be written to the transmit FIFO when servicing this interrupt.
2. The transmitter FIFO empty indicators are delayed one character time minus the last stop bit time whenever
the following occurs:
THRE = 1, and there has not been a minimum of two bytes at the same time in transmit FIFO since the last
THRE = 1. The first transmitter interrupt after changing FCR0 is immediate, however, assuming it is
enabled.
Receiver FIFO trigger level and character time-out interrupts have the same priority as the receive data
available interrupt. The transmitter holding register empty interrupt has the same priority as the transmitter FIFO
empty interrupt.
FIFO polled mode operation
Clearing IER0, IER1, IER2, IER3, or all to zero with FCR0 = 1 puts the ACE into the FIFO polled mode. receiver
and transmitter are controlled separately. Either or both can be in the polled mode.
In the FIFO polled mode, there is no time-out condition indicated or trigger level reached. However, the Receiver
and transmit FIFOs still have the capability of holding characters. The LSR must be read to determine the ACE
status.
interrupt enable register (IER)
The IER independently enables the four serial channel interrupt sources that activate the interrupt (INTA, B, C,
D) output. All interrupts are disabled by clearing IER0 – IER3 of the IER. Interrupts are enabled by setting the
appropriate bits of the IER. Disabling the interrupt system inhibits the IIR and the active (high) interrupt output.
All other system functions operate in their normal manner, including the setting of the LSR and MSR. The
contents of the IER are shown in Table 3 and described in the following bulleted list:
18
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ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PRINCIPLES OF OPERATION
interrupt enable register (IER) (continued)
D
D
D
D
D
Bit 0: When IER0 is set, IER0 enables the received data available interrupt and the timeout interrupts in
the FIFO mode.
Bit 1: When IER1 is set, the transmitter holding register empty interrupt is enabled.
Bit 2: When IER2 is set, the receiver line status interrupt is enabled.
Bit 3: When IER3 is set, the modem status interrupt is enabled.
Bits 4 – 7: IER4 – IER7. These four bits of the IER are cleared.
interrupt identification register (IIR)
In order to minimize software overhead during data character transfers, the serial channel prioritizes interrupts
into four levels. The four levels of interrupt conditions are as follows:
D
D
D
D
Priority 1 – Receiver line status (highest priority)
Priority 2 – Receiver data ready or receiver character timeout
Priority 3 – Transmitter holding register empty
Priority 4 – Modem status (lowest priority)
Information indicating that a prioritized interrupt is pending and the type of interrupt that is stored in the IIR. The
IIR indicates the highest priority interrupt pending. The contents of the IIR are indicated in Table 5.
Table 5. Interrupt Control Functions
INTERRUPT
IDENTIFICATION
REGISTER
INTERRUPT SET AND RESET FUNCTIONS
BIT 3
BIT 2
BIT 1
BIT 0
PRIORITY
LEVEL
INTERRUPT TYPE
INTERRUPT SOURCE
INTERRUPT
RESET CONTROL
0
0
0
1
—
None
None
—
0
1
1
0
First
Receiver line status
OE, PE, FE, or BI
LSR read
0
1
0
0
Second
Received data available
Receiver data available or
trigger level reached
RBR read until FIFO
drops below the trigger
level
1
1
0
0
Second
Character time-out
indicator
No characters have been
removed from or input to the
receiver FIFO during the last
four character times, and there
is at least one character in it
during this time.
RBR read
0
0
1
0
Third
THRE
THRE
IIR read if THRE is the
interrupt source or THR
write
0
0
0
0
Fourth
Modem status
CTS, DSR, RI, or DCD
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TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PRINCIPLES OF OPERATION
interrupt identification register (IIR) (continued)
D
D
D
D
D
Bit 0: IIR0 indicates whether an interrupt is pending. When IIR0 is cleared, an interrupt is pending.
Bits 1 and 2: IIR1 and IIR2 identify the highest priority interrupt pending as indicated in Table 5.
Bit 3: IIR3 is always cleared when in the TL16C450 mode. This bit is set along with bit 2 when in the FIFO
mode and a trigger change level interrupt is pending.
Bits 4 and 5: IIR4 and IIR5 are always cleared.
Bits 6 and 7: IIR6 and IIR7 are set when FCR0 = 1.
line control register (LCR)
The format of the data character is controlled by the LCR. The LCR may be read. Its contents are described
in the following bulleted list and shown in Figure 15.
D
D
D
D
D
D
D
20
Bits 0 and 1: LCR0 and LCR1 are word length select bits. These bits program the number of bits in each
serial character and are shown in Figure 15.
Bit 2: LCR2 is the stop bit select bit. This bit specifies the number of stop bits in each transmitted character.
The receiver always checks for one stop bit.
Bit 3: LCR3 is the parity enable bit. When LCR3 is set, a parity bit between the last data word bit and stop
bit is generated and checked.
Bit 4: LCR4 is the even parity select bit. When this bit is set and parity is enabled (LCR3 is set), even parity
is selected. When this bit is cleared and parity is enabled, odd parity is selected.
Bit 5: LCR5 is the stick parity bit. When parity is enabled (LCR3 is set) and this bit is set, the transmission
and reception of a parity bit is placed in the opposite state from the value of LCR4. This forces parity to a
known state and allows the receiver to check the parity bit in a known state.
Bit 6: LCR6 is a break control bit. When this bit is set, the serial outputs TXx are forced to the spacing state
(low). The break control bit acts only on the serial output and does not affect the transmitter logic. If the
following sequence is used, no invalid characters are transmitted because of the break.
Step 1.
Load a zero byte in response to the transmitter holding register empty (THRE) status indicator.
Step 2.
Set the break in response to the next THRE status indicator.
Step 3.
Wait for the transmitter to be idle when transmitter empty status signal is set (TEMT = 1); then
clear the break when the normal transmission has to be restored.
Bit 7: LCR7 is the divisor latch access bit (DLAB) bit. This bit must be set to access the divisor latches DLL
and DLM of the baud rate generator during a read or write operation. LCR7 must be cleared to access the
receiver buffer register, the transmitter holding register, or the interrupt enable register.
POST OFFICE BOX 655303
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ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PRINCIPLES OF OPERATION
line control register (LCR) (continued)
LINE CONTROL REGISTER
LCR
7
LCR LCR
6
5
LCR
4
LCR
3
LCR LCR
2
1
LCR
0
Word Length
Select
0
0
1
1
0 = 5 Data Bits
1 = 6 Data Bits
0 = 7 Data Bits
1 = 8 Data bits
Stop Bit
Select
0 = 1 Stop Bit
1 = 1.5 Stop Bits if 5 Data Bits Selected
2 Stop Bits if 6, 7, 8 Data Bits Selected
Parity Enable
0 = Parity Disabled
1 = Parity Enabled
Even Parity
Select
0 = Odd Parity
1 = Even Parity
Stick Parity
0 = Stick Parity Disabled
1 = Stick Parity Enabled
Break Control
0 = Break Disabled
1 = Break Enabled
Divisor Latch
Access BIt
0 = Access Receiver Buffer
1 = Access Divisor Latches
Figure 15. Line Control Register Contents
line status register (LSR)
The LSR is a single register that provides status indicators. The LSR shown in Table 6 is described in the
following bulleted list:
D
D
D
D
Bit 0: LSR0 is the data ready (DR) bit. Data ready is set when an incoming character is received and
transferred into the receiver buffer register or the FIFO. LSR0 is cleared by a CPU read of the data in the
receiver buffer register or the FIFO.
Bit 1: LSR1 is the overrun error (OE) bit. An overrun error indicates that data in the receiver buffer register
is not read by the CPU before the next character is transferred into the receiver buffer register overwriting
the previous character. The OE indicator is cleared whenever the CPU reads the contents of the LSR. An
overrun error occurs in the FIFO mode after the FIFO is full and the next character is completely received.
The overrun error is detected by the CPU on the first LSR read after it happens. The character in the shift
register is not transferred to the FIFO, but it is overwritten.
Bit 2: LSR2 is the parity error (PE) bit. A parity error indicates that the received data character does not
have the correct parity as selected by LCR3 and LCR4. The PE bit is set upon detection of a parity error
and is cleared when the CPU reads the contents of the LSR. In the FIFO mode, the parity error is associated
with a particular character in the FIFO. LSR2 reflects the error when the character is at the top of the FIFO.
Bit 3: LSR3 is the framing error (FE) bit. A framing error indicates that the received character does not have
a valid stop bit. LSR3 is set when the stop bit following the last data bit or parity bit is detected as a zero
bit (spacing level). The FE indicator is cleared when the CPU reads the contents of the LSR. In the FIFO
mode, the framing error is associated with a particular character in the FIFO. LSR3 reflects the error when
the character is at the top of the FIFO.
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TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PRINCIPLES OF OPERATION
line status register (LSR) (continued)
D
Bit 4: LSR4 is the break interrupt (BI) bit. Break interrupt is set when the received data input is held in the
spacing (low) state for longer than a full word transmission time (start bit + data bits + parity + stop bits).
The BI indicator is cleared when the CPU reads the contents of the LSR. In the FIFO mode, this is associated
with a particular character in the FIFO. LSR2 reflects the BI when the break character is at the top of the
FIFO. The error is detected by the CPU when its associated character is at the top of the FIFO during the
first LSR read. Only one zero character is loaded into the FIFO when BI occurs.
LSR1 – LSR4 are the error conditions that produce a receiver line status interrupt (priority 1 interrupt in the
interrupt identification register) when any of the conditions are detected. This interrupt is enabled by setting IER2
in the interrupt enable register.
D
D
D
Bit 5: LSR5 is the transmitter holding register empty (THRE) bit. THRE indicates that the ACE is ready to
accept a new character for transmission. The THRE bit is set when a character is transferred from the
transmitter holding register (THR) into the transmitter shift register (TSR). LSR5 is cleared by the loading
of the THR by the CPU. LSR5 is not cleared by a CPU read of the LSR. In the FIFO mode, when the transmit
FIFO is empty, this bit is set. It is cleared when one byte is written to the transmit FIFO. When the THRE
interrupt is enabled by IER1, THRE causes a priority 3 interrupt in the IIR. If THRE is the interrupt source
indicated in IIR, INTRPT is cleared by a read of the IIR.
Bit 6: LSR6 is the transmitter register empty (TEMT) bit. TEMT is set when the THR and the TSR are both
empty. LSR6 is cleared when a character is loaded into THR and remains low until the character is
transferred out of TXx. TEMT is not cleared by a CPU read of the LSR. In the FIFO mode, when both the
transmitter FIFO and shift register are empty, this bit is set.
Bit 7: LSR7 is the receiver FIFO error bit. The LSR7 bit is cleared in the TL16C450 mode (see FCR bit 0).
In the FIFO mode, it is set when at least one of the following data errors is in the FIFO: parity error, framing
error, or break interrupt indicator. It is cleared when the CPU reads the LSR if there are no subsequent errors
in the FIFO.
NOTE
The LSR may be written. However, this function is intended only for factory test. It should be considered as read
only by applications software.
Table 6. Line Status Register BIts
LSR BITS
1
0
Ready
Not ready
LSR1 overrun error (OE)
Error
No error
LSR2 parity error (PE)
Error
No error
LSR0 data ready (DR)
LSR3 framing error (FE)
Error
No error
LSR4 break interrupt (BI)
Break
No break
LSR5 transmitter holding register empty (THRE)
Empty
Not empty
LSR6 transmitter register empty (TEMT)
LSR7 receiver FIFO error
22
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• DALLAS, TEXAS 75265
TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PRINCIPLES OF OPERATION
modem control register (MCR)
The MCR controls the interface with the modem or data set as described in Figure 16. MCR can be written and
read. The RTS and DTR outputs are directly controlled by their control bits in this register. A high input asserts
a low signal (active) at the output terminals. MCR bits 0, 1, 2, 3, and 4 are shown as follows:
D
D
D
D
D
D
Bit 0: When MCR0 is set, the DTR output is forced low. When MCR0 is cleared, the DTR output is forced
high. The DTR output of the serial channel may be input into an inverting line driver in order to obtain the
proper polarity input at the modem or data set.
Bit1: When MCR1 is set, the RTS output is forced low. When MCR1 is cleared, the RTS output is forced
high. The RTS output of the serial channel may be input into an inverting line driver to obtain the proper
polarity input at the modem or data set.
Bit 2: MCR2 has no affect on operation.
Bit 3: When MCR3 is set, the external serial channel interrupt is enabled.
Bit 4: MCR4 provides a local loopback feature for diagnostic testing of the channel. When MCR4 is set,
serial output TXx is set to the marking (high) state and SIN is disconnected. The output of the TSR is looped
back into the RSR input. The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected. The
modem control outputs (DTR and RTS) are internally connected to the four modem control inputs. The
modem control output terminals are forced to their inactive (high) state on the TL16C554. In the diagnostic
mode, data transmitted is immediately received. This allows the processor to verify the transmit and receive
data paths of the selected serial channel. Interrupt control is fully operational; however, interrupts are
generated by controlling the lower four MCR bits internally. Interrupts are not generated by activity on the
external terminals represented by those four bits.
Bit 5 – Bit 7: MCR5, MCR6, and MCR7 are permanently cleared.
MODEM CONTROL REGISTER
MCR MCR MCR MCR MCR
7
6
5
4
3
MCR MCR
1
2
MCR
0
Data Terminal
Ready
0 = DTR Output Inactive (high)
1 = DTR Output Active (low)
Request
to Send
0 = RTS Output Inactive (high)
1 = RTS Output Active (low)
Out1 (internal)
No affect on external operation
Out2 (internal)
0 = External Interrupt Disabled
1 = External Interrupt Enabled
Loop
0 = Loop Disabled
1 = Loop Enabled
Bits Are Set to Logic 0
Figure 16. Modem Control Register Contents
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TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
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PRINCIPLES OF OPERATION
modem status register (MSR)
The MSR provides the CPU with status of the modem input lines for the modem or peripheral devices. The MSR
allows the CPU to read the serial channel modem signal inputs by accessing the data bus interface of the ACE.
It also reads the current status of four bits of the MSR that indicate whether the modem inputs have changed
since the last reading of the MSR. The delta status bits are set when a control input from the modem changes
states and are cleared when the CPU reads the MSR.
The modem input lines are CTS, DSR, and DCD. MSR4 – MSR7 are status indicators of these lines. A status
bit = 1 indicates the input is low. When the status bit is cleared, the input is high. When the modem status interrupt
in the IER is enabled (IIR3 is set), an interrupt is generated whenever MSR0 – MSR3 is set. The MSR is a priority
4 interrupt. The contents of the MSR are described in Table 7.
D
D
D
D
D
D
D
D
Bit 0: MSR0 is the delta clear-to-send (∆ CTS) bit. DCTS indicates that the CTS input to the serial channel
has changed state since it was last read by the CPU.
Bit 1: MSR1 is the delta data set ready (∆ DSR) bit. ∆ DSR indicates that the DSR input to the serial channel
has changed states since the last time it was read by the CPU.
Bit 2: MSR2 is the trailing edge of ring indicator (TERI) bit. TERI indicates that the RIx input to the serial
channel has changed states from low to high since the last time it was read by the CPU. High-to-low
transitions on RI do not activate TERI.
Bit 3: MSR3 is the delta data carrier detect (∆ DCD) bit. ∆ DCD indicates that the DCD input to the serial
channel has changed states since the last time it was read by the CPU.
Bit 4: MSR4 is the clear-to-send (CTS) bit. CTS is the complement of the CTS input from the modem
indicating to the serial channel that the modem is ready to receive data from SOUT. When the serial channel
is in the loop mode (MCR4 = 1), MSR4 reflects the value of RTS in the MCR.
Bit 5: MSR5 is the data set ready DSR bit. DSR is the complement of the DSR input from the modem to
the serial channel that indicates that the modem is ready to provide received data from the serial channel
receiver circuitry. When the channel is in the loop mode (MCR4 is set), MSR5 reflects the value of DTR in
the MCR.
Bit 6: MSR6 is the ring indicator (RI) bit. RI is the complement of the RIx inputs. When the channel is in the
loop mode (MCR4 is set), MSR6 reflects the value of OUT1 in the MCR.
Bit 7: MSR7 is the data carrier detect (DCD) bit. Data carrier detect indicates the status of the data carrier
detect (DCD) input. When the channel is in the loop mode (MCR4 is set), MSR7 reflects the value of OUT2
in the MCR.
Reading the MSR clears the delta modem status indicators but has no affect on the other status bits. For LSR
and MSR, the setting of status bits is inhibited during status register read operations. If a status condition is
generated during a read IOR operation, the status bit is not set until the trailing edge of the read. When a status
bit is set during a read operation and the same status condition occurs, that status bit is cleared at the trailing
edge of the read instead of being set again. In the loopback mode when modem status interrupts are enabled,
CTS, DSR, RI, and DCD inputs are ignored; however, a modem status interrupt can still be generated by writing
to MCR3 – MCR0. Applications software should not write to the MSR.
24
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TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PRINCIPLES OF OPERATION
modem status register (MSR) (continued)
Table 7. Modem Status Register BIts
MSR BIT
MNEMONIC
MSR0
∆ CTS
Delta clear to send
DESCRIPTION
MSR1
∆ DSR
Delta data set ready
MSR2
TERI
Trailing edge of ring indicator
MSR3
∆ DCD
MSR4
CTS
Clear to send
MSR5
DSR
Data set ready
MSR6
RI
Ring indicator
MSR7
DCD
Delta data carrier detect
Data carrier detect
programming
The serial channel of the ACE is programmed by the control registers LCR, IER, DLL, DLM, MCR, and FCR.
These control words define the character length, number of stop bits, parity, baud rate, and modem interface.
While the control registers can be written in any order, the IER should be written last because it controls the
interrupt enables. Once the serial channel is programmed and operational, these registers can be updated any
time the ACE serial channel is not transmitting or receiving data.
programmable baud rate generator
The ACE serial channel contains a programmable baud rate generator (BRG) that divides the clock (dc to
8 MHz) by any divisor from 1 to (216 – 1). Two 8-bit divisor latch registers store the divisor in a 16-bit binary
format. These divisor latch registers must be loaded during initialization. Upon loading either of the divisor
latches, a 16-bit baud counter is immediately loaded. This prevents long counts on initial load. The BRG can
use any of three different popular frequencies to provide standard baud rates. These frequencies are 1.8432
MHz, 3.072 MHz, and 8 MHz. With these frequencies, standard bit rates from 50 kbps to 512 kbps are available.
Tables 8, 9, 10, and 11 illustrate the divisors needed to obtain standard rates using these three frequencies. The
output frequency of the baud rate generator is 16 × the data rate [divisor # = clock + (baud rate × 16)] referred
to in this document as RCLK.
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TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PRINCIPLES OF OPERATION
programmable baud rate generator (continued)
Table 8. Baud Rates Using an 1.8432-MHz Crystal
BAUD RATE
DESIRED
DIVISOR (N) USED TO
GENERATE 16 × CLOCK
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL
50
2304
—
75
1536
—
110
1047
0.026
134.5
857
0.058
150
768
—
300
384
—
600
192
—
1200
96
—
1800
64
—
2000
58
0.690
2400
48
—
3600
32
—
4800
24
—
7200
16
—
9600
12
—
19200
6
—
38400
3
—
56000
2
2.860
Table 9. Baud Rates Using an 3.072-MHz Crystal
BAUD RATE
DESIRED
26
DIVISOR (N) USED TO
GENERATE 16 × CLOCK
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL
50
3840
—
75
2560
—
110
1745
0.026
134.5
1428
0.034
150
1280
—
300
640
—
—
600
320
1200
160
—
1800
107
0.312
2000
96
—
2400
80
—
3600
53
0.628
4800
40
—
7200
27
1.230
9600
20
—
19200
10
—
38400
5
—
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ASYNCHRONOUS COMMUNICATIONS ELEMENT
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PRINCIPLES OF OPERATION
programmable baud rate generator (continued)
Table 10. Baud Rates Using an 8-MHz Clock
BAUD RATE
DESIRED
DIVISOR (N) USED TO
GENERATE 16 × CLOCK
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL
50
10000
—
75
6667
0.005
110
4545
0.010
134.5
3717
0.013
150
333
0.010
300
1667
0.020
600
883
0.040
1200
417
0.080
1800
277
0.080
2000
250
—
2400
208
0.160
3600
139
0.080
4800
104
0.160
7200
69
0.644
9600
52
0.160
19200
26
0.160
38400
13
0.160
56000
9
0.790
128000
4
2.344
256000
2
2.344
512000
1
2.400
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TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PRINCIPLES OF OPERATION
programmable baud rate generator (continued)
Table 11. Baud Rates Using an 16-MHz Clock
BAUD RATE
DESIRED
DIVISOR (N) USED TO
GENERATE 16 × CLOCK
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL
50
20000
0
75
13334
0.00
110
9090
0.01
134.5
7434
0.01
150
6666
0.01
300
3334
– 0.02
600
1666
0.04
1200
834
– 0.08
1800
554
0.28
2000
500
0.00
2400
416
0.16
3600
278
– 0.08
4800
208
0.16
7200
138
0.64
9600
104
0.16
19200
52
0.16
38400
26
0.16
56000
18
– 0.79
128000
8
– 2.34
256000
4
– 2.34
512000
2
– 2.34
1000000
1
0.00
receiver
Serial asynchronous data is input into the RXx terminal. The ACE continually searches for a high-to-low
transition from the idle state. When the transition is detected, a counter is reset and counts the 16 × clock to
7 1/2, which is the center of the start bit. The start bit is valid when the RXx is still low. Verifying the start bits
prevents the receiver from assembling a false data character due to a low going noise spike on the RXx input.
The LCR determines the number of data bits in a character (LCR0, LCR1). When parity is enabled, LCR3 and
the polarity of parity LCR4 are needed. Status for the receiver is provided in the LSR. When a full character is
received including parity and stop bits, the data received indicator in LSR0 is set. The CPU reads the RBR, which
clears LSR0. If the character is not read prior to a new character transfer from the RSR to the RBR, the overrun
error status indicator is set in LSR1. If there is a parity error, the parity error is set in LSR2. If a stop bit is not
detected, a framing error indicator is set in LSR3.
In the FIFO mode operation, the data character and the associated error bits are stored in the receiver FIFO.
If the data into RXx is a symmetrical square wave, the center of the data cells occurs within ± 3.125% of the actual
center, providing an error margin of 46.875%. The start bit can begin as much as one 16 × clock cycle prior to
being detected.
28
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TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PRINCIPLES OF OPERATION
reset
After power up, the ACE RESET input should be held high for one microsecond to reset the ACE circuits to an
idle mode until initialization. A high on RESET causes the following:
1. It initializes the transmitter and receiver internal clock counters.
2. It clears the LSR, except for transmitter register empty (TEMT) and transmit holding register empty (THRE),
which are set. The MCR is also cleared. All of the discrete lines, memory elements, and miscellaneous logic
associated with these register bits are also cleared or turned off. The LCR, divisor latches, RBR, and
transmitter buffer register are not affected.
RXRDY operation
In mode 0, RXRDY is asserted (low) when the receive FIFO is not empty; it is released (high) when the FIFO
is empty. In this way, the receiver FIFO is read when RXRDY is asserted (low).
In mode 1, RXRDY is asserted (low) when the receive FIFO has filled to the trigger level or a character time-out
has occurred (four character times with no transmission of characters); it is released (high) when the FIFO is
empty. In this mode, multiple received characters are read by the DMA device, reducing the number of times
it is interrupted.
RXRDY and TXRDY outputs from each of the four internal ACEs of the TL16C554 are ANDed together
internally. This combined signal is brought out externally to RXRDY and TXRDY.
Following the removal of the reset condition (RESET low), the ACE remains in the idle mode until programmed.
A hardware reset of the ACE sets the THRE and TEMT status bits in the LSR. When interrupts are subsequently
enabled, an interrupt occurs due to THRE. A summary of the effect of a reset on the ACE is given in Table 12.
Table 12. RESET Affects on Registers and Signals
REGISTER/SIGNAL
RESET CONTROL
RESET STATE
Interrupt enable register
Reset
All bits cleared (0 – 3 forced and 4 – 7 permanent)
Interrupt identification register
Reset
Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared,
Bits 4 – 5 are permanently cleared
Line control register
Reset
All bits cleared
Modem control register
Reset
All bits cleared (5 – 7 permanent)
FIFO control register
Reset
All bits cleared
Line status register
Reset
All bits cleared, except bits 5 and 6 are set
Modem status register
Reset
Bits 0 – 3 cleared, bits 4 – 7 input signals
TXx
Reset
High
Read LSR/Reset
Low
Interrupt (RCVR ERRS)
Interrupt (receiver data ready)
Read RBR/Reset
Low
Read IIR/Write THR/Reset
Low
Read MSR/Reset
Low
RTS
Reset
High
DTR
Reset
High
Interrupt (THRE)
Interrupt (modem status changes)
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TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
PRINCIPLES OF OPERATION
scratchpad register
The scratch register is an 8-bit read/write register that has no affect on either channel in the ACE. It is intended
to be used by the programmer to hold data temporarily.
TXRDY operation
In mode 0, TXRDY is asserted (low) when the transmit FIFO is empty; it is released (high) when the FIFO
contains at least one byte. In this way, the FIFO is written with 16 bytes when TXRDY is asserted (low).
In mode 1, TXRDY is asserted (low) when the transmit FIFO is not full; in this mode, the transmit FIFO is written
with another byte when TXRDY is asserted (low).
VCC
VCC
Driver
XTAL1
External
Clock
XTAL1
C1
Crystal
RP
Optional
Driver
Optional
Clock
Output
RX2
Oscillator Clock
to Baud
Generator Logic
XTAL2
Oscillator Clock
to Baud
Generator Logic
XTAL2
C2
TYPICAL CRYSTAL OSCILLATOR NETWORK
CRYSTAL
RP
RX2
C1
C2
3.1 MHz
1 MΩ
1.5 kΩ
10 – 30 pF
40 – 60 pF
1.8 MHz
1 MΩ
1.5 kΩ
10 – 30 pF
40 – 60 pF
Figure 17. Typical Clock Circuits
30
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TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
MECHANICAL DATA
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
E
18
D2 / E2
E1
D2 / E2
14
8
0.021 (0,53)
0.013 (0,33)
0.007 (0,18) M
0.050 (1,27)
9
13
0.008 (0,20) NOM
D/E
D2 / E2
D1 / E1
NO. OF
PINS
**
MIN
MAX
MIN
MAX
MIN
MAX
20
0.385 (9,78)
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.169 (4,29)
28
0.485 (12,32)
0.495 (12,57)
0.450 (11,43)
0.456 (11,58)
0.191 (4,85)
0.219 (5,56)
44
0.685 (17,40)
0.695 (17,65)
0.650 (16,51)
0.656 (16,66)
0.291 (7,39)
0.319 (8,10)
52
0.785 (19,94)
0.795 (20,19)
0.750 (19,05)
0.756 (19,20)
0.341 (8,66)
0.369 (9,37)
68
0.985 (25,02)
0.995 (25,27)
0.950 (24,13)
0.958 (24,33)
0.441 (11,20)
0.469 (11,91)
84
1.185 (30,10)
1.195 (30,35)
1.150 (29,21)
1.158 (29,41)
0.541 (13,74)
0.569 (14,45)
4040005 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
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TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
MECHANICAL DATA
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
41
60
61
40
80
21
0,13 NOM
1
20
Gage Plane
9,50 TYP
12,20
SQ
11,80
14,20
SQ
13,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 / B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
32
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