3D7701 MONOLITHIC GATED DELAY LINE OSCILLATOR (SERIES 3D7701) FEATURES • • • • • • • • • PACKAGES All-silicon, low-power CMOS technology TTL/CMOS compatible inputs and outputs Vapor phase, IR and wave solderable Auto-insertable (DIP pkg.) Frequency range: 0.3MHz through 100MHz Frequency tolerance: 0.5% typical Temperature stability: ±1.5% typical (-40C to 85C) Vdd stability: ±0.5% typical (4.75V to 5.25V) 14-pin DIP available as drop-in replacements for hybrid delay line oscillator (DLO31F) O1 NC NC GND 1 2 3 4 8 7 6 5 VDD NC O2 EN O1 1 14 VDD NC 2 13 NC NC 3 12 NC NC 4 11 NC NC 5 10 O2 NC 6 9 NC GND 7 8 EN 3D7701Z-xx SOIC-8 3D7701-xx 3D7701K-xx DIP-14 NC pins removed For mechanical dimensions, click here. For package marking details, click here. FUNCTIONAL DESCRIPTION PIN DESCRIPTIONS The 3D7701 Delay Line Oscillator product family consists of fixedEN Oscillator Enable frequency CMOS integrated circuit oscillators. Each package contains a O1 Oscillator Output 1 single oscillator, which is gated and can therefore be synchronized to an O2 Oscillator Output 2 external signal. The device frequency can range from 0.3MHz through VDD +5 Volts 100MHz. The 3D7701 has two outputs that are in phase when the GND Ground oscillator is running, and can be used as a drop-in replacement for the DLO31F hybrid oscillator. The 3D7701 is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads. It is offered in a standard 14-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC package. TABLE 1: PART NUMBER SPECIFICATIONS DASH NUMBER -0.3 -0.4 -0.5 -0.75 -1 -2 -2.5 -3 -4 -5 -7.5 -10 -20 -25 -30 -40 -50 -75 -100 NOTE: OUTPUT FREQUENCY (MHz) 25C -40C to 85C Vdd=5.00V 4.75<Vdd<5.25 0.3 ± 0.002 0.3 ± 0.008 0.4 ± 0.002 0.4 ± 0.010 0.5 ± 0.003 0.5 ± 0.013 0.75 ± 0.004 0.75 ± 0.019 1.0 ± 0.005 1.0 ± 0.025 2.0 ± 0.010 2.0 ± 0.050 2.5 ± 0.013 2.5 ± 0.063 3.0 ± 0.015 3.0 ± 0.075 4.0 ± 0.020 4.0 ± 0.100 5.0 ± 0.025 5.0 ± 0.125 7.5 ± 0.038 7.5 ± 0.188 10.0 ± 0.05 10.0 ± 0.25 20.0 ± 0.10 20.0 ± 0.50 25.0 ± 0.13 25.0 ± 0.63 30.0 ± 0.15 30.0 ± 0.75 40.0 ± 0.20 40.0 ± 1.00 50.0 ± 0.25 50.0 ± 1.25 75.0 ± 0.38 75.0 ± 3.75 100.0 ± 0.50 100.0 ± 7.00 Any dash number between 0.3 and 100 not shown is also available as standard. Doc #06023 12/5/2006 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 2006 Data Delay Devices 1 3D7701 APPLICATION NOTES OPERATIONAL DESCRIPTION The 3D7701 delay line oscillator architecture is shown in Figure 1. The internal delay line is composed of a number of delay cells connected in series and is compensated for thermal and supply voltage variations. A low-going edge on the EN input starts the oscillator, with the O2 output responding immediately. The O1 output is delayed by ½ cycle. The response of the output when the oscillator is disabled depends on the status of O2 when the EN signal goes high, as shown in Figure 2. If O2 is low, it will remain low, and the final pulse on O1 will be ½ of the period. If O2 is high, it will go low as soon as EN goes high, and the final pulse on both outputs will have a width smaller than ½ the period. Temp & Vdd Compensation VDD O1 GND Delay Line O2 EN Figure 1: 3D7701 Functional Diagram EN 5ns typ O2 O1 EN 5ns typ 5ns typ O2 O1 Figure 2: 3D7701 Timing Diagrams Doc #06023 12/5/2006 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 2 3D7701 APPLICATION NOTES (CONT’D) temperature frequency setting. The power supply coefficient is reduced, over the 4.75V to 5.25V operating range, to ±0.5% of the frequency setting at the nominal 5.0VDC power supply. These specifications hold for the lower frequencies only. For higher dash numbers, the variations will be slightly greater, as noted in Table 1. It is essential that the power supply pin be adequately bypassed and filtered. In addition, the power bus should be of as low an impedance construction as possible. Power planes are preferred. POWER SUPPLY AND TEMPERATURE CONSIDERATIONS The delay of CMOS integrated circuits is strongly dependent on power supply and temperature. The monolithic 3D7701 oscillator utilizes novel and innovative compensation circuitry to minimize the frequency variations induced by fluctuations in power supply and/or temperature. The thermal coefficient is reduced to 250 PPM/C, which is equivalent to a variation, over the -40C to 85C operating range, of ±1.5% from the room- DEVICE SPECIFICATIONS TABLE 2: ABSOLUTE MAXIMUM RATINGS PARAMETER DC Supply Voltage Input Pin Voltage Input Pin Current Storage Temperature Lead Temperature SYMBOL VDD VIN IIN TSTRG TLEAD MIN -0.3 -0.3 -1.0 -55 MAX 7.0 VDD+0.3 1.0 150 300 UNITS V V mA C C NOTES 25C 10 sec TABLE 3: DC ELECTRICAL CHARACTERISTICS (-40C to 85C, 4.75V to 5.25V) PARAMETER Static Supply Current* High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Current Low Level Output Current Output Rise & Fall Time SYMBOL IDD VIH VIL IIH IIL IOH MIN IOL 4.0 12/5/2006 MAX 5.5 -35.0 0.8 1.0 1.0 -4.0 2.0 TR & TF *IDD(Dynamic) = 2 * CLD * VDD * F where: CLD = Average capacitance load/output (pf) F = Device frequency (GHz) Doc #06023 TYP 3.5 15.0 2.0 UNITS mA V V µA µA mA mA 2.5 ns NOTES VIH = VDD VIL = 0V VDD = 4.75V VOH = 2.4V VDD = 4.75V VOL = 0.4V CLD = 5 pf Input Capacitance = 10 pf typical Output Load Capacitance (CLD) = 25 pf max DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 3 3D7701 SILICON DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: Ambient Temperature: 25oC ± 3oC Supply Voltage (Vcc): 5.0V ± 0.1V Input Pulse: High = 3.0V ± 0.1V Low = 0.0V ± 0.1V Source Impedance: 50Ω Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6V and 2.4V ) OUTPUT: Rload: Cload: Threshold: Device Under Test 10KΩ ± 10% 5pf ± 10% 1.5V (Rising & Falling) Digital Scope 10KΩ 470Ω 5pf NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. PRINTER COMPUTER SYSTEM REF O1 PULSE GENERATOR OUT EN TRIG DEVICE UNDER TEST (DUT) IN O2 TRIG FREQUENCY/ TIME INTERVAL COUNTER Figure 3: Test Setup tFALL EN tRISE 2.4V 1.5V 0.6V VIL 1/fOSC tENB O2 1.5V 2.4VVIH 1.5V 0.6V tDIS 1.5V 1.5V Figure 4: Timing Diagram Doc #06023 12/5/2006 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 4