ETC TSXPC603RMGSU14LC

Features
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7.4 SPECint95, 6.1 SPECfp95 @ 300 MHz (estimated)
Superscalar (3 instructions per clock peak)
Dual 16 KB Caches
Selectable Bus Clock
32-bit Compatibility PowerPC Implementation
On Chip Debug Support
PD typical = 3.5 Watts (266 MHz), Full Operating Conditions
Nap, Doze and Sleep Modes for Power Savings
Branch Folding
64-bit Data Bus (32-bit Data Bus Option)
4G byte Direct Addressing Range
Pipelined Single/double Precision Float Unit
IEEE 754 Compatible FPU
IEEE P 1149-1 Test Mode (JTAG/C0P)
fint max = 300 MHz
fbus max = 75 MHz
Compatible CMOS Input / TTL Output
Screening / Quality / Packaging
This product is manufactured in full compliance with:
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CI-CGA 255: MIL-STD-883 class Q or According to ATMEL-Grenoble standards
•
CBGA 255: Upscreenings based upon ATMEL-Grenoble standards
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Full Military Temperature Range (Tc = -55°C, Tc= +125°C)
IndustriaL Temperature Range (Tc = -40°C, Tc= +110°C)
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Internal // I/O Power Supply = 2.5 ± 5% // 3.3V ± 5%
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255 Pin CBGA Package and 255 Pin CBGA with SCI (CI-CGA) Package
PowerPC
603e™ RISC
Microprocessor
Family
PID7t-603e
Specification
TSPC603R
Description
The PID7t-603e implementation of PowerPC603e (after named 603r) is a low-power
implementation of reduced instruction set computer (RISC) microprocessors PowerPC family. The 603r implements 32-bit effective addresses, integer data types of
8, 16 and 32 bits, and floating-point data types of 32 and 64 bits.
The 603r is a low-power 2.5/3.3-volt design and provides four software controllable
power-saving modes.
The 603r is a superscalar processor capable of issuing and retiring as many as three
instructions per clock. Instructions can execute out of order for increased performance; however, the 603r makes completion appear sequential. The 603r integrates
five execution units and is able to execute five instructions in parallel.
The 603r provides independent on-chip, 16K byte, four-way set-associative, physically addressed caches for instructions and data and on-chip instruction and data
memory management units (MMUs). The MMUs contain 64-entry, two-way set-associative, data and instruction translation look aside buffers that provide support for
demand-paged virtual memory address translation and variable-sized block
translation.
The 603r has a selectable 32 or 64-bit data bus and a 32-bit address bus. The 603r
interface protocol allows multiple masters to complete for system resources through a
central external arbiter. The 603r supports single-beat and burst data transfers for
memory accesses, and supports memory-mapped I/O.
Rev. 2125A–12/01
1
The 603r uses an advanced, 2.5/3.3V CMOS process technology and maintains full interface compatibility with TTL
devices.
The 603r integrates in system testability and debugging features through JTAG boundary-scan capability.
G suffix
CBGA 255
Ceramic Ball Grid Array
General
Description
GS suffix
CI-CGA 255
Ceramic Ball Grid Array
with Solder Column Interposer (SCI)
Figure 1. Block Diagram
Fetch
Unit
Completion
Unit
Integer
Unit
Gen
Reg
Unit
Branch
Unit
Dispatch
Unit
Load/
Store
Unit
Gen
Rename
FP
Rename
FP
Reg
File
D MMU
I MMU
16K Data Cache
16K Inst. Cache
Float
Unit
Bus Interface Unit
64b
data
32b
address
System Bus
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TSPC603R
2125A–12/01
TSPC603R
Introduction
The 603r is a low-power implementation of the PowerPC microprocessor family of reduced
instruction set computer (RISC) microprocessors. The 603r implements the 32-bit portion of
the PowerPC architecture, which provides 32-bit effective addresses, integer data types of 8,
16 and 32 bits, and floating-point data types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC architecture provides 64-bit integer data types, 64-bit addressing, and
other features required to complete the 64-bit architecture.
The 603r provides four software controllable power-saving modes. Three of the modes (the
nap, doze, and sleep modes) are static in nature, and progressively reduce the amount of
power dissipated by the processor. The fourth is a dynamic power management mode that
causes the functional units in the 603r to automatically enter a low-power mode when the
functional units are idle without affecting operational performance, software execution, or any
external hardware.
The 603r is a superscalar processor capable of issuing and retiring as many as three instructions per clock. Instructions can execute out of order for increased performance; however, the
603r makes completion appear sequential.
The 603e integrates five execution units—an integer unit (IU), a floating-point unit (FPU), a
branch processing unit (BPU), a load/store unit (LSU) and a system register unit (SRU). The
ability to execute five instructions in parallel and the use of simple instructions with rapid execution times yield high efficiency and throughput for 603r-based systems. Most integer
instructions execute in one clock cycle. The FPU is pipelined so a single-precision multiply-add instruction can be issued every clock cycle.
The 603r provides independent on-chip, 16K byte, four-way set-associative, physically
addressed caches for instructions and data and on-chip instruction and data memory management units (MMUs). The MMUs contain 64-entry, two-way set-associative, data and
instruction translation look aside buffers (DTLB and ITLB) that provide support for
demand-paged virtual memory address translation and variable-sized block translation. The
TLBs and caches use a least recently used (LRU) replacement algorithm. The 603r also supports block address translation through the use of two independent instruction and data block
address translation (IBAT and DBAT) arrays of four entries each. Effective addresses are
compared simultaneously with all four entries in the BAT array during block translation. In
accordance with the PowerPC architecture, if an effective address hits in both the TLB and
BAT array, the BAT translation takes priority.
The 603r has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603r interface
protocol allows multiple masters to compete for system resources through a central external
arbiter. The 603r provides a three-state coherency protocol that supports the exclusive, modified, and invalid cache states. This protocol as a compatible subset of the MESI
(modified/exclusive/shared/invalid) four-state protocol and operates coherently in systems that
contain four-state caches. The 603r supports single-beat and burst data transfers for memory
accesses, and supports memory-mapped I/O.
The 603r uses an advanced, 0.29 µm 5 metal layer CMOS process technology and maintains
full interface compatibility with TTL devices.
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Pin Assignments
CBGA 255 and CI-CGA
255 Packages
Figure 2 (pin matrix) shows the pinout as viewed from the top of the CBGA and CI-CGA packages. The direction of the top surface view is shown by the side profile of the packages.
Figure 2. CBGA 255 and CI–CGA 255 Top View
Pin matrix top view
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Substrate Assembly
Die
View
CBGA 255
Encapsulant
CI±CGA 255
Not to scale
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TSPC603R
2125A–12/01
TSPC603R
Pinout Listing
Table 1. Power and Ground Pins
VDD2
PLL (AVDD)
A10
Internal Logic
F06, F08, F09, F11, G07, G10, H06, H08, H09, H11,
J06, J08, J09, J11, K07, K10, L06, L08, L09, L11
Output Drivers
C07, E05, E07, E10, E12, G03, G05, G12, G14, K03,
K05, K12, K14, M05, M07, M10, M12, P07, P10
GND
C05, C12, E03, E06, E08, E09, E11, E14, F05, F07,
F10, F12, G06, G08, G09, G11, H05, H07, H10, H12,
J05, J07, J10, J12, K06, K08, K09, K11, L05, L07, L10,
L12, M03, M06, M08, M09, M11, M14, P05, P12
Table 2. Signal Pinout Listing
Signal Name
CBGA Pin Number
Active
I/O
A[0-31]
C16, E04, D13, F02, D14, G01, D15, E02, D16, D04, E13, G02, E15, H01, E16, H02,
F13, J01, F14, J02, F15, H03, F16, F04, G13, K01, G15, K02, H16, M01, J15, P01
High
I/O
AACK
L02
Low
Input
ABB
K04
Low
I/O
AP[0-3]
C01, B04, B03, B02
High
I/O
APE
A04
Low
Output
ARTRY
J04
Low
I/O
BG
L01
Low
Input
BR
B06
Low
Output
CI
E01
Low
Output
CKSTP_IN
D08
Low
Input
CKSTP_OUT
A06
Low
Output
CLK_OUT
D07
-
Output
CSE[0-1]
B01, B05
High
Output
DBB
J14
Low
I/O
DBG
N01
Low
Input
DBDIS
H15
Low
Input
DBWO
G04
Low
Input
DH[0-31]
P14, T16, R15, T15, R13, R12, P11, N11, R11, T12, T11, R10, P09, N09, T10, R09,
T09, P08, N08, R08, T08, N07, R07, T07, P06, N06, R06, T06, R05, N05, T05, T04
High
I/O
DL[0-31]
K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16, P15,
R16, R14, T14, N10, P13, N12, T13, P03, N03, N04, R03, T01, T02, P04, T03, R04
High
I/O
DP[0-7]
M02, L03, N02, L04, R01, P02, M04, R02
High
I/O
DPE
A05
Low
Output
DRTRY
G16
Low
Input
GBL
F01
Low
I/O
HRESET
A07
Low
Input
INT
B15
Low
Input
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Table 2. Signal Pinout Listing
Signal Name
Active
I/O
D11
-
Input
L2_TSTCLK
D12
-
Input
LSSD_MODE(1)
B10
Low
Input
MCP
C13
Low
Input
PLL_CFG[0-3]
A08, B09, A09, D09
High
Input
QACK
D03
Low
Input
QREQ
J03
Low
Output
RSRV
D01
Low
Output
SMI
A16
Low
Input
SRESET
B14
Low
Input
SYSCLK
C09
-
Input
TA
H14
Low
Input
TBEN
C02
High
Input
TBST
A14
Low
I/O
TC[0-1]
A02, A03
High
Output
TCK
C11
-
Input
TDI
A11
High
Input
TDO
A12
High
Output
TEA
H13
Low
Input
TLBISYNC
C04
Low
Input
TMS
B11
High
Input
TRST
C10
Low
Input
TS
J13
Low
I/O
TSIZ[0-2]
A13, D10, B12
High
I/O
TT[0-4]
B13, A15, B16, C14, C15
High
I/O
WT
D02
Low
Output
B07, B08, C03, C06, C08, D05, D06, F03, H04, J16
Low
Input
(1)
(1)
CBGA Pin Number
L1_TSTCLK
NC
(3)
VOLTDETGND
F03
Low
Output
Notes: 1. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.
2. OVDD inputs supply power to the I/O drivers and VDD inputs supply power to the processor core.
3. NC (no-connect) in the 603e BGA package; internally tied to GND in the 603r BGA package to indicate to the power supply
that a low-voltage processor is present.
Signal Description
Figure 3, Table 3 and Table 4 describe the signals on the TSPC603r and indicate signal functions. The test signals, TRST, TMS, TCK, TDI and TDO, comply with subset P-1149.1 of the
IEEE testability bus standard.
The 3 signals LSSD_MODE, LI_TSTCLK and L2_TSTCLK are test signals for factory use only
and must be pulled up to VDD for normal machine operations.
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TSPC603R
Figure 3. Functional Signal Groups
BG
ADDRESS
ARBITRATION
ABB
ADDRESS
START
TS
A[0-31]
ADDRESS
BUS
AP[0-3]
APE
TT[0-4]
TBST
TSIZ[0-2]
GBL
TRANSFER
ATTRIBUTE
CI
WT
1
1
1
1
1
1
1
64
32
8
1
1
4
PLL_CFG[0-3]
POWER SUPPLY
INDICATOR
VOLTDETGND
DPE
DATA
TRANSFER
DBDIS
INT, SMI
1
1
1
2
CKSTP_IN, CKSTP_OUT
2
HRESET, SRESET
INTERRUPTS
CHECKSTOPS
RESET
1
RSRV
QREQ, QACK
TBEN
PROCESSOR
STATUS
1
1
1
1
5
CLOCKS
DP[0-7]
2
2
SYSCLK
DH[0-31], DL[0-31]
3
TC[0-1]
CLK_OUT
DATA
ATTRIBUTION
DRTRY
TEA
1
2
ARTRY
DBB
1
1
5
1
2
ADDRESS
TERMINATION
DBWO
TA
CSE[0-1]
AACK
DBG
1
1
603r
BR
1
1
3
4
1
MCP
TLBISYNC
TRST, TCK, TMS, TDI, TD0
LSSD_MODE,
L1_TSTCLK, L2_TSTCLK
20
VDD
19
OVDD
40
1
DATA
TERMINATION
GND
JTAG/COP
INTERFACE
LSSD TEST
CONTROL
POWER SUPPLY
AVDD
Table 3. Address and data bus signal index
Signal
type
Signal Name
Mnemonic
Signal function
Address Bus
A[0-31]
if output, physical address of data to be transferred.
if input, represents the physical address of a snoop operation.
I/O
Data Bus
DH[0-31]
Represents the state of data, during a data write operation if output, or during a
data read operation if input.
I/O
Data Bus
DL[0-31]
Represents the state of data, during a data write operation if output, or during a
data read operation if input.
I/O
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2125A–12/01
Table 4. Signal index
Signal Name
Mnemonic
Signal function
Signal
type
Address Acknowledge
AACK
The address phase of a transaction is complete
Input
Address Bus Busy
ABB
If output, the 603r is the address bus master
If input, the address bus is in use
I/O
Address Bus Parity
AP[0-3]
If output, represents odd parity for each of 4 bytes of the physical address for a
transaction
If input, represents odd parity for each of 4 bytes of the physical address for
snooping operations
I/O
Address Parity Error
APE
Incorrect address bus parity detected on a snoop
Output
Address Retry
ARTRY
If output, detects a condition in which a snooped address tenure must be
retried
If input, must retry the preceding address tenure
I/O
Bus Grant
BG
May, with the proper qualification, assume mastership of the address bus
Input
Bus Request
BR
Request mastership of the address bus
Output
Cache Inhibit
Cl
A single-beat transfer will not be cached
Output
Test Clock
CLK_OUT
Provides PLL clock output for PLL testing and monitoring
Output
Checkstop Input
CKSTP_IN
Must terminate operation by internally gating off all clocks, and release all
outputs
Input
Checkstop Output
CKSTP_OUT
Has detected a checkstop condition and has ceased operation
Output
Cache Set Entry
CSE[0-1]
Cache replacement set element for the current transaction reloading into or
writing out of the cache
Output
Data Bus Busy
DBB
If output, the 603r is the data bus master
If input, another device is bus master
I/O
Data Bus Disable
DBDIS
(For a write transaction) must release data bus and the data bus parity to high
impedance during the following cycle
Input
Data Bus Grant
DBG
May, with the proper qualification, assume mastership of the data bus
Input
Data Bus Write Only
DBW0
May run the data bus tenure
Input
Data Bus Parity
DP[0-7]
If output, odd parity for each of 8 bytes of data write transactions
If input, odd parity for each byte of read data
I/O
Data Parity Error
DPE
Incorrect data bus parity
Output
Data Retry
DRTRY
Must invalidate the data from the previous read operation
Input
Global
GBL
If output, a transaction is global
If input, a transaction must be snooped by the 603r
I/O
Hard Reset
HRESET
Initiates a complete hard reset operation
Input
Interrupt
INT
Initiates an interrupt if bit EE of MSR register is set
Input
LSSD_MODE
LSSD test control signal for factory use only
Input
L1_TSTCLK
LSSD test control signal for factory use only
Input
L2_TSTCLK
LSSD test control signal for factory use only
Input
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TSPC603R
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TSPC603R
Table 4. Signal index
Signal
type
Signal Name
Mnemonic
Signal function
Machine Check
Interrupt
MCP
Initiates a machine check interrupt operation if the bit ME of MSR register and
bit EMCP of HID0 register are set
Input
PLL Configuration
PLL_CFG[0-3]
Configures the operation of the PLL and the internal processor clock frequency
Input
Quiescent
Acknowledge
QACK
All bus activity has terminated and the 603r may enter a quiescent (or low
power) state
Input
Quiescent Request
QREQ
Is requesting all bus activity normally to enter a quiescent (low power) state
Output
Reservation
RSRV
Represents the state of the reservation coherency bit in the reservation
address register
Output
System Management
Interrupt
SMI
Initiates a system management interrupt operation if the bit EE of MSR register
is set
Input
Soft Reset
SRESET
Initiates processing for a reset exception
Input
System Clock
SYSCLK
Represents the primary clock input for the 603r, and the bus clock frequency
for 603r bus operation
Input
Transfer Acknowledge
TA
A single-beat data transfer completed successfully or a data beat in a burst
transfer completed successfully
Input
Timebase Enable
TBEN
The timebase should continue clocking
Input
Transfer Burst
TBST
If output, a burst transfer is in progress
If input, when snooping for single-beat reads
I/O
Transfer Code
TC[0-1]
Special encoding for the transfer in progress
Output
Test Clock
TCK
Clock signal for the IEEE P1149.1 test access port (TAP)
Input
Test Data Input
TDI
Serial data input for the TAP
Input
Test Data Output
TDO
Serial data output for the TAP
Output
Transfer Error
Acknowledge
TEA
A bus error occurred
Input
TLBI Sync
TLBISYNC
Instruction execution should stop after execution of a tlbsync instruction
Input
Test Mode Select
TMS
Selects the principal operations of the test-support circuitry
Input
Test Reset
TRST
Provides an asynchronous reset of the TAP controller
Input
Transfer Size
TSIZ[0-2]
For memory accesses, these signals along with TBST indicate the data
transfer size for the current bus operation
I/O
Transfer start
TS
If output, begun a memory bus transaction and the address bus and transfer
attribute signals are valid
If input, another master has begun a bus transaction and the address bus and
transfer attribute signals are valid for snooping (see GBL)
I/O
Transfer Type
TT[0-4]
Type of transfer in progress
I/O
Write-Through
WT
A single-beat transaction is write-through
Output
Power supply indicator
VOLTDETGND
Available only on BGA package
Indicates to the power supply that a low-voltage processor is present.
Output
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2125A–12/01
Detailed
Specifications
Scope
This drawing describes the specific requirements for the microprocessor TSPC603r, in compliance with MIL-STD-883 class B or ATMEL-Grenoble standard screening.
Applicable
Documents
1. MIL-STD-883: Test methods and procedures for electronics.
2. MIL-PRF-38535: General specifications for microcircuits.
Requirements
General
The microcircuits are in accordance with the applicable documents and as specified herein.
Design and
construction
• Terminal connections
The terminal connections shall be as shown in Figure 15 and Figure 3.
• Lead material and finish
Lead material and finish shall be as specified in MIL-STD-1835.
Absolute Maximum
Ratings
Absolute maximum ratings are stress rating only and functional operation at the maximum is
not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent
damage to the device.
Table 5. Absolute Maximum Rating for the 603r
Parameter
Symbol
Min
Max
Unit
Core Supply Voltage
Vdd
-0.3
2.75
V
PLL Supply Voltage
AVdd
-0.3
2.75
V
I/O Supply Voltage
OVdd
-0.3
3.6
V
Input Voltage
Vin
-0.3
5.5
V
Storage Temperature Range
Tstg
-55
+150
°C
Notes:
1. Functional operating conditions are given in AC and DC electrical specifications. Stresses beyond the absolute maximums
listed may affect device reliability or cause permanent damage to the device.
2. Caution: Input voltage must not be greater than OVdd by more than 2.5V at any times, including during power-on reset.
3. Caution: OVdd voltage must not be greater than Vdd/AVdd by more than 1.2V at any times, including during power-on reset.
4. Caution: Vdd/AVdd voltage must not be greater than OVdd by more than 0.4V at any times, including during power-on reset.
Recommended
Operating Conditions
These are the recommended and tested operating conditions. Proper device operation outside
of these conditions is not guaranteed.
Parameter
Symbol
Min
Max
Unit
Core Supply Voltage
Vdd
2.375
2.625
V
PLL Supply Voltage
AVdd
2.375
2.625
V
I/O Supply Voltage
OVdd
3.135
3.465
V
Input Voltage
Vin
GND
5.5
V
Operating Temperature
Tc
-55
+125
°C
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TSPC603R
Thermal
Characteristics
The data found in this section concerns 603r’s packaged in the 255-lead 21 mm multi-layer
ceramic (MLC), ceramic BGA package. Data is shown for the case of using the Thermalloy
#2328B heat sink.
The internal thermal resistance for this package is negligible due to the exposed die design. A
thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance.
Additionally, the CBGA package offers an excellent thermal connection to the card and power
planes. Heat generated at the chip is dissipated through the package, the heat sink (when
used) and the card. The parallel heat flow paths result in the lowest overall thermal resistance
as well as offer significantly better power dissipation capability if a heat sink is not used.
The thermal characteristics for the flip-chip CBGA and CI-CGA packages are as follows:
Thermal resistance (junction-to-case) = Rjc or
θjc = 0.095°C/Watt for the 2 packages.
Thermal resistance (junction-to-ball) = Rjb or
θjb = 3.5°C/Watt for the CBGA package.
Thermal resistance (junction-to-bottom SCI) = Rjs or
θjs = 3.7°C/Watt for the CI-CGA package.
The junction temperature can be calculated from the junction to ambient thermal resistance,
as follow:
Junction temperature:
Tj = Ta + (Rjc + Rcs + Rsa) * P
Where:
Ta is the ambient temperature in the vicinity
of the device
Rjc is the die junction-to-case thermal
resistance of the device
Rcs is the case-to-heat sink thermal
resistance of the interface material
Rsa is the heat sink-to-ambient
thermal resistance
P is the power dissipated by the device
During operation, the die-junction temperatures (Tj) should be maintained less than the value
specified in Table 5.
The thermal resistance of the thermal interface material (Rcs) is typically about 1°C/Watt.
Assuming a Ta of 85°C and a consumption (P) of 3.6 Watts, the junction temperature of the
device would be as follow:
Tj = 85°C + (0.095°C/Watt + 1°C/Watt + Rsa) * 3.5 Watts.
For the Thermalloy heat sink #2328B, the heat sink-to-ambient thermal resistance (Rsa) versus
airflow velocity is shown in Figure 4.
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Figure 4. CBGA Thermal Management Example
Heat Sink Thermal Resistance
Rsa (˚C/W)
7
6
5
4
3
2
1
0
0
1
2
3
Approach air velocity (m/sec)
Assuming an air velocity of 1.0 m/sec, the associated overall thermal resistance and junction
temperature, found in Table 6 will result.
Table 6. Thermal Resistance and Junction Temperature
Configuration
With 2328B heat sink
Rja (°C/W)
Tj (°C)
5.0
106
Vendors such as Aavid Engineering Inc., Thermalloy, and Wakefield Engineering can supply
heat sinks with a wide range of thermal performance.
Power Consideration
The PowerPC603r is a microprocessor specifically designed for low-power operation. As the
603e microprocessor version, the 603r provides both automatic and program-controllable
power reduction modes for progressive reduction of power consumption. This chapter
describes the hardware support provided by the 603r for power management.
• Dynamic Power Management
Dynamic power management automatically powers up and down the individual execution units
of the 603r, based upon the contents of the instruction stream. For example, if no floating-point
instructions are being executed, the floating-point unit is automatically powered down. Power
is not actually removed from the execution unit; instead, each execution unit has an independent clock input, which is automatically controlled on a clock-by-clock basis. Since CMOS
circuits consume negligible power when they are not switching, stopping the clock to an execution unit effectively eliminates its power consumption. The operation of DPM is completely
transparent to software or any external hardware. Dynamic power management is enabled by
setting bit 11 in HID0 on power-up, of following HRESET.
• Programmable Power Modes
The 603r provides four programmable power states—full power, doze, nap and sleep. Software selects these modes by setting one (and only one) of the three power saving mode bits.
Hardware can enable a power management state through external asynchronous interrupts
The hardware interrupt causes the transfer of program flow to interrupt handler code. The
appropriate mode is then set by the software. The 603r provides a separate interrupt and interrupt vector for power management—the system management interrupt (SMI). The 603r also
contains a decrement timer which allows it to enter the nap or doze mode for a predetermined
amount of time and then return to full power operation through the decrementer interrupt (DI).
12
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TSPC603R
Note that the 603r cannot switch from on power management mode to another without first
returning to full on mode. The nap and sleep modes disable bus snooping; therefore, a hardware handshake is provided to ensure coherency before the 603r enters these power
management modes. Table 7 summarizes the four power states.
Table 7. Power PC 603r Microprocessor Programmable Power Modes
PM Mode
Functioning Units
Activation Method
Full-Power Wake Up Method
Full Power
All units active
—
—
Full Power (with DPM)
Requested logic by demand
By instruction dispatch
—
Doze
- Bus snooping
- Data cache as needed
- Decrementer timer
Controlled by SW
External asynchronous exceptions(1)
Decrementer interrupt
Reset
Nap
Decrementer timer
Controlled by hardware and
software
External asynchronous exceptions
Decrementer interrupt
Reset
Sleep
None
Controlled by hardware and
software
External asynchronous exceptions
Reset
Note:
1. Exceptions are referred to as interrupts in the architecture specification
• Power Management Modes
The following sections describe the characteristics of the 603r’s power management modes,
the requirements for entering and exiting the various modes, and the system capabilities provided by the 603r while the power management modes are active.
FULL-POWER MODE WITH DPM DISABLED: Full-power mode with DPM disabled power
mode is selected when the DPM enable bit (bit 11) in HID0 is cleared.
•
Default state following power-up and HRESET.
•
All functional units are operating at full processor speed at all times.
FULL-POWER MODE WITH DPM ENABLED: Full-power mode with DPM enabled (HID0[11]
= 1) provides on-chip power management without affecting the functionality or performance of
the 603r.
•
Required functional units are operating at full processor speed.
•
Functional units are clocked only when needed.
•
No software or hardware intervention required after mode is set.
•
Software/hardware and performance transparent.
DOZE MODE: Doze mode disables most functional units but maintains cache coherency by
enabling the bus interface unit and snooping. A snoop hit will cause the 603r to enable the
data cache, copy the data back to memory, disable the cache, and fully return to the doze
state.
•
Most functional units disabled.
•
Bus snooping and time base/decrementer still enabled.
•
Dose mode sequence:
- Set doze bit (HID0[8) = 1).
- 603r enters doze mode after several processor clocks.
•
Several methods of returning to full-power mode:
- Assert INT, SMI, MCP or decrementer interrupts.
- Assert hard reset or soft reset.
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•
Transition to full-power state takes no more than a few processor cycles.
•
PLL running and locked to SYSCLK.
NAP MODE: The nap mode disables the 603r but still maintains the phase locked loop (PLL)
and the time base/decrementer. The time base can be used to restore the 603r to full-on state
after a programmed amount of time. Because bus snooping is disabled for nap and sleep
mode, a hardware handshake using the quiesce request (QREQ) and quiesce acknowledge
(QACK) signals are requires to maintain data coherency. The 603r will assert the QREQ signal
to indicate that it is ready to disable bus snooping. When the system has ensured that snooping is no longer necessary, it will assert QACK and the 603r will enter the sleep or nap mode.
•
Time base/decrementer still enabled.
•
Most functional units disabled (including bus snooping).
•
All nonessential input receivers disables.
•
Nap mode sequence:
- Set nap bit (HID0[9] = 1).
- 603r asserts quiesce request (QREQ) signal.
- System asserts quiesce acknowledge (QACK) signal.
- 603r enters sleep mode after several processor clocks.
•
Several methods of returning to full-power mode:
- Assert INT, SPI, MCP or decrementer interrupts.
- Assert hard reset or soft reset.
•
Transition to full-power takes no more than a few processor cycles.
•
PLL running and locked to SYSCLK.
SLEEP MODE: Sleep mode consumes the least amount of power of the four modes since all
functional units are disabled. To conserve the maximum amount of power, the PLL may be
disabled and the SYSCLK may be removed. Due to the fully static design of the 603r, internal
processor state is preserved when no internal clock is present. Because the time base and
decrementer are disabled while the 603r is in sleep mode, the 603r’s time base contents will
have to be updated from an external time base following sleep mode if accurate time-of-day
maintenance is required. Before the 603r enters the sleep mode, the 603r will assert the
QREQ signal to indicate that it is ready to disable bus snooping. When the system has
ensured that snooping is no longer necessary, it will assert QACK and the 603r will enter the
sleep mode.
14
•
All functional units disabled (including bus snooping and time base).
•
All nonessential input receivers disabled:
- Internal clock regenerators disabled.
- PLL still running (see below).
•
Sleep mode sequence:
- Set sleep bit (HID0[10] = 1).
- 603r asserts quiesce request (QREQ).
- System asserts quiesce acknowledge (QACK).
- 603r enters sleep mode after several processor clocks.
•
Several methods of returning to full-power mode:
- Assert INT, SMI, or MCP interrupts.
- Assert hard reset or soft reset.
•
PLL may be disabled and SYSCLK may be removed while in sleep mode.
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TSPC603R
•
Return to full-power mode after PLL and SYSCLK disabled in sleep mode:
- Enable SYSCLK.
- Reconfigure PLL into desired processor clock mode.
- System logic waits for PLL startup and relock time (100 µsec).
- System logic asserts one of the sleep recovery signals (for example, INT or SMI).
• Power Management Software Considerations
Since the 603r is a dual issue processor with out-of-order execution capability, care must be
taken in how the power management mode is entered. Furthermore, nap and sleep modes
require all outstanding bus operations to be completed before the power management mode is
entered. Normally during system configuration time, one of the power management modes
would be selected by setting the appropriate HID0 mode bit. Later on, the power management
mode is invoked by setting the MSR[POW] bit. To provide a clean transition into and out of the
power management mode, the stmsr[POW] should be preceded by a sync instruction and followed by an isync instruction.
• Power Dissipation
Table 8. Power Dissipation
Vdd/AVdd = 2.5 ± 5%V dc, OVdd = 3.3 ± 5%V dc, GND = 0V dc, 0°C ≤ TC ≤ 125°C
CPU Clock Frequency
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
Units
Full-On Mode (DPM Enabled)
Typical
2.1
2.5
3.0
3.5
4.0
W
Max
3.2
4.0
4.6
5.3
6.0
W
1.5
1.7
1.8
2.0
2.1
W
100
120
140
160
180
mW
96
110
123
135
150
mW
60
60
60
60
mW
Doze Mode
Typical
Nap Mode
Typical
Sleep Mode
Typical
Sleep Mode-PLL Disabled
Typical
60
Sleep Mode-PLL and SYSCLK Disabled
Typical
25
25
25
25
25
mW
Maximum
60
60
60
80
100
mW
Notes:
1. These values apply for all valid PLL_CFG[0-3] settings and do not include output driver power (OVDD) or analog supply
power (AVDD). OVDD power is system dependent but is typically ≤10% of VDD. Worst-case AVDD = 15 mW.
2. Typical power is an average value measured at VDD = AVDD = 2.5V, OVV = 3.3V, in a system executing typical applications
and benchmark sequences.
3. Maximum power is measured at VDD = 2.625V using a worst-case instruction mix.
4. To calculate the power consumption at low temperature (-55°C), use a factor of 1.25.
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Marking
The document where are defined the marking are identified in the related reference documents. Each microcircuit are legible and permanently marked with the following information as
minimum:
•
ATMEL logo,
•
Manufacturer’s part number,
•
Class B identification if applicable,
•
Date-code of inspection lot,
•
ESD identifier if available,
•
Country of manufacturing.
Electrical
Characteristics
General Requirements
All static and dynamic electrical characteristics specified for inspection purposes and the relevant measurement conditions are given below:
•
Table 9: Static electrical characteristics for the electrical variants.
•
Table 10: Dynamic electrical characteristics for the 603r.
These specifications are for 166 MHz to 300 MHz processor core frequencies. The processor
core frequency is determined by the bus (SYSCLK) frequency and the settings of the
PLL_CFG0 to PLL_CFG3 signals. All timings are specified respective to the rise edge of
SYSCLK.
Static Characteristics
Table 9. Electrical Characteristics
Vdd = AVdd = 2.5V ± 5%; OVdd = 3.3 ± 5%V dc, GND = 0V dc, -55°C ≤ TC ≤ 125°C
Characteristics
Symbol
Min
Max
Unit
Input High Voltage (all inputs except SYSCLK)
VIH
2.0
5.5
V
Input Low Voltage (all inputs except SYSCLK)
VIL
GND
0.8
V
SYSCLK Input High Voltage
CVIH
2.4
5.5
V
SYSCLK Input Low Voltage
CVIL
GND
0.4
V
Iin
-
30
µA
Iin
-
300
µA
ITSI
-
30
µA
Input Leakage Current
Vin = 3.465V(1)(3)
(1)(3)
Vin = 5.5V
(1)(3)
Hi-Z (off-state)
Leakage Current
Vin = 3.465V
Vin = 5.5V
ITSI
-
300
µA
Output High Voltage
IOH = -7 mA
VOH
2.4
-
V
IOL = +7 mA
VOL
-
0.4
V
Capacitance, Vin = 0V, f = 1 MHz
(excludes TS, ABB, DBB, and ARTRY)
Cin
-
10.0
pF
Capacitance, Vin = 0V, f = 1 MHz(2)
(for TS, ABB, DBB, and ARTRY)
Cin
-
15.0
pF
Output Low Voltage
(1)(3)
(2)
Notes:
16
1. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK, and JTAG signals).
2. Capacitance is periodically sampled rather than 100% tested.
3. Leakage currents are measured for nominal OVdd and Vdd or both OVdd and Vdd. Same variation (for example, both Vdd and
OVdd vary by either +5% or -5%).
TSPC603R
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TSPC603R
Dynamic
Characteristics
• Clock AC Specifications
Table 10 provides the clock AC timing specifications as defined in Figure 5.
Table 10. Clock AC Timing Specifications
Vdd = AVdd = 2.5V ± 5%; OVdd = 3.3 ± 5%V dc, GND = 0V dc, -55°C ≤ TC ≤ 125°C
166 MHz
Num
200 MHz
233 MHz
266 MHz
300 MHz
Characteristics
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Note
Processor Frequency
150
166
150
200
180
233
180
266
180
300
MHz
5
VCO Frequency
300
332
300
400
360
466
360
532
360
600
MHz
5
SYSCLK (bus)
Frequency
25
66.7
33.3
66.7
33.3
75
33.3
75
33.3
75
MHz
5
1
SYSCLK Cycle Time
15
30
13.3
30
13.3
30
13.3
30
13.3
30
ns
2,3
SYSCLK Rise and Fall
Time
-
2.0
-
2.0
-
2.0
-
2.0
-
2.0
ns
1
4
SYSCLK Duty Cycle
(1.4V measured)
40.0
60.0
40.0
60.0
40.0
60.0
40.0
60.0
40.0
60.0
%
3
SYSCLK Jitter
-
±150
-
±150
-
±150
-
±150
-
±150
ps
2
603r Internal PLL
Relock Time
-
100
-
100
-
100
-
100
-
100
µs
3,4
Notes:
1.
2.
3.
4.
Rise and fall times for the SYSCLK input are measured from 0.4V to 2.4V.
Cycle-to-cycle jitter is guaranteed by design.
Timing is guaranteed by design and characterization, and is not tested.
PLL relock time is the maximum amount of time required for PLL lock after a stable Vdd, OVdd, AVdd and SYSCLK are
reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after
the PLL relock time (100 µs) during the power-on reset sequence.
5. Caution: The SYSCLK frequency and PLL_CFG[0-3] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0-3] signal description for valid PLL_CFG[0-3] settings.
Figure 5. SYSCLK Input Timing Diagram
• Input AC specifications
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Table 11 provides the input AC timing specifications for the 603r as defined in Figure 6 and
Figure 7.
Table 11. Input AC Timing Specifications
Vdd = AVdd = 2.5V ± 5%; OVdd = 3.3 ± 5%V dc, GND = 0V dc, -55°C ≤ TC ≤ 125°C
166,200 MHz
233,266 MHz
300 MHz
Num
Characteristics
Min
Max
Min
Max
Min
Max
Unit
Note
10a
Address/data/transfer attribute inputs valid to SYSCLK
(input setup)
2.5
-
2.5
-
2.5
-
ns
2
10b
All other inputs valid to SYSCLK (input setup)
4.0
-
3.5
-
3.5
-
ns
3
10c
Mode select inputs valid to HRESET (input setup) (for
DRTRY, QACK and TLBISYNC)
8
-
8
-
8
-
tsysclk
4,5,6,
7
11a
SYSCLK to address/data/transfer attribute inputs invalid
(input hold)
1.0
-
1.0
-
1.0
-
ns
2
11b
SYSCLK to all other inputs invalid (input hold)
1.0
-
1.0
-
1.0
-
ns
3
11c
HRESET to mode select inputs invalid (input hold) (for
DRTRY, QACK, and TLBISYNC)
0
-
0
-
0
-
ns
4,6,7
Notes:
1. All input specifications are measured from the TTL level (0.8 or 2.0V) of the signal in question to the 1.4V of the rising edge
of the input SYSCLK. Both input and output timings are measured at the pin. See Figure 7.
2. Address/data/transfer attribute input signals are composed of the following: A[0-31], AP[0-3], TT[0-4], TC[0-1], TBST,
TSIZ[0-2], GBL, DH[0-31], DL[0-31], DP[9-7].
3. All other input signals are composed of the following: TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO, TA, DRTRY, TEA,
DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC.
4. The setup and hold time is with respect to the rising edge of HRESET. See Figure 7.
5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied
by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.
6. These values are guaranteed by design, and are not tested.
7. This specification is for configuration mode only. Also note that HRESET must be held asserted for a minimum of 255 bus
clocks after the PLL relock time (100 µs) during the power-on reset sequence.
Figure 6. Input Timing Diagram
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TSPC603R
Figure 7. Mode Select Input Timing Diagram
• Output AC Specifications
Table 12 provides the output AC timing specifications for the 603r (shown in Figure 8).
Table 12. Output AC Timing Specifications
Vdd = AVdd = 2.5V ± 5%; OVdd = 3.3 ± 5%V dc, GND = 0V dc, CL = 50 pF, -55°C ≤ TC ≤ 125°C
166,200 MHz
233,266 MHz
Characteristic
Min
Max
Min
Max
Min
Max
Unit
12
SYSCLK to output driven (output enable time)
1.0
-
1.0
-
1.0
-
ns
13a
SYSCLK to output valid (5.5V to 0.8V—TS, ABB,
ARTRY, DBB)
-
9.0
-
9.0
-
9.0
ns
4
13b
SYSCLK to output valid (TS, ABB, ARTRY, DBB)
-
8.0
-
8.0
-
8.0
ns
6
14a
SYSCLK to output valid (5.5V to 0.8V—all except TS,
ABB, ARTRY, DBB)
-
11.0
-
11.0
-
11.0
ns
4
14b
SYSCLK to output valid (all except
TS,ABB,ARTRY,DBB)
-
9.0
-
9.0
-
9.0
ns
6
15
SYSCLK to output invalid (output hold)
1.0
-
1.0
-
1.0
-
ns
3
16
SYSCLK to output high impedance (all except ARTRY,
ABB, DBB)
-
8.5
-
8.0
-
8.0
ns
17
SYSCLK to ABB, DBB, high impedance after
precharge
-
1.0
-
1.0
-
1.0
tsysclk
18
SYSCLK to ARTRY high impedance before precharge
-
8.0
-
7.5
-
7.5
ns
19
SYSCLK to ARTRY precharge enable
0.2 *
tsysclk
+ 1.0
-
0.2 *
tsysclk
+ 1.0
-
0.2 *
tsysclk
+ 1.0
-
ns
3, 5,
8
20
Maximum delay to ARTRY precharge
-
1.0
-
1.0
-
1.0
tsysclk
5, 8
21
SYSCLK to ARTRY high impedance after precharge
-
2.0
-
2.0
-
2.0
tsysclk
6, 8
Num
Notes:
300 MHz
Note
5, 7
1. All output specifications are measured from the 1.4V of the rising edge of SYSCLK to the TTL level (0.8V or 2.0V) of the signal in question. Both input and output timings are measured at the pin. See Figure 8.
2. All maximum timing specifications assume CL = 50 pF.
3. This minimum parameter assumes CL = 0 pF.
4. SYSCLK to output valid (5.5V to 0.8V) includes the extra delay associated with discharging the external voltage from 5.5V to
0.8V instead of from Vdd to 0.8V (5V CMOS levels instead of 3.3V CMOS levels).
19
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5. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.
6. Output signal transitions from GND to 2.0V or Vdd to 0.8V.
7. Nominal precharge width for ABB and DBB is 0.5 * tsysclk.
8. Nominal precharge width for ARTRY is 1.0 * tsysclk.
Figure 8. Output Timing Diagram
JTAG AC Timing
Specifications
Table 13. JTAG AC Timing Specifications (independent of SYSCLK)
Vdd = AVdd = 2.5V ± 5%; OVdd = 3.3 ± 5%V dc, GND = 0V dc, CL = 50 pF, -55°C ≤ TC ≤ 125°C
Num
Characteristic
TCK frequency of operation
20
Min
Max
Unit
0
16
MHz
62.5
—
ns
Notes
1
TCK cycle time
2
TCK clock pulse width measured at 1.4V
25
—
ns
3
TCK rise and fall times
0
3
ns
4
TRST setup time to TCK rising edge
13
—
ns
5
TRST assert time
40
—
ns
6
Boundary scan input data setup time
6
—
ns
2
7
Boundary scan input data hold time
27
—
ns
2
8
TCK to output data valid
4
25
ns
3
9
TCK to output high impedance
3
24
ns
3
1
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TSPC603R
Table 13. JTAG AC Timing Specifications (independent of SYSCLK)
Vdd = AVdd = 2.5V ± 5%; OVdd = 3.3 ± 5%V dc, GND = 0V dc, CL = 50 pF, -55°C ≤ TC ≤ 125°C
Num
Characteristic
Min
Max
Unit
10
TMS, TDI data setup time
0
—
ns
11
TMS, TDI data hold time
25
—
ns
12
TCK to TDO data valid
4
24
ns
15
ns
13
Notes: 1.
2.
3.
TCK to TDO high impedance
3
TRST is an asynchronous signal. The setup time is for test purposes only.
Non-test signal input timing with respect to TCK.
Non-test signal output timing with respect to TCK.
Notes
Figure 9. Clock Input Timing Diagram
Figure 10. TRST Timing Diagram
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Figure 11. Boundary-scan Timing Diagram
Figure 12. Test Access Port Timing Diagram
Functional
Description
PowerPC Registers
and Programming
Model
The PowerPC architecture defines register-to-register operations for most computational
instructions. Source operands for these instructions are accessed from the registers or are
provided as immediate values embedded in the instruction opcode. The three-register instruction format allows specification of a target register distinct from the two source operands. Load
and store instructions transfer data between registers and memory.
PowerPC processors have two levels of privilege - supervisor mode of operation (typically
used by the operating system) and user mode of operation (used by the application software).
The programming models incorporate 32 GPRs, 32 FPRs, special-purpose registers (SPRs)
and several miscellaneous registers. Each PowerPC microprocessor also has its own unique
set of hardware implementation (HID) registers.
22
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2125A–12/01
TSPC603R
Having access to privilege instructions, registers, and other resources allows the operating
system to control the application environment (providing virtual memory and protecting operating-system and critical machine resources). Instructions that control the state of the processor,
the address translation mechanism, and supervisor registers can be executed only when the
processor is operating in supervisor mode.
The following sections summarize the PowerPC registers that are implemented in the 603r.
• General-Purpose Registers (GPRs)
The PowerPC architecture defines 32 user-level, general-purpose registers (GPRs). These
registers are either 32 bits wide in 32-bit PowerPC microprocessors and 64 bits wide in 64-bit
PowerPC microprocessors. The GPRs serve as the data source or destination for all integer
instructions.
• Floating-Point Registers (FPRs)
The PowerPC architecture also defines 32 user-level, 64-bit floating-point registers (FPRs).
The FPRs serve as the data source or destination for floating-point instructions. These registers can contain data objects of either single- or double-precision floating-point formats.
• Condition Register (CR)
The CR is a 32-bit user-level register that consists of eight four-bit fields that reflect the results
of certain operations, such as move, integer and floating-point compare, arithmetic, and logical
instructions, and provide a mechanism for testing and branching.
• Floating-Point Status and Control Register (FPSCR)
The floating-point status and control register (FPSCR) is a user-level register that contains all
exception signal bits, exception summary bits, exception enable bits, and rounding control bits
needed for compliance with the IEEE 754 standard.
• Machine State Register (MSR)
The machine state register (MSR) is a supervisor-level register that defines the state of the
processor. The contents of this register are saved when an exception is taken and restored
when the exception handling completes. The 603r implements the MSR as a 32-bit register,
64-bit PowerPC processors implement a 64-bit MSR.
• Segment Registers (SRs)
For memory management, 32-bit PowerPC microprocessors implement sixteen 32-bit segment registers (SRs). To speed access, the 603r implements the segment registers as two
arrays; a main array (for data memory accesses) and a shadow array (for instruction memory
accesses). Loading a segment entry with the Move to Segment Register (stsr) instruction
loads both arrays.
• Special-Purpose Registers (SPRs)
The powerPC operating environment architecture defines numerous special-purpose registers
that serve a variety of functions, such as providing controls, indicating status, configuring the
processor, and performing special operations. During normal execution, a program can
access the registers, shown in Figure 13, depending on the program’s access privilege (supervisor or user, determined by the privilege-level (PR) bit in the MSR). Note that register such as
the GPRs and FPRs are accessed through operands that are part of the instructions. Access
to registers can be explicit (that is, through the use of specific instructions for that purpose
such as Move to Special-Purpose Register (mtspr) and Move from Special-Purpose Register
23
2125A–12/01
(mfspr) instructions) or implicit, as the part of the execution of an instruction. Some registers
are accessed both explicitly and implicitly.
Il the 603r, all SPRs are 32 bits wide.
USER-LEVEL SPRs: The following 603r SPRs are accessible by user-level software:
•
Link register (LR) - The link register can be used to provide the branch target address and
to hold the return address after branch and link instructions. The LR is 32 bits wide in
32-bit implementations.
•
Count register (CTR) - The CRT is decremented and tested automatically as a result of
branch-and-count instructions. The CTR is 32 bits wide in 32-bit implementations.
•
Integer exception register (XER) - The 32-bit XER contains the summary overflow bit,
integer carry bit, overflow bit, and a field specifying the number of bytes to be transferred
by a Load String Word Indexed (lswx) or Store String Word Indexed (stswx) instruction.
SUPERVISOR-LEVEL SPRs: The 603r also contains SPRs that can be accessed only by
supervisor-level software. These registers consist of the following:
24
•
The 32-bit DSISR defines the cause of data access and alignment exceptions.
•
The data address register (DAR) is a 32-bit register that holds the address of an access
after an alignment or DSI exception.
•
Decrementer register (DEC) is a 32-bit decrementing counter that provides a mechanism
for causing a decrementer exception after a programmable delay.
•
The 32-bit SDR1 specifies the page table format used in virtual-to-physical address
translation for pages. (Note that physical address is referred to as real address in the
architecture specification).
•
The machine status save/restore register 0 (SRR0) is a 32-bit register that is used by the
603r for saving the address of the instruction that caused the exception, and the address
to return to when a Return from Interrupt (rfi) instruction is executed.
•
The machine status save/restore register 1 (SRR1) is a 32-bit register used to save
machine status on exceptions and to restore machine status when an rfi instruction is
executed.
•
The 32-bit SPRG0-SPRG3 registers are provided for operating system use.
•
The external access register (EAR) is a 32-bit register that controls access to the external
control facility through the External Control In Word Indexed (eciwx) and External Control
Out Word Indexed (ecowx) instructions.
•
The time base register (TB) is a 64-bit register that maintains the time of day and operates
interval timers. The TB consists of two 32-bit fields - time base upper (TBU) and time base
lower (TBL).
•
The processor version register (PVR) is a 32-bit, read-only register that identifies the
version (model) and revision level of the PowerPC processor.
•
Block address translation (BAT) arrays - The PowerPC architecture defines 16 BAT
registers, divided into four pairs of data BATs (DBATs) and four pairs of instruction BATs
(IBATs). See Figure 13 for a list of the SPR numbers for the BAT arrays.
•
The following supervisor-level SPRs are implementation-specific to the 603r:
•
The DMISS and IMISS registers are read-only registers that are loaded automatically
upon an instruction or data TLB miss.
•
The HASH1 and HASH2 registers contain the physical addresses of the primary and
secondary page table entry groups (PTEGs).
•
The ICMP and DCMP registers contain a duplicate of the first word in the page table entry
(PTE) for which the table search is looking.
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•
The required physical address (RPA) register is loaded by the processor with the second
word of the correct PTE during a page table search.
•
The hardware implementation (HID0 and HID1) registers provide the means for enabling
the 603r’s checkstops and features, and allows software to read the configuration of the
PLL configuration signals.
•
The instruction address breakpoint register (IABR) is loaded with an instruction address
that is compared to instruction addresses in the dispatch queue. When an address match
occurs, an instruction address breakpoint exception is generated.
Figure 13 shows all the 603r registers available at the user and supervisor level. The number
to the right of the SPRs indicate the number that is used in the syntax of the instruction operands to access the register.
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Figure 13. PowerPC Microprocessor Programming Model - Register
26
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Instruction Set and
Addressing Modes
The following subsections describe the PowerPC instruction set and addressing modes in
general.
• PowerPC Instruction Set and Addressing Modes
All PowerPC instructions are encoded as single-word (32-bit) opcodes. Instruction formats are
consistent among all instruction types, permitting efficient decoding to occur in parallel with
operand accesses. This fixed instruction length and consistent format greatly simplifies
instruction pipelining.
PowerPC INSTRUCTION SET: The PowerPC instructions are divided into the following
categories:
•
Integer instructions - These include computational and logical instructions.
- Integer arithmetic instructions.
- Integer compare instructions.
- Integer logical instructions.
- Integer rotate and shift instructions.
•
Floating-point instructions -These include floating-point computational instructions, as
well as instructions that affect the FPSCR.
- Floating-point arithmetic instructions.
- Floating-point multiply/add instructions.
- Floating-point rounding and conversion instructions.
- Floating-point compare instructions.
- Floating-point status and control instructions.
•
Load/store instructions - These include integer and floating-point load and store
instructions.
- Integer load and store instruction.
- Integer load and store multiple instructions.
- Floating-point load and store.
- Primitives used to construct atomic memory operations (lwarx and stwcx. instructions).
•
Flow control instructions - These include branching instructions, condition register
logical instructions, trap instructions, and other instructions that affect the instruction flow.
- Branch and trap instructions.
- Condition register logical instructions.
•
Processor control instructions - These instructions are used for synchronizing memory
accesses and management of caches, TLBs, and the segment registers.
- Move to/from SPR instructions.
- Move to/from MSR.
- Synchronize.
- Instruction synchronize.
•
Memory control instruction - These instructions provide control of caches, TLBs, and
segment registers.
- Supervisor-level cache management instructions.
- User-level cache instructions.
- Segment register manipulation instructions.
- Translation look aside buffer management instructions.
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Note that this grouping of the instructions does not indicate which execution unit executes a
particular instruction or group of instructions.
Integer instructions operate on byte, half-word, and word operands. Floating-point instructions
operate on single-precision (one word) and double-precision (one double word) floating-point
operands. The PowerPC architecture uses instructions that are four bytes long and
word-aligned. It provides for byte, half-word, and word operand loads and stores between
memory and a set of 32 GPRs. It also provides for word and double-word operand loads and
stores between memory and a set of 32 floating-point registers (FPRs).
Computational instructions do not modify memory. To use a memory operand in a computation and then modify the same or another memory location, the memory contents must be
loaded into a register, modified, and then written back to the target location with distinct
instructions.
PowerPC processors follow the program flow when they are in the normal execution state.
However, the flow of instructions can be interrupted directly by the execution of an instruction
or by an asynchronous event. Either kind of exception may cause one of several components
of the system software to be invoked.
CALCULATING EFFECTIVE ADDRESSES: The effective address (EA) is the 32-bit address
computed by the processor when executing a memory access or branch instruction or when
fetching the next sequential instruction.
The PowerPC architecture supports two simple memory addressing modes:
•
EA = (RA|0) + offset (including offset = 0) (register indirect with immediate index).
•
EA = (RA|0) + rB (register indirect with index).
These simple addressing modes allow efficient address generation for memory accesses. Calculation of the effective address for aligned transfers occurs in a single clock cycle.
For a memory access instruction, if the sum of the effective address and the operand length
exceeds the maximum effective address, the memory operand is considered to wrap around
from the maximum effective address to effective address 0.
Effective address computations for both data and instruction accesses use 32-bit unsigned
binary arithmetic. A carry from bit 0 is ignored in 32-bit implementations.
• PowerPC 603r Microprocessor Instruction Set
The 603r instruction set is defined as follows:
28
•
The 603r provides hardware support for all 32-bit PowerPC instructions.
•
The 603r provides two implementation-specific instructions used for software table search
operations following TLB misses:
- Load Data TLB Entry (tlbld).
- Load Instruction TLB Entry (tlbli).
•
The 603r implements the following instructions which are defined as optional by the
PowerPC architecture :
- External Control In Word Indexed (eciwx).
- External Control Out Word Indexed (ecowx).
- Floating Select (fsed).
- Floating Reciprocal Estimate Single-Precision (fres).
- Floating Reciprocal Square Root Estimate (frsqrte).
- Store Floating-Point as Integer Word (stfiwx).
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Cache Implementation
The following subsections describe the PowerPC architecture’s treatment of cache in general,
and the 603r specific implementation, respectively.
• PowerPC Cache Characteristics
The PowerPC architecture does not define hardware aspects of cache implementations. For
example, some PowerPC processors, including the 603r, have separate instruction and data
caches (hardware architecture), while others, such as the PowerPC 601 microprocessor,
implement a unified cache.
PowerPC microprocessor control the following memory access modes on a page or block
basis:
•
Write-back/write-through mode.
•
Cache-inhibited mode.
•
Memory coherency.
Note that in the 603r, a cache line is defined as eight words. The VEA defines cache management instructions that provide a means by which the application programmer can affect the
cache contents.
• PowerPC 603r Microprocessor Cache Implementation
The 603r has two 16-Kbyte, four-way set-associative (instruction and data) caches. The
caches are physically addressed, and the data cache can operate in either write-back or
write-through mode as specified by the PowerPC architecture.
The data cache is configured as 128 sets of 4 lines each. Each line consists of 32 bytes, two
state bits, and an address tag. The two state bits implement the three-state MEI (modified/exclusive/invalid) protocol. Each line contains eight 32-bit words. Note that the PowerPC
architecture defines the term block as the cacheable unit. For the 603r, the block size is equivalent to a cache line. A block diagram of the data cache organization is shown in Figure 14.
The instruction cache also consists of 128 sets of 4 lines, and each line consists of 32 bytes,
an address tag, and a valid bit. The instruction cache may not be written to except through a
line fill operation. The instruction cache is not snooped, and cache coherency must be maintained by software. A fast hardware invalidation capability is provided to support cache
maintenance. The organization of the instruction cache is very similar to the data cache shown
in Figure 14.
Each cache line contains eight contiguous words from memory that are loaded from an 8-word
boundary (that is, bits A27-A32 of the effective addresses are zero); thus, a cache line never
crosses a page boundary. Misaligned accesses across a page boundary can incur a performance penalty.
The 603’s cache lines are loaded in four beats of 64 bits each. The burst load is performed as
“critical double word first”. The cache that is being loaded is blocked to internal accesses until
the load completes. The critical double word is simultaneously written to the cache and forwarded to the requesting unit, thus minimizing stalls due to load delays.
To ensure coherency among caches in a multiprocessor (or multiple caching-device) implementation, the 603r implemements the MEI protocol. These three states, modified, exclusive,
and invalid, indicate the state of the cache block as follows:
•
Modified - The cache line is modified with respect to system memory; that is, data for this
address is valid only in the cache and not in system memory.
•
Exclusive - This cache line holds valid data that is identical to the data at this address in
system memory. No other cache has this data.
•
Invalid - This cache line does not hold valid data.
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Cache coherency is enforced by on-chip bus snooping logic. Since the 603r’s data cache tags
are single ported, a simultaneous load or store and snoop access represent a resource contention. The snoop access is given first access to the tags. The load or store then occurs on
the clock following snoop.
Figure 14. Data Cache Organization
Exception Model
The following subsections describe the PowerPC exception model and the 603r implementation, respectively.
• PowerPC Exception Model
The PowerPC exception mechanism allows the processor to change to supervisor state as a
result of external singles, errors, or unusual conditions arising in the execution of instructions,
and differ from the arithmetic exceptions defined by the IEEE for floating-point operations.
When exceptions occur, information about the state of the processor is saved to certain registers and the processor begins execution at an address (exception vector) predetermined for
each exception. Processing of exceptions occurs in supervisor mode.
Although multiple exception conditions can map to a single exception vector, a more specific
condition may be determined by examining a register associated with the exception - for
example, the DSISR and the FPSCR. Additionally, some exception conditions can be explicitly
enable or disabled by software.
The PowerPC architecture requires that exceptions be handled in program order; therefore,
although a particular implementation may recognize exception conditions out of order, they
are presented strictly in order. When an instruction-caused exception is recognized, any unexecuted instructions that appear earlier in the instruction stream, including any that have not yet
entered the execute state, are required to complete before the exception is taken. Any exceptions caused by those instructions are handled first. Likewise, exceptions that are
asynchronous and precise are recognized when they occur, but are not handled until the
instruction currently in the completion state successfully completes execution or generates an
exception, and the completed store queue is emptied.
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Unless a catastrophic causes a system reset or machine check exception, only one exception
is handled at a time. If, for example, a single instruction encounters multiple exception conditions, those conditions are encountered sequentially. After the exception handler handles an
exception, the instruction execution continues until the next exception condition is encountered. However, in many cases there is no attempt to re-execute the instruction. This method
of recognizing and handling exception conditions sequentially guarantees that exceptions are
recoverable.
Exception handlers should save the information stored in SRR0 and SRR1 early to prevent the
program state from being lost due to a system reset and machine check exception or to an
instruction-caused exception in the exception handler, and before enabling external interrupts.
The PowerPC architecture support four types of exceptions:
•
Synchronous, precise - These are causes by instructions. All instruction-caused
exceptions are handled precisely; that is, the machine state at the time the exception
occurs is known and can be completely restored. This means that (excluding the trap and
system call exceptions) the address of the faulting instruction is provided to the exception
handler and that neither the faulting instruction nor subsequent instructions in the code
stream will complete execution before the exception is taken. Once the exception is
processed, execution resumes at the address of the faulting instruction (or at an alternate
address provided by the exception handler). When an exception is taken due to an trap or
system call instruction, execution resumes at an address provided by the handler.
•
Synchronous, imprecise - The PowerPC architecture defines two imprecise
floating-point exception modes, recoverable and nonrecoverable. Even though the 603r
provides a means to enable he imprecise modes, it implements these modes identically to
the precise mode (-hat is, all enabled floating-point enabled exceptions are always precise
on the 603r).
•
Asynchronous, maskable - The external, SMI, and decrementer interrupts are maskable
asynchronous exceptions. When these exceptions occur, their handling is postponed until
the next instruction, and any exceptions associated with that instruction, completes
execution. If there are no instructions in the execution units, the exception is taken
immediately upon determination of the correct restart address (for loading SRR0).
•
Asynchronous, non maskable - There are two non maskable asynchronous exceptions:
system reset and the machine check exception. These exceptions may not be
recoverable, or may provide a limited degree of recoverability. All exceptions report
recoverability through the SMR[RI] bit.
• PowerPC 603r Microprocessor Exception Model
A specified by the PowerPC architecture, all 603r exceptions can be described as either precise or imprecise and either synchronous or asynchronous. Asynchronous exceptions (some
or which are maskable) are caused by events external to the processor’s execution; synchronous exceptions, which are all handled precisely by the 603r, are caused by instructions. The
603r exception classes are shown in Table 14.
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Table 14. PowerPC 603r Microprocessor Exception Classifications
Synchronous/Asynchronous
Precise/Imprecise
Exception Type
Asynchronous, Non Maskable
Imprecise
Machine check
System reset
Asynchronous, Maskable
Precise
External interrupt
Decrementer
System management interrupt
Synchronous
Precise
Instruction-caused exceptions
Although exceptions have other characteristics as well, such as whether they are maskable or
non maskable, the distinctions shown in Table 14 define categories of exceptions that the 603r
handles uniquely. Note that Table 14 includes no synchronous imprecise instructions. While
the PowerPC architecture supports imprecise handling of floating-point exceptions, the 603r
implements these exception modes as precise exceptions.
The 603r’s exceptions, and conditions that cause them, are listed in Table 15. Exceptions that
are specific to the 603r are indicated.
Table 15. Exceptions and Conditions
Exception Type
Vector Offset
(hex)
Causing Conditions
Reserved
00000
—
System Reset
00100
A system reset is caused by the assertion of either SRESET or HRESET.
Machine Check
00200
A machine check is caused by the assertion of the TEA signal during a data bus
transaction, assertion of MCP, or an address or data parity error.
DSI
00300
The cause of a DSI exception can be determined by the bit settings in the DSISR, listed as
follows:
1 Set if the translation of an attempted access is not found in the primary hash table entry
group (HTEG), or in the rehashed secondary HTEG, or in the range of the DBAT register;
otherwise cleared.
4 Set if a memory access is not permitted by the page or DBAT protection mechanism;
otherwise cleared.
5 Set by an eciwx or ecowx instruction if the access is to an address that is marked as
write-through, or execution of a load/store instruction that accesses a direct-store segment.
6 Set for a store operation and cleared for a load operation.
11 Set if eciwx or ecowx is used and EAR[E] is cleared.
ISI
00400
An ISI exception is caused when an instruction fetch cannot be performed for any of the
following reasons:
• The effective (logical) address cannot be translated. That is, there is a page fault for this
portion of the translation, so an ISI exception must be taken to load the PTE (and possibly
the page) into memory.
• The fetch access violates memory protection. If the key bits (Ks and Kp) in the segment
register and the PP bits in the PTE are set to prohibit read access, instructions cannot be
fetched from this location.
External interrupt
00500
An external interrupt is caused when MSR[EE] = 1 and the INT signal is asserted.
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Table 15. Exceptions and Conditions (Continued)
Exception Type
Vector Offset
(hex)
Alignment
00600
An alignment exception is caused when the 603e cannot perform a memory access for any
of the reasons described below:
• The operand of a floating-point load or store instruction is not word-aligned.
• The operand of lmw, stmw, lwarx, and stwcx, instructions are not aligned.
• The operand of a single-register load or store operation is not aligned, and the 603e is in
little-endian mode.
• The instruction is lmw, stmw, lswi, lwsx, stswi, stswx and the 603e is in little-endian mode.
• The operand of dcbz is in storage that is write-through-required, or caching inhibited.
Program
00700
A program exception is caused by one of the following exception conditions, which
correspond to bit settings in SRR1 and arise during execution of an instruction:
• Floating-point enabled exception—A floating-point enabled exception condition is
generated when the following condition is met: (MSR[FE0] | MSR[FE1]) & FPSCR[FEX] is
1. FPSCR[FEX] is set by the execution of a floating-point instruction that causes an
enabled exception or by the execution of one of the “move to FPSCR” instructions that
results in both an exception condition bit and its corresponding enable bit being set in the
FPSCR.
• Illegal instruction—An illegal instruction program exception is generated when execution
of an instruction is attempted with an illegal opcode or illegal combination of opcode and
extended opcode fields (including PowerPC instructions not implemented in the 603e), or
when execution of an optional instruction not provided in the 603e is attempted (these do
not include those optional instructions that are treated as no-ops).
• Privileged instruction—A privileged instruction type program exception is generated when
the execution of a privileged instruction is attempted and the MSR register user privilege
bit, MSR[PR], is set. In the 603e, this exception is generated for mtspr or mfspr with an
invalid SPR field if SPR[0] = 1 and MSR[PR] = 1. This may not be true for all PowerPC
processors.
• Trap—A trap type program exception is generated when any of the conditions specified in
a trap instruction is met.
Floating-point
unavailable
00800
A floating-point unavailable exception is caused by an attempt to execute a floating-point
instruction (including floating-point load, store, and more instructions) when the floatingpoint available bit is disabled, (MSR[FP] = 0).
Decrementer
00900
The decrementer exception occurs when the most significant bit of the decrementer (DEC)
register transitions from 0 to 1. Must also be enabled with the MSR[EE] bit.
Reserved
00A00–00BFF
—
System call
00C00
A system call exception occurs when a System Call (sc) instruction is executed.
Trace
00D00
A trace execution is taken when MSR[SE] = 1 or when the currently completing instruction
is a branch and MSR[BE] = 1.
Reserved
00E00
The 603e does not generate an exception to this vector. Other PowerPC processors may
use this vector for floating-point assist exceptions.
Reserved
00E10–00FFF
—
Instruction
translation miss
01000
An instruction translation miss exception is caused when an effective address for an
instruction fetch cannot be translated by the ITLB.
Data load
translation miss
01100
A data load translation miss exception is caused when an effective address for a data load
operation cannot be translated by the DTLB.
Data store
translation miss
01200
A data store translation miss exception is caused when an effective address for a data
store operation cannot be translated by the DTLB; or where a DTLB hit occurs, and the
change
Causing Conditions
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Table 15. Exceptions and Conditions (Continued)
Exception Type
Vector Offset
(hex)
Causing Conditions
Instruction address
breakpoint
01300
An instruction address breakpoint exception occurs when the address (bits 0-29) in the
IABR matches the next instruction to complete in the completion unit, and the IABR enable
bit (bit 30) is set to 1.
System
management
interrupt
01400
A system management interrupt is caused when MSR[EE] = 1 and the SMI input signal is
asserted.
Reserved
01500–02FFF
—
Memory Management
The following subsections describe the memory management features of the PowerPC architecture, and the 603r implementation, respectively.
• PowerPC Memory Management
The primary functions of the MMU are to translate logical (effective) addresses to physical
addresses for memory accesses, and to provide access protection on blocks and pages of
memory.
There are two types of accesses generated by the 603r that require address translation—
instruction accesses, and data accesses to memory generated by load and store instructions.
The PowerPC MMU and exception model support demand-paged virtual memory. Virtual
memory management permits execution of programs larger than the size of physical memory;
demand-paged implies that individual pages are loaded into physical memory from system
memory only when they are first accessed by an executing program.
The hashed page table is a variable-sized data structure that defines the mapping between
virtual page numbers and physical page numbers. The page table size is a power of 2, and its
starting address is a multiple of its size.
The page table contains a number of page table entry groups (PTEGs). A PTEG contains
eight page table entries (PTEs) of eight bytes each; therefore, each PTEG is 64 bytes long.
PTEG addresses are entry points for table search operations.
Address translations are enabled by setting bits in the MSR-MSR[IR] enables instruction
address translations and MSR[DR] enables data address translations.
• PowerPC 603r Microprocessor Memory Management
The instruction and data memory management units in the 603r provide 4G byte of logical
address space accessible to supervisor and user programs with a 4K byte page size and
256M byte segment size. Block sizes range from 128K byte to 256M byte and are software
selectable. In addition, the 603r uses an interim 52-bit virtual address and hashed page tables
for generating 32-bit physical addresses. The MMUs in the 603r rely on the exception processing mechanism for the implementation of the paged virtual memory environment and for
enforcing protection of designated memory areas.
Instruction and data TLBs provide address translation in parallel with the on-chip cache
access, incurring no additional time penalty in the event of a TLB hit. A TLB is a cache of the
most recently used page table entries. Software is responsible for maintaining the consistency
of the TLB with memory. The 603r’s TLBs are 64-entry, two-way set-associative caches that
contain instruction and data address translations. The 603r provides hardware assist for software table search operations through the ashed page table on TLB misses. Supervisor
software can invalidate TLB entries selectively.
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The 603r also provides independent four-entry BAT arrays for instructions and data that maintain address translations for blocks of memory. These entries define blocks that can vary from
128K byte to 256M byte. The BAT arrays are maintained by system software.
As specified by the PowerPC architecture, the hashed page table is a variable-sized data
structure that defines the mapping between virtual page numbers and physical page numbers.
The page table size is a power of 2, and its starting address is a multiple of its size.
Also as specified by the PowerPC architecture, the page table contains a number of page
table entry groups (PTEGs). A PTEG contains eight page table entries (PTEs) of eight bytes
each; therefore, each PTEG is 64 bytes long. PTEG addresses are entry points for table
search operations.
Instruction Timing
The 603r is a pipelined superscalar processor. A pipelined processor is one in which the processing of an instruction is reduced into discrete stages. Because the processing of an
instruction is broken into a series of stages, an instruction does not require the entire
resources of an execution unit. For example, after an instruction completes the decode stage,
it can pass on to the next stage, while the subsequent instruction can advance into the decode
stage. This improves the throughput of the instruction flow. For example, it may take three
cycles for a floating-point instruction to complete, but if there are no stalls in the floating-point
pipeline, a series of floating-point instructions can have a throughput of one instruction per
cycle.
The instruction pipeline in the 603r has four major pipeline stages, described a follows:
•
The fetch pipeline stage primarily involves retrieving instructions from the memory system
and determining the location of the next instruction fetch. Additionally, the BPU decodes
branches during the fetch stage and folds out branch instructions before the dispatch
stage if possible.
•
The dispatch pipeline stage is responsible for decoding the instructions supplied by the
instruction fetch stage, and determining which of the instructions are eligible to be
dispatched in the current cycle. in addition, the source operands of the instructions are
read from the appropriate register file and dispatched with the instruction to the execute
pipeline stage. At the end of the dispatch pipeline stage, the dispatched instructions and
their operands are latched by the appropriate execution unit.
•
During the execute pipeline stage each execution unit that has an executable instruction
executes the selected instruction (perhaps over multiple cycles), writes the instruction’s
result into the appropriate rename register, and notifies the completion stage that the
instruction has finished execution. In the case of an internal exception, the execution unit
reports the exception to the completion/writeback pipeline stage and discontinues
instruction execution until the exception is handled. The exception is not signaled until that
instruction is the next to be completed. Execution of most floating-point instructions is
pipelined within the FPU allowing up to three instructions to be executing in the FPU
concurrently. The pipeline stages for the floating-point unit are multiply, add, and
round-convert. Execution of most load/store instructions is also pipelined. The load/store
units has two pipeline stages. The first stage is for effective address calculation and MMU
translation and the second stage is for accessing the data in the cache.
•
The complete/writeback pipeline stage maintains the correct architectural machine state
and transfers the contents of the rename registers to the GPRs and FPRs as instructions
are retired. If the completion logic detects an instruction causing an exception, all following
instructions are cancelled, their execution results in rename registers are discarded, and
instructions are fetched from the correct instruction stream.
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A superscalar processor is one that issues multiple independent instructions into multiple pipelines allowing instructions to execute in parallel. The 603r has five independent execution
units, one each for integer instructions, floating-point instructions, branch instructions,
load/store instructions, and system register instructions. The IU and the FPU each have dedicated register files for maintaining operands (GPRs and FPRs, respectively), allowing integer
calculations and floating-point calculations to occur simultaneously without interference.
Because the PowerPC architecture can be applied to such a wide variety of implementations,
instruction timing among various PowerPC processors varies accordingly.
Preparation for
Delivery
Packaging
Microcircuits are prepared for delivery in accordance with MIL-PRF-38535.
Certificate of
Compliance
ATMEL-Grenoble offers a certificate of compliances with each shipment of parts, affirming the
products are in compliance either with MIL-STD-883 and guarantying the parameters not
tested at temperature extremes for the entire temperature range.
Handling
MOS devices must be handled with certain precautions to avoid damage due to accumulation
of static charge. Input protection devices have been designed in the chip to minimize the effect
of this static buildup. However, the following handling practices are recommended:
1. Devices should be handled on benches with conductive and grounded surfaces.
2. Ground test equipment, tools and operator.
3. Do not handle devices by the leads.
4. Store devices in conductive foam or carriers.
5. Avoid use of plastic, rubber, or silk in MOS areas.
6. Maintain relative humidity above 50 percent if practical.
Packages
Mechanical Data
The following sections provide the package parameters and mechanical dimensions for the
CBGA packages.
CBGA Package
Parameters
The package parameters are as provided in the following list. The package type is 21 mm,
255-lead ceramic ball grid array (CBGA).
36
Package outline
21 mm x 21 mm
Interconnects
255
Pitch
1.27 mm
Maximum module height
3.00 mm
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Mechanical
dimensions of the
CBGA package
Figure 15 provides the mechanical dimensions and bottom surface nomenclature of the CBGA
package.
Figure 15. Mechanical Dimensions and Bottom Surface Nomenclature of the CBGA Package
Notes: 1. Dimensioning and tolerancing per
ASME Y14.5M—1994.
2. Controlling dimension: millimeter
Dim
A
B
C
D
G
H
K
N
P
CI-CGA Package
Parameters
Millimeters
Min
Max
21.000 BSC
21.000 BSC
2.450
3.000
0.820
0.930
1.270 BSC
0.790
0.990
0.635 BSC
5.000
16.000
5.000
16.000
Inches
Min
Max
0.827 BSC
0.827 BSC
0.097
0.118
0.032
0.036
0.050 BSC
0.031
0.039
0.025 BSC
0.197
0.630
0.197
0.630
The package parameters are as provided in the following list. The package type is 21 mm,
255-lead ceramic ball grid array (CI-CGA).
Package outline
21 mm x 21 mm
Interconnects
255
Pitch
1.27 mm
Typical module height
3.84 mm
37
2125A–12/01
Mechanical
Dimensions of the CICGA Package
Figure 16 provides the mechanical dimensions and bottom surface nomenclature of the CBGA
package.
Figure 16. Mechanical Dimensions and Bottom Surface Nomenclature of the CI-CGA Package
Notes: 1. Dimensioning and tolerancing per
ASME Y14.5M—1994.
2. Controlling dimension: millimeter.
Dim
A
B
C
D
G
H
K
N
P
R
U
V
Millimeters
Min
Max
21.000 BSC
21.000 BSC
3.84 BSC
0.790 0.990
1.270 BSC
1.545 1.695
0.635 BSC
5.000 16.000
5.000
16.000
3.02 BSC
0.10 BSC
0.25 0.35
H
U
V
R
C
38
TSPC603R
2125A–12/01
TSPC603R
Clock
Relationships
Choice
The 603r microprocessors offer customers numerous clocking options. An internal phase-lock
loop synchronizes the processor (CPU) clock to the bus or system clock (SYSCLK) at various
ratios.
Inside each PowerPC microprocessor is a phase-lock loop circuit. A voltage controlled oscillator (VCO) is precisely controlled in frequency and phase by a frequency/phase detector which
compares the input bus frequency (SYSCLK frequency) to a submultiple of the VCO.
The ratio of CPU to SYSCLK frequencies is often referred to as the bus mode (for example,
2:1 bus mode).
In the Table 16, the horizontal scale represents the bus frequency (SYSCLK) and the vertical
scale represents the PLL-CFG[0-3] signals.
For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and
VCO frequency of operation.
Table 16. CPU Frequencies for Common Bus Frequencies and Multipliers
CPU Frequency in MHZ (VCO Frequency in MHz)
PLL_CFG[0-3]
Bus-toCore
Multiplier
Core-to
VCO
Multiplier
Bus
25 MHz
Bus
33.33 MHz
Bus
40 MHz
Bus
50 MHz
Bus
60 MHz
Bus
66.67 MHz
Bus
75 MHz
0100
2x
2x
-
-
-
-
-
-
150
(300)
0101
2x
4x
-
-
-
-
-
-
-
0110
2.5x
2x
-
-
-
-
150
(300)
166
(333)
187
(375)
1000
3x
2x
-
-
-
150
(300)
180
(360)
200
(400)
225
(450)
1110
3.5x
2x
-
-
-
175
(350)
210
(420)
233
(466)
263
(525)
1010
4x
2x
-
-
160
(320)
200
(400)
240
(480)
267
(533)
300
(600)
0111
4.5x
2x
-
150
(300)
180
(360)
225
(450)
270
(540)
300
(600)
-
1011
5x
2x
-
166
(333)
200
(400)
250
(500)
300
(600)
-
-
1001
5.5x
2x
-
183
(366)
220
(440)
275
(550)
-
-
-
1101
6x
2x
150
(300)
200
(400)
240
(480)
300
(600)
-
-
-
Notes:
0011
PLL bypass
1111
Clock off
1. Some PLL configurations may select bus, CPU or VCO frequencies which are not supported
2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode
is set for 1:1 mode operation. This mode is intended for factory use only.
Note: the AC timing specifications given in this document do not apply in PLL-bypass mode.
3. In clock-off mode, no clocking occurs inside the 603e regardless of the SYSCLK input.
39
2125A–12/01
System Design
Information
PLL Power Supply
Filtering
The A Vdd power signal is provided on the 603e to provide power to the clock generation
phase-locked loop. To ensure stability of the internal clock, the power supplied to the AVdd
input signal should be filtered using a circuit similar to the one shown in Figure 17. The circuit
should be placed as close to the AVdd pin to ensure it filters out as much noise as possible.
The 0.1 µF capacitor should be closest to the AVdd pin, followed by the 10 µF capacitor, and
finally the 10Ω resistor to Vdd. These traces should be kept short and direct.
Figure 17. PLL Power Supply Filter Circuit
Vdd
10 Ω
AVdd
10 µF
0.1 µF
GND
Decoupling
Recommendations
Due to the 603e’s dynamic power management feature, large address and data buses, and
high operating frequencies, the 603e can generate transient power surges and high frequency
noise in its power supply, especially while driving large capacitive loads. This noise must be
prevented from reaching other components in the 603e system, and the 603e itself requires a
clean, tightly regulated source of power. Therefore, it is recommended that the system
designer place at least one decoupling capacitor at each Vdd and OVdd pin of the 603e. It is
also recommended that these decoupling capacitors receive their power from separate Vdd,
OVdd, and GND power planes in the PCB, utilizing short traces to minimize inductance.
These capacitors should vary in value from 220 pF to 10 µF to provide both high-and low-frequency filtering, and should be placed as close as possible to their associated Vdd or OVdd pin.
Suggested values for the Vdd pins 220 pF (ceramic), 0,01 µF (ceramic) and 0,1 µf (ceramic).
Suggested values for the OVdd pins 0,01 µF (ceramic), 0,1 µF (ceramic), and 10 µF (tantalum).
Only SMT (surface mount technology) capacitors should be used to minimize lead inductance.
In addition, it is recommended that there be several bulk storage capacitors distributed around
the PCB, feeding the Vdd and OVdd planes, to enable quick recharging of the smaller chip
capacitors. These bulk capacitors should also have a low ESR (equivalent series resistance)
rating to ensure the quick response time necessary. They should also be connected to the
power and ground planes through two vias to minimize inductance. Suggested bulk capacitors
100 µF (AVX TPS tantalum) or 330 µf (AVX TPS tantalum).
Connection
Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to Vdd. Unused active high inputs
should be connected to GND. ALL NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external Vdd, OVdd, and GND pins of the
603e.
Pull-up Resistor
Requirements
40
The 603e requires high-resistive (weak: 10 KΩ) pull-up resistors on several control signals of
the bus interface to maintain the control signals in the negated state after they have been
actively negated and released by the 603e or other bus master. These signals are: TS, ABB,
DBB, and ARTRY.
TSPC603R
2125A–12/01
TSPC603R
In addition, the 603e has three open-drain style outputs that require pull-up resistors (weak or
stronger: 4.7 KΩ - 10 KΩ) if they are used by the system. These signals are: APE, DPE, and
CKSTP_OUT.
During inactive periods on the bus, the address and transfer attributes on the bus are not
driven by any master and may float in the high-impedance state for relatively long periods of
time. Since the 603e must continually monitor these signals for snooping, this float condition
may cause excessive power draw by the input revivers on the 603e. It is recommended that
these signals be pulled up trough weak (10 KΩ) pull-up resistors or restored in some manner
by the system. The snooped address and transfer attribute inputs are: A[0-3], AP[0-3], TT[0-4],
TBST, and GBL.
The data bus input receivers are normally turned off when no read operation is in progress and
do not require pull-up resistors on the data bus.
Ordering
Information
TS (X) PC603R M G B /Q
12 L
(C)
Revision level
Prefix
Bus divider
(to be confirmed)
Prototype
Type
L
:
Any bus @ 75 MHz
Temperature range : TC
M : -55, +125°C
V : -40, +1 10°C
Max internal processor speed
6
8
10
12
14
Package :
G :
GS :
CBGA
CI-CGA
:
:
:
:
:
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
Screening level :
__ :
B/Q:
B/T :
U :
U/T :
Note:
Standard
MIL-STD-883, class Q
according to MIL-STD-883
Upscreening
Upscreening + burn-in
For availability of the different versions, contact your ATMEL-Grenoble sales office.
41
2125A–12/01
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© Atmel Corporation 2001.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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®
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are registered trademarks and trademarks of Atmel Corporation.
Terms and product names in this document may be trademarks of others.
2125A–12/01/xM