Low Power CMOS SRAM 64K X 16 UC62LV1024 -55/-70 Description Features: • Vcc operation voltage : 1.5 V~ 3.6V • Low power consumption : 15mA (Max.) operating current 1uA (Typ.) CMOS standby current • High Speed Access time : 70ns (Max.) at Vcc = 1.5V • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Data retention supply voltage as low as 1.2V • Easy expansion with CE\ and OE\ options The UC62LV1024 is a high performance, low power CMOS Static Random Access Memory organized as 65,536 words by 16 and operates from 1.5 V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 1uA and maximum access time of 70ns in 1.5V operation. Easy memory expansion is provided enable (CE\), and active LOW output enable (OE\) and three-state output drivers. The UC62LV1024 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The US62LV1024 is available in the JEDEC standard 44 pin TSOP (Type II) and 48 pin mini-BGA. PRODUCT FAMILY Product Family UC62LV1024JC UC62LV1024KC UC62LV1024AC UC62LV1024JI UC62LV1024KI Operating Tempature Vcc Range 0℃ ~ 70℃ -40℃ ~ 85℃ Speed (ns) Power Consumption STANDBY Operating Vcc=1.5V(Max.) Vcc=3.3V(Typ.) Vcc=3.6V(Max.) 1.5V ~ 3.6V 55/70 1uA 15mA 1.5V ~ 3.6V 55/70 1uA 15mA Package Type TSOP-44 BGA-48 DICE TSOP-44 BGA-48 UC62LV1024AI DICE PIN CONFIGURATIONS OE A0 A1 A2 NC DQ8 UB A3 A4 CE DQ0 DQ9 DQ10 A5 A6 DQ1 DQ2 GND DQ11 NC A7 DQ3 VCC VCC DQ12 NC NC DQ4 GND DQ14 DQ13 A14 A15 DQ5 DQ6 DQ15 NC A12 A13 WE DQ7 NC A8 A9 A10 A11 NC U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. COL Address MEMORY ARRAY 64K X 16 Bits COLUMN DECODER CE WE OE UB CONTROL BLOCK LB CE WE OE UB LB ROW Address ROW DECODER UC62LV1024JC UC62LV1024JI A5 A6 A7 OE UB LB DQ15 DQ14 DQ13 DQ12 GND VCC DQ11 DQ10 DQ9 DQ8 NC A8 A9 A10 A11 NC CONTROL INPUT BUFFER NC BLOCK DIAGRAM 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 ADDRESS INPUT BUFFER VCC GND DQ4 DQ5 DQ6 DQ7 WE A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A0 - A15 A4 A3 A2 A1 A0 CE DQ0 DQ1 DQ2 DQ3 SENSE AMPLIFIER & WRITE DRIVER X16 I/O BUFFER LB DQ0 ~ DQ15 Preliminary Rev. 1.0 PAGE 1 Low Power CMOS SRAM 64K X 16 UC62LV1024 -55/-70 PIN DESCRIPTION Name Type Function A0 – A15 Input Address inputs for selecting one of the 65,536 x 16 bit words in the RAM CE\ Input CE\ is active LOW. Chip enable must be active when data read from or write to the device. If chip enable is not active, the device is deselected and not in a standby power down mode. The DQ pins will be in high impedance state when the device is deselected. WE\ Input The Write enable input is active LOW and controls read and write operations. With the chip selected, when WE\ is HIGH and OE\ is LOW, output data will be present on the DQ pins, when WE\ is LOW, the data present on the DQ pins will be written into the selected memory location. OE\ Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE\ is inactive. UB\ and LB\ Input DQ0 – DQ15 I/O Vcc Power Power Supply Gnd Power Ground Lower byte and upper byte data input/output control pins. These 16 bi-directional ports are used to read data from or write data into the RAM. TRUTH TABLE Mode WE\ CE\ OE\ LB\ UB\ I/O 0 ~ 7 I/O 8 ~ 15 Vcc Current Not Selected X H X X X High Z High Z ISB,ISB1 H L H X X High Z High Z ICC X L X H H H L L L H DOUT High Z H L L H L High Z DOUT Output Disabled Read Write H L L L L DOUT DOUT L L X L H DIN High Z L L X H L High Z DIN L L X L L DIN DIN ABSOLUTE MAXIMUM RATINGS(1) SYMBOL PARAMETER VTERM Terminal Voltage with Respect to GND TBIAS Temperature Under Bias TSTG Storage Temperature RATING -0.5 to VCC+0.5 ICC ICC OPERATING RANGE RANGE UNIT V Commercial -40 to 125 ℃ Industrial -50 to 150 ℃ PT Power Dissipation 0.5 W IOUT DC Output Current 10 mA 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. AMBIENT TEMPERATURE VCC 0℃ to 70℃ 1.5V ~ 3.6V -40℃ to 85℃ 1.5V ~ 3.6V CAPACITANCE(1)(TA=25℃,f=1.0MHz) SYMBOL PARAMETER CONDITIONS MAX. UNIT Input VIN=0V 6 pF CIN Capacitance Input/Output VDQ 8 pF CDQ Capacitance 1. This parameter is guaranteed and not 100% tested. U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Preliminary Rev. 1.0 PAGE 2 Low Power CMOS SRAM 64K X 16 UC62LV1024 -55/-70 DC ELECTRICAL CHARACTERISTICS (TA=0℃ to 70℃) Symbol MIN. TYP.(1) MAX. UNITS VCC=2.4V -0.5 - 0.8 V VCC=3.6V 2.0 - Vcc-0.2 V Test Condition Comment VIH Guaranteed Input Low (2) Voltage Guaranteed Input High (2) Voltage IL Input Leakage Current VCC=3.6V VIN=0V to VCC - - 1 uA IOL Output Leakage Current VCC=3.6V CE\=VIH or OE\=VIH VIO=0V t VCC - - 1 uA VOL Output Low Voltage VCC=3.6V, IOL=2mA - - 0.4 V VOH Output High Voltage VCC=3.0V, IOH=-1mA 2.4 - - V ICC Operating Power Supply Current CE\=VIL,IDQ=0mA, F=Fmax - - 15 mA ISB1 TTL Standby Current CE\=VIH, VIN=VIH to VIL - - 1 mA ISB2 CMOS Standby Current CE\≧VCC-0.2V, VIN=VCC-0.2V (4) or 0.2V , F=0 - 1 5 uA VIL (3) o 1. Typical characteristics are at TA = 25 C. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC . 4. F=0 means input signals must be keep in static state. DATA RETENTION CHARACTERISTICS ( TA=0℃ to 70℃) Symbol Comment VDR VCC to Data Retention ICCDR Data Retention Current tDR tR Test Condition CE\≧VCC - 0.2V VIN≧VCC-0.2V or VIN≦0.2V CE\≧VCC - 0.2V VIN≧VCC-0.2V or VIN≦0.2V Chip Deselect to Data Retention Time VCC = 1.5V, TA = 25℃. 2. tRC = Read Cycle Time (1) TYP. MAX. UNITS 1.2 - - V - 0.05 0.5 uA 0 - - ns - - ns See Retention Waveform Operation Recovery Time 1. MIN. TRC (2) LOW VCC DATA RETENTION WAVEFORM(1) (CE\ Controlled) Vcc CE tCDR VIH Data Retention Mode VDR >= 1.2V CE >= VCC - 0.2V U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. tR VIH Preliminary Rev. 1.0 PAGE 3 Low Power CMOS SRAM 64K X 16 KEY TO SWITCHING WAVEFORMS AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level UC62LV1024 -55/-70 VCC to 0V 1V/ns 0.5VCC WAVEFORMS INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H DON’T CARE ANY CHANGE PERMITTED CHANGE STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE OFF STATE AC TEST LOADS AND WAVEFORMS 3.3V 3.3V INCLUDING JIG AND SCOPE 1269Ω 1269Ω INCLUDING JIG AND SCOPE 5pF 100pF 1404Ω OUTPUT 1404Ω OUTPUT FIGURE 1A FIGURE 1B TERMINAL EQUIVALENT 667Ω OUTPUT 1.73V ALL INPUT PULSES VCC GND 90% 90% 10% 10% FIGURE 2 1V/ns 1V/ns AC ELECTRICAL CHARACTERISTICS (TA=0℃ to 70℃, VCC=1.5V~3.6V) READ CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION tAVAX tRC Read Cycle Time tAVQV tAA tELQV UC62LV1024-55 UC62LV1024-70 Min Typ Max Min Typ Max 55 - - 70 - - ns Address Access Time - - 55 - - 70 ns tCE Chip Select Access Time - - 55 - - 70 ns tBA tBA Data Byte Control Access Time 35 ns tGLQV tOE Output Enable to Output Valid tELQX tCLZ tGLQX 30 UNIT - - 30 - - 35 ns Chip Select to Output Low Z 10 - - 10 - - ns tOLZ Output Enable to Output Low Z 5 - - 5 - - ns tBE tBE Data Byte Control To Output Low Z 10 tEHQZ tCHZ Chip Deselect to Output in High Z - - 20 - - 20 ns tGHQZ tOHZ Output Disable to Output in High Z - - 20 - - 20 ns tBDO tBDO Data Byte Control To Output High Z - 20 - 20 ns tAXOX tOH Address Chang to Output Change - 10 - ns U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. 10 10 - Preliminary ns - Rev. 1.0 PAGE 4 Low Power CMOS SRAM 64K X 16 UC62LV1024 -55/-70 SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) tRC ADDRESS tOH tAA tOH DOUT READ CYCLE2 (1,3,4) CE tCLZ (5) tCE tCHZ (5) DOUT READ CYCLE3 (1,4) tRC ADDRESS tAA tOH OE tOE tOHZ (1,5) tOLZ CE tCLZ (5) tCE tCHZ (5) UB/LB tBE tBA tBDO DOUT NOTES: 1. 2. 3. 4. 5. WE\ is high in read cycle. Device is continuously selected when CE\ = VIL Address valid prior to or coincident with CE\ transition low. OE\ = VIL. Transition is measured ±500mV from steady state with CL=5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. AC ELECTRICAL CHARACTERISTICS (TA=0℃ to 70℃, VCC=1.5V~3.6V) U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Preliminary Rev. 1.0 PAGE 5 Low Power CMOS SRAM 64K X 16 UC62LV1024 -55/-70 WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION tAVAX tWC tE1LWH UC62LV1024-55 UC62LV1024-70 Min Typ Max Min Typ Max Write Cycle Time 55 - - 70 - - ns tCW Chip Select to END of Write 40 - - 50 - - ns tAVWL tAS Address Setup Time 0 - - 0 - - ns tAVWH tAW Address valid to End of Write 40 - - 50 - - ns tBW tBW Data Byte Control End of Write 40 tWLWH tWP Write Pulse Width 40 - - 50 - - ns tWHAX tWR Write Recovery Time 0 - - 0 - - ns tWLOZ tWHZ Write to Output in High Z - - 20 - - 20 ns tDVWH tDW Data to Write Time Overlap 35 - 40 - tWHDX tDH Data Hold Time for Write End 0 - - 0 - - ns tGHOZ tOHZ Output Disable to Output In High Z - - 20 - - 20 ns tWHQX tOW End of Write to Output Active 10 - - 10 - - ns UNIT 50 Ns ns SWITCHING WAVEFORMS (WRITE CYCLE) WRITECYCLE1(1) tWC ADDRESS tAW OE tCW(11) CE tAS (4,10) tWP(2) WE tBW UB/LB tOHZ DOUT tDW tDH DIN U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Preliminary Rev. 1.0 PAGE 6 Low Power CMOS SRAM 64K X 16 UC62LV1024 -55/-70 WRITE CYCLE2(1,6) tWC ADDRESS tAW tCW(11) CE tAS tWP(2) WE tWHZ tOH DOUT (7) tDW (8) tDH DIN NOTES: 1. WE\ must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE\ and WE\ low. All signals must be active to initiate a write and any one can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE\ or WE\ going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE\ low transition occurs simultaneously with the WE\ low transitions or after the WE\ transition, output remain in a high impedance state. 6. OE\ is continuously low (OE\ = VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE\ is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE\ going low to the end of write. U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Preliminary Rev. 1.0 PAGE 7 Low Power CMOS SRAM 64K X 16 UC62LV1024 -55/-70 ORDERING INFORMATION UC62LV1024 AB -- YY A => GRADE J :TSOP(II) K :BGA A :DICE B => GRADE C :COMMERCIAL (0 ~ 70℃) I :INDUSTRIAL (-40 ~ 85℃) YY => SPEED 55: 55ns 70: 70ns U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Preliminary Rev. 1.0 PAGE 8 Low Power CMOS SRAM 64K X 16 UC62LV1024 -55/-70 PACKAGE DIMENSIONS 23 44 A UNIT INCH MM 0.0433±0.004 0.004±0.002 0.039±0.002 0.012 ~ 0.018 0.012 ~ 0.016 0.005 ~ 0.008 0.005 ~ 0.006 0.725±0.004 0.400±0.004 0.463±0.008 0.0315±0.004 0.0197±0.004 0.0197±0.004 0.004 Max. 0° ~ 8° 1.10±0.1 0.1±0.05 1.00±0.05 0.3 ~ 0.45 0.3 ~ 0.4 0.12 ~ 0.21 0.12 ~ 0.16 18.41±0.1 10.16±0.1 11.76±0.20 0.80±0.10 0.50±0.1 0.80±0.1 0.1 Max. 0° ~ 8° SYMBOL θ E E1 A L L1 22 1 e "A" b D A b WITH PLATING A1 A2 DETAIL "A" (2:1) Seating Plane "y" A A1 A2 b b1 c c1 D E E1 e L L1 y θ c c1 BASE METAL TSOPII - 44 b1 0.25 ± 0.05 1.4 MAX SECTION A-A S id e V iew D 8 .0 B all p itch e= 0 .7 5 E D1 6 .0 5 .2 5 E1 3 .7 5 D ± 0 .1 S old er B a ll d iam eter = 0 .3 5 ± 0 .0 5 E±0.1 E1 e D1 F ig. A Fig. A T O P V iew 4 8 M in i-B G A 6 * 8 m m U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Preliminary Rev. 1.0 PAGE 9