UJA1069 LIN fail-safe system basis chip Rev. 04 — 28 October 2009 Product data sheet 1. General description The UJA1069 fail-safe System Basis Chip (SBC) replaces basic discrete components which are common in every Electronic Control Unit (ECU) with a Local Interconnect Network (LIN) interface. The fail-safe SBC supports all networking applications which control various power and sensor peripherals by using LIN as a local sub-bus. The fail-safe SBC contains the following integrated devices: • • • • • • LIN transceiver compliant with LIN 2.0 and SAE J2602, and compatible with LIN 1.3 Advanced independent watchdog Dedicated voltage regulator for microcontroller Serial peripheral interface (full duplex) Local wake-up input port Inhibit/limp-home output port In addition to the advantages of integrating these common ECU functions in a single package, the fail-safe SBC offers an intelligent combination of system-specific functions such as: • • • • Advanced low-power concept Safe and controlled system start-up behavior Advanced fail-safe system behavior that prevents any conceivable deadlock Detailed status reporting on system and sub-system levels The UJA1069 is designed to be used in combination with a microcontroller and a LIN controller. The fail-safe SBC ensures that the microcontroller is always started up in a defined manner. In failure situations the fail-safe SBC will maintain the microcontroller function for as long as possible, to provide full monitoring and software driven fall-back operation. The UJA1069 is designed for 14 V single power supply architectures and for 14 V and 42 V dual power supply architectures. UJA1069 NXP Semiconductors LIN fail-safe system basis chip 2. Features 2.1 General n Contains a full set of LIN ECU functions: u LIN transceiver u Voltage regulator for the microcontroller (5.0 V) u Enhanced window watchdog with on-chip oscillator u Serial Peripheral Interface (SPI) for the microcontroller u ECU power management system u Fully integrated autonomous fail-safe system n Designed for automotive applications: u Supports 14 V and 42 V architectures u Excellent ElectroMagnetic Compatibility (EMC) performance u ±8 kV ElectroStatic Discharge (ESD) protection Human Body Model (HBM) for off-board pins u ±4 kV ElectroStatic Discharge (ESD) protection IEC 61000-4-2 for off-board pins u ±60 V short-circuit proof LIN-bus pin u Battery and LIN-bus pins are protected against transients in accordance with ISO 7637-3 u Very low sleep current n Supports remote flash programming via the LIN-bus n Available in: u Small 6.4 mm × 7.8 mm HTSSOP24 package with low thermal resistance u Small 8 mm × 11 mm HTSSOP32 package with low thermal resistance 2.2 LIN transceiver n LIN 2.0 and SAE J2602 compliant LIN transceiver n Enhanced error signalling and reporting n Downward compatible with LIN 1.3 and the TJA1020 2.3 Power management n n n n n Smart operating modes and power management modes Cyclic wake-up capability in Standby and Sleep mode Local wake-up input with cyclic supply feature Remote wake-up capability via the LIN-bus External voltage regulators can easily be incorporated in the power supply system (flexible and fail-safe) n 42 V battery related high-side switch for driving external loads such as relays and wake-up switches n Intelligent maskable interrupt output UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 2 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 2.4 Fail-safe features n Safe and predictable behavior under all conditions n Programmable fail-safe coded window and time-out watchdog with on-chip oscillator, guaranteeing autonomous fail-safe system supervision n Fail-safe coded 16-bit SPI interface for the microcontroller n Global enable pin for the control of safety-critical hardware n Detection and detailed reporting of failures: u On-chip oscillator failure and watchdog alerts u Battery and voltage regulator undervoltages u LIN-bus failures (short-circuits) u TXDL and RXDL clamping situations and short-circuits u Clamped or open reset line u SPI message errors u Overtemperature warning n Rigorous error handling based on diagnostics n Supply failure early warning allows critical data to be stored n 23 bits of access-protected RAM is available e.g. for logging of cyclic problems n Reporting in a single SPI message; no assembly of multiple SPI frames needed n Limp-home output signal for activating application hardware in case system enters Fail-safe mode (e.g. for switching on warning lights) n Fail-safe coded activation of Software development mode and Flash mode n Unique SPI readable device type identification n Software-initiated system reset 3. Ordering information Table 1. Ordering information Type number Package Name Description UJA1069TW HTSSOP32 plastic thermal enhanced thin shrink small outline package; 32 leads; SOT549-1 body width 6.1 mm; lead pitch 0.65 mm; exposed die pad UJA1069TW24 HTSSOP24 plastic thermal enhanced thin shrink small outline package; 24 leads; SOT864-1 body width 4.4 mm; lead pitch 0.65 mm; exposed die pad UJA1069_4 Product data sheet Version © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 3 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 4. Block diagram SENSE BAT42 BAT14 SYSINH V3 INH/LIMP INTN WAKE TEST 31 (23) BAT MONITOR 32 (24) 27 (19) SDI SDO SCS RTLIN LIN TXDL RXDL GND V1 UJA1069 29 (21) 30 (22) 17 (13) INH V1 MONITOR 7 (6) 18 (14) WAKE RESET/EN 16 (12) CHIP TEMPERATURE SCK (3) 4 V1 (5) 6 (7) 8 RSTN EN SBC FAIL-SAFE SYSTEM WATCHDOG 11 (10) 9 (8) 10 (9) SPI OSCILLATOR 12 (11) 26 (18) 25 (17) 3 (2) LIN 5 (4) 23 (15) BAT42 001aad669 The pin numbers in parenthesis are for the UJA1069TW24 version. Fig 1. Block diagram UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 4 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 5. Pinning information 5.1 Pinning n.c. 1 32 BAT42 n.c. 2 31 SENSE TXDL 3 30 V3 V1 4 29 SYSINH RXDL 5 28 n.c. RSTN 6 27 BAT14 INTN 7 26 RTLIN EN 8 SDI 9 25 LIN UJA1069TW 24 n.c. SDO 10 23 GND SCK 11 22 n.c. SCS 12 21 n.c. n.c. 13 20 n.c. n.c. 14 19 n.c. n.c. 15 18 WAKE 17 INH/LIMP TEST 16 001aad676 Fig 2. Pin configuration (HTSSOP32) n.c. 1 24 BAT42 TXDL 2 23 SENSE V1 3 22 V3 RXDL 4 21 SYSINH RSTN 5 20 n.c. INTN 6 EN 7 SDI 8 17 LIN SDO 9 16 n.c. UJA1069TW24 19 BAT14 18 RTLIN SCK 10 15 GND SCS 11 14 WAKE TEST 12 13 INH/LIMP 001aad677 Fig 3. Pin configuration (HTSSOP24) UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 5 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 5.2 Pin description Table 2. Symbol Pin description Pin Description HTSSOP32 HTSSOP24 n.c. 1 1 not connected n.c. 2 - not connected TXDL 3 2 LIN transmit data input (LOW for dominant, HIGH for recessive) V1 4 3 voltage regulator output for the microcontroller (5 V) RXDL 5 4 LIN receive data output (LOW when dominant, HIGH when recessive) RSTN 6 5 reset output to microcontroller (active LOW; will detect clamping situations) INTN 7 6 interrupt output to microcontroller (active LOW; open-drain, wire-AND this pin to other ECU interrupt outputs) EN 8 7 enable output (active HIGH; push-pull, LOW with every reset / watchdog overflow) SDI 9 8 SPI data input SDO 10 9 SPI data output (floating when pin SCS is HIGH) SCK 11 10 SPI clock input SCS 12 11 SPI chip select input (active LOW) n.c. 13 - not connected n.c. 14 - not connected n.c. 15 - not connected TEST 16 12 test pin (should be connected to ground in application) INH/LIMP 17 13 inhibit / limp home output (BAT14 related, push-pull, default floating) WAKE 18 14 local wake-up input (BAT42 related, continuous or cyclic sampling) n.c. 19 - not connected n.c. 20 - not connected n.c. 21 - not connected n.c. 22 - not connected GND 23 15 ground n.c. 24 16 not connected LIN 25 17 LIN bus line (LOW in dominant state) RTLIN 26 18 LIN-bus termination resistor connection BAT14 27 19 14 V battery supply input n.c. 28 20 not connected SYSINH 29 21 system inhibit output (BAT42 related; e.g. for controlling external DC-to-DC converter) UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 6 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip Table 2. Symbol Pin description …continued Pin Description HTSSOP32 HTSSOP24 V3 30 22 unregulated 42 V output (BAT42 related; continuous output, or cyclic mode synchronized with local wake-up input) SENSE 31 23 fast battery interrupt / chatter detector input BAT42 32 24 42 V battery supply input (connect this pin to BAT14 in 14 V applications) The exposed die pad at the bottom of the package allows better dissipation of heat from the SBC via the printed-circuit board. The exposed die pad is not connected to any active part of the IC and can be left floating, or can be connected to GND for the best EMC performance. 6. Functional description 6.1 Introduction The UJA1069 combines all peripheral functions around a microcontroller within typical automotive networking applications into one dedicated chip. The functions are as follows: • • • • • • • • • • • • Power supply for the microcontroller Switched BAT42 output System reset Watchdog with Window mode and Time-out mode On-chip oscillator LIN transceiver for serial communication SPI control interface Local wake-up input Inhibit or limp-home output System inhibit output port Compatibility with 42 V power supply systems Fail-safe behavior 6.2 Fail-safe system controller The fail-safe system controller is the core of the UJA1069 and is supervised by a watchdog timer which is clocked directly by the dedicated on-chip oscillator. The system controller manages the register configuration and controls all internal functions of the SBC. Detailed device status information is collected and presented to the microcontroller. The system controller also provides the reset and interrupt signals. The fail-safe system controller is a state machine. The different operating modes and the transitions between these modes are illustrated in Figure 4. The following sections give further details about the SBC operating modes. UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 7 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip mode change via SPI watchdog trigger Standby mode V1: ON SYSINH: HIGH LIN: off-line watchdog: time-out/OFF mode change via SPI INH/LIMP: HIGH/LOW/float mode change via SPI EN: HIGH/LOW watchdog trigger wake-up detected with its wake-up interrupt disabled OR mode change to Sleep with pending wake-up OR watchdog time-out with watchdog timeout interrupt disabled OR watchdog OFF and IV1 > I thH(V1) with reset option OR interrupt ignored > t RSTN(INT) OR RSTN falling edge detected OR V1 undervoltage detected flash entry enabled (111/001/111 mode sequence) OR illegal Mode register code OR mode change to Sleep with pending wake-up OR watchdog not properly served OR interrupt ignored > tRSTN(INT) OR RSTN falling edge detected OR V1 undervoltage detected OR illegal Mode register code mode change via SPI Normal mode V1: ON SYSINH: HIGH LIN: all modes available watchdog: window INH/LIMP: HIGH/LOW/float EN: HIGH/LOW Sleep mode V1: OFF SYSINH: HIGH/float LIN: off-line watchdog: time-out/OFF INH/LIMP: LOW/float RSTN: LOW EN: LOW wake-up detected OR watchdog time-out OR V3 overload detected init Normal mode via SPI successful Start-up mode V1: ON init Normal mode via SPI successful SYSINH: HIGH supply connected for the first time LIN: off-line watchdog: start-up INH/LIMP: HIGH/LOW/float EN: LOW t > t WD(init) OR SPI clock count < > 16 OR RSTN falling edge detected OR RSTN released and V1 undervoltage detected OR illegal Mode register code leave Flash mode code OR watchdog time-out OR interrupt ignored > t RSTN(INT) OR RSTN falling edge detected OR V1 undervoltage detected OR illegal Mode register code Restart mode V1: ON SYSINH: HIGH init Flash mode via SPI AND flash entry enabled wake-up detected AND oscillator ok AND t > t ret LIN: off-line watchdog: start-up INH/LIMP: LOW/float watchdog trigger Flash mode V1: ON SYSINH: HIGH LIN: all modes available watchdog: time-out INH/LIMP: HIGH/LOW/float EN: LOW EN: HIGH/LOW t > t WD(init) OR SPI clock count < > 16 OR RSTN falling edge detected OR RSTN released and V1 undervoltage detected OR illegal Mode register code Fail-safe mode V1: OFF SYSINH: HIGH/float LIN: off-line watchdog: OFF INH/LIMP: LOW RSTN: LOW EN: LOW oscillator fail OR RSTN externally clamped HIGH detected > t RSTN(CHT) OR RSTN externally clamped LOW detected > t RSTN(CLT) OR V1 undervoltage detected > t V1(CLT) from any mode 001aad670 Fig 4. Main state diagram UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 8 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 6.2.1 Start-up mode Start-up mode is the ‘home page’ of the SBC. This mode is entered when battery and ground are connected for the first time. Start-up mode is also entered after any event that results in a system reset. The reset source information is provided by the SBC to support different software initialization cycles that depend on the reset event. It is also possible to enter Start-up mode via a wake-up from Standby mode, Sleep mode or Fail-safe mode. Such a wake-up can originate either from the LIN-bus or from the local WAKE pin. On entering Start-up mode a lengthened reset time tRSTNL is observed. This reset time is either user-defined (via the RLC bit in the System Configuration register) or defaults to the value as given in Section 6.12.12. During the reset lengthening time pin RSTN is held LOW by the SBC. When the reset time is completed (pin RSTN is released and goes HIGH) the watchdog timer will wait for initialization. If the watchdog initialization is successful, the selected operating mode (Normal mode or Flash mode) will be entered. Otherwise the Restart mode will be entered. 6.2.2 Restart mode The purpose of the Restart mode is to give the application a second chance to start up, should the first attempt from Start-up mode fail. Entering Restart mode will always set the reset lengthening time tRSTNL to the higher value to guarantee the maximum reset length, regardless of previous events. If start-up from Restart mode is successful (the previous problems do not reoccur and watchdog initialization is successful), then the selected operating mode will be entered. From Restart mode this must be Normal mode. If problems persist or if V1 fails to start up, then Fail-safe mode will be entered. 6.2.3 Fail-safe mode Severe fault situations will cause the SBC to enter Fail-safe mode. Fail-safe mode is also entered if start-up from Restart mode fails. Fail-safe mode offers the lowest possible system power consumption from the SBC and from the external components controlled by the SBC. A wake-up (via the LIN-bus or the WAKE pin) is needed to leave Fail-safe mode. This is only possible if the on-chip oscillator is running correctly. The SBC restarts from Fail-safe mode with a defined delay tret, to guarantee a discharged V1 before entering Start-up mode. Regulator V1 will restart and the reset lengthening time tRSTNL is set to the higher value; see Section 6.5.1. 6.2.4 Normal mode Normal mode gives access to all SBC system resources, including LIN, INH/LIMP and EN. Therefore in Normal mode the SBC watchdog runs in (programmable) Window mode, for strictest software supervision. Whenever the watchdog is not properly served a system reset is performed. UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 9 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip Interrupts from SBC to the host microcontroller are also monitored. A system reset is performed if the host microcontroller does not respond within tRSTN(INT). Entering Normal mode does not activate the LIN transceiver automatically. The LIN Mode Control (LMC) bit must be used to activate the LIN medium if required, allowing local cyclic wake-up scenarios to be implemented without affecting the LIN-bus. 6.2.5 Standby mode In Standby mode the system is set into a state with reduced current consumption. The watchdog will, however, continue to monitor the microcontroller (Time-out mode) since it is powered via pin V1. In the event that the host microcontroller can provide a low-power mode with reduced current consumption in its Standby mode or Stop mode, the watchdog can be switched off entirely in Standby mode of the SBC. The SBC monitors the microcontroller supply current to ensure that there is no unobserved phase with disabled watchdog and running microcontroller. The watchdog will remain active until the supply current drops below IthL(V1). Below this current limit the watchdog is disabled. Should the current increase to IthH(V1), e.g. as result of a microcontroller wake-up from application specific hardware, the watchdog will start operating again with the previously used time-out period. If the watchdog is not triggered correctly, a system reset will occur and the SBC will enter Start-up mode. If Standby mode is entered from Normal mode with the selected watchdog OFF option, the watchdog will use the maximum time-out as defined for Standby mode until the supply current drops below the current detection threshold; the watchdog is now OFF. If the current increases again, the watchdog is immediately activated, again using the maximum watchdog time-out period. If the watchdog OFF option is selected during Standby mode, the last used watchdog period will define the time for the supply current to fall below the current detection threshold. This allows the user to align the current supervisor function to the application needs. Generally, the microcontroller can be activated from Standby mode via a system reset or via an interrupt without reset. This allows implementation of differentiated start-up behavior from Standby mode, depending on the application needs: • If the watchdog is still running during Standby mode, the watchdog can be used for cyclic wake-up behavior of the system. A dedicated Watchdog Time-out Interrupt Enable (WTIE) bit enables the microcontroller to decide whether to receive an interrupt or a hardware reset upon overflow. The interrupt option will be cleared in hardware automatically with each watchdog overflow to ensure that a failing main routine is detected while the interrupt service still operates. So the application software must set the interrupt behavior each time before a standby cycle is entered. • Any wake-up via the LIN-bus together with a local wake-up event will force a system reset event or an interrupt to the microcontroller. So it is possible to exit Standby mode without any system reset if required. When an interrupt event occurs the application software has to read the Interrupt register within tRSTN(INT). Otherwise a fail-safe system reset is forced and Start-up mode will be entered. If the application has read out the Interrupt register within the specified time, it can decide whether to switch into Normal mode via an SPI access or to stay in Standby mode. UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 10 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip The following operations are possible from Standby mode: • Cyclic wake-up by the watchdog via an interrupt signal to the microcontroller (the microcontroller is triggered periodically and checked for the correct response) • Cyclic wake-up by the watchdog via a reset signal (a reset is performed periodically; the SBC provides information about the reset source to allow different start sequences after reset) • Wake-up by activity on the LIN-bus via an interrupt signal to the microcontroller • Wake-up by bus activity on the LIN-bus via a reset signal • Wake-up by increasing the microcontroller supply current without a reset signal (where a stable supply is needed for the microcontroller RAM contents to remain valid and wake-up from an external application not connected to the SBC) • Wake-up by increasing the microcontroller supply current with a reset signal • Wake-up due to a falling edge at pin WAKE forcing an interrupt to the microcontroller • Wake-up due to a falling edge at pin WAKE forcing a reset signal 6.2.6 Sleep mode In Sleep mode the microcontroller power supply (V1) and the INH/LIMP controlled external supplies are switched off entirely, resulting in minimum system power consumption. In this mode, the watchdog runs in Time-out mode or is completely off. Entering Sleep mode results in an immediate LOW level on pin RSTN, thus stopping any operation of the microcontroller. The INH/LIMP output is floating in parallel and pin V1 is disabled. It is also possible for V3 to be ON, OFF or in Cyclic mode to supply external wake-up switches. If the watchdog is not disabled in software, it will continue to run and force a system reset upon overflow of the programmed period time. The SBC enters Start-up mode and pin V1 becomes active again. This behavior can be used for a cyclic wake-up from Sleep mode. Depending on the application, the following operations can be selected from Sleep mode: • Cyclic wake-up by the watchdog (only in Time-out mode); a reset is performed periodically, the SBC provides information about the reset source to allow different start sequences after reset • Wake-up by activity on the LIN-bus or falling edge at pin WAKE • An overload on V3, only if V3 is in a cyclic or in continuously ON mode 6.2.7 Flash mode Flash mode can only be entered from Normal mode by entering a specific Flash mode entry sequence. This fail-safe control sequence comprises three consecutive write accesses to the Mode register, within the legal windows of the watchdog, using the operating mode codes 111, 001 and 111 respectively. As a result of this sequence, the SBC will enter Start-up mode and perform a system reset with the related reset source information (bits RSS[3:0] = 0110). UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 11 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip From Start-up mode the application software now has to enter Flash mode within tWD(init) by writing Operating Mode code 011 to the Mode register. This feeds back a successfully received hardware reset (handshake between the SBC and the microcontroller). The transition from Start-up mode to Flash mode is possible only once after completing the Flash entry sequence. The application can also decide not to enter Flash mode but to return to Normal mode by using the Operating Mode code 101 for handshaking. This erases the Flash mode entry sequence. The watchdog behavior in Flash mode is similar to its time-out behavior in Standby mode, but Operating mode code 111 must be used for serving the watchdog. If this code is not used or if the watchdog overflows, the SBC immediately forces a reset and enters Start-up mode. Flash mode is properly exited using the Operating Mode code 110 (leave Flash mode), which results in a system reset with the corresponding reset source information. Other Mode register codes will cause a forced reset with reset source code ‘illegal Mode register code’. 6.3 On-chip oscillator The on-chip oscillator provides the clock signal for all digital functions and is the timing reference for the on-chip watchdog and the internal timers. If the on-chip oscillator frequency is too low or the oscillator is not running at all, there is an immediate transition to Fail-safe mode. The SBC will stay in Fail-safe mode until the oscillator has recovered to its normal frequency and the system receives a wake-up event. 6.4 Watchdog The watchdog provides the following timing functions: • Start-up mode; needed to give the software the opportunity to initialize the system • Window mode; detects too early and too late accesses in Normal mode • Time-out mode; detects a too late access, can also be used to restart or interrupt the microcontroller from time to time (cyclic wake-up function) • OFF mode; fail-safe shut-down during operation thus preventing any blind spots in the system supervision The watchdog is clocked directly by the on-chip oscillator. To guarantee fail-safe control of the watchdog via the SPI, all watchdog accesses are coded with redundant bits. Therefore, only certain codes are allowed for a proper watchdog service. The following corrupted watchdog accesses result in an immediate system reset: • Illegal watchdog period coding; only ten different codes are valid • Illegal operating mode coding; only six different codes are valid Any microcontroller driven mode change is synchronized with a watchdog access by reading the mode information and the watchdog period information from the same register. This enables an easy software flow control with defined watchdog behavior when switching between different software modules. UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 12 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 6.4.1 Watchdog start-up behavior Following any reset event the watchdog is used to monitor the ECU start-up procedure. It observes the behavior of the RSTN pin for any clamping condition or interrupted reset wire. In case the watchdog is not properly served within tWD(init), another reset is forced and the monitoring procedure is restarted. In case the watchdog is again not properly served, the system enters Fail-safe mode (see also Figure 4, Start-up mode and Restart mode). 6.4.2 Watchdog window behavior Whenever the SBC enters Normal mode, the Window mode of the watchdog is activated. This ensures that the microcontroller operates within the required speed; a too fast as well as a too slow operation will be detected. Watchdog triggering using the Window mode is illustrated in Figure 5. period too early trigger restarts period trigger window 100 % 50 % trigger via SPI last trigger point earliest possible trigger point latest possible trigger point trigger restarts period (with different duration if desired) 50 % too early 100 % trigger window new period trigger via SPI earliest possible trigger point Fig 5. latest possible trigger point mce626 Watchdog triggering using Window mode The SBC provides 10 different period timings, scalable with a 4-factor watchdog prescaler. The period can be changed within any valid trigger window. Whenever the watchdog is triggered within the window time, the timer will be reset to start a new period. The watchdog window is defined to be between 50 % and 100 % of the nominal programmed watchdog period. Any too early or too late watchdog access or wrong Mode register code access will result in an immediate system reset, entering Start-up mode. UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 13 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 6.4.3 Watchdog time-out behavior Whenever the SBC operates in Standby mode, in Sleep mode or in Flash mode, the active watchdog operates in Time-out mode. The watchdog has to be triggered within the actual programmed period time; see Figure 6. The Time-out mode can be used to provide cyclic wake-up events to the host microcontroller from Standby mode and Sleep mode. period trigger range time-out trigger via SPI earliest possible trigger point latest possible trigger point trigger restarts period (with different duration if desired) trigger range time-out new period mce627 Fig 6. Watchdog triggering using Time-out mode In Standby and in Flash mode the nominal periods can be changed with any SPI access to the Mode register. Any illegal watchdog trigger code results in an immediate system reset, entering Start-up mode. 6.4.4 Watchdog OFF behavior In Standby mode and Sleep mode it is possible to switch off the watchdog entirely. For fail-safe reasons this is only possible if the microcontroller has stopped program execution. To ensure that there is no program execution, the V1 supply current is monitored by the SBC while the watchdog is switched off. When selecting the watchdog OFF code, the watchdog remains active until the microcontroller supply current has dropped below the current monitoring threshold IthL(V1). After the supply current has dropped below the threshold, the watchdog stops at the end of the watchdog period. In case the supply current does not drop below the monitoring threshold, the watchdog stays active. If the microcontroller supply current increases above IthH(V1) while the watchdog is OFF, the watchdog is restarted with the last used watchdog period time and a watchdog restart interrupt is forced, if enabled. In case of a direct mode change towards Standby mode with watchdog OFF selected, the longest possible watchdog period is used. It should be noted that in Sleep mode V1 current monitoring is not active. UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 14 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 6.5 System reset The reset function of the UJA1069 offers two signals to deal with reset events: • RSTN; the global ECU system reset • EN; a fail-safe global enable signal 6.5.1 RSTN pin The system reset pin (RSTN) is a bidirectional input / output. Pin RSTN is active LOW with selectable pulse length upon the following events; see Figure 4: • Power-on (first battery connection) or VBAT42 below power-on reset threshold voltage • Low V1 supply • V1 current above threshold during Standby mode while watchdog OFF behavior is selected • • • • • V3 is down due to short-circuit condition during Sleep mode • • • • Wake-up event from Fail-safe mode RSTN externally forced LOW, falling edge event Successful preparation for Flash mode completed Successful exit from Flash mode Wake-up from Standby mode via pins LIN or WAKE if programmed accordingly, or any wake-up event from Sleep mode Watchdog trigger failures (too early, overflow, wrong code) Illegal mode code via SPI applied Interrupt not served within tRSTN(INT) All of these reset events have a dedicated reset source in the System Status register to allow distinction between the different events. The SBC will lengthen any reset event to 1 ms or 20 ms to ensure that external hardware is properly reset. After the first battery connection, a short power-on reset of 1 ms is provided after voltage V1 is present. Once started, the microcontroller can set the Reset Length Control (RLC) bit within the System Configuration Register; this allows the reset pulse to be adjusted for future reset events. With this bit set, all reset events are lengthened to 20 ms. Due to fail-safe behavior, this bit will be set automatically (to 20 ms) in Restart mode or Fail-safe mode. With this mechanism it is guaranteed that an erroneously shortened reset pulse will restart any microcontroller, at least within the second trial by using the long reset pulse. The behavior of pin RSTN is illustrated in Figure 7. The duration of tRSTNL depends on the setting of the RLC bit (defines the reset length). Once an external reset event is detected the system controller enters the Start-up mode. The watchdog now starts to monitor pin RSTN as illustrated in Figure 8. If the RSTN pin is not released in time then Fail-safe mode is entered as shown in Figure 4. UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 15 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip V1 Vrel(UV)(V1) Vdet(UV)(V1) time power-up undervoltage missing watchdog access VRSTN undervoltage spike powerdown time tRSTNL Fig 7. tRSTNL tRSTNL coa054 Reset pin behavior VRSTN time t RSTNL RSTN externally forced LOW t WD(init) VRSTN time t RSTNL RSTN externally forced LOW t WD(init) 001aad181 Fig 8. Reset timing diagram Pin RSTN is monitored for a continuously clamped LOW situation. Once the SBC pulls pin RSTN HIGH but pin RSTN level remains LOW for longer than tRSTN(CLT), the SBC immediately enters Fail-safe mode since this indicates an application failure. UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 16 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip The SBC also detects if pin RSTN is clamped HIGH. If the HIGH-level remains on the pin for longer than tRSTN(CHT) while pin RSTN is driven internally to a LOW-level by the SBC, the SBC falls back immediately to Fail-safe mode since the microcontroller cannot be reset any more. By entering Fail-safe mode, the V1 voltage regulator shuts down and the microcontroller stops. Additionally, chattering reset signals are handled by the SBC in such a way that the system safely falls back to Fail-safe mode with the lowest possible power consumption. 6.5.2 EN output Pin EN can be used to control external hardware such as power components or as a general purpose output if the system is running properly. During all reset events, when pin RSTN is pulled LOW, the EN control bit will be cleared, pin EN will be pulled LOW and will stay LOW after pin RSTN is released. In Normal mode and Flash mode of the SBC, the microcontroller can set the EN control bit via the SPI. This results in releasing pin EN which then returns to a HIGH-level. 6.6 Power supplies 6.6.1 BAT14, BAT42 and SYSINH The SBC has two supply pins, pin BAT42 and pin BAT14. Pin BAT42 supplies most of the SBC where pin BAT14 only supplies the linear voltage regulators and the INH/LIMP output pin. This supply architecture allows different supply strategies including the use of external DC-to-DC converters controlled by the pin SYSINH. 6.6.1.1 SYSINH output The SYSINH output is a high-side switch from BAT42. It is activated whenever the SBC requires supply voltage to pin BAT14, e.g. when V1 is on (see Figure 4 and Figure 8). Otherwise pin SYSINH is floating. Pin SYSINH can be used to control e.g. an external step-down voltage regulator to BAT14, to reduce power consumption in low-power modes. 6.6.2 SENSE input The SBC has a dedicated SENSE pin for dynamic monitoring of the battery contact of an electronic control unit. Connecting this pin in front of the polarity protection diode of the ECU provides an early warning if the battery becomes disconnected. 6.6.3 Voltage regulator V1 The UJA1069 has an independent voltage regulator supplied out of the BAT14 pin. Regulator V1 is intended to supply the microcontroller. The V1 voltage is continuously monitored to provide the system reset signal when undervoltage situations occur. Whenever the V1 voltage falls below one of the three programmable thresholds, a hardware reset is forced. A dedicated V1 supply comparator (V1 Monitor) observes V1 for undervoltage events lower than VUV(VFI). This allows the application to receive a supply warning interrupt in case one of the lower V1 undervoltage reset thresholds is selected. The V1 regulator is overload protected. The maximum output current available from pin V1 depends on the voltage applied to pin BAT14 according to Table 25. For thermal reasons, the total power dissipation should be taken into account. UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 17 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 6.6.4 Switched battery output V3 V3 is a high-side switched BAT42-related output which is used to drive external loads such as wake-up switches or relays. The features of V3 are as follows: • Three application controlled modes of operation; ON, OFF or Cyclic mode. • Two different cyclic modes allow the supply of external wake-up switches; these switches are powered intermittently, thus reducing the system’s power consumption in case a switch is continuously active; the wake-up input of the SBC is synchronized with the V3 cycle time. • The switch is protected against current overloads. If V3 is overloaded, pin V3 is automatically disabled. The corresponding Diagnosis register bit is reset and an interrupt is forced (if enabled). During Sleep mode, a wake-up is forced and the corresponding reset source code becomes available in the RSS bits of the System Status register. This signals that the wake-up source via V3 supplied wake-up switches has been lost. 6.7 LIN transceiver The integrated LIN transceiver of the UJA1069 is a LIN 2.0 compliant transceiver. The transceiver has the following features: • SAE J2602 compliant and compatible with LIN revision 1.3 • Fail-safe LIN termination to BAT42 via dedicated RTLIN pin • Enhanced error handling and reporting of bus and TXD failures; these failures are separately identified in the System Diagnosis register 6.7.1 Mode control The controller of the LIN transceiver provides two modes of operation: Active mode and Off-line mode; see Figure 9. In Off-line mode the transmitter and receiver do not consume current, but wake-up events will be recognized by the separate wake-up receiver. UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 18 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip Active mode transmitter: ON/OFF (LTC) receiver: ON RXDL: bitstream RTLIN: ON/75 µA SBC enters Normal or Flash mode AND LMC = 1 SBC enters Stand-by, Start-up, Restart or Fail-safe mode OR LMC = 0 Off-line mode power-on transmitter: OFF receiver: wake-up RXDL: wake-up status RTLIN: 75 µA/OFF SBC enters Fail-safe mode 001aad184 Fig 9. 6.7.1.1 States LIN transceiver Active mode In Active mode the LIN transceiver can transmit data to and receive data from the LIN bus. To enter Active mode the LMC bit must be set in the Physical Layer register and the SBC must be in Normal mode or Flash mode. The LTC bit can be used to set the LIN transceiver to a Listen-only mode. The transmitter output stage is disabled in this mode. When leaving Active mode the LIN transmitter is disabled and the LIN receiver is monitoring the LIN-bus for a valid wake-up. 6.7.1.2 Off-line mode Off-line mode is the low-power mode of the LIN transceiver. The LIN transceiver is disabled to save supply current. Pin RXDL reflects any wake-up event at the LIN-bus. 6.7.2 LIN wake-up For a remote wake-up via LIN a LIN-bus signal is required as shown in Figure 10. UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 19 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip LIN wake-up tBUS(LIN) 001aad447 Fig 10. LIN wake-up timing diagram 6.7.3 Termination control The RTLIN pin is in one of 3 different states: RTLIN = on, RTLIN = off or RTLIN = 75 µA; see Figure 11. Active mode and receiver dominant > t LIN(dom)(det) OR Off-line mode RTLIN = 75 µA RTLIN = ON supplied directly out of BAT42 supplied directly out of BAT42 Active mode and receiver recessive > t LIN(dom)(rec) OR mode change to Active mode Off-line mode AND receiver recessive > t LIN(dom)(rec) Off-line mode AND receiver dominant > t LIN(dom)(det) mode change to Active mode power-on RTLIN = OFF 001aad183 Fig 11. States of the RTLIN pin During Active mode, with no short-circuit between the LIN-bus and GND, pin RTLIN provides an internal switch to BAT42. For master and slave operation an external resistor, 1 kΩ or 30 kΩ respectively, can be applied between pins RTLIN and LIN. An external diode in series with the termination resistor is not required due to the incorporated internal diode. 6.7.4 LIN slope control The LSC bit in the Physical Layer Control register offers a choice between two LIN slope times, allowing communication up to 20 kbit/s (normal) or up to 10.4 kbit/s (low slope). UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 20 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 6.7.5 LIN driver capability Setting the LDC bit in the Physical Layer Control register will increase the driver capability of the LIN output stage. This feature is used in auto-addressing systems, where the standard LIN 2.0 drive capability is insufficient. 6.7.6 Bus and TXDL failure detection The SBC handles and reports the following LIN-bus related failures: • LIN-bus shorted to ground • LIN-bus shorted to VBAT14 or VBAT42; the transmitter is disabled • TXDL clamped dominant; the transmitter is disabled These failure events force an interrupt to the microcontroller whenever the status changes and the corresponding interrupt is enabled. 6.7.6.1 TXDL dominant clamping If the TXDL pin is clamped dominant for longer than tTXDL(dom)(dis) the LIN transmitter is disabled. After the TXDL pin becomes recessive the transmitter is reactivated automatically when detecting bus activity or manually by setting and clearing the LTC bit. 6.7.6.2 LIN dominant clamping When the LIN-bus is clamped dominant for longer than tLIN(dom)(det) (which is longer than tTXDL(dom)(dis)), the state of the LIN termination is changed according to Figure 11. 6.7.6.3 LIN recessive clamping If the LIN bus pin is clamped recessive while TXDL is driven dominant the LIN transmitter is disabled. The transmitter is reactivated automatically when the LIN bus becomes dominant or manually by setting and clearing the LTC bit. 6.8 Inhibit and limp-home output The INH/LIMP output pin is a 3-state output pin which can be used either as an inhibit for an extra (external) voltage regulator, or as a ‘limp-home’ output. The pin is controlled via the ILEN bit and ILC bit in the System Configuration register; see Figure 12. UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 21 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip state change via SPI OR enter Fail-safe mode INH/LIMP: HIGH INH/LIMP: LOW ILEN = 1 ILC = 1 ILEN = 1 ILC = 0 state change via SPI state change via SPI OR (enter Start-up mode after wake-up reset, external reset or V1 undervoltage) OR enter Restart mode OR enter Sleep mode state change via SPI OR enter Fail-safe mode state change via SPI state change via SPI INH/LIMP: floating power-on ILEN = 0 ILC = 1/0 001aad178 Fig 12. States of the INH/LIMP pin When pin INH/LIMP is used as inhibit output, a pull-down resistor to GND ensures a default LOW level. The pin can be set to HIGH according to the state diagram. When pin INH/LIMP is used as limp-home output, a pull-up resistor to VBAT42 ensures a default HIGH level. The pin is automatically set to LOW when the SBC enters Fail-safe mode. 6.9 Wake-up input The WAKE input comparator is triggered by negative edges on pin WAKE. Pin WAKE has an internal pull-up resistor to BAT42. It can be operated in two sampling modes which are selected via the WAKE Sample Control bit (WSC): • Continuous sampling (with an internal clock) if the bit is set • Sampling synchronized to the cyclic behavior of V3 if the bit is cleared; see Figure 13. This is to save bias current within the external switches in low-power operation. Two repetition times are possible, 16 ms and 32 ms. If V3 is continuously ON, the WAKE input will be sampled continuously, regardless of the level of bit WSC. The dedicated bits Edge Wake-up Status (EWS) and WAKE Level Status (WLS) in the System Status register reflect the actual status of pin WAKE. The WAKE port can be disabled by clearing the WEN bit in the System Configuration register. UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 22 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip tw(CS) ton(CS) V3 tsu(CS) approximately 70 % sample active VWAKE signal already HIGH due to biasing (history) button pushed button released signal remains LOW due to biasing (history) flip flop VINTN 001aac307 Fig 13. Pin WAKE, cyclic sampling via V3 6.10 Interrupt output Pin INTN is an open-drain interrupt output. It is forced LOW whenever at least one bit in the Interrupt register is set. By reading the Interrupt register all bits are cleared. The Interrupt register will also be cleared during a system reset (RSTN LOW). As the microcontroller operates typically with an edge-sensitive interrupt port, pin INTN will be HIGH for at least tINTN after each read-out of the Interrupt register. Without further interrupts within tINTN pin INTN stays HIGH, otherwise it will revert to LOW again. To prevent the microcontroller from being slowed down by repetitive interrupts, in Normal mode some interrupts are only allowed to occur once per watchdog period; see Section 6.12.7. If an interrupt is not read out within tRSTN(INT) a system reset is performed. 6.11 Temperature protection The temperature of the SBC chip is monitored as long as the microcontroller voltage regulator V1 is active. To avoid an unexpected shutdown of the application by the SBC, the temperature protection will not switch off any part of the SBC or activate a defined system stop of its own accord. If the temperature is too high it generates an interrupt to the microcontroller, if enabled, and the corresponding status bit will be set. The microcontroller can then decide whether to switch off parts of the SBC to decrease the chip temperature. UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 23 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 6.12 SPI interface The Serial Peripheral Interface (SPI) provides the communication link with the microcontroller, supporting multi-slave and multi-master operation. The SPI is configured for full duplex data transfer, so status information is returned when new control data is shifted in. The interface also offers a read-only access option, allowing registers to be read back by the application without changing the register content. The SPI uses four interface signals for synchronization and data transfer: • • • • SCS - SPI chip select; active LOW SCK - SPI clock; default level is LOW due to low-power concept SDI - SPI data input SDO - SPI data output; floating when pin SCS is HIGH Bit sampling is performed on the falling clock edge and data is shifted on the rising clock edge; see Figure 14. SCS SCK 02 01 03 04 15 16 sampled SDI SDO X floating X MSB 14 13 12 01 LSB MSB 14 13 12 01 LSB X floating mce634 Fig 14. SPI timing protocol To protect against wrong or illegal SPI instructions, the SBC detects the following SPI failures: • SPI clock count failure (wrong number of clock cycles during one SPI access): only 16 clock periods are allowed within one SCS cycle. Any deviation from the 16 clock cycles results in an SPI failure interrupt, if enabled. The access is ignored by the SBC. In Start-up and Restart mode a reset is forced instead of an interrupt • Forbidden mode changes according to Figure 4 result in an immediate system reset • Illegal Mode register code. Undefined operating mode or watchdog period coding results in an immediate system reset; see Section 6.12.3 UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 24 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 6.12.1 SPI register mapping Any control bit which can be set by software is readable by the application. This allows software debugging as well as control algorithms to be implemented. Watchdog serving and mode setting is performed within the same access cycle; this only allows an SBC mode change whilst serving the watchdog. Each register carries 12 data bits; the other 4 bits are used for register selection and read/write definition. 6.12.2 Register overview The SPI interface gives access to all SBC registers; see Table 3. The first two bits (A1 and A0) of the message header define the register address, the third bit is the Read Register Select bit (RRS) to select one out of two possible feedback registers; the fourth bit (RO) allows ‘read only’ access to one of the feedback registers. Which of the SBC registers can be accessed also depends on the SBC operating mode. Table 3. Register overview Register address bits (A1, A0) Operating mode Write access (RO = 0) 00 all modes 01 10 11 Read access (RO = 0 or RO = 1) Read Register Select (RRS) bit = 0 Read Register Select (RRS) bit = 1 Mode register System Status register System Diagnosis register Normal mode; Standby mode; Flash mode Interrupt Enable register Interrupt Enable Feedback register Interrupt register Start-up mode; Restart mode Special Mode register Interrupt Enable Feedback register Special Mode Feedback register Normal mode; Standby mode System Configuration register System Configuration Feedback register General Purpose Feedback register 0 Start-up mode; Restart mode; Flash mode General Purpose register 0 System Configuration Feedback register General Purpose Feedback register 0 Normal mode; Standby mode Physical Layer Control register Physical Layer Control Feedback register General Purpose Feedback register 1 Start-up mode; Restart mode; Flash mode General Purpose register 1 Physical Layer Control Feedback register General Purpose Feedback register 1 6.12.3 Mode register In the Mode register the watchdog is defined and re-triggered, and the SBC operating mode is selected. The Mode register also contains the global enable output bit (EN) and the Software Development Mode (SDM) control bit. During system operation cyclic access to the Mode register is required to serve the watchdog. This register can be written to in all modes. At system start-up the Mode register must be written to within tWD(init) from releasing RSTN (HIGH-level on pin RSTN). Any write access is checked for proper watchdog and system mode coding. If an illegal code is detected, access is ignored by the SBC and a system reset is forced in accordance with the state diagram of the system controller; see Figure 4. UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 25 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip Table 4. Mode register bit description (bits 15 to 12 and 5 to 0) Bit Symbol Description Value Function 15 and 14 A1, A0 register address 00 select Mode register 13 RRS Read Register Select 1 read System Diagnosis register 0 read System Status register Read Only 1 read selected register without writing to Mode register 0 read selected register and write to Mode register 001 Normal mode 010 Standby mode 011 initialize Flash mode[1] 100 Sleep mode 101 initialize Normal mode 110 leave Flash mode 111 Flash mode [1] Software Development Mode 1 Software development mode enabled[2] 0 normal watchdog, interrupt, reset monitoring and fail-safe behavior EN output pin HIGH 12 RO 11 to 6 NWP[5:0] see Table 5 5 to 3 OM[2:0] Operating Mode 2 SDM 1 EN Enable 1 0 EN output pin LOW 0 - reserved 0 reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit [1] Flash mode can be entered only with the watchdog service sequence ‘Normal mode to Flash mode to Normal mode to Flash mode’, while observing the watchdog trigger rules. With the last command of this sequence the SBC forces a system reset, and enters Start-up mode to prepare the microcontroller for flash memory download. The four RSS bits in the System Status register reflect the reset source information, confirming the Flash entry sequence. By using the Initializing Flash mode (within tWD(init) after system reset) the SBC will now successfully enter Flash mode. [2] See Section 6.13.1. UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 26 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip Table 5. Bit 11 to 6 Mode register bit description (bits 11 to 6)[1] Symbol NWP[5:0] Description Value 00 1001 Nominal Watchdog Period 00 1100 WDPRE = 00 (as 01 0010 set in the Special 01 0100 Mode register) Time Normal mode (ms) Standby mode (ms) Flash mode (ms) Sleep mode (ms) 4 20 20 160 8 40 40 320 16 80 80 640 32 160 160 1024 01 1011 40 320 320 2048 10 0100 48 640 640 3072 10 1101 56 1024 1024 4096 11 0011 64 2048 2048 6144 11 0101 72 4096 4096 8192 80 OFF[2] 8192 OFF[3] 6 30 30 240 12 60 60 480 24 120 120 960 48 240 240 1536 60 480 480 3072 10 0100 72 960 960 4608 10 1101 84 1536 1536 6144 11 0011 96 3072 3072 9216 11 0101 108 6144 6144 12288 120 OFF[2] 12288 OFF[3] 10 50 50 400 20 100 100 800 40 200 200 1600 11 0110 Nominal 00 1001 Watchdog Period 00 1100 WDPRE = 01 (as 01 0010 set in the Special 01 0100 Mode register) 01 1011 11 0110 Nominal 00 1001 Watchdog Period 00 1100 WDPRE = 10 (as 01 0010 set in the Special 01 0100 Mode register) 80 400 400 2560 01 1011 100 800 800 5120 10 0100 120 1600 1600 7680 10 1101 140 2560 2560 10240 11 0011 160 5120 5120 15360 11 0101 180 10240 10240 20480 200 OFF[2] 20480 OFF[3] 11 0110 UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 27 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip Table 5. Bit Mode register bit description (bits 11 to 6)[1] …continued Symbol 11 to 6 NWP[5:0] Description Value Time Normal mode (ms) Standby mode (ms) Flash mode (ms) Sleep mode (ms) 14 70 70 560 28 140 140 1120 56 280 280 2240 112 560 560 3584 140 1120 1120 7168 10 0100 168 2240 2240 10752 10 1101 196 3584 3584 14336 11 0011 224 7168 7168 21504 11 0101 252 14336 14336 28672 280 OFF[2] 28672 OFF[3] 00 1001 Nominal Watchdog Period 00 1100 WDPRE = 11 (as 01 0010 set in the Special 01 0100 Mode register) 01 1011 11 0110 [1] The nominal watchdog periods are directly related to the SBC internal oscillator. The given values are valid for fosc = 512 kHz. [2] See Section 6.4.4. [3] The watchdog is immediately disabled on entering Sleep mode, with watchdog OFF behavior selected, because pin RSTN is immediately pulled LOW by the mode change. V1 is switched off after pulling pin RSTN LOW to guarantee a safe Sleep mode entry without dips on V1. See Section 6.4.4. 6.12.4 System Status register This register allows status information to be read back from the SBC. This register can be read in all modes. Table 6. Bit System Status register bit description Symbol Description Value Function 15 and 14 A1, A0 13 RRS register address 00 read System Status register Read Register Select 0 12 RO Read Only 1 read System Status register without writing to Mode register 0 read System Status register and write to Mode register UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 28 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip Table 6. System Status register bit description …continued Bit Symbol Description Value Function 11 to 8 RSS[3:0] Reset Source[1] 0000 power-on reset; first connection of BAT42 or BAT42 below power-on voltage threshold or RSTN was forced LOW externally 0001 cyclic wake-up out of Sleep mode 0010 low V1 supply; V1 has dropped below the selected reset threshold 0011 V1 current above threshold within Standby mode while watchdog OFF behavior and reset option (V1CMC bit) are selected 0100 V3 voltage is down due to overload occurring during Sleep mode 0101 SBC successfully left Flash mode 0110 SBC ready to enter Flash mode 0111 reserved for SBCs with CAN transceiver 1000 LIN wake-up event 1001 local wake-up event (via pin WAKE) 1010 wake-up out of Fail-safe mode 1011 watchdog overflow 1100 watchdog not initialized in time; tWD(init) exceeded 1101 watchdog triggered too early; window missed 1110 illegal SPI access 1111 interrupt not served within tRSTN(INT) 0 reserved for SBCs with CAN transceiver 7 - reserved 6 LWS LIN Wake-up Status 5 EWS 4 WLS 3 TWS 2 SDMS 1 ENS 0 [1] PWONS Edge Wake-up Status WAKE Level Status 1 LIN wake-up detected; cleared upon read 0 no LIN wake-up 1 pin WAKE negative edge detected; cleared upon read 0 pin WAKE no edge detected 1 pin WAKE above threshold 0 pin WAKE below threshold Temperature Warning Status 1 chip temperature exceeds the warning limit 0 chip temperature is below the warning limit Software Development Mode Status 1 Software Development mode on 0 Software Development mode off Enable Status 1 pin EN output activated (V1-related HIGH level) 0 pin EN output released (LOW level) 1 power-on reset; cleared after a successfully entered Normal mode 0 no power-on reset Power-on reset Status The RSS bits are updated with each reset event and not cleared. The last reset event is captured. 6.12.5 System Diagnosis register This register allows diagnosis information to be read back from the SBC. This register can be read in all modes. UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 29 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip Table 7. System Diagnosis register bit description Bit Symbol Description Value Function 15 and 14 A1, A0 register address 00 read System Diagnosis register 13 RRS Read Register Select 1 12 RO Read Only 1 read System Diagnosis register without writing to Mode register 0 read System Diagnosis register and write to Mode register 11 to 7 - reserved 0 0000 reserved for SBCs with CAN transceiver 6 and 5 LINFD[1:0] LIN failure diagnosis 11 TXDL is clamped dominant 10 LIN is shorted to GND (dominant clamped) 01 LIN is shorted to VBAT (recessive clamped) 00 no failure 1 OK 0 fail; V3 is disabled due to an overload situation 1 reserved for SBCs with another voltage regulator 4 V3D V3 diagnosis 3 - reserved 2 V1D V1 diagnosis 1 and 0 - reserved 1 OK; V1 always above VUV(VFI) since last read access 0 fail; V1 was below VUV(VFI) since last read access; bit is set again with read access 00 reserved for SBCs with CAN transceiver 6.12.6 Interrupt Enable register and Interrupt Enable Feedback register These registers allow setting, clearing and reading back the interrupt enable bits of the SBC. Table 8. Interrupt Enable and Interrupt Enable Feedback register bit description Bit Symbol Description Value Function 15 and 14 A1, A0 register address 01 select the Interrupt Enable register 13 RRS Read Register Select 12 11 10 RO WTIE OTIE Read Only Watchdog Time-out Interrupt Enable[1] Over-Temperature Interrupt Enable 1 read the Interrupt register 0 read the Interrupt Enable Feedback register 1 read the register selected by RRS without writing to Interrupt Enable register 0 read the register selected by RRS and write to Interrupt Enable register 1 a watchdog overflow during Standby causes an interrupt instead of a reset event (interrupt based cyclic wake-up feature) 0 no interrupt forced on watchdog overflow; a reset is forced instead 1 exceeding or dropping below the temperature warning limit causes an interrupt 0 no interrupt forced 9 - reserved 0 reserved for SBCs with CAN transceiver 8 SPIFIE SPI clock count Failure Interrupt Enable 1 wrong number of CLK cycles (more than, or less than 16) forces an interrupt; from Start-up mode and Restart mode a reset is performed instead of an interrupt 0 no interrupt forced; SPI access is ignored if the number of cycles does not equal 16 UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 30 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip Table 8. Interrupt Enable and Interrupt Enable Feedback register bit description …continued Bit Symbol Description Value Function 7 BATFIE BAT Failure Interrupt Enable 1 falling edge at SENSE forces an interrupt 0 no interrupt forced 6 VFIE Voltage Failure Interrupt 1 Enable 0 clearing of V1D or V3D forces an interrupt 5 - reserved 0 reserved for SBCs with CAN transceiver 4 LINFIE LIN Failure Interrupt Enable 1 any change of the LIN Failure status bits forces an interrupt 0 no interrupt forced WAKE Interrupt Enable[2] 1 a negative edge at pin WAKE generates an interrupt in Normal mode, Flash mode or Standby mode 0 a negative edge at pin WAKE generates a reset in Standby mode; no interrupt in any other mode 1 a watchdog restart during watchdog OFF generates an interrupt 0 no interrupt forced 3 WIE 2 WDRIE Watchdog Restart Interrupt Enable no interrupt forced 1 - reserved 0 reserved for SBCs with CAN transceiver 0 LINIE LIN Interrupt Enable 1 LIN-bus event results in a wake-up interrupt in Standby mode and in Normal or Flash mode (unless LIN is in Active mode already) 0 LIN-bus event results in a reset in Standby mode; no interrupt in any other mode [1] This bit is cleared automatically upon each overflow event. It has to be set in software each time the interrupt behavior is required (fail-safe behavior). [2] WEN (in the System Configuration register) has to be set to activate the WAKE port function globally. 6.12.7 Interrupt register The Interrupt register allows the cause of an interrupt event to be read. The register is cleared upon a read access and upon any reset event. Hardware ensures that no interrupt event is lost in case there is a new interrupt forced while reading the register. After reading the Interrupt register pin INTN is released for tINTN to guarantee an edge event at pin INTN. The interrupts can be classified into two groups: • Timing critical interrupts which require immediate reaction (SPI clock count failure which needs a new SPI command to be resent immediately, and a BAT failure which needs critical data to be saved immediately into the nonvolatile memory) • Interrupts which do not require an immediate reaction (overtemperature and LIN failures, V1 and V3 failures and the wake-ups via LIN and WAKE. These interrupts will be signalled in Normal mode to the microcontroller once per watchdog period (maximum); this prevents overloading the microcontroller with unexpected interrupt events (e.g. a chattering LIN failure). However, these interrupts are reflected in the Interrupt register UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 31 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip Table 9. Interrupt register bit description Bit Symbol Description Value Function 15 and 14 A1, A0 register address 01 read Interrupt register 13 RRS Read Register Select 1 12 RO Read Only 1 read the Interrupt register without writing to the Interrupt Enable register 0 read the Interrupt register and write to the Interrupt Enable register 1 a watchdog overflow during Standby mode has caused an interrupt (interrupt-based cyclic wake-up feature) 0 no interrupt OverTemperature Interrupt 1 the temperature warning status (TWS) has changed 0 no interrupt 11 10 WTI OTI Watchdog Time-out Interrupt 9 - reserved 0 reserved for SBCs with CAN transceiver 8 SPIFI SPI clock count Failure Interrupt 1 wrong number of CLK cycles (more than, or less than 16) during SPI access 0 no interrupt; SPI access is ignored if the number of CLK cycles does not equal 16 1 falling edge at pin SENSE has forced an interrupt 0 no interrupt 7 BATFI BAT Failure Interrupt 6 VFI Voltage Failure Interrupt 1 5 - reserved 4 LINFI LIN Failure Interrupt 3 2 WI WDRI Wake-up Interrupt Watchdog Restart Interrupt 1 - reserved 0 LINI LIN Wake-up Interrupt V1D or V3D has been cleared 0 no interrupt 0 reserved for SBCs with CAN transceiver 1 LIN failure status has changed 0 no interrupt 1 a negative edge at pin WAKE has been detected 0 no interrupt 1 A watchdog restart during watchdog OFF has caused an interrupt 0 no interrupt 0 reserved for SBCs with CAN transceiver 1 LIN wake-up event has caused an interrupt 0 no interrupt 6.12.8 System Configuration register and System Configuration Feedback register These registers allow configuration of the behavior of the SBC, and allow the settings to be read back. Table 10. System Configuration and System Configuration Feedback register bit description Bit Symbol Description Value Function 15 and 14 A1, A0 register address 10 select System Configuration register 13 RRS Read Register Select 1 read the General Purpose Feedback register 0 0 read the System Configuration Feedback register UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 32 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip Table 10. System Configuration and System Configuration Feedback register bit description …continued Bit Symbol Description Value Function 12 RO Read Only 1 read register selected by RRS without writing to System Configuration register 0 read register selected by RRS and write to System Configuration register 11 and 10 - reserved 00 reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit 9 - reserved 0 reserved for SBCs with CAN transceiver Reset Length Control 1[1] tRSTNL long reset lengthening time selected 0 tRSTNL short reset lengthening time selected 11 Cyclic mode 2; tw(CS) long period; see Figure 13 10 Cyclic mode 1; tw(CS) short period; see Figure 13 01 continuously ON 00 OFF 8 RLC 7 and 6 V3C[1:0] V3 Control 5 - reserved 0 reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit 4 V1CMC V1 Current Monitor Control 1 an increasing V1 current causes a reset if the watchdog was disabled in Standby mode 0 an increasing V1 current only reactivates the watchdog in Standby mode 1 WAKE pin enabled 0 WAKE pin disabled 1 Wake mode cyclic sample 0 Wake mode continuous sample 3 WEN 2 WSC 1 ILEN 0 ILC Wake Enable[2] Wake Sample Control INH/LIMP Enable INH/LIMP Control 1 INH/LIMP pin active (See ILC bit) 0 INH/LIMP pin floating 1 INH/LIMP pin HIGH if ILEN bit is set 0 INH/LIMP pin LOW if ILEN bit is set [1] RLC is set automatically with entering Restart mode or Fail-safe mode. This guarantees a safe reset period in case of serious failure situations. External reset spikes are lengthened by the SBC until the programmed reset length is reached. [2] If WEN is not set, the WAKE port is completely disabled. There is no change of the bits EWS and WLS within the System Status register. 6.12.9 Physical Layer Control register and Physical Layer Control Feedback register These registers allow configuration of the LIN transceiver of the SBC and allow the settings to be read back. Table 11. Bit Physical Layer Control and Physical Layer Control Feedback register bit description Symbol Description Value Function 15 and 14 A1, A0 register address 11 select Physical Layer Control register 13 RRS Read Register Select 1 read the General Purpose Feedback register 1 0 read the Physical Layer Control Feedback register UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 33 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip Table 11. Physical Layer Control and Physical Layer Control Feedback register bit description …continued Bit Symbol Description Value Function 12 RO Read Only 1 read the register selected by RRS without writing to the Physical Layer Control register 0 read the register selected by RRS and write to Physical Layer Control register 11 to 5 - reserved 000 0000 reserved for SBCs with CAN transceiver 4 LMC LIN Mode Control 1 LIN Active mode (in Normal mode and Flash mode only) 0 LIN Active mode disabled 3 LSC 2 LIN Slope Control LDC LIN Driver Control 1 up to 10.4 kbit/s (low slope) 0 up to 20 kbit/s (normal) 1 increased LIN driver current capability 0 LIN driver in conformance with the LIN 2.0 standard 1 - reserved 0 reserved for SBCs with CAN transceiver 0 LTC LIN Transmitter Control[1] 1 LIN transmitter is disabled 0 LIN transmitter is enabled [1] In case of an RXDL / TXDL interfacing failure the LIN transmitter is disabled without setting LTC. Recovery from such a failure is automatic when LIN communication (with correct interfacing levels) is received. Manual recovery is also possible by setting and clearing the LTC bit under software control. 6.12.10 Special Mode register and Special Mode Feedback register These registers allow configuration of global SBC parameters during start-up of a system and allow the settings to be read back. Table 12. Special Mode register and Special Mode Feedback register bit description Bit Symbol Description Value Function 15 and 14 A1, A0 register address 01 select Special Mode register 13 RRS Read Register Select 0 read the Interrupt Enable Feedback register 1 read the Special Mode Feedback register 12 RO Read Only 1 read the register selected by RRS without writing to the Special Mode register 0 read the register selected by RRS and write to the Special Mode register 11 and 10 - reserved 0 reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit 9 ISDM Initialize Software Development Mode[1] 1 initialization of software development mode 0 normal watchdog interrupt, reset monitoring and fail-safe behavior 8 - reserved 0 reserved for SBCs with CAN transceiver 7 - reserved 0 reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit 6 and 5 WDPRE[1:0] Watchdog Prescaler 00 watchdog prescale factor 1 01 watchdog prescale factor 1.5 10 watchdog prescale factor 2.5 11 watchdog prescale factor 3.5 UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 34 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip Table 12. Special Mode register and Special Mode Feedback register bit description …continued Bit Symbol Description Value Function 4 and 3 V1RTHC[1:0] V1 Reset Threshold Control 11 V1 reset threshold = 0.9 × VV1(nom) 10 V1 reset threshold = 0.7 × VV1(nom) 01 V1 reset threshold = 0.8 × VV1(nom) 00 V1 reset threshold = 0.9 × VV1(nom) 000 reserved for future use; should remain cleared to ensure compatibility with future functions which might use this bit 2 to 0 [1] - reserved See Section 6.13.1. 6.12.11 General Purpose registers and General Purpose Feedback registers The UJA1069 offers two 12-bit General Purpose registers (and accompanying General Purpose Feedback registers) with no predefined bit definition. These registers can be used by the microcontroller for advanced system diagnosis or for storing critical system status information outside the microcontroller. After Power-up General Purpose register 0 will contain a ‘Device Identification Code’ consisting of the SBC type and SBC version. This code is available until it is overwritten by the microcontroller (as indicated by the DIC bit). Table 13. General Purpose register 0 and General Purpose Feedback register 0 bit description Bit Symbol Description Value Function 15, 14 A1, A0 register address 10 read the General Purpose Feedback register 0 13 RRS Read Register Select 12 RO 11 DIC 10 to 0 GP0[10:0] 1 read the General Purpose Feedback register 0 0 read the System Configuration Feedback register 1 read the register selected by RRS without writing to the General Purpose register 0 0 read the register selected by RRS and write to the General Purpose register 0 Device Identification Control[1] 1 General Purpose register 0 contains user-defined bits 0 General Purpose register 0 contains the Device Identification Code General Purpose bits[2] 1 user-defined 0 user-defined Read Only [1] The Device Identification Control bit is cleared during power-up of the SBC, indicating that General Purpose register 0 is loaded with the Device Identification Code. Any write access to General Purpose register 0 will set the DIC bit, regardless of the value written to DIC. [2] During power-up the General Purpose register 0 is loaded with a ‘Device Identification Code’ consisting of the SBC type and SBC version, and the DIC bit is cleared. Table 14. General Purpose register 1 and General Purpose Feedback register 1 bit description Bit Symbol Description Value Function 15 and 14 A1, A0 register address 11 select General Purpose register 1 13 RRS Read Register Select 1 read the General Purpose Feedback register 1 0 read the Physical Layer Control Feedback register UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 35 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip Table 14. General Purpose register 1 and General Purpose Feedback register 1 bit description …continued Bit Symbol Description Value Function 12 RO Read Only 1 read the register selected by RRS without writing to the General Purpose register 1 0 read the register selected by RRS and write to the General Purpose register 1 user-defined 0 user-defined 11 to 0 GP1[11:0] General Purpose bits 6.12.12 Register configurations at reset At Power-on, Start-up and Restart mode the setting of the SBC registers is predefined. Table 15. System Status register: status at reset Symbol Name Power-on Start-up [1] Restart [1] RSS Reset Source Status 0000 (power-on reset) any value except 1100 0000 or 0010 or 1100 or 1110 LWS LIN Wake-up Status 0 (no LIN wake-up) 1 if reset is caused by a LIN wake-up, otherwise no change no change EWS Edge Wake-up Status 0 (no edge detected) 1 if reset is caused by a wake-up via pin WAKE, otherwise no change no change WLS WAKE Level Status actual status actual status actual status TWS Temperature Warning Status 0 (no warning) actual status actual status SDMS Software Development Mode Status actual status actual status actual status ENS Enable Status 0 (EN = LOW) 0 (EN = LOW) 0 (EN = LOW) PWONS Power-on Status 1 (power-on reset) no change no change Start-up Restart [1] Depends on history. Table 16. Symbol System Diagnosis register: status at reset Name Power-on LINFD LIN Failure Diagnosis 00 (no failure) actual status actual status V3D V3 Diagnosis 1 (OK) actual status actual status V1D V1 Diagnosis 0 (fail) actual status actual status Table 17. Interrupt Enable register and Interrupt Enable Feedback register: status at reset Symbol Name Power-on Start-up Restart All all bits 0 (interrupt disabled) no change no change Table 18. Interrupt register: status at reset Symbol Name Power-on Start-up Restart All all bits 0 (no interrupt) 0 (no interrupt) 0 (no interrupt) UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 36 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip Table 19. System Configuration register and System Configuration Feedback register: status at reset Symbol Name Power-on Start-up Restart Fail-Safe RLC Reset Length Control 0 (short) no change 1 (long) 1 (long) V3C V3 Control 00 (off) no change no change no change V1CMC V1 Current Monitor Control 0 (watchdog restart) no change no change no change WEN Wake Enable 1 (enabled) no change no change no change WSC Wake Sample Control 0 (control) no change no change no change ILEN INH/LIMP Enable 0 (floating) 0 (floating) if ILC = 1, 1 (active) see Figure 12 if ILC = 1, otherwise no change otherwise no change ILC INH/LIMP Control 0 (LOW) no change Table 20. no change 0 (LOW) Physical Layer Control register and Physical Layer Control Feedback register: status at reset Symbol Name Power-on Start-up Restart Fail-Safe LMC LIN Mode Control 0 (Active mode disabled) no change no change no change LSC LIN Slope Control 0 (normal) no change no change no change LDC LIN Driver Control 0 (LIN 2.0) no change no change no change LTC LIN Transmitter Control 0 (on) no change no change no change Table 21. Special Mode register: status at reset Symbol Name Power-on Start-up Restart ISDM Initialize Software Development Mode 0 (no) no change no change WDPRE Watchdog Prescale Factor 00 (factor 1) no change no change V1RTHC V1 Reset Threshold Control 00 (90 %) no change 00 (90 %) Table 22. General Purpose register 0 and General Purpose Feedback register 0: status at reset Symbol Name Power-on Start-up Restart DIC Device Identification Control 0 (Device ID) no change no change GP0[10:7] general purpose bits 10 to 7 (version) Mask version no change no change GP0[6:0] general purpose bits 6 to 0 (SBC type) 000 1001 (UJA1069) no change no change Table 23. General Purpose register 1 and General Purpose Feedback register 1: status at reset Symbol Name Power-on Start-up Restart GP1[11:0] general purpose bits 11 to 0 0000 0000 0000 no change no change UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 37 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 6.13 Test modes 6.13.1 Software development mode The Software development mode is intended to support software developers in writing and pretesting application software without having to work around watchdog triggering and without unwanted jumps to Fail-safe mode. In Software development mode the following events do not force a system reset: • • • • Watchdog overflow in Normal mode Watchdog window miss Interrupt time-out Elapsed start-up time However, in case of a watchdog trigger failure the reset source information is still provided in the System Status register as if there was a real reset event. The exclusion of watchdog related resets allows simplified software testing, because possible problems in the watchdog triggering can be indicated by interrupts instead of resets. The SDM bit does not affect the watchdog behavior in Standby and Sleep mode. This allows the cyclic wake-up behavior to be evaluated during Standby and Sleep mode of the SBC. All transitions to Fail-safe mode are disabled. This allows working with an external emulator that clamps the reset line LOW in debugging mode. A V1 undervoltage of more than tV1(CLT) is the only exception that results in entering Fail-safe mode (to protect the SBC). Transitions from Start-up mode to Restart mode are still possible. There are two possibilities to enter Software development mode. One is by setting the ISDM bit via the Special Mode register; possible only once after a first battery connection while the SBC is in Start-up mode. The second possibility to enter Software development mode is by applying the correct Vth(TEST) input voltage at pin TEST before the battery is applied to pin BAT42. To stay in Software development mode the SDM bit in the Mode register has to be set with each Mode register access (i.e. watchdog triggering) regardless of how Software development mode was entered. The Software development mode can be exited at any time by clearing the SDM bit in the Mode register. Reentering the Software development mode is only possible by reconnecting the battery supply (pin BAT42), thereby forcing a new power-on reset. UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 38 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 6.13.2 Forced normal mode For system evaluation purposes the UJA1069 offers the Forced normal mode. This mode is strictly for evaluation purposes only. In this mode the characteristics as defined in Section 9 and Section 10 cannot be guaranteed. In Forced normal mode the SBC behaves as follows: • • • • • • SPI access (writing and reading) is blocked Watchdog disabled Interrupt monitoring disabled Reset monitoring disabled Reset lengthening disabled All transitions to Fail-safe mode are disabled, except a V1 undervoltage for more than tV1(CLT) • V1 is started with the long reset time tRSTNL. In case of a V1 undervoltage, a reset is performed until V1 is restored (normal behavior), and the SBC stays in Forced normal mode; in case of an overload at V1 > tV1(CLT) Fail-safe mode is entered • • • • • V3 is on; overload protection active LIN is in Active mode and cannot switch to Off-line mode INH/LIMP pin is HIGH SYSINH is HIGH EN pin at same level as RSTN pin Forced normal mode is activated by applying the correct Vth(TEST) input voltage at the TEST pin during first battery connection. UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 39 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 7. Limiting values Table 24. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND. Symbol Parameter VBAT42 BAT42 supply voltage VBAT14 BAT14 supply voltage Conditions Min Max Unit −0.3 +60 V - +60 V continuous −0.3 +33 V load dump; t ≤ 500 ms - +45 V V1 −0.3 +5.5 V V3 and SYSINH −1.5 VBAT42 + 0.3 V INH/LIMP −0.3 VBAT42 + 0.3 V SENSE −0.3 VBAT42 + 1.2 V WAKE −1.5 +60 V −60 +60 V TXDL, RXDL, SDO, SDI, SCK, SCS, RSTN, INTN and EN −0.3 VV1 + 0.3 V TEST −0.3 +15 V −150 +100 V load dump; t ≤ 500 ms VDC(n) VBAT42 ≥ VBAT14 − 1 V DC voltage on pins LIN and RTLIN Vtrt transient voltage at pin LIN IWAKE DC current at pin WAKE Tstg storage temperature Tamb ambient temperature Tvj VESD with respect to any other pin in accordance with ISO 7637-3 [1] virtual junction temperature [2] electrostatic discharge voltage [3] HBM at pins LIN, RTLIN, WAKE, BAT42, V3, SENSE; with respect to GND [4][5] at any other pin MM; at any pin [6] −15 - mA −55 +150 °C −40 +125 °C −40 +150 °C −8.0 +8.0 kV −2.0 +2.0 kV −200 +200 V [1] Only relevant if VWAKE < VGND − 0.3 V; current will flow into pin GND. [2] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + Pd × Rth(vj-amb), where Rth(vj-amb) is a fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (Pd) and ambient temperature (Tamb). [3] Human Body Model (HBM): CHBM = 100 pF; RHBM = 1.5 kΩ. [4] Only applies for pin BAT42 if CBAT42 (connected between pin BAT42 and GND) ≥ 10 nF; otherwise VESD = ±4 kV for pin BAT42. [5] ESD performance according to IEC 61000-4-2 (CIEC = 150 pF, RIEC = 330 Ω) of pins LIN, RTLIN, WAKE and BAT42 with respect to GND was verified by an external test house. The following results were obtained: a) Equal or better than ±4 kV (unaided) b) Equal or better than ±20 kV for pin LIN (using external ESD protection: NXP Semiconductors PESD1LIN diode). [6] Machine Model (MM): CMM = 200 pF; LMM = 0.75 µH; RMM = 10 Ω. UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 40 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 8. Thermal characteristics V1 dissipation V3 dissipation other dissipation Tvj 6 K/W 23 K/W 6 K/W 6 K/W Tcase(heat sink) Rth(c-a) Tamb 001aad671 Fig 15. Thermal model of the HTSSOP32 package V1 dissipation V3 dissipation other dissipation Tvj 6 K/W 17 K/W 6 K/W 6 K/W Tcase(heat sink) Rth(c-a) Tamb 001aae136 Fig 16. Thermal model of the HTSSOP24 package UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 41 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 9. Static characteristics Table 25. Static characteristics Tvj = −40 °C to +150 °C, VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42 ≥ VBAT14 − 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC.[1] Symbol Parameter Conditions Min Typ Max Unit BAT42 supply current V1 and V3 off; LIN in Off-line mode; OTIE = BATFIE = 0; ISYSINH = IWAKE = IRTLIN = ILIN = 0 mA VBAT42 = 8.1 V to 52 V - 50 70 µA VBAT42 = 5.5 V to 8.1 V - 70 93 µA V1 on; ISYSINH = 0 mA - 53 76 µA Supply; pin BAT42 IBAT42 IBAT42(add) additional BAT42 supply current V3 in Cyclic mode; IV3 = 0 mA - 0 1 µA V3 continuously on; IV3 = 0 mA - 30 50 µA Tvj warning enabled; OTIE = 1 - 20 40 µA SENSE enabled; BATFIE = 1 - 2 7 µA LIN in Active mode; LMC = 1; VTXDL = VV1; IRTLIN = ILIN = 0 mA - 650 1300 µA VBAT42 = 12 V - 1.5 5 mA VBAT42 = 27 V - 3 10 mA 4.45 - 5 V 4.75 - 5.5 V LIN in Active mode; LMC = 1; VTXDL = 0 V (t < tLIN(dom)(det)); IRTLIN = ILIN = 0 mA VPOR(BAT42) BAT42 voltage level for power-on reset status bit change for setting PWONS PWONS = 0; VBAT42 falling for clearing PWONS PWONS = 1; VBAT42 rising Supply; pin BAT14 IBAT14 BAT14 supply current V1 off; LIN in Off-line mode; ILEN = 0; IINH/LIMP = 0 mA - 2 5 µA IBAT14(add) additional BAT14 supply current V1 on; IV1 = 0 mA - 200 300 µA V1 on; IV1 = 0 mA; VBAT14 = 12 V - 150 200 µA INH/LIMP enabled; ILEN = 1; IINH/LIMP = 0 mA - 1 2 µA for normal output current capability at V1 9 - 27 V for high output current capability at V1 6 - 8 V VBAT14 BAT14 voltage level UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 42 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip Table 25. Static characteristics …continued Tvj = −40 °C to +150 °C, VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42 ≥ VBAT14 − 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC.[1] Symbol Parameter Conditions Min Typ Max Unit Battery supply monitor input; pin SENSE Vth(SENSE) IIH(SENSE) input threshold low battery voltage detection 1 2.5 3 V release 1.7 - 4 V HIGH-level input current Normal mode; BATFIE = 1 20 50 100 µA Standby mode; BATFIE = 1 5 10 20 µA Normal mode or Standby mode; BATFIE = 0 - 0.2 2 µA VBAT14 = 5.5 V to 18 V; IV1 = −120 mA to −5 mA; Tj = 25 °C VV1(nom) − 0.1 VV1(nom) VV1(nom) + 0.1 V VBAT14 = 14 V; IV1 = −5 mA; Tj = 25 °C VV1(nom) − 0.025 VV1(nom) VV1(nom) + 0.025 V supply voltage regulation VBAT14 = 9 V to 16 V; IV1 = −5 mA; Tj = 25 °C - 1 25 mV load regulation VBAT14 = 14 V; IV1 = −50 mA to −5 mA; Tj = 25 °C - 5 25 mV voltage drift with temperature VBAT14 = 14 V; IV1 = −5 mA; Tj = −40 °C to +150 °C - - 200 ppm/K undervoltage detection and reset activation level VBAT14 = 14 V; V1RTHC[1:0] = 00 or 11 0.90 × VV1(nom) 0.92 × VV1(nom) 0.95 × VV1(nom) V VBAT14 = 14 V; V1RTHC[1:0] = 01 0.80 × VV1(nom) 0.82 × VV1(nom) 0.85 × VV1(nom) V VBAT14 = 14 V; V1RTHC[1:0] = 10 0.70 × VV1(nom) 0.72 × VV1(nom) 0.75 × VV1(nom) V VBAT14 = 14 V; V1RTHC[1:0] = 00 or 11 - 0.94 × VV1(nom) - V VBAT14 = 14 V; V1RTHC[1:0] = 01 - 0.84 × VV1(nom) - V VBAT14 = 14 V; V1RTHC[1:0] = 10 - 0.74 × VV1(nom) - V VBAT14 = 14 V; VFIE = 1 0.90 × VV1(nom) 0.93 × VV1(nom) 0.97 × VV1(nom) V Voltage source; pin V1; see also Figure 17 to Figure 23 Vo(V1) ∆VV1 Vdet(UV)(V1) Vrel(UV)(V1) output voltage undervoltage detection release level [2] VUV(VFI) undervoltage level for generating a VFI interrupt IthH(V1) undercurrent threshold for watchdog enable −10 −5 −2 mA IthL(V1) undercurrent threshold for watchdog disable −6 −3 −1.5 mA UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 43 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip Table 25. Static characteristics …continued Tvj = −40 °C to +150 °C, VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42 ≥ VBAT14 − 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC.[1] Symbol Parameter Conditions Min Typ Max Unit IV1 output current capability VBAT14 = 9 V to 27 V; δVV1 = 0.05 × VV1(nom) −200 −135 −120 mA VBAT14 = 9 V to 27 V; V1 shorted to GND −200 −110 - mA VBAT14 = 8 V to 9 V; δVV1 = 0.05 × VV1(nom) - - −120 mA VBAT14 = 5.5 V to 8 V; δVV1 = 0.05 × VV1(nom) - - −150 mA - 3 5 Ω Zds(on) regulator impedance VBAT14 = 4 V to 5 V between pins BAT14 and V1 Voltage source; pin V3 VBAT42-V3(drop) VBAT42 to VV3 voltage VBAT42 = 9 V to 52 V; drop IV3 = −20 mA - - 1.0 V Idet(OL)(V3) overload current detection threshold VBAT42 = 9 V to 52 V −165 - −60 mA IL leakage current VV3 = 0 V; V3C[1:0] = 00 - 0 5 µA VBAT42-SYSINH(drop) VBAT42 to VSYSINH voltage drop ISYSINH = −0.2 mA - 1.0 2.0 V IL VSYSINH = 0 V - - 5 µA IINH/LIMP = −10 µA; ILEN = ILC = 1 - 0.7 1.0 V IINH/LIMP = −200 µA; ILEN = ILC = 1 - 1.2 2.0 V System inhibit output; pin SYSINH leakage current Inhibit/limp-home output; pin INH/LIMP VBAT14-INH(drop) VBAT14 to VINH voltage drop Io(INH/LIMP) output current capability VINH/LIMP = 0.4 V; ILEN = 1; ILC = 0 0.8 - 4 mA IL leakage current VINH/LIMP = 0 V to VBAT14; ILEN = 0 - - 5 µA 2.0 3.3 5.2 V −25 - −1.3 µA V Wake input; pin WAKE Vth(WAKE) wake-up voltage threshold IWAKE(pu) pull-up input current VWAKE = 0 V Serial peripheral interface inputs; pins SDI, SCK and SCS VIH(th) HIGH-level input threshold voltage 0.7 × VV1 - VV1 + 0.3 VIL(th) LOW-level input threshold voltage −0.3 - +0.3 × VV1 V Rpd(SCK) pull-down resistor at pin SCK VSCK = 2 V; VV1 ≥ 2 V 50 130 400 kΩ Rpu(SCS) pull-up resistor at pin SCS VSCS = 1 V; VV1 ≥ 2 V 50 130 400 kΩ UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 44 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip Table 25. Static characteristics …continued Tvj = −40 °C to +150 °C, VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42 ≥ VBAT14 − 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC.[1] Symbol Parameter Conditions ISDI input leakage current VSDI = 0 V to VV1 at pin SDI Min Typ Max Unit −5 - +5 µA Serial peripheral interface data output; pin SDO IOH HIGH-level output current VSCS = 0 V; VO = VV1 − 0.4 V −50 - −1.6 mA IOL LOW-level output current VSCS = 0 V; VO = 0.4 V 1.6 - 20 mA IOL(off) OFF-state output leakage current VSCS = VV1; VO = 0 V to VV1 −5 - +5 µA Reset output with clamping detection; pin RSTN IOH HIGH-level output current VRSTN = 0.7 × VV1(nom) −1000 - −50 µA IOL LOW-level output current VRSTN = 0.9 V 1 - 5 mA VOL LOW-level output voltage VV1 = 1.5 V to 5.5 V; pull-up resistor to V1 ≥ 4 kΩ 0 - 0.2 × VV1 V VIH(th) HIGH-level input threshold voltage 0.7 × VV1 - VV1 + 0.3 V VIL(th) LOW-level input threshold voltage −0.3 - +0.3 × VV1 V Enable output; pin EN IOH HIGH-level output current VOH = VV1 − 0.4 V −20 - −1.6 mA IOL LOW-level output current VOL = 0.4 V 1.6 - 20 mA VOL LOW-level output voltage IOL = 20 µA; VV1 = 1.2 V 0 - 0.4 V VOL = 0.4 V 1.6 - 15 mA Interrupt output; pin INTN IOL LOW-level output current LIN transmit data input; pin TXDL VIL LOW level input voltage −0.3 - +0.3 × VV1 V VIH HIGH-level input voltage 0.7 × VV1 - VV1 + 0.3 V RTXDL(pu) TXDL pull-up resistor VTXDL = 0 V 5 12 25 kΩ LIN receive data output; pin RXDL IOH HIGH-level output current VRXDL = VV1 − 0.4 V −50 - −1.6 mA IOL LOW-level output current VRXDL = 0.4 V 1.6 - 20 mA UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 45 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip Table 25. Static characteristics …continued Tvj = −40 °C to +150 °C, VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42 ≥ VBAT14 − 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC.[1] Symbol Parameter Conditions Min Typ Max Unit 0 - 0.20 × VBAT42 V Active mode; VBAT42 = 7.6 V to 18 V; LDC = 1; t < tTXDL(dom)(dis); VTXDL = 0 V; ILIN = 40 mA 0.7 1.4 2.1 V VLIN = VBAT42; VTXDL = VV1 −10 0 +10 µA VBAT42 = 8 V; VLIN = 8 V to 18 V; VTXDL = VV1 −10 0 +10 µA LIN-bus line; pin LIN Vo(dom) ILIH LIN dominant output Active mode; voltage VBAT42 = 7 V to 18 V; LDC = 0; t < tTXDL(dom)(dis); VTXDL = 0 V; RBAT42-LIN = 500 Ω HIGH-level input leakage current ILIL LOW-level input leakage current VBAT42 = 12 V; VLIN = 0 V; VTXDL = VV1 −100 - - µA Io(sc) short-circuit output current Active mode; VLIN = VBAT42 = 12 V; VTXDL = 0 V; t < tTXDL(dom)(dis); LDC = 0 27 40 60 mA Active mode; VLIN = VBAT42 = 18 V; VTXDL = 0 V; t < tTXDL(dom)(dis); LDC = 0 40 60 90 mA Vth(dom) receiver dominant state VBAT42 = 7 V to 27 V - - 0.4 × VBAT42 V Vth(reces) receiver recessive state VBAT42 = 7 V to 27 V 0.6 × VBAT42 - - V Vth(hyst) receiver threshold voltage hysteresis VBAT42 = 7 V to 27 V 0.05 × VBAT42 - 0.175 × VBAT42 V Vth(cen) receiver threshold voltage center VBAT42 = 7 V to 27 V 0.475 × VBAT42 0.500 × VBAT42 0.525 × VBAT42 V Ci input capacitance - - 10 pF IL leakage current VBAT42 = 0 V −5 0 +5 µA VGND = VBAT42 = 12 V −10 0 +10 µA Active mode; IRTLIN = −10 µA; VBAT42 = 7 V to 27 V VBAT42 − 1.0 VBAT42 − 0.7 VBAT42 − 0.2 V Off-line mode; IRTLIN = −10 µA; VBAT42 = 7 V to 27 V VBAT42 − 1.2 VBAT42 − 1.0 - V Active mode; IRTLIN = −10 µA to −10 mA; VBAT42 = 7 V to 27 V - 0.65 2 V [2] VLIN = 0 V to 18 V LIN-bus termination resistor connection; pin RTLIN VRTLIN ∆VRTLIN RTLIN output voltage RTLIN load regulation UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 46 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip Table 25. Static characteristics …continued Tvj = −40 °C to +150 °C, VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42 ≥ VBAT14 − 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC.[1] Symbol Parameter Conditions Min Typ Max Unit IRTLIN(pu) RTLIN pull-up current Active mode; VRTLIN = VLIN = 0 V; t > tLIN(dom)(det) −150 −60 −35 µA Off-line mode; VRTLIN = VLIN = 0 V; t < tLIN(dom)(det) −150 −60 −35 µA Off-line mode; VRTLIN = VLIN = 0 V; t > tLIN(dom)(det) −10 0 +10 µA for entering Software development mode; Tj = 25 °C 1 5 8 V for entering Forced normal mode; Tj = 25 °C 2 10 13.5 V between pin TEST and GND 2 4 8 kΩ 160 175 190 °C ILL LOW-level leakage current TEST input; pin TEST Vth(TEST) R(pd)TEST input threshold voltage pull-down resistor Temperature detection Tj(warn) high junction temperature warning level [1] All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 °C ambient temperature on wafer level (pretesting). Cased products are 100 % tested at 25 °C ambient temperature (final testing). Both pretesting and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. [2] Not tested in production. UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 47 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 015aaa089 6 VV1 (V) 5 IV1 = −100 µA −50 mA −120 mA −250 mA 4 3 2 2 3 4 5 6 7 VBAT14 (V) a. Tj = 25 °C. 015aaa090 6 VV1 (V) 5 4 IV1 = −100 µA −50 mA −120 mA −250 mA 3 2 2 3 4 5 6 7 VBAT14 (V) b. Tj = 150 °C. Fig 17. V1 output voltage (dropout) as a function of battery voltage UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 48 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 015aaa091 10 Tj = +150 °C IBAT14 − IV1 (mA) Tj = −40 °C 8 +25 °C 6 +150 °C 4 +25 °C −40 °C VBAT14 = 8 V 2 0 0 −50 −100 −150 −200 −250 IV1 (mA) a. At Tj = −40 °C, +25 °C and +150 °C. 015aaa092 5 IBAT14 − IV1 (mA) 4 3 VBAT14 = 9 V to 27 V 2 1 0 0 −50 −100 −150 −200 −250 IV1 (mA) b. At Tj = −40 °C to +150 °C. Fig 18. V1 quiescent current as a function of output current UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 49 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 015aaa093 6 VV1 (V) 4 2 0 −40 0 −80 −120 −160 IV1 (mA) VBAT14 = 9 V to 27 V. Tj = 25 °C to 125 °C. Fig 19. V1 output voltage as a function of output current 015aaa094 160 PSRR (dB) VBAT14 = 14 V 120 Tj = 25 °C 14 V 150 °C 80 5.5 V 25 °C to 150 °C 5.5 V 150 °C 40 0 1 10 102 103 f (Hz) IV1 = −120 mA. Fig 20. V1 power supply ripple rejection as a function of frequency UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 50 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 001aaf250 16 200 ∆VV1 (mV) VBAT14 (V) VBAT14 12 100 ∆VV1 8 −100 500 4 0 100 200 300 0 400 t (µs) IV1 = −5 mA; C = 1 µF; ESR = 0.01 Ω; Tj = 25 °C. a. Line transient response 001aaf251 −75 400 ∆VV1 (mV) IV1 (mA) −25 200 IV1 ∆VV1 25 −200 500 75 0 100 200 300 0 400 t (µs) VBAT14 = 14 V; C = 1 µF; ESR = 0.01 Ω; Tj = 25 °C. b. Load transient response Fig 21. V1 transient response as a function of time UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 51 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 001aaf249 1 ESR (Ω) 10−1 stable operation area 10−2 unstable operation area 10−3 0 −40 −80 −120 IV1 (mA) Fig 22. V1 output stability related to ESR value of output capacitor UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 52 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip BAT42 VBAT 100 µF/ 0.1 Ω BAT14 Iload = 30 mA V1 SBC 100 nF 100 nF 47 µF/ 0.1 Ω Rload GND 001aaf572 a. Test circuit 015aaa095 6 VV1 (V) 4 VBAT = 8 V VBAT = 5.5 V 2 VBAT = 12 V 0 0 0.4 0.8 1.2 1.6 2.0 t (ms) b. Behavior at Tj = 25 °C 015aaa096 6 VV1 (V) VBAT = 8 V 4 VBAT = 5.5 V 2 VBAT = 12 V 0 0 0.4 0.8 1.2 1.6 2.0 t (ms) c. Behavior at Tj = 85 °C Fig 23. Switch-on behavior of VV1 UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 53 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 10. Dynamic characteristics Table 26. Dynamic characteristics Tvj = −40 °C to +150 °C; VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42 ≥ VBAT14 − 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC.[1] Symbol Parameter Conditions Min Typ Max Unit Serial peripheral interface timing; pins SCS, SCK, SDI and SDO (see Figure 24)[2] Tcyc clock cycle time 960 - - ns tlead enable lead time clock is low when SPI select falls 240 - - ns tlag enable lag time clock is low when SPI select rises 240 - - ns tSCKH clock HIGH time 480 - - ns tSCKL clock LOW time 480 - - ns tsu input data setup time 80 - - ns th input data hold time 400 - - ns tDOV output data valid time - - 400 ns tSSH SPI select HIGH time 480 - - ns LIN transceiver; pins LIN, TXDL and pin SDO; CL = 10 pF RXDL[3] δ1 duty cycle 1 Vth(reces)(max) = 0.744 × VBAT42; Vth(dom)(max) = 0.581 × VBAT42; LSC = 0; tbit = 50 µs; VBAT42 = 7 V to 18 V [4] 0.396 - - δ2 duty cycle 2 Vth(reces)(min) = 0.422 × VBAT42; Vth(dom)(min) = 0.284 × VBAT42; LSC = 0; tbit = 50 µs; VBAT42 = 7.6 V to 18 V [5] - - 0.581 δ3 duty cycle 3 Vth(reces)(max) = 0.778 × VBAT42; Vth(dom)(max) = 0.616 × VBAT42; LSC = 1; tbit = 96 µs; VBAT42 = 7 V to 18 V [4] 0.417 - - δ4 duty cycle 4 Vth(reces)(min) = 0.389 × VBAT42; Vth(dom)(min) = 0.251 × VBAT42; LSC = 1; tbit = 96 µs; VBAT42 = 7.6 V to 18 V [5] - - 0.590 tp(rx) propagation delay of receiver CRXDL = 20 pF - - 6 µs tp(rx)(sym) symmetry of receiver propagation delay rising edge with respect to falling edge; CRXDL = 20 pF −2 - +2 µs tBUS(LIN) minimum dominant time for Off-line mode wake-up of the LIN-transceiver 30 - 150 µs tLIN(dom)(det) continuously dominant Active mode; VLIN = 0 V clamped LIN-bus detection time 40 - 160 ms tLIN(dom)(rec) continuously dominant clamped LIN-bus recovery time 0.8 - 2.2 ms Active mode UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 54 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip Table 26. Dynamic characteristics …continued Tvj = −40 °C to +150 °C; VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42 ≥ VBAT14 − 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC.[1] Symbol Parameter Conditions tTXDL(dom)(dis) TXDL permanent dominant Active mode; VTXDL = 0 V disable time Min Typ Max Unit 20 - 80 ms Battery monitoring tBAT42(L) BAT42 LOW time for setting PWONS 5 - 20 µs tSENSE(L) BAT42 LOW time for setting BATFI 5 - 20 µs Start-up mode; V1 active 229 - 283 ms V3C[1:0] = 10; see Figure 13 14 - 18 ms V3C[1:0] = 11; see Figure 13 28 - 36 ms Power supply V1; pin V1 tV1(CLT) V1 clamped LOW time during ramp-up of V1 Power supply V3; pin V3 tw(CS) ton(CS) cyclic sense period cyclic sense on-time V3C[1:0] = 10; see Figure 13 345 - 423 µs V3C[1:0] = 11; see Figure 13 345 - 423 µs VBAT42 = 5 V to 27 V 5 - 120 µs Wake-up input; pin WAKE tWU(ipf) input port filter time VBAT42 = 27 V to 52 V 30 - 250 µs tsu(CS) cyclic sense sample setup time V3C[1:0] = 11 or 10; see Figure 13 310 - 390 µs tWD(ETP) earliest watchdog trigger point programmed Nominal Watchdog Period (NWP); Normal mode 0.45 × NWP - 0.55 × NWP tWD(LTP) latest watchdog trigger point programmed nominal watchdog period; Normal mode, Standby mode and Sleep mode 0.9 × NWP - 1.1 × NWP tWD(init) watchdog initializing period watchdog time-out in Start-up mode 229 - 283 ms Fail-safe mode; wake-up detected 1.3 1.5 1.7 s Watchdog Fail-safe mode tret retention time Reset output; pin RSTN tRSTN(CHT) clamped HIGH time, pin RSTN RSTN driven LOW internally but RSTN pin remains HIGH 115 - 141 ms tRSTN(CLT) clamped LOW time, pin RSTN RSTN driven HIGH internally but RSTN pin remains LOW 229 - 283 ms tRSTN(INT) interrupt monitoring time INTN = LOW 229 - 283 ms tRSTNL reset lengthening time after internal or external reset has been released; RLC = 0 0.9 - 1.1 ms after internal or external reset has been released; RLC =1 18 - 22 ms UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 55 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip Table 26. Dynamic characteristics …continued Tvj = −40 °C to +150 °C; VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42 ≥ VBAT14 − 1 V; unless otherwise specified. All voltages are defined with respect to ground. Positive currents flow into the IC.[1] Symbol Parameter Conditions Min Typ Max Unit after SPI has read out the Interrupt register 2 - - µs 460.8 512 563.2 kHz Interrupt output; pin INTN tINTN interrupt release Oscillator oscillator frequency fosc [1] All parameters are guaranteed over the virtual junction temperature range by design. Products are 100 % tested at 125 °C ambient temperature on wafer level (pretesting). Cased products are 100 % tested at 25 °C ambient temperature (final testing). Both pretesting and final testing use correlated test conditions to cover the specified temperature and power supply voltage range. [2] SPI timing is guaranteed for VBAT42 voltages down to 5 V. For VBAT42 voltages down to 4.5 V the guaranteed SPI timing values double, so at these lower voltages a lower maximum SPI communication speed must be observed. [3] tbit = selected bit time, depends on LSC bit; 50 µs or 96 µs (20 kbit/s or 10.4 kbit/s respectively); bus load conditions (R1/R2/C1): 1 kΩ/1 kΩ/10 nF; 1 kΩ/2 kΩ/6.8 nF; 1 kΩ/open/1 nF; see Figure 25 and Figure 26. [4] t bus ( rec ) ( min ) δ1, δ3 = ------------------------------2 × t bit [5] t bus ( rec ) ( max ) δ2, δ4 = ------------------------------2 × t bit SCS tlead tlag Tcyc tSCKH tSCKL tsu th tSSH SCK SDI MSB X LSB X tDOV floating SDO floating X MSB LSB 001aaa405 Fig 24. SPI timing UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 56 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip BAT42 RXDL RTLIN R1 SBC 20 pF TXDL R2 LIN GND C1 001aad179 Fig 25. Timing test circuit for LIN transceiver tbit tbit tbit VTXDL tbus(dom)(max) tbus(rec)(min) VBAT42 Vth(reces)(max) Vth(dom)(max) LIN BUS signal Vth(reces)(min) Vth(dom)(min) tbus(dom)(min) receiving node 1 thresholds of receiving node 2 tbus(rec)(max) VRXDL1 tp(rx)f receiving node 2 thresholds of receiving node 1 tp(rx)r VRXDL2 tp(rx)r tp(rx)f 001aaa346 Fig 26. Timing diagram LIN transceiver 11. Test information Immunity against automotive transients (malfunction and damage) in accordance with LIN EMC Test Specification / Version 1.0; August 1, 2004. 11.1 Quality information This product has been qualified to the appropriate Automotive Electronics Council (AEC) standard Q100 or Q101 and is suitable for use in automotive applications. UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 57 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 12. Package outline HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad SOT549-1 E D A X c y HE exposed die pad side v M A Dh Z 32 17 A2 Eh (A3) A A1 pin 1 index θ Lp L detail X 16 1 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D(1) Dh E(2) Eh e HE L Lp v w y Z θ mm 1.1 0.15 0.05 0.95 0.85 0.25 0.30 0.19 0.20 0.09 11.1 10.9 5.1 4.9 6.2 6.0 3.6 3.4 0.65 8.3 7.9 1 0.75 0.50 0.2 0.1 0.1 0.78 0.48 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT549-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 03-04-07 05-11-02 MO-153 Fig 27. Package outline SOT549-1 (HTSSOP32) UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 58 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip HTSSOP24: plastic thermal enhanced thin shrink small outline package; 24 leads; body width 4.4 mm; lead pitch 0.65 mm; exposed die pad D SOT864-1 A E c y X exposed die pad HE v M A DH Z 13 24 (A 3) A2 Eh A A1 pin 1 index θ Lp detail X 1 L 12 e w bp M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max mm 1.1 A1 A2 0.15 0.95 0.05 0.80 A3 bp c D (1) Dh E (2) Eh e HE L Lp v w y Z θ 0.25 0.30 0.19 0.2 0.1 7.9 7.7 4.3 4.1 4.5 4.3 3.3 3.1 0.65 6.6 6.2 1 0.75 0.50 0.2 0.13 0.1 0.5 0.2 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT864-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-09-23 05-12-06 MO-153 Fig 28. Package outline SOT864-1 (HTSSOP24) UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 59 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 13.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 60 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 29) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 27 and 28 Table 27. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 28. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 29. UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 61 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 29. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Revision history Table 29. Revision history Document ID Release date Data sheet status Change notice Supersedes UJA1069_4 20091028 Product data sheet - UJA1069_3 Modifications: • • • • • • 3.3 V versions (UJA1069TW/3V3 and UJA1069TW24/3V3) discontinued 3.0 V versions (UJA1069TW/3V0 and UJA1069TW24/3V0) discontinued Table 24: table note section revised Section 6.2.5: text of third paragraph revised Table 10: text of bit 4, V1CMC, revised Figure 23: unit corrected UJA1069_3 20070910 Product data sheet - UJA1069_2 20070305 Preliminary data sheet - UJA1069_1 UJA1069_1 20051222 Objective data sheet - - UJA1069_4 Product data sheet UJA1069_2 © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 62 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] UJA1069_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 28 October 2009 63 of 64 UJA1069 NXP Semiconductors LIN fail-safe system basis chip 17. Contents 1 2 2.1 2.2 2.3 2.4 3 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.5 6.5.1 6.5.2 6.6 6.6.1 6.6.1.1 6.6.2 6.6.3 6.6.4 6.7 6.7.1 6.7.1.1 6.7.1.2 6.7.2 6.7.3 6.7.4 6.7.5 6.7.6 6.7.6.1 6.7.6.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . 2 Power management . . . . . . . . . . . . . . . . . . . . . 2 Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Fail-safe system controller . . . . . . . . . . . . . . . . 7 Start-up mode. . . . . . . . . . . . . . . . . . . . . . . . . . 9 Restart mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Fail-safe mode . . . . . . . . . . . . . . . . . . . . . . . . . 9 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 10 Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 On-chip oscillator . . . . . . . . . . . . . . . . . . . . . . 12 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Watchdog start-up behavior . . . . . . . . . . . . . . 13 Watchdog window behavior . . . . . . . . . . . . . . 13 Watchdog time-out behavior . . . . . . . . . . . . . . 14 Watchdog OFF behavior. . . . . . . . . . . . . . . . . 14 System reset. . . . . . . . . . . . . . . . . . . . . . . . . . 15 RSTN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 EN output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . 17 BAT14, BAT42 and SYSINH . . . . . . . . . . . . . . 17 SYSINH output . . . . . . . . . . . . . . . . . . . . . . . . 17 SENSE input. . . . . . . . . . . . . . . . . . . . . . . . . . 17 Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . 17 Switched battery output V3. . . . . . . . . . . . . . . 18 LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . 18 Mode control . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Off-line mode . . . . . . . . . . . . . . . . . . . . . . . . . 19 LIN wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Termination control . . . . . . . . . . . . . . . . . . . . . 20 LIN slope control. . . . . . . . . . . . . . . . . . . . . . . 20 LIN driver capability . . . . . . . . . . . . . . . . . . . . 21 Bus and TXDL failure detection . . . . . . . . . . . 21 TXDL dominant clamping . . . . . . . . . . . . . . . . 21 LIN dominant clamping . . . . . . . . . . . . . . . . . . 21 6.7.6.3 6.8 6.9 6.10 6.11 6.12 6.12.1 6.12.2 6.12.3 6.12.4 6.12.5 6.12.6 6.12.7 6.12.8 6.12.9 6.12.10 6.12.11 6.12.12 6.13 6.13.1 6.13.2 7 8 9 10 11 11.1 12 13 13.1 13.2 13.3 13.4 14 15 15.1 15.2 15.3 15.4 16 17 LIN recessive clamping . . . . . . . . . . . . . . . . . 21 Inhibit and limp-home output . . . . . . . . . . . . . 21 Wake-up input . . . . . . . . . . . . . . . . . . . . . . . . 22 Interrupt output. . . . . . . . . . . . . . . . . . . . . . . . 23 Temperature protection . . . . . . . . . . . . . . . . . 23 SPI interface. . . . . . . . . . . . . . . . . . . . . . . . . . 24 SPI register mapping . . . . . . . . . . . . . . . . . . . 25 Register overview. . . . . . . . . . . . . . . . . . . . . . 25 Mode register . . . . . . . . . . . . . . . . . . . . . . . . . 25 System Status register . . . . . . . . . . . . . . . . . . 28 System Diagnosis register . . . . . . . . . . . . . . . 29 Interrupt Enable register and Interrupt Enable Feedback register. . . . . . . . . . . . . . . . . . . . . . 30 Interrupt register. . . . . . . . . . . . . . . . . . . . . . . 31 System Configuration register and System Configuration Feedback register . . . . . . . . . . 32 Physical Layer Control register and Physical Layer Control Feedback register . . . . . . . . . . . . . . . 33 Special Mode register and Special Mode Feedback register. . . . . . . . . . . . . . . . . . . . . . 34 General Purpose registers and General Purpose Feedback registers. . . . . . . . . . . . . . . . . . . . . 35 Register configurations at reset . . . . . . . . . . . 36 Test modes. . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Software development mode . . . . . . . . . . . . . 38 Forced normal mode . . . . . . . . . . . . . . . . . . . 39 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 40 Thermal characteristics . . . . . . . . . . . . . . . . . 41 Static characteristics . . . . . . . . . . . . . . . . . . . 42 Dynamic characteristics . . . . . . . . . . . . . . . . . 54 Test information. . . . . . . . . . . . . . . . . . . . . . . . 57 Quality information . . . . . . . . . . . . . . . . . . . . . 57 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 58 Soldering of SMD packages . . . . . . . . . . . . . . 60 Introduction to soldering. . . . . . . . . . . . . . . . . 60 Wave and reflow soldering . . . . . . . . . . . . . . . 60 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 60 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 61 Revision history . . . . . . . . . . . . . . . . . . . . . . . 62 Legal information . . . . . . . . . . . . . . . . . . . . . . 63 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 63 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Contact information . . . . . . . . . . . . . . . . . . . . 63 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 28 October 2009 Document identifier: UJA1069_4