ETC VRS560

VRS550 / VRS560
VERSA
Datasheet Rev 1.1
VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU
VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
Datasheet Rev 1.1
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
Tel: (514) 871-2447
http://www.goalsemi.com
1
VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Feature Set
Overview
The VRS550 and the VRS560 are both low cost 8-bit
microcontrollers based on the standard 80C51
microcontroller family architecture. They are pin-to-pin
compatible and drop-in replacements for most 8051
MCUs. The VRS550 and VRS560 have 8kB and 16kB,
respectively of Flash memory. Both devices have 256
bytes of RAM memory.
The hardware features of these devices and their reprogrammability make them suitable for a wide range of
applications.
These VRS550 and VRS560 are both available in
PLCC-44 and QFP-44 packages in the Industrial
temperature range. The Flash memory can be
programmed using programmers available from Goal
Semiconductor or other 3rd party commercial
programmers.
General 80C51/80C52 pin compatible
12 clock periods per machine cycle
8k / 16k on-chip Flash memory
256 Bytes on-chip data RAM
32 I/O lines on four 8-bit ports
Full duplex serial port (UART)
3, 16-bit Timers/Counters
Watch Dog Timer
8-bit Unsigned Division / Multiply
BCD arithmetic
Direct and Indirect Addressing
Two levels of interrupt priority and nested interrupts
Power saving modes
Code protection function
Operates at a clock frequency of up to 25MHz
Low EMI (inhibit ALE)
Programming voltage: 12V
Industrial Temperature range (-40°C to +85°C)
5V and 3V versions available (see Ordering information.)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ADDRESS/
DATA BUS
7
P1.5
8k / 16k
FLASH
PORT 0
8
PORT 1
8
P0.3/AD3
P0.1/AD1
P0.0/AD0
P0.2/AD2
NC
VDD
P0.5/AD5
P0.7/AD7
#EA
VRS550 / VRS560
PLCC-44
NC
TXD/P3.1
NC
ALE
#INT0/P3.2
#PSEN
P2.7/A15
P2.6/A14
WATCHDOG
TIMER
P0.3/AD3
34
P2 .4/A12
P2.7/A15
P2.6/A14
33
23
22
P0.2/AD2
P2.2/A10
P0.0/AD0
VDD
P2.1/A9
P2.0/A8
VRS550 / VRS560
QFP-44
NC
T2/P1.0
NC
VSS
T2EX/P1.1
P1.2
XTAL1
XTAL2
44
#INT1/P3.3
TXD/P3.1
#INT0/P3.2
NC
RESET
RXD/P3.0
P1.7
P1.6
Tel: (514) 871-2447
#RD/P3.7
#WR/P3.6
T0/P3.4
T1/P3.5
12
11
1
P1.5
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
P2.4/A12
P2.3/A11
P0.1/AD1
P1.3
P1.4
P2.5/A13
P2.5/A13
P2 .3/A11
P2 .1/A9
P2.2/A10
ALE
29
#PSEN
NC
P2 .0/A8
VSS
P0.7/AD7
#EA
NC
POWER
CONTROL
P0.6/AD6
P0.4/AD4
TIMER 0
XTAL1
8
XTAL2
PORT 3
28
P0.5/AD5
2 INTERRUPT
INPUTS
17
18
#RD/P3 .7
8
P0.4/AD4
P0.6/AD6
RESET
#WR/P3.6
PORT 2
RESET
39
#INT1/P3.3
UART
TIMER 2
40
1
P1.7
T0/P3.4
T1/P3.5
TIMER 1
P1.2
6
P1.6
RXD/P3.0
256 bytes of
RAM
T2/P1.0
P1.3
P1.4
8051
PROCESSOR
T2EX/P1.1
FIGURE 2: VRS550 / VRS560 PLCC AND QFP PINOUT DIAGRAMS
FIGURE 1: VRS550 / VRS560 FUNCTIONAL DIAGRAM
http://www.goalsemi.com
2
VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Pin Descriptions for QFP-44
TABLE 1: PIN DESCRIPTIONS FOR QFP-44/
44
P1.4
I/O
Bit 4 of Port 1
P0.3/AD3
34
38
39
40
41
33
P2.5/A13
Bit 3 of Port 1
37
P2.7/A15
I/O
36
P2.6/A14
P1.3
35
23
22
P0.2/AD2
P0.1/AD1
P2.2/A10
P0.0/AD0
VDD
P2.1/A9
P2.0/A8
VRS550 / VRS560
QFP-44
NC
T2/P1.0
NC
VSS
T2EX/P1.1
P1.2
P1.3
P1.4
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
P2.4/A12
P2.3/A11
XTAL1
XTAL2
44
12
11
1
Tel: (514) 871-2447
#RD/P3.7
#WR/P3.6
T0/P3.4
T1/P3.5
23
43
34
ALE
22
42
33
#PSEN
21
32
TXD/P3.1
20
31
#INT1/P3.3
19
30
#INT0/P3.2
18
26
27
28
29
P0.7/AD7
14
15
16
17
25
#EA
13
24
NC
12
Function
Bit 6 of Port 2
Bit 14 of External Memory Address
Bit 7 of Port 2
Bit 15 of External Memory Address
Program Store Enable
Address Latch Enable
No Connect
External Access
Bit 7 Of Port 0
Data/Address Bit 7 of External Memory
Bit 6 of Port 0
Data/Address Bit 6 of External Memory
Bit 5 of Port 0
Data/Address Bit 5 of External Memory
Bit 4 of Port 0
Data/Address Bit 4 of External Memory
Bit 3 Of Port 0
Data/Address Bit 3 of External Memory
Bit 2 of Port 0
Data/Address Bit 2 of External Memory
Bit 1 of Port 0 & Data
Address Bit 1 of External Memory
Bit 0 Of Port 0 & Data
Address Bit 0 of External Memory
VCC
No Connect
Timer 2 Clock Out
Bit 0 of Port 1
Timer 2 Control
Bit 1 of Port 1
Bit 2 of Port 1
NC
11
I/O
I/O
O
I/O
O
O
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I
I/O
I/O
RXD/P3.0
10
Name
P2.6
A14
P2.7
A15
#PSEN
ALE
NC
#EA
P0.7
AD7
P0.6
AD6
P0.5
AD5
P0.4
AD4
P0.3
AD3
P0.2
AD2
P0. 1
AD1
P0.0
AD0
VDD
NC
T2
P1.0
T2EX
P1.1
P1.2
P0.5/AD5
9
Bit 5 of Port 1
Bit 6 of Port 1
Bit 7 of Port 1
Reset
Receive Data
Bit 0 of Port 3
No Connect
Transmit Data &
Bit 1 of Port 3
External Interrupt 0
Bit 2 of Port 3
External Interrupt 1
Bit 3 of Port 3
Timer 0
Bit 4 of Port 3
Timer 1 & 3
Bit 5 of Port
Ext. Memory Write
Bit 6 of Port 3
Ext. Memory Read
Bit 7 of Port 3
Oscillator/Crystal Output
Oscillator/Crystal In
Ground
No Connect
Bit 0 of Port 2
Bit 8 of External Memory Address
Bit 1 of Port 2
Bit 9 of External Memory Address
Bit 2 of Port 2
Bit 10 of External Memory Address
Bit 3 of Port 2 &
Bit 11 of External Memory Address
Bit 4 of Port 2
Bit 12 of External Memory Address
Bit 5 of Port 2
Bit 13 of External Memory Address
P0.6/AD6
8
I/O
I/O
I/O
I
I
I/O
O
I/O
I
I/O
I
I/O
I
I/O
I
I/O
O
I/O
O
I/O
O
I
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
P1.7
7
P1.5
P1.6
P1.7
RES
RXD
P3.0
NC
TXD
P3.1
#INT0
P3.2
#INT1
P3.3
T0
P3.4
T1
P3.5
#WR
P3.6
#RD
P3.7
XTAL2
XTAL1
VSS
NC
P2.0
A8
P2.1
A9
P2.2
A10
P2.3
A11
P2.4
A12
P2.5
A13
QFP
- 44
RESET
6
Function
P1.5
5
I/O
P1.6
1
2
3
4
Name
P0.4/AD4
QFP
- 44
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3
VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Pin Descriptions for PLCC-44
TABLE 2: PIN DESCRIPTIONS FOR PLCC-44
16
17
18
19
20
21
22
23
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
I/O
I/O
AD6
I/O
P0.5
I/O
AD5
I/O
P0.4
I/O
AD4
I/O
P0.3
I/O
AD3
I/O
P0.2
I/O
AD2
I/O
P0. 1
AD1
P0.0
AD0
VDD
I/O
I/O
I/O
I/O
-
P1.4
44
AD7
P0.6
P1.5
7
Bit 0 of Port 2
Bit 8 of External Memory Address
Bit 1 of Port 2
Bit 9 of External Memory Address
Bit 2 of Port 2
Bit 10 of External Memory Address
Bit 3 of Port 2 &
Bit 11 of External Memory Address
Bit 4 of Port 2
Bit 12 of External Memory Address
Bit 5 of Port 2
Bit 13 of External Memory Address
Bit 6 of Port 2
Bit 14 of External Memory Address
Bit 7 of Port 2
Bit 15 of External Memory Address
Program Store Enable
Address Latch Enable
No Connect
External Access
Bit 7 Of Port 0
Data/Address Bit 7 of External
Memory
Bit 6 of Port 0
Data/Address Bit 6 of External
Memory
Bit 5 of Port 0
Data/Address Bit 5 of External
Memory
Bit 4 of Port 0
Data/Address Bit 4 of External
Memory
Bit 3 Of Port 0
Data/Address Bit 3 of External
Memory
Bit 2 of Port 0
Data/Address Bit 2 of External
Memory
Bit 1 of Port 0 & Data
Address Bit 1 of External Memory
Bit 0 Of Port 0 & Data
Address Bit 0 of External Memory
VCC
6
P0.2/AD2
15
27
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
O
O
I
I/O
P0.3/AD3
14
26
P2.0
A8
P2.1
A9
P2.2
A10
P2.3
A11
P2.4
A12
P2.5
A13
P2.6
A14
P2.7
A15
#PSEN
ALE
NC
#EA
P0.7
Function
P0.0/AD0
13
25
I/O
P0.1/AD1
12
24
Name
VDD
11
No Connect
Timer 2 Clock Out
Bit 0 of Port 1
Timer 2 Control
Bit 1 of Port 1
Bit 2 of Port 1
Bit 3 of Port 1
Bit 4 of Port 1
Bit 5 of Port 1
Bit 6 of Port 1
Bit 7 of Port 1
Reset
Receive Data
Bit 0 of Port 3
No Connect
Transmit Data &
Bit 1 of Port 3
External Interrupt 0
Bit 2 of Port 3
External Interrupt 1
Bit 3 of Port 3
Timer 0
Bit 4 of Port 3
Timer 1 & 3
Bit 5 of Port
Ext. Memory Write
Bit 6 of Port 3
Ext. Memory Read
Bit 7 of Port 3
Oscillator/Crystal Output
Oscillator/Crystal In
Ground
No Connect
NC
4
5
6
7
8
9
10
I
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I/O
O
I/O
I
I/O
I
I/O
I
I/O
I
I/O
O
I/O
O
I/O
O
I
-
PLCC
- 44
T2EX/P1.1
3
NC
T2
P1.0
T2EX
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RES
RXD
P3.0
NC
TXD
P3.1
#INT0
P3.2
#INT1
P3.3
T0
P3.4
T1
P3.5
#WR
P3.6
#RD
P3.7
XTAL2
XTAL1
VSS
NC
Function
T2/P1.0
2
I/O
P1.2
1
Name
P1.3
PLCC
- 44
40
1
39
P0.5/AD5
P1.7
P0.6/AD6
RESET
RXD/P3.0
P0.7/AD7
#EA
VRS550 / VRS560
PLCC-44
NC
TXD/P3.1
NC
ALE
#INT0/P3.2
#PSEN
P2.7/A15
#INT1/P3.3
P2.6/A14
17
18
29
P2.5/A13
P2.4/A12
P2.3/A11
P2.1/A9
P2.2/A10
NC
Tel: (514) 871-2447
P2.0/A8
VSS
XTAL1
XTAL2
28
#RD/P3.7
#WR/P3.6
T0/P3.4
T1/P3.5
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
P0.4/AD4
P1.6
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4
VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Instruction Set
Mnemonic
The following two tables describe the instruction set of the
VRS550 and VRS560 devices. The instructions are binary
code compatible and perform the same functions as the
industry standard 8051 ones.
TABLE 3: LEGEND FOR I NSTRUCTION SET TABLE
Symbol
A
Rn
Direct
@Ri
rel
bit
#data
#data 16
addr 16
addr 11
Function
Accumulator
Register R0-R7
Internal register address
Internal register pointed to by R0 or R1 (except MOVX)
Two's complement offset byte
Direct bit address
8-bit constant
16-bit constant
16-bit destination address
11-bit destination address
TABLE 4: VRS550/VRS560 I NSTRUCTION SET
Mnemonic
Description
Arithmetic instructions
Add register to A
ADD A, Rn
Add direct byte to A
ADD A, direct
Add data memory to A
ADD A, @Ri
Add immediate to A
ADD A, #data
Add register to A with carry
ADDC A, Rn
Add direct byte to A with carry
ADDC A, direct
Add data memory to A w ith carry
ADDC A, @ Ri
Add immediate to A w ith carry
ADDC A, #data
Subtract register from A w ith borrow
SUBB A, Rn
Subtract direct byte from A w ith borrow
SUBB A, direct
Subtract data mem from A w ith borrow
SUBB A, @Ri
Subtract immediate from A w ith borrow
SUBB A, #data
Increment A
INC A
Increment register
INC Rn
Increment direct byte
INC direct
Increment data memory
INC @Ri
Decrement A
DEC A
Decrement register
DEC Rn
Decrement direct byte
DEC direct
Decrement data memory
DEC @Ri
Increment data pointer
INC DPTR
Multiply A by B
MUL AB
Divide A by B
DIV AB
Decimal adjust A
DA A
Logical Instructions
AND register to A
ANL A, Rn
AND direct byte to A
ANL A, direct
AND data memory to A
ANL A, @ Ri
AND immediate to A
ANL A, #data
AND A to direct byte
ANL direct, A
AND immediate data to direct byte
ANL direct, #data
OR register to A
ORL A, Rn
OR direct byte to A
ORL A, direct
OR data memory to A
ORL A, @Ri
OR immediate to A
ORL A, #data
OR A to direct byte
ORL direct, A
OR immediate data to direct byte
ORL direct, #data
Exclusive-OR register to A
XRL A, Rn
Exclusive-OR direct byte to A
XRL A, direct
Exclusive-OR data memory to A
XRL A, @Ri
Exclusive-OR immediate to A
XRL A, #data
Exclusive-OR A to direct byte
XRL direct, A
Exclusive-OR immediate to direct byte
XRL direct, #data
Clear A
CLR A
Compliment A
CPL A
Sw ap nibbles of A
SWAP A
Rotate A left
RL A
Rotate A left through carry
RLC A
Rotate A right
RR A
Rotate A right through carry
RRC A
Size
(bytes)
Instr. Cycles
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
4
4
1
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
Description
Boolean Instruction
Clear Carry bit
CLR C
Clear bit
CLR bit
Set Carry bit to 1
SETB C
Set bit to 1
SETB bit
Complement Carry bit
CPL C
Complement bit
CPL bit
Logical AND betw een Carry and bit
ANL C,bit
Logical AND betw een Carry and not bit
ANL C,#bit
Logical ORL betw een Carry and bit
ORL C,bit
Logical ORL betw een Carry and not bit
ORL C,#bit
Copy bit value into Carry
MOV C,bit
Copy Carry value into Bit
MOV bit,C
Data Transfer Instructions
Move register to A
MOV A, Rn
Move direct byte to A
MOV A, direct
Move data memory to A
MOV A, @Ri
Move immediate to A
MOV A, #data
Move A to register
MOV Rn, A
Move direct byte to register
MOV Rn, direct
Move immediate to register
MOV Rn, #data
Move A to direct byte
MOV direct, A
Move register to direct byte
MOV direct, Rn
Move direct byte to direct byte
MOV direct, direct
Move data memory to direct byte
MOV direct, @Ri
Move immediate to direct byte
MOV direct, #data
Move A to data memory
MOV @Ri, A
Move direct byte to data memory
MOV @Ri, direct
Move immediate to data memory
MOV @Ri, #data
Move immediate to data pointer
MOV DPTR, #data
MOVC A, @A+DPTR
Move code byte relative DPTR to A
Move code byte relative PC to A
MOVC A, @A+PC
Move external data (A8) to A
MOVX A, @Ri
Move external data (A16) to A
MOVX A, @DPTR
Move A to external data (A8)
MOVX @Ri, A
Move A to external data (A16)
MOVX @DPTR, A
Push direct byte onto stack
PUSH direct
Pop direct byte from stack
POP direct
Exchange A and register
XCH A, Rn
Exchange A and direct byte
XCH A, direct
Exchange A and data memory
XCH A, @Ri
Exchange A and data memory nibble
XCHD A, @Ri
Branching Instructions
Absolute call to subroutine
ACALL addr 11
Long call to subroutine
LCALL addr 16
Return from subroutine
RET
Return from interrupt
RETI
Absolute jump unconditional
AJMP addr 11
Long jump unconditional
LJMP addr 16
Short jump (relative address)
SJMP rel
Jump on carry = 1
JC rel
Jump on carry = 0
JNC rel
Jump on direct bit = 1
JB bit, rel
Jump on direct bit = 0
JNB bit, rel
Jump on direct bit = 1 and clear
JBC bit, rel
Jump indirect relative DPTR
JMP @A+DPTR
Jump on accumulator = 0
JZ rel
Jump on accumulator 1= 0
JNZ rel
Compare A, direct JNE relative
CJNE A, direct, rel
Compare A, immediate JNE relative
CJNE A, #d, rel
Compare reg, immediate JNE relative
CJNE Rn, #d, rel
Compare ind, immediate JNE relative
CJNE @ Ri, #d, rel
Decrement register, JNZ relative
DJNZ Rn, rel
Decrement direct byte, JNZ relative
DJNZ direct, rel
Miscellaneous Instruction
No operation
NOP
Rn:
An y of the register R0 to R7
@Ri:
Indirect addressing using Register R0 or R1
#data: immediate Data provided with Instruction
#data16: Immediate data included with instruction
bit:
address at the bit level
rel:
relative address to Program counter from +127 to –128
Addr11: 11-bit address range
Addr16: 16-bit address range
#d:
Immediate Data supplied with instruction
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
Tel: (514) 871-2447
Size
(bytes)
Instr. Cycles
1
2
1
2
1
2
2
2
2
2
2
2
1
1
1
1
1
1
2
2
2
2
1
2
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
1
1
1
1
2
1
1
2
2
2
2
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
2
3
1
1
2
3
2
2
2
3
3
3
1
2
2
3
3
3
3
2
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
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5
VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Special Function Registers (SFR)
Addresses 80h to FFh of the SFR address space can be accessed in direct addressing mode only. The following table
lists the VRS550 and VRS560 Special Function Registers.
TABLE 5: SPECIAL FUNCTION REGISTERS (SFR)
SFR
Register
P0
SP
DPL
DPH
Reserved
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
P1
SCON
SBUF
WDTCON
P2
IE
P3
IP
SYSCON
T2CON
RCAP2L
RCAP2H
TL2
TH2
PSW
ACC
B
SFR
Adrs
80h
81h
82h
83h
84h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
90h
98h
99h
9Fh
A0h
A8h
B0h
B8h
BFh
C8h
CAh
CBh
CCh
CDh
D0h
E0h
F0h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
SMOD
TF1
GATE1
SM0
WDTE
EA
WDRESET
TF2
-
TR1
C/T1
SM1
EXF2
-
TF0
M1.1
SM2
WDCLR
ET2
PT2
RCLK
-
TR0
M0.1
REN
ES
PS
TCLK
-
GF1
IE1
GATE0
TB8
ET1
PT1
EXEN2
-
GF0
IT1
C/T0
RB8
WDPS2
EX1
PX1
PDOWN
IE0
M1.0
TI
WDPS1
ET0
PT0
TR2
-
C/T2
-
IDLE
IT0
M0.0
RI
WDPS0
EX0
PX0
ALEI
CP/RL2
-
CY
-
AC
-
F0
-
RS1
-
RS0
-
OV
-
-
P
-
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Reset Value
00000000b
00000000b
00000000b
00000000b
0*0**000b
00000000b
00000000b
0******0b
00000000b
00000000b
00000000b
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6
VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Data Pointer
Program Memory Structure
Program Memory
The VRS550 includes 8k of on-chip Flash that can be
used as general program memory. The Flash memory
size of the VRS560 is 16k.
The VRS550 and VRS560 have one 16-bit data
pointer. The DPTR is accessed through two SFR
addresses: DPL located at address 82h and DPH
located at address 83h.
Data Memory
The VRS550 and the VRS560 have a total of: 256 bytes
of RAM configured like the internal memory structure of
a standard 8052.
FIGURE 3: VRS560 / VRS550 I NTERNAL PROGRAM MEMORY
3FFFh
FIGURE 4: VRS550 /VRS560 RAM MEMORY
FF
VRS560
Flash Memory
(16k Bytes)
Upper 128 bytes
(Can only be accessed in
indirect addressing mode)
1FFFh
VRS550
Flash Memory
(8k Bytes)
0000h
Lower 128 bytes (00h to 7Fh, Bank 0 & Bank 1)
0000h
The lower 128 bytes of data memory (from 00h to 7Fh)
can be summarized in the following points:
The register below contains the program state flags.
These flags may be read or written to by the user.
•
•
TABLE 6: PROGRAM STATUS W ORD REGISTER (PSW) - SFR DOH
Bit
7
6
5
4
3
2
1
0
6
AC
5
F0
Mnemonic
CY
AC
F0
RS1
RS0
OV
P
4
RS1
3
RS0
80
Lower 128 bytes
(Can be accessed in indirect and
direct addressing mode)
Program Status Word Register
7
CY
SFR
(Can only be accessed in direct
addressing mode)
2
OV
1
-
Description
Carry Bit
Auxiliary Carry Bit from bit 3 to 4.
User definer flag
R0-R7 Registers bank select bit 0
R0-R7 Registers bank select bit 1
Overflow flag
Parity flag
0
P
•
•
Address range 00h to 7Fh can be accessed in
direct and indirect addressing modes.
Address range 00h to 1Fh includes R0-R7
registers area.
Address range 20h to 2Fh is bit addressable.
Address range 30h to 7Fh is not bit addressable
and can be used as general-purpose storage.
Upper 128 bytes (80h to FFh, Bank 2 & Bank 3)
The upper 128 bytes of the data memory ranging from
80h to FFh can be accessed using indirect addressing
or by using the bank mapping in direct addressing
mode.
FIGURE 5: VRS550 / VRS560 RAM STRUCTURE
FFh
RS1
0
0
1
1
RS0
0
1
0
1
Active Bank
0
1
2
3
Address
00h-07h
08h-0Fh
10h-17h
18-1Fh
FFh
SFR A rea
Direc t or Bit Acc ess
Only
128 B ytes of
Indir ect Ac ces s RAM
(SP, R0,R1 )
85
84
83
82
81
80
DPH
DPL
SP
P0
80h
7 Fh
8 0 Byte s of
Genera l Pur pos e RAM
30h
2 Fh
20h
18h
10h
08h
00h
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7F
7E
7D
7C
7B
7A
79
78
77
76
75
74
73
72
71
70
0F
0E
0D
0C
0B
0A
09
08
07
06
05
04
03
02
01
00
R7
R0
R7
R0
R7
R0
R7
R0
Re gister s Ba nk 3
Re gister s Ba nk 2
Re gister s Ba nk 1
Re gister s Ba nk 0
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VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Description of Peripherals
TABLE 8: POWER CONTROL REGISTER (PCON) - SFR 87H
System Control Register
7
The register represented in the following table is used
for system control. The WDRESET bit (7) indicates if
the system has been reset due to the overflow of the
Watch Dog Timer.
The bit 0 of the SYSCON register is the ALE output
inhibit bit. Setting this bit to 1 will inhibit the Fosc/6
clock signal output to the ALE pin.
TABLE 7: SYSTEM CONTROL REGISTER (SYSCON) – SFR BFH
7
6
5
WDRESET
Bit
7
Mnemonic
6
5
4
3
2
1
0
Unused
Unused
Unused
Unused
Unused
Unused
ALEI
WDRESET
4
3
Unused
2
1
XRAME
0
ALEI
Description
This is the Watch Dog Timer reset bit. It
will be set to 1 when the reset signal
generated by WDT overflows.
ALE output inhibit bit, which is used to
reduce EMI.
Bit
7
6
5
4
Unused
Mnemonic
SMOD
3
2
1
RAM1
0
RAM0
Description
1: Double the baud rate of the serial port
frequency that was generated by Timer 1.
0: Normal serial port baud rate generated by
Timer 1.
6
5
4
3
2
1
0
GF1
GF0
PDOWN
IDLE
General Purpose Flag
General Purpose Flag
Power down mode control bit
Idle mode control bit
Power Control Register
The VRS550 / VRS560 devices provide two power
saving modes: Idle and Power Down. These two
modes serve to reduce the power consumption of the
device.
In Idle mode, the processor is stopped but the oscillator
is still running. The content of the RAM, I/O state and
SFR registers are maintained. Timer operation is
maintained, as well as the external interrupts.
This mode is useful for applications in which stopping
the processor to save power is required. The processor
will be woken up when an external event, triggering an
interrupt, occurs.
In Power Down mode, the oscillator of the VRS550 /
VRS560 is stopped. This means that all the peripherals
are disabled. The content of the RAM and the SFR
registers, however, is maintained.
The minimum VCC in Power down Mode is 2V
These power saving modes are controlled by the
PDOWN and IDLE bits of the PCON register at
address 87h.
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VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Input/Output Ports
The VRS550 and VRS560 have a total of 32 bidirectional I/O lines grouped in four 8-bit I/O ports.
These I/Os can be individually configured as input or
output
Except for the P0 I/Os, which are of the open drain
type, each I/O is made of a transistor connected to
ground and a weak pull-up resistor.
Writing a 0 in a given I/O port bit register will activate
the transistor connected to ground, this will bring the
I/O to a LOW level.
Writing a 1 into a given I/O port bit register deactivates
the transistor between the pin and ground. In this case
the pull-up resistor will bring the corresponding pin to a
HIGH level.
To use a given I/O as an input, one must write a 1 into
its associated port register bit.
By default, upon reset all the I/Os are configured as
input.
General Structure of an I/O Port
The following elements establish the link between the
core unit and the pins of the microcontroller:
•
•
FIGURE 6: I NTERNAL STRUCTURE OF ONE OF THE EIGHT I/O PORT LINES
Read Register
Q
Internal Bus
D Flip-Flop
Write to
Register
This is how one would read the content of the register.
It is also possible to link the value of the pin to the
internal bus. This is done by the “read pin” instruction.
In short, the user may read the value of the register or
the pin.
IC Pin
Q
Read Pin
Structure of the P1, P2, P3
The following figure gives a general idea of the
structure P1, P2 and P3 ports. Note that the figure
below does not show the intermediary logic that
connects the output of the register and the output stage
together because this logic varies with the auxiliary
function of each port.
FIGURE 7: GENERAL STRUCTURE OF THE OUTPUT STAGE OF P1, P2 AND P3
Read Register
Special Function Register (same name as port)
Output Stage Amplifier (the structure of this
element varies with its auxiliary function)
From the next figure, one can see that the D flip-flop
stores the value received from the internal bus after
receiving a write signal from the core. Also, note that
the Q output of the flip-flop can be linked to the internal
bus by executing a read instruction.
Output
Stage
Vcc
Pull-up
Network
Q
Internal Bus
IC Pin
D Flip-Flop
Write to
Register
Q
X1
Read Pin
Each line may be used independently as a logical
input or output. When used as an input, as mentioned
earlier, the corresponding port register bit must be
high.
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VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Structure of Port 0
Port P0 and P2 as Address and Data Bus
The internal structure of P0 is shown below. The
auxiliary function of this port requires a particular logic.
As opposed to the other ports, P0 is truly bi-directional.
In other words, when used as an input, it is considered
to be in a floating logical state (high impedance state).
This arises from the absence of the internal pull-up
resistance. The pull-up resistance is actually replaced
by a transistor that is only used when the port functions
to access external memory/data bus (EA=0).
The output stage may receive data from two sources
When used as an I/O port, P0 acts as an open drain
port and the use of an external pull-up resistor is likely
to be required for most applications.
FIGURE 9: P2 PORT STRUCTURE
•
The outputs of register P0 or the bus address
itself multiplexed with the data bus for P0.
•
The outputs of the P2 register or the high part
(A8/A15) of the bus address for the P2 port.
Read Register
A ddress
V cc
Pull-up
Network
FIGURE 8: PORT P0’ S PARTICULAR STRUCTURE
Q
Internal Bus
I C Pin
D Flip-Flop
Write t o
Register
Address A0/A7
Read Register
Control
Vcc
Internal Bus
Q
Q
Control
Read P in
IC Pin
D Flip-Flop
W rite t o
Register
X1
Q
X1
Read Pin
When P0 is used as an external memory bus input (for
a MOVX instruction, for example), the outputs of the
register are automatically forced to 1.
When the ports are used as an address or data bus,
the special function registers P0 and P2 are
disconnected from the output stage. The 8-bits of the
P0 register are forced to 1 and the content of the P2
register remains constant.
Auxiliary Port 1 Functions
The port 1 I/O pins are shared with the T2EX and T2
inputs as shown below:
Pin
P1.0
P1.1
P1.2
Mnemonic
T2
T2EX
Function
Timer 2 counter input
Timer 2 Auxiliary input
P1.3
P1.4
P1.5
P1.6
P1.7
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VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Auxiliary P3 Port Functions
Software Particularities Concerning the Ports
The Port 3 I/O pins are shared with the UART
interface, INT0 and INT1 interrupts, Timer 0 and Timer
1 inputs and finally the #WR and #RD lines when
external memory access is performed.
Some instructions allow the user to read the logic state
of the output pin, while others allow the user to read
the content of the associated port register. These
instructions are called read-modify-write instructions. A
list of these instructions may be found in the table
below.
FIGURE 10: P3 PORT STRUCTURE
Auxiliary
Function: Output
Read Regist er
Vcc
IC Pin
Q
Internal Bus
X1
D Flip-Flop
Write to
Regist er
Q
Read Pin
Auxiliary
Function: Input
Upon execution of these instructions, the content of the
port register (at least 1 bit) is modified. The other read
instructions take the present state of the input into
account. For example, the instruction ANL P3, #01h
obtains the value in the P3 register; performs the
desired logic operation with the constant 01h; and
recopies the result into the P3 register. When users
want to take the present state of the inputs into
account, they must first read these states and perform
an AND operation between the reading and the
constant.
The following table describes the auxiliary function of
the port 3 I/O pins.
TABLE 9: P3 AUXILIARY FUNCTION TABLE
Pin
P3.0
Mnemonic
RXD
P3.1
TXD
P3.2
INT0
P3.3
INT1
P3.4
P3.5
P3.6
T0
T1
P3.7
RD
WR
Function
Serial Port:
Receive data in asynchronous
mode. Input and output data in
synchronous mode.
Serial Port:
Transmit data in asynchronous
mode. Output clock value in
synchronous mode.
External Interrupt 0
Timer 0 Control Input
External Interrupt 1
Timer 1 Control Input
Timer 0 Counter Input
Timer 1 Counter Input
Write signal for external memory
Read signal for external memory
!
"
When the port is used as an output, the register
contains information on the state of the output pins.
Measuring the state of an output directly on the pin is
inaccurate because the electrical level depends mostly
on the type of charge that is applied to it. The functions
shown below take the value of the register rather than
that of the pin.
TABLE 10: LIST OF I NSTRUCTIONS THAT READ AND MODIFY THE PORT USING REGISTER
VALUES
Instruction
ANL
ORL
XRL
JBC
CPL
INC
DEC
DJNZ
MOV P., C
CLR P.x
SETB P.x
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Function
Logical AND ex: ANL P0, A
Logical OR ex: ORL P2, #01110000B
Exclusive OR ex: XRL P1, A
Jump if the bit of the port is set to 0
Complement one bit of the port
Increment the port register by 1
Decrement the port register by 1
Decrement by 1 and jump if the result
is not equal to 0
Copy the held bit C to the port
Set the port bit to 0
Set the port bit to 1
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VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Port Operation Timing
Writing to a Port (Output)
When an operation induces a modification of the
content in a port register, the new value is placed at the
output of the D flip-flop during the T12 period of the last
machine cycle that the instruction needed to execute.
It is important to note, however, that the output stage
only samples the output of the registers on the P1
phase of each period. It follows that the new value only
appears at the output after the T12 period of the
following machine cycle.
Reading a Port (Input)
The reading of an I/O pin takes place:
•
•
•
During T9 cycle for P0, P1
During T10 cycle for P2, P3
When the ports are configured as I/Os (see
Figure 25).
In order to get sampled, the signal duration present on
the I/O inputs must have a duration longer than
Fosc/12.
I/O Ports Driving Capability
The maximum allowable continuous current that the
device can sink on I/O port is defined by the following:
Maximum sink current on one given I/O
Maximum total sink current for P0
Maximum total sink current for P1, 2, 3
Maximum total sink current on all I/O
10mA
26mA
15mA
70mA
It is not recommended to exceed the sink current
expressed in the above table. Doing so is likely to
make the low-level output voltage exceed the device’s
specification and it is likely to affect the device’s
reliability.
The VRS550 / VRS560 port are not designed to source
current.
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VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Timers
TABLE 11: TIMER MODE CONTROL REGISTER (TMOD) – SFR 89H
7
GATE
Both the VRS550 and VRS560 include three 16-bit
timers: T0, T1 and T2.
The timers can operate in two specific modes:
• Event counting mode
• Timer mode
When operating in counting mode, the counter is
incremented each time an external event, such as a
transition in the logical state of the timer input (T0, T1,
T2 input), is detected. When operating in timer mode,
the counter is incremented by the microcontroller’s
direct clock pulse or by a divided version of this pulse.
Timer 0 and Timer 1
Timers 0 and 1 have four modes of operation. These
modes allow the user to change the size of the
counting register or to authorize an automatic reload
when provided with a specific value. Timer 1 can even
be used as a baud rate generator to generate
communication frequencies for the serial interface.
Timer 1 and Timer 0 are configured by the TMOD and
TCON registers.
6
C/T
5
M1
Bit
7
Mnemonic
GATE1
6
C/T1
5
4
3
M1.1
M0.1
GATE0
2
C/T0
1
0
M1.0
M0.0
4
M0
3
GATE
2
C/T
1
M1.0
0
M0.0
Description
1: Enables external gate control (pin INT1 for
Counter 1). When INT1 is high, and TRx bit is
set (see TCON register), a counter is
incremented every falling edge on the T1IN
input pin.
Selects timer or counter operation (Timer 1).
1 = A counter operation is performed
0 = The corresponding register will function
as a timer.
Selects mode for Timer/Counter 1
Selects mode for Timer/Counter 1
If set, enables external gate control (pin INT0
for Counter 0). When INT0 is high, and TRx
bit is set (see TCON register), a counter is
incremented every falling edge on the T0IN
input pin.
Selects timer or counter operation (Timer 0).
1 = A counter operation is performed
0 = The corresponding register will function
as a timer.
Selects mode for Timer/Counter 0.
Selects mode for Timer/Counter 0.
The table below summarizes the four modes of
operation of timers 0 and 1. The timer-operating mode
is selected by the bits M1 and M0 of the TMOD
register.
TABLE 12: TIMER/COUNTER MODE DESCRIPTION SUMMARY
M1
M0
Mode
Function
0
0
1
0
1
0
Mode 0
Mode 1
Mode 2
1
1
Mode 3
13-bit Counter
16-bit Counter
8-bit auto-reload Counter/Timer. The reload
value is kept in TH0 or TH1, while TL0 or TL1
is incremented every machine cycle. When TLx
overflows, the value of THx is copied to TLx.
If Timer 1 M1 and M0 bits are set to 1, Timer 1
stops.
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VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Timer 0 / Timer1 Counter / Timer Functions
Operating Modes
Timing Function
The user may change the operating mode by varying
the M1 and M0 bits of the TMOD SFR.
When operating as a timer, the counter is automatically
incremented at every machine cycle. A flag is raised in
the event that an overflow occurs and the counter
acquires a value of zero. These flags (TF0 and TF1)
are located in the TCON register.
TABLE 13: TIMER 0 AND 1 CONTROL REGISTER (TCON) –SFR 88 H
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Bit
7
Mnemonic
TF1
Description
Timer 1 Overflow Flag. Set by hardware on
Timer/Counter overflow. Cleared by
hardware on Timer/Counter overflow.
Cleared by hardware when processor
vectors to interrupt routine.
6
TR1
5
TF0
Timer 1 Run Control Bit. Set/cleared by
software to turn Timer/Counter on or off.
Timer 0 Overflow Flag. Set by hardware on
Timer/Counter overflow. Cleared by
hardware when processor vectors to
interrupt routine.
Timer 0 Run Control Bit. Set/cleared by
software to turn Timer/Counter on or off.
Interrupt Edge Flag. Set by hardware when
external interrupt edge is detected. Cleared
when interrupt processed.
Interrupt 1 Type Control Bit. Set/cleared by
software to specify falling edge/low level
triggered external interrupts.
Interrupt 0 Edge Flag. Set by hardware
when external interrupt edge is detected.
Cleared when interrupt processed.
Interrupt 0 Type control bit. Set/cleared by
software to specify falling edge/low level
triggered external interrupts.
4
TR0
3
IE1
2
IT1
1
IE0
0
IT0
Counting Function
When operating as a counter, the timer’s register is
incremented at every falling edge of the T0, T1 and T2
signals located at the input of the timer. In this case,
the signal is sampled at the T10 phase of each
machine cycle for Timer 0, Timer 1 and T9 for Timer 2.
When the sampler sees a high immediately followed by
a low in the next machine cycle, the counter is
incremented. Two machine cycles are required to
detect and record an event. This reduces the counting
frequency by a factor of 24 (24 times less than the
oscillator’s frequency).
Mode 0
A schematic representation of this mode of operation
can be found below in Figure 10. From the figure, we
notice that the timer operates as an 8-bit counter
preceded by a divide-by-32 prescaler made of the
5LSB of TL1. The register of the counter is configured
to be 13 bits long. When an overflow causes the value
of the register to roll over to 0, the TFx interrupt signal
goes to 1. The count value is validated as soon as TRx
goes to 1 and the GATE bit is 0, or when INTx is 1.
FIGURE 11: TIMER/COUNTER 1 MODE 0: 13-BIT COUNTER
CLK
÷12
0
TL1
C/T =0
CLK
1
T1PIN
0
4
7
Mode 0
C/T =1
Co ntro l
Mode 1
TR1
GATE
0
TH1
7
INT1 PIN
TF1
INT
Mode 1
Mode 1 is almost identical to Mode 0. They differ in
that, in Mode 1, the counter uses the full 16-bits and
has no prescaler.
Mode 2
In this mode, the register of the timer is configured as
an 8-bit automatically re-loadable counter. In Mode 2, it
is the lower byte TLx that is used as the counter. In the
event of a counter overflow, the TFx flag is set to 1 and
the value contained in THx, which is preset by
software, is reloaded into the TLx counter. The value of
THx remains unchanged.
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VRS550 / VRS560
VERSA
Datasheet Rev 1.1
FIGURE 12: TIMER/COUNTER 1 MODE 2: 8-BIT AUTOMATIC RELOAD
CLK
÷12
0
C/T =0
TL1
0
7
C/T=1
1
Control
T1 Pin
Re loa d
0
7
TH1
TR1
GATE
TF1
INT
INT0 PIN
Mode 3
In Mode 3, Timer 1 is blocked as if its control bit, TR1,
was set to 0. In this mode, Timer 0’s registers TL0 and
TH0 are configured as two separate 8-bit counters.
Also, the TL0 counter uses Timer 0’s control bits C/T,
GATE, TR0, INT0, TF0 and the TH0 counter is held in
Timer Mode (counting machine cycles) and gains
control over TR1 and TF1 from Timer 1. At this point,
TH0 controls the Timer 1 interrupt.
FIGURE 13: TIMER/COUNTER 0 MODE 3
CLK
0
TH0
7
Cont rol
TF1
TR1
CLK
0
TL0
C/T =0
CLK
1
T0PIN
INTERRUPT
÷12
0
7
C/T =1
Cont rol
TF0
INTERRUPT
TR0
GATE
INT0 PIN
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VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Timer 2
0
Timer 2 of the VRS550 / VRS560 devices is a 16-bit
Timer/Counter. Similar to Timers 0 and 1, Timer 2 can
operate either as an event counter or as a timer. The
user may switch functions by writing to the C/T2 bit
located in the T2CON special function register. Timer 2
has three operating modes: “Auto-Load” “Capture”, and
“Baud Rate Generator”. The T2CON SFR configures
the modes of operation of Timer 2. The next table
describes each bit in the T2CON special function
register.
TABLE 14: TIMER 2 CONTROL REGISTER (T2CON) –SFR C8H
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Bit
7
6
5
4
3
2
1
Mnemonic
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
Description
Timer 2 Overflow Flag: Set by an overflow
of Timer 2 and must be cleared by
software. TF2 will not be set when either
RCLK =1 or TCLK =1.
Timer 2 external flag change in state occurs
when either a capture or reload is caused
by a negative transition on T2EX and
EXEN2=1. When Timer 2 is enabled,
EXF=1 will cause the CPU to Vector to the
Timer 2 interrupt routine. Note that EXF2
must be cleared by software.
Serial Port Receive Clock Source.
1: Causes Serial Port to use Timer 2
overflow pulses for its receive clock in
modes 1 and 3.
0: Causes Timer 1 overflow to be used for
the Serial Port receive clock.
Serial Port Transmit Clock.
1: Causes Serial Port to use Timer 2
overflow pulses for its transmit clock in
modes 1 and 3.
0: Causes Timer 1 overflow to be used for
the Serial Port transmit clock.
Timer 2 External Mode Enable.
1: Allows a capture or reload to occur as a
result of a negative transition on T2EX if
Timer 2 is not being used to clock the Serial
Port.
0: Causes Timer 2 to ignore events at
T2EX.
Start/Stop Control for Timer 2.
1: Start Timer 2
0: Stop Timer 2
Timer or Counter Select (Timer 2)
1: External event counter falling edge
triggered.
0: Internal Timer (OSC/12)
Capture/Reload Select.
1: Capture of Timer 2 value into RCAP2H,
RCAP2L is performed if EXEN2=1 and a
negative transitions occurs on the T2EX
pin. The capture mode requires RCLK and
TCLK to be 0.
CP/RL2
0: Auto-reload reloads will occur either with
Timer 2 overflows or negative transitions at
T2EX when EXEN2=1. When either RCK
=1 or TCLK =1, this bit is ignored and the
timer is forced to auto-reload on Timer 2
overflow.
As shown below, there are different possible
combinations of control bits that may be used for the
mode selection of Timer 2.
TABLE 15: TIMER 2 MODE SELECTION BITS
RCLK + TCLK
CP/RL2
TR2
0
0
1
0
1
1
1
X
1
X
X
0
MODE
16-bit AutoReload Mode
16-bit Capture
Mode
Baud Rate
Generator Mode
Off
The details of each mode are described below.
Capture Mode
In Capture Mode the EXEN2 bit value defines if the
external transition on the T2EX pin will be able to
trigger the capture of the timer value.
When EXEN2 = 0, Timer 2 acts as a 16-bit timer or
counter, which, upon overflowing, will set bit TF2
(Timer 2 overflow bit). This overflow can be used to
generate an interrupt.
FIGURE 14: TIMER 2 IN CAPTURE MODE
FO SC
÷12
0
TIMER
C/T 2
1
0
TL2
7
0
7
0
T H2
7
COUNTER
T2 Pin
0
TR2
RCAP2L
RCAP2H
7
TF2
T2 EX Pin
EXF2
EXEN2
Timer 2
Interrupt
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When EXEN2 = 1, the above still applies. In addition, it
is possible to allow a 1 to 0 transition at the T2EX input
to cause the current value stored in the Timer 2
registers (TL2 and TH2) to be captured into the
RCAP2L and RCAP2H registers. Furthermore, the
transition at T2EX causes bit EXF2 in T2CON to be
set, and EXF2, like TF2, can generate an interrupt.
Note that both EXF2 and TF2 share the same interrupt
vector.
Baud Rate Generator Mode
The baud rate generator mode is activated when RCLK
is set to 1 and/or TCLK is set to 1. This mode will be
described in the serial port section.
FIGURE 16: TIMER 2 IN AUTOMATIC BAUD GENERATOR MODE
FOS C
÷2
0
Auto-Reload Mode
TIME R
In this mode, there are also two options. The user may
choose either option by writing to bit EXEN2 in T2CON.
1
TL2
0
C/T2
TH2
7
0
7
0
COUNTER
T2 Pin
0
RCAP2L
TR2
RCA P2H
1
0
If EXEN2 = 0, when Timer 2 rolls over, it not only sets
TF2, but also causes the Timer 2 registers to be
reloaded with the 16-bit value in the RCAP2L and
RCAP2H registers previously initialised. In this mode,
Timer 2 can be used as a baud rate generator source
for the serial port.
7
0
Timer 1 Overflow
÷2
÷16
TX Clock
÷16
RX Clock
1
0
1
SMOD
T2 EX Pin
TCLK
7
RCLK
EXF2
Timer 2
Interrupt
Request
EXEN2
If EXEN2=1, then Timer 2 still performs the above
operation, but a 1 to 0 transition at the external T2EX
input will also trigger an anticipated reload of the Timer
2 with the value stored in RCAP2L, RCAP2H and set
EXF2.
FIGURE 15: TIMER 2 IN AUTO-RELOAD MODE
F OSC
÷12
0
TIMER
C/T2
1
0
TL2
7
0
7
0
TH2
7
CO UNTER
T2 Pin
0
TR2
RCAP2L
RCAP2H
7
TF2
T2 E X Pin
EXF2
EXEN2
Timer 2
Int errupt
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VRS550 / VRS560
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Datasheet Rev 1.1
Serial Port
The serial port included in the VRS550 and VRS560
can operate in full duplex; in other words, it can
transmit and receive data simultaneously. This occurs
at the same speed if one timer is assigned as the clock
source for both transmission and reception, and at
different speeds if transmission and reception are each
controlled by their own timer.
The serial port receive is buffered, which means that it
can begin reception of a byte even if the one previously
received byte has not been retrieved from the receive
register by the processor. However, if the first byte has
still not been read by the time reception of the second
byte is complete, the byte present in the receive buffer
will be lost.
One SFR register, SBUF, gives access to the transmit
and receive registers of the serial port. When users
read from the SBUF register, they will access the
receive register. When users write to the SBUF, the
transmit register will be loaded.
Serial Port Control Register
The serial port control register and status register
SCON contain the 9th data bit for transmit and receive
(TB8 and RB8) and all the mode selection bits. SCON
also contains the serial port interrupt bits (TI and RI).
TABLE 16: SERIAL PORT CONTROL REGIS TER (SCON) – SFR 98H
7
6
5
4
3
2
1
0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
7
Mnemonic
SM0
6
SM1
5
SM2
Description
Bit to select mode of operation (see table
below)
Bit to select mode of operation (see table
below)
Multiprocessor communication is possible
in modes 2 and 3.
3
TB8
2
RB8
9th data bit transmitted in modes 2 and 3
This bit must be set by software and
cleared by software.
9th data bit received in modes 2 and 3.
TI
In Mode 1, if SM2 = 0, RB8 is the stop bit
that was received.
In Mode 0, this bit is not used.
This bit must be cleared by software.
Transmission Interrupt flag.
RI
Automatically set to 1 when:
• The 8th bit has been sent in Mode 0.
• Automatically set to 1 when the stop bit
has been sent in the other modes.
This bit must be cleared by software.
Reception Interrupt flag
1
0
Automatically set to 1 when:
• The 8th bit has been received in Mode 0.
• Automatically set to 1 when the stop bit
has been sent in the other modes (see
SM2 exception).
This bit must be cleared by software.
TABLE 17: SERIAL PORT MODES OF OPERATION
SM0
SM1
Mode
Description
1
1
3
9-bit UART
0
0
1
0
1
0
0
1
2
Shift Register
8-bit UART
9-bit UART
Baud Rate
Fosc /12
Variable
Fosc /64 or
Fosc /32
Variable
Modes of Operation
The VRS550 / VRS560 devices serial port can operate
in four different modes. In all four modes, a
transmission is initiated by an instruction that uses the
SBUF SFR as a destination register. In Mode 0,
reception is initiated by setting RI to 0 and REN to 1.
An incoming start bit initiates reception in the other
modes provided that REN is set to 1. The following
paragraphs describe the four modes.
In modes 2 or 3 if SM2 is set to 1, RI will
not be activated if the received 9th data bit
(RB8) is 0.
4
REN
In Mode 1, if SM2 = 1 then RI will not be
activated if a valid stop bit was not
received.
Serial Reception Enable Bit
This bit must be set by software and
cleared by software.
1: Serial reception enabled
0: Serial reception disabled
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Mode 0
In this mode, the serial data exits and enters through
the RXD pin. TXD is used to output the shift clock. The
signal is composed of 8 data bits starting with the LSB.
The baud rate in this mode is 1/12 the oscillator
frequency.
The SEND signal enables the output of the shift
register to the alternate output function line of P3.0 and
enables SHIFT CLOCK to the alternate output function
line of P3.1. SHIFT CLOCK is high during T11, T12
and T1, T2 and T3, T4 of every machine cycle and low
during T5, T6, T7, T8, T9 and T10. At T12 of every
machine cycle in which SEND is active, the contents of
the transmit shift register are shifted to the right by one
position.
Internal Bus
1
Write to
SBUF
Q
S
SBUF
RXD P3.0
D
CLK
Shift
ZERO DETECTOR
Shift
Clock
TXD P3.1
Shift
Start
TX Control Unit
TX Clock
F osc/12
Send
TI
Serial Port
Interrupt
RI
RX Clock
Receive
Reception in Mode 0
RX Control Unit
RI
REN
Start Shift 1
RXD P3.0
Input Function
1
1
1
1
1
1
Zeros come in from the left as data bits shift out to the
right. The TX control block sends its final shift and
deactivates SEND while setting T1 after one condition
is fulfilled: When the MSB of the data byte is at the
output position of the shift register; the 1 that was
initially loaded into the 9th position is just to the left of
the MSB; and all positions to the left of that contain
zeros. Once these conditions are met, the deactivation
of SEND and the setting of T1 occur at T1 of the 10th
machine cycle after the “write to SBUF” pulse.
0
Shift Register
RXD P3.0
SBUF
READ SBUF
Internal Bus
FIGURE 17: SERIAL PORT MODE 0 BLOCK DIAGRAM
Transmission in Mode 0
Any instruction that uses SBUF as a destination
register may initiate a transmission. The “write to
SBUF” signal also loads a 1 into the 9th position of the
transmit shift register and tells the TX control block to
begin a transmission. The internal timing is such that
one full machine cycle will elapse between a write to
SBUF instruction and the activation of SEND.
When REN and R1 are set to 1 and 0 respectively,
reception is initiated. The bits 11111110 are written to
the receive shift register at T12 of the next machine
cycle by the RX control unit. In the following phase, the
RX control unit will activate RECEIVE.
SHIFT CLOCK to the alternate output function line of
P3.1 is enabled by RECEIVE. At every machine cycle,
SHIFT CLOCK makes transitions at T5 and T11. The
contents of the receive shift register are shifted one
position to the left at T12 of every machine in which
RECEIVE is active. The value that comes in from the
right is the value that was sampled at the P3.0 pin at
T10 of the same machine cycle.
1’s are shifted out to the left as data bits are shifted in
from the right. The RX control block is flagged to do
one last shift and load SBUF when the 0 that was
initially loaded into the rightmost position arrives at the
leftmost position in the shift register.
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Mode 1
For an operation in Mode 1, 10 bits are transmitted
through TXD or received through RXD. The
transactions are composed of: a Start bit (Low), 8 data
bits (LSB first) and one Stop bit (high). The reception is
completed once the Stop bit sets the RB8 flag in the
SCON register. Either Timer 1 or Timer 2 controls the
baud rate in this mode.
The following diagram shows the serial port structure
when configured in Mode 1.
FIGURE 18: SERIAL PORT MODE 1 AND 3 BLOCK DIAGRAM
Internal Bus
Write to
SBUF
Q
S
SBUF
TXD
D
CLK
Timer 2
Overflo w
÷2
ZERO DETECTOR
0 1
SMOD
0
1
0
1
Shift
Start
÷16
RCLK
TX Clock
Send
TI
÷16
Serial Port
Interrupt
RX Clock
1-0 Transition
Detector
RXD
Data
TX Control Unit
TCLK
Start
RI
Load
SB UF
RX Control Unit
Bit
Detector
SHIFT
9-Bit Sh ift Register
Shift
LOAD SBUF
In this mode, zeros are clocked in from the left as data
bits are shifted out to the right. When the most
significant bit of the data byte is at the output position
of the shift register, the 1 that was initially loaded into
the 9th position is to the immediate left of the MSB, and
all positions to the left of that contain zeros. This
condition flags the TX Control Unit to shift one more
time.
Reception in Mode 1
1
Timer 1
Overflow
When a transmission begins, it places the start bit at
TXD. Data transmission is activated one bit time later.
This activation enables the output bit of the transmit
shift register to TXD. One bit time after that, the first
shift pulse occurs.
SBUF
READ SBUF
Inte rn al Bus
Transmission in Mode 1
Transmission is initiated by any instruction that makes
use of SBUF as a destination register. The 9th bit
position of the transmit shift register is loaded by the
“write to SBUF” signal. This event also flags the TX
Control Unit that a transmission has been requested.
It is after the next rollover in the divide-by-16 counter
when transmission actually begins at T1 of the
machine cycle. It follows that the bit times are
synchronized to the divide-by-16 counter and not to the
“write to SBUF” signal.
One to zero transitions at RXD initiate reception. It is
for this reason that RXD is sampled at a rate of 16
multiplied by the baud rate that has been established.
When a transition is detected, 1FFh is written into the
input shift register and the divide-by-16 counter is
immediately reset. The divide-by-16 counter is reset in
order to align its rollovers with the boundaries of the
incoming bit times.
In total, there are 16 states in the counter. During the
7th, 8th and 9th counter states of each bit time; the bit
detector samples the value of RXD. The accepted
value is the value that was seen in at least two of the
three samples. The purpose of doing this is for noise
rejection. If the value accepted during the first bit time
is not zero, the receive circuits are reset and the unit
goes back to searching for another one to zero
transition. All false start bits are rejected by doing this.
If the start bit is valid, it is shifted into the input shift
register, and the reception of the rest of the frame will
proceed.
For a receive operation, the data bits come in from the
right as 1’s shift out on the left. As soon as the start bit
arrives at the leftmost position in the shift register, (9bit register), it tells the RX control block to perform one
last shift operation: to set RI and to load SBUF and
RB8. The signal to load SBUF and RB8, and to set RI,
will be generated if, and only if, the following conditions
are met at the time the final shift pulse is generated:
-
Either SM2 = 0 or the received stop bit = 1
RI = 0
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If both conditions are met, the stop bit goes into RB8,
the 8 data bits go into SBUF, and RI is activated. If one
of these conditions is not met, the received frame is
completely lost. At this time, whether the above
conditions are met or not, the unit goes back to
searching for a one to zero transition in RXD.
Mode 3
Mode 2
Mode 3 is identical to Mode 2 in all respects but one;
the baud rate. Either Timer 1 or Timer 2 generates the
baud rate in Mode 3.
In Mode 3, 11 bits are transmitted through TXD or
received through RXD. The transactions are
composed of: a Start bit (Low), 8 data bits (LSB first),
a programmable 9th data bit, and one Stop bit (High).
In Mode 2 a total of 11 bits are transmitted through
TXD or received through RXD. The transactions are
composed of: a Start bit (Low), 8 data bits (LSB first), a
programmable 9th data bit, and one Stop bit (High).
FIGURE 20: SERIAL PORT MODE 3 BLOCK DIAGRAM
Internal Bus
1
th
For transmission, the 9 data bit comes from the TB8
bit of SCON. For example, the parity bit P in the PSW
could be moved into TB8.
Write to
SBUF
Timer 1
Overflow
Q
S
SBUF
TXD
D
th
In the case of receive, the 9 data bit is automatically
written into RB8 of the SCON register.
CLK
Timer 2
Overflow
÷2
ZERO DETECTOR
0 1
SMOD
In Mode 2, the baud rate is programmable to either
1/32 or 1/64 the oscillator frequency.
0
Start
1
Shift
0
÷16
1
RCLK
FIGURE 19: SERIAL PORT MODE 2 BLOCK DIAGRAM
Data
TX Control Unit
T CLK
TX Clock
Send
TI
÷16
SAMPLE
RX Clock
1-0 T ransition
Detector
Start
Serial Port
Interrupt
RI
Load
SBUF
RX Control Unit
SHIFT
Internal Bus
1
W rite to
SBUF
RXD
Bit
Detector
9-Bit Shift R egister
Shift
LOAD SBUF
Q
S
Fosc/2
SBUF
TXD
D
SBUF
CLK
READ SBUF
ZERO DETECTOR
÷2
Internal Bus
0 1
Shift
Stop
SMOD
Start
÷16
TX Control Unit
TX Clock
Send
TI
÷16
Sample
1-0 Transition
Detector
RXD
Start
Data
Serial Port
Interrupt
RX Clock
Control
Bit
Detector
RI
Load
SBUF
RX Control Unit
SHIFT
9-Bit Shift Register
Shift
LOAD SBUF
SBUF
READ SBUF
Internal Bus
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VRS550 / VRS560
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Mode 2 and 3: Additional Information
Reception in Mode 2 and Mode 3
As mentioned earlier, for an operation in these modes,
11 bits are transmitted through TXD or received
through RXD. The signal comprises: a logical low Start
bit, 8 data bits (LSB first), a programmable 9th data bit,
and one logical high Stop bit.
One to zero transitions at RXD initiate reception. It is
for this reason that RXD is sampled at a rate of 16
multiplied by the baud rate that has been established.
When a transition is detected, the 1FFh is written into
the input shift register and the divide-by-16 counter is
immediately reset.
On transmit, (TB8 in SCON) can be assigned the value
of 0 or 1. On receive; the 9th data bit goes into RB8 in
SCON. The baud rate is programmable to either 1/32
or 1/64 the oscillator frequency in Mode 2. Mode 3
may have a variable baud rate generated from either
Timer 1 or Timer 2 depending on the states of TCLK
and RCLK.
Transmission in Mode 2 and Mode 3
The transmission is initiated by any instruction that
makes use of SBUF as the destination register. The 9th
bit position of the transmit shift register is loaded by the
“write to SBUF” signal. This event also informs the TX
control unit that a transmission has been requested.
After the next rollover in the divide-by-16 counter, a
transmission actually begins at T1 of the machine
cycle. The bit times are synchronized to the divide-by16 counter and not to the “write to SBUF” signal, as in
the previous mode.
Transmissions begin when the SEND signal is
activated, which places the Start bit at TXD. Data is
activated one bit time later. This activation enables the
output bit of the transmit shift register to TXD. The first
shift pulse occurs one bit time after that.
The first shift clocks a Stop bit (1) into the 9th bit
position of the shift register to TXD. Thereafter, only
zeros are clocked in. Thus, as data bits shift out to the
right, zeros are clocked in from the left. When TB8 is at
the output position of the shift register, the stop bit is
just to the left of TB8, and all positions to the left of that
contain zeros. This condition signals to the TX control
unit to shift one more time and set TI, while
deactivating SEND. This occurs at the 11th divide-by-16
rollover after “write to SBUF”.
During the 7th, 8th and 9th counter states of each bit
time; the bit detector samples the value of RXD. The
accepted value is the value that was seen in at least
two of the three samples. If the value accepted during
the first bit time is not zero, the receive circuits are
reset and the unit goes back to searching for another
one to zero transition. If the start bit is valid, it is shifted
into the input shift register, and the reception of the rest
of the frame will proceed.
For a receive operation, the data bits come in from the
right as 1’s shift out on the left. As soon as the start bit
arrives at the leftmost position in the shift register (9-bit
register), it tells the RX control block to do one more
shift, to set RI, and to load SBUF and RB8. The signal
to set RI and to load SBUF and RB8 will be generated
if, and only if, the following conditions are satisfied at
the instance when the final shift pulse is generated:
- Either SM2 = 0 or the received 9th bit is equal to 1
- RI = 0
If both conditions are met, the 9th data bit received
goes into RB8, and the first 8 data bits go into SBUF. If
one of these conditions is not met, the received frame
is completely lost. One bit time later, whether the
above conditions are met or not, the unit goes back to
searching for a one to zero transition at the RXD input.
Please note that the value of the received stop bit is
unrelated to SBUF, RB8 or RI.
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VRS550 / VRS560
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UART Baud Rates Calculation
The value to put into the TH1 register is defined by the
following formula:
In Mode 0, the baud rate is fixed and can be
represented by the following formula:
TH1 = 256 -
Mode 0 Baud Rate = Oscillator Frequency
12
In Mode 2, the baud rate depends on the value of the
SMOD bit in the PCON SFR. From the formula below,
we can see that if SMOD = 0 (which is the value on
reset), the baud rate is 1/32 the oscillator frequency.
Mode 2 Baud Rate = 2
SMOD
x (Oscillator Frequency)
64
The Timer 1 and/or Timer 2 overflow rate determines
the baud rates in modes 1 and 3.
Generating Baud Rate with Timer 1
When Timer 1 functions as a baud rate generator, the
baud rate in modes 1 and 3 are determined by the
Timer 1 overflow rate.
Mode 1, 3 Baud Rate = 2SMOD x Timer 1 Overflow Rate
32
Timer 1 must be configured as an 8-bit timer (TL1) with
auto-reload with TH1 value when an overflow occurs
(Mode 2). In this application, the Timer 1 interrupt
should be disabled.
The two following formulas can be used to calculate
the baud rate and the reload value to put in the TH1
register.
Mode 1, 3 Baud Rate =
2SMOD x Fosc
32 x 12x (Baud Rate)
It is possible to use Timer 1 in 16-bit mode to generate
the baud rate for the serial port. To do this, leave the
Timer 1 interrupt enabled, configure the timer to run as
a 16-bit timer (high nibble of TMOD = 0001B), and use
the Timer 1 interrupt to perform a 16-bit software
reload. This can achieve very low baud rates.
Generating Baud Rates with Timer 2
Timer 2 is often preferred to generate the baud rate, as
it can be easily configured to operate as a 16-bit timer
with auto-reload. This allows for much better resolution
than using Timer 1 in 8-bit auto-reload mode.
The baud rate using Timer 2 is defined as:
Mode 1, 3 Baud Rate = Timer 2 Overflow Rate
16
The timer can be configured as either a timer or a
counter in any of its 3 running modes. In most typical
application, it is configured as a timer (C/T2 is set to 0).
To make the Timer 2 operate as a baud rate generator
the TCLK and RCLK bits of the T2CON register must
be set to 1.
The baud rate generator mode is similar to the autoreload mode in that an overflow in TH2 causes the
Timer 2 registers to be reloaded with the 16-bit value in
registers RCAP2H and RCAP2L, which are preset by
software. However, when Timer 2 is configured as a
baud rate generator, its clock source is Osc/2.
2SMOD x Fosc
32 x 12(256 – TH1)
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VRS550 / VRS560
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The following formula can be used to calculate the
baud rate in modes 1 and 3 using the Timer 2:
Modes 1, 3 Baud Rate =
Oscillator Frequency
32x[65536 – (RCAP2H, RCAP2L)]
The formula below is used to define the reload value to
put into the RCAP2h, RCAP2L registers to achieve a
given baud rate.
(RCAP2H, RCAP2L) = 65536 -
Fosc
32x[Baud Rate]
In the above formula, RCAP2H and RCAP2L are the
content of RCAP2H and RCAP2L taken as a 16-bit
unsigned integer.
Note that a rollover in TH2 does not set TF2, and will
not generate an interrupt. Because of this, the Timer 2
interrupt does not have to be disabled when Timer 2 is
configured in baud rate generator mode.
Also, if EXEN2 is set, a 1-to-0 transition in T2EX will
set EXF2 but will not cause a reload from RCAP2x to
Tx2. Therefore, when Timer 2 is used as a baud rate
generator, T2EX can be used as an extra external
interrupt.
Furthermore, when Timer 2 is running (TR2 is set to 1)
as a timer in baud rate generator mode, the user
should not try to read or write to TH2 or TL2. When
operating under these conditions, the timer is being
incremented every state time and the results of a read
or write command may be inaccurate.
The RCAP2 registers, however, may be read but
should not be written to, because a write may overlap a
reload operation and generate write and/or reload
errors. In this case, before accessing the Timer 2 or
RCAP2 registers, be sure to turn the timer off by
clearing TR2.
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VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Interrupt Vectors
Interrupts
The VRS550 and VRS560 have 8 interrupt sources (9
if we include the WDT) and 7 interrupt vectors
(including reset) to handle them.
The interrupt can be enabled via the IE register shown
below:
TABLE 18: IEN0 I NTERR UPT ENAB LE REGISTER –SFR A8H
7
6
EA
Bit
7
6
5
-
Mnemonic
EA
3
ES
ET1
2
EX1
1
ET0
0
EX0
Description
Disables All Interrupts
0: no interrupt acknowledgment
1: Each interrupt source is individually
enabled or disabled by setting or clearing
its enable bit.
Reserved
Timer 2 Interrupt Enable Bit
Serial Port Interrupt Enable Bit
Timer 1 Interrupt Enable Bit
External Interrupt 1 Enable Bit
Timer 0 Interrupt Enable Bit
External Interrupt 0 Enable Bit
-
5
4
3
2
1
0
4
ET2
ET2
ES
ET1
EX1
ET0
EX0
The following figure illustrates the various interrupt
sources on the VRS550 / VRS560.
FIGURE 21: I NTERRUP T SOURCES
INT0
IT0
TF1
T1
RI
IT1
IE1
TABLE 19: I NTERRUP T VECTOR COR RESPONDING FLAGS ANS VECTOR ADDRESS
Interrupt Source
RESET (+ WDT)
INT0
Timer 0
INT1
Timer 1
Serial Port
Timer 2
Flag
WDRESET
IE0
TF0
IE1
TF1
RI+TI
TF2+EXF2
Vector
Address
0000h
0003h
000Bh
0013h
001Bh
0023h
002Bh
External Interrupts
The VRS550 and the VRS560 have two external
interrupt inputs named INT0 and INT1. These interrupt
lines are shared with P3.2 and P3.3.
The bits IT0 and IT1 of the TCON register determine
whether the external interrupts are level or edge
sensitive.
If ITx = 1, the interrupt will be raised when a 1-> 0
transition occurs at the interrupt pin. For the interrupt
to be noticed by the processor, the duration of the sum
high and low condition must be at least equal to 12
oscillator cycles.
If ITx = 0, the interrupt will occur when a logic low
condition is present on the interrupt pin.
IE0
TF0
INT1
The table below specifies each interrupt source, its flag
and its vector address.
INTERRUPT
SOURCES
The state of the external interrupt, when enabled, can
be monitored using the flags, IE0 and IE1 of the TCON
register that are set when the interrupt condition
occurs.
In the case where the interrupt was configured as edge
sensitive, the associated flag is automatically cleared
when the interrupt is serviced.
If the interrupt is configured as level sensitive, then the
interrupt flag must be cleared by the software.
TF2
EXF2
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VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Timer 0 and Timer 1 Interrupt
Execution of an Interrupt
Both Timer 0 and Timer 1 can be configured to
generate an interrupt when a rollover of the
timer/counter occurs (except Timer 0 in Mode 3).
When the processor receives an interrupt request, an
automatic jump to the desired subroutine occurs. This
jump is similar to executing a branch to a subroutine
instruction: the processor automatically saves the
address of the next instruction on the stack. An internal
flag is set to indicate that an interrupt is taking place,
and then the jump instruction is executed. An interrupt
subroutine must always end with the RETI instruction.
This instruction allows users to retrieve the return
address placed on the stack.
The TF0 and TF1 flags serve to monitor timer overflow
occurring from Timer 0 and Timer 1. These interrupt
flags are automatically cleared when the interrupt is
serviced.
Timer 2 Interrupt
Timer 2 interrupt can occur if TF2 and/or EXF2 flags
are set to 1 and if the Timer 2 interrupt is enabled.
The RETI instruction also allows updating of the
internal flag that will take into account an interrupt with
the same priority.
The TF2 flag is set when a rollover of Timer 2
Counter/Timer occurs. The EXF2 flag can be set by a
1->0 transition on the T2EX pin by the software.
Interrupt Enable and Interrupt Priority
Note that neither flag is cleared by the hardware upon
execution of the interrupt service routine. The service
routine may have to determine whether it was TF2 or
EXF2 that generated the interrupt. These flag bits will
have to be cleared by the software.
When the VRS550 / VRS560 is initialized, all interrupt
sources are inhibited by the bits of the IE register being
reset to 0. It is necessary to start by enabling the
interrupt sources that the application requires. This is
achieved by setting bits in the IE register, as discussed
previously.
Every bit that generates interrupts can either be
cleared or set by the software, yielding the same result
as when the operation is done by the hardware. In
other words, pending interrupts can be cancelled and
interrupts can be generated by the software.
This register is part of the bit addressable internal
RAM. For this reason, it is possible to modify each bit
individually in one instruction without having to modify
the other bits of the register. All interrupts can be
inhibited by setting EA to 0.
Serial Port Interrupt
The order in which interrupts are serviced is shown in
the following table:
The serial port can generate an interrupt upon byte
reception or once the byte transmission is completed.
Those two conditions share the same interrupt vector
and it is up to the interrupt service routine to find out
what caused the interrupt by looking at the serial
interrupt flags RI and TI.
Note that neither of these flags is cleared by the
hardware upon execution of the interrupt service
routine. The software must clear these flags.
TABLE 20: I NTERRUP T NA TU RAL PRIORITY
Interrupt Source
RESET + WDT (Highest Priority)
IE0
TF0
IE1
TF1
RI+TI
TF2+EXF2 (Lowest Priority)
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VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Modifying the Interrupt Order of Priority
The VRS550 / VRS560 allows the user to modify the
natural priority of the interrupts. One may modify the
order by programming the bits in the IP (Interrupt
Priority) register. When any bit in this register is set to
1, it gives the corresponding source a greater priority
than interrupts coming from sources that don’t have
their corresponding IP bit set to 1.
The IP register is represented in the table below.
TABLE 21: IP I NTERRUP T PRIORITY REGISTER –SFR B8H
7
EA
6
-
5
4
ET2
ES
3
ET1
2
EX1
1
ET0
0
EX0
Bit
7
6
Mnemonic
-
Description
5
4
3
2
1
0
PT2
PS
PT1
PX1
PT0
PX0
Gives Timer 2 Interrupt Higher Priority
Gives Serial Port Interrupt Higher Priority
Gives Timer 1 Interrupt Higher Priority
Gives INT1 Interrupt Higher Priority
Gives Timer 0 Interrupt Higher Priority
Gives INT0 Interrupt Higher Priority
Watch Dog Timer
The Watch Dog Timer (WDT) is a 16-bit free-running
counter that generates a reset signal if the counter
overflows. The WDT is useful for systems that are
susceptible to noise, power glitches and other
conditions that can cause the software to go into
infinite dead loops or runaways. The WDT function
gives the user software a recovery mechanism from
abnormal software conditions.
The Watch Dog Timer of the VRS550 and VRS560
devices is driven by the oscillator.
Once the WDT is enabled, the user software must
clear it periodically. In the case where the WDT is not
cleared, its overflow will trigger a reset of the device.
The user should check the WDRESET bit of the
SYSCON register whenever an unpredicted reset has
taken place.
The WDT timeout delay can be adjusted by configuring
the clock divider input for the time base source clock of
the WDT. To select the divider value, bit2-bit0
(WDPS2~WDPS0) of the Watch Dog Timer Control
Register (WDTCON) should be set accordingly.
Clearing the WDT is accomplished by setting the CLR
bit of the WDTCON to 1. This action will clear the
contents of the 16-bit counter and force it to restart.
Watch Dog Timer Registers
Three registers of the VRS550/VRS560 devices are
associated with the Watch Dog Timer: WDTCON, the
WDTLOCK and the SYSCON registers. The WDTCON
register allows the user to enable the WDT, to clear the
counter and to divide the clock source. The WDRESET
bit of the SYSCON register indicates whether the
Watch Dog Timer has caused the device reset.
TABLE 22: W ATCHDOG TIM ER REGISTERS : WDTCON – SFR 9FH
7
WDTE
Bit
7
6
5
[4:3]
2
1
0
6
Unused
5
WDCLR
4
3
Unused
2
1
0
WDTPS [2:0]
Mnemonic
WDTE
Unused
WDCLR
Unused
Description
Watch Dog Timer Enable Bit
Watch Dog Timer Counter Clear Bit
-
WDPS [2:0]
Watchdog Timer Clock Source Divider
To enable the WDT, the user must set bit 7 (WDTE) of
the WDTCON register to 1. Once WDTE has been set
to 1, the 16-bit counter will start to count with the
selected time base source clock configured in
WDPS2~WDPS0. The Watch Dog Timer will generate
a reset signal if an overflow has taken place.
The WDTE bit will be cleared to 0 automatically when
the device is reset by either the hardware or a WDT
reset.
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VRS550 / VRS560
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Datasheet Rev 1.1
The table below gives examples of Watchdog timeout
period the user will obtain for different values of the
WDPSx bits of the Watch Dog Timer Register.
TABLE 23: W ATCH DOG TIM ER PERIOD VS . WDWDPS [2:0] BIT
WDT
Timeout
(ms) @
20MHz
000
8
26.2
001
16
52.4
XTAL
3MHz
6MHz
12MHz
16MHz
25MHz
010
32
104.8
011
64
209.7
C1
C2
R
30 pF
30 pF
open
30 pF
30 pF
open
30 pF
30 pF
open
30 pF
30 pF
open
15 pF
15 pF
62K
100
128
419.4
101
256
838.8
110
512
1677.7
111
1024
3355.4
The System Control Register
The System Control register is used to monitor the
status of the Watch Dog Timer and inhibit the address
Latch Enable signal output.
TABLE 24: THE SYSTEM CONTROL REGISTER (SYSCON)–SFR BF H
6
5
WDRESET
Bit
7
[6:3]
2
1
0
The crystal connected to the VRS550 / VRS560
oscillator input should be of a parallel type, operating in
fundamental mode.
Fosc Division
Factor
WDPS [2:0]
7
Crystal Consideration
Mnemonic
WDRESET
Unused
Unused
Unused
ALEI
4
Unused
3
2
1
XRAME
0
ALEI
The following table shows the value of capacitors and
feedback resistor that must be used at different
operating frequencies.
Note: Oscillator circuits may differ with different
crystals or ceramic resonators in higher oscillation
frequency.
Crystals or ceramic resonator characteristics vary from
one manufacturer to the other.
The user should check the specific crystal or ceramic
resonator technical literature available or contact the
manufacturer to select the appropriate values for the
external components.
XTAL1
Description
Watch Dog Timer Reset Status Bit
1: Enable Electromagnetic Interference
Reducer
0: Disable Electromagnetic Interference
Reducer
The WDRESET bit of the SYSCON register is the
Watch Dog Timer Reset bit. It will be set to 1 when a
reset signal is generated by the WDT overflow. The
user should check the WDRESET bit state if a reset
has taken place in application where the Watch Dog
timer is activated
XTAL
R
C1
VRS550
VRS560
XTAL2
C2
Reduced EMI Function
The VRS550 and the VRS560 devices can also be set
up to reduce its EMI (electromagnetic interference) by
setting bit 0 (ALEI) of the SYSCON register to 1. This
function will inhibit the Fosc/6Hz clock signal output to
the ALE pin.
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VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Operating Conditions
TABLE 25: OPERATING CONDI TIONS
Symbol
Description
Min.
Typ.
Max.
Unit
Remarks
TA
TS
VCC5V
VCC3V
Fosc 25
Operating temperature
Storage temperature
Supply voltage
Supply voltage
Oscillator Frequency
-40
-55
4.5
3.0
3.0
25
25
5.0
3.3
25
85
155
5.5
3.6
25
ºC
ºC
V
V
MHz
Ambient temperature operating
5 Volts devices
3.3 Volts devices
For 5V & 3.3V application
DC Characteristics
TABLE 26: DC CHARA C TERISTICS
AM BIENT TEM PERATURE = -40°C
TO
85°C, 3.0V
TO
5.5V
Symbol
VIL1
VIL2
VIH1
VI H2
VOL1
VOL2
Parameter
Input Low Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
Valid
P o r t 0 ,1,2,3,4,#EA
RES, XTAL1
P o r t 0,1,2,3,4,#EA
RES, XTAL1
Port 0, ALE, #PSEN
P o r t 1,2,3,4
VOH1
Output High Voltage
Port 0
Output High Voltage
Port
1,2,3,4,ALE,#PSEN
IIL
Logical 0 Input Current
P o r t 1,2,3,4
ITL
Logical Transition
Current
ILI
R RES
Input Leakage Current
Reset Pull-down
Resistance
VOH2
-
C 10
IC C
Min.
-0.5
0
2.0
70% VCC
2.4
Unit
V
V
V
V
V
V
V
Test Conditions
IOL=3.2mA
IOL=1.6mA
IOH=-800uA (Vcc = 5V)
90% VCC
V
IOH=-80uA
2.4
90% VCC
V
V
IOH=-60uA (Vcc = 5V)
IOH=-10uA
-75
uA
Vin=0.45V
P o r t 1,2,3,4
-650
uA
Vin=2.O V
P o r t 0, #EA
+10
uA
0.45V< Vin<VCC
300
Kohm
10
pF
Freq=1 MHz, Ta=25 C
15
10
mA
mA
Active mode 25MHz
Active mode 16MHz
7.5
6
150
mA
mA
uA
Idle mode 25MHz
Idle mode, 16MHz
Power down mode
RES
50
Pin Capacitance
Power Supply Current
Max.
0.8
0 .8
VCC+0.5
VCC+0.5
0.45
0.45
VDD
FIGURE 22: ICC I DLE MODE TEST CIRCUI T
°
FIGURE 23: ICC AC TIVE MODE TEST CIRCUI T
Vcc
Vcc
Vcc
Icc
RST
VCC
PO
EA
VCC
8
(NC)
XTAL2
XTAL1
VSS
PO
EA
RST
VRS550
VRS560
Clock Signal
Icc
8
VRS550
VRS560
(NC)
Clock Signal
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XTAL2
XTAL1
VSS
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VRS550 / VRS560
VERSA
Datasheet Rev 1.1
AC Characteristics
TABLE 27: AC CHARA C TERISTICS
Symbol
T LHLL
T AVLL
T LLAX
T LLIV
T LLPL
T PLPH
T PLIV
T PXIX
T PXIZ
T AVI V
T PLAZ
T RLRH
T WLWH
T RLDV
T RHDX
T RHDZ
T LLDV
T AVDV
T LLYL
T AVYL
T QVWH
T QVWX
T WHQX
T RLAZ
T YALH
T CHCL
T CLCX
T CLCH
T CHCX
T ,T C LCL
Parameter
ALE Pulse Width
Address Valid to ALE Low
Address Hold after ALE Low
ALE Low to Valid Instruction In
ALE Low to #PSEN low
#PSEN Pulse Width
#PSEN Low to Valid Instruction In
Instruction Hold after #PSEN
Instruction Float after #PSEN
Address to Valid Instruction In
#PSEN Low to Address Float
#RD Pulse Width
#WR Pulse Width
#RD Low to Valid Data In
Data Hold after #RD
Data Float after #RD
ALE Low to Valid Data In
Address to Valid Data In
ALE low to #WR High or #RD Low
Address Valid to #WR or #RD Low
Data Valid to #WR High
Data Valid to #WR Transition
Data Hold after #WR
#RD Low to Address Float
#W R or #RD High to ALE High
Clock Fall Time
Clock Low Time
Clock Rise Time
Clock High Time
Clock Period
Valid
Cycle
RD/WRT
RD/WRT
RD/WRT
RD
RD
RD
RD
RD
RD
RD
RD
RD
WRT
RD
RD
RD
RD
RD
RD/WRT
RD/WRT
WRT
WRT
WRT
RD
RD/WRT
Fosc 16
Min.
115
43
53
53
173
0
Type
Variable Fosc
Max.
240
177
Min.
2xT - 10
T - 20
T - 10
Type
4xT - 10
T - 10
3xT - 15
3xT -10
0
87
292
10
365
365
0
178
230
403
38
73
53
Max.
T + 25
5xT - 20
10
6xT - 10
6xT - 10
302
145
590
542
197
72
2xT
8xT
9xT
3xT
3xT - 10
4xT - 20
7xT - 35
T - 25
T + 10
+ 20
- 10
- 20
+ 10
5
T+10
T -10
63
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5xT - 10
0
1/fosc
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Unit
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
30
VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Data Memory Read Cycle Timing
The following timing diagram shows what occurs at each signal during a Data Memory Read Cycle.
FIGURE 24: DA TA MEM ORY READ CYCLE TIMING
T12
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T1
T2
T3
OSC
1
ALE
2
#PSEN
5
#RD
7
3
ADDRESS A15-A8
PORT2
3
PORT0
INST in
Float
A7-A0
4
6
Float
8
Data in
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Float
ADDRESS or
Float
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VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Program Memory Read Cycle Timing
The following timing diagram shows what occurs at each signal during a Program Memory Read Cycle.
FIGURE 25: PROGRAM MEM ORY READ CYCLE
T12
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T1
T2
T3
OSC
ALE
1
2
5
#PSEN
7
#RD,#WR
3
ADDRESS A15-A8
PORT2
3
PORT0
Float
A7-A0
4
Float
6
ADDRESS A15-A8
8
INST in
Float
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A7-A0
Float
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Float
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VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Data Memory Write Cycle Timing
The following timing diagram shows what occurs at each signal during a Data Memory Write Cycle.
FIGURE 26: DA TA MEM ORY W RITE CYCLE TIM ING
T12
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T1
T2
T3
OSC
ALE
1
#PSEN
5
#WR
6
2
ADDRESS A15-A8
PORT2
2
PORT0
INST in
Float
A7-A0
3
4
Data out
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ADDRESS or
Float
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VRS550 / VRS560
VERSA
Datasheet Rev 1.1
I/O Port Timing
The following timing diagram shows what occurs during I/O Port Timing.
FIGURE 27: I/O PORTS TIMING
T7
T8
T9
T10
T11
T12
T1
T2
T3
T4
T5
T6
T7
T8
X1
Sampled
Inputs P0,P1
Sampled
Inputs P2,P3
Output by Mov
Px, Src
RxD at Serial
Port Shift
Clock Mode 0
Current Data
Next Data
Sampled
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VRS550 / VRS560
VERSA
Datasheet Rev 1.1
External Clock Timing
FIGURE 28: TIM ING REQUIREM ENT OF EXTERNAL CLOCK (VSS= 0.0V IS ASSUM ED)
TCLCL
Vdd - 0.5V
0.45V
70% Vdd
20% Vdd-0.1V
TCLCX
TCHCX
TCHCL
TCLCH
External Program Memory Read Cycle
The following timing diagram shows what occurs at each signal during an External Program Memory Read Cycle.
FIGURE 29: EX TERNAL PROGRAM MEM ORY READ CYCLE
TPLPH
#PSEN
TLLPL
ALE
TLHLL
TAVLL
PORT 0
TPXIZ
TLLAX
A0-A7
TPLIV
TPLAZ
TPXIX
Instruction IN
A0-A7
TAVIV
PORT2
P2.0-P2.7 or AB-A15 from DPH
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A8-A15
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VRS550 / VRS560
VERSA
Datasheet Rev 1.1
External Data Memory Read Cycle
The following timing diagram shows what occurs at each signal during an External Data Memory Read Cycle.
FIGURE 30: EX TERNAL D A TA MEM ORY READ CYCLE
#PSEN
TYHLH
ALE
TLLDV
TRLRH
TLLYL
#RD
TAVLL
PORT 0
TRLDV
TLLAX
TRLAZ
A0-A7
From Ri or DPL
TRHDZ
TRHDX
DATA IN
A0-A7
From PCL
INSTRL
IN
TAVYL
TAVDV
PORT 2
P2.0-P2.7 or A8 -A15 from DPH
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A8-A15 from PCH
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VRS550 / VRS560
VERSA
Datasheet Rev 1.1
External Data Memory Write Cycle
The following timing diagram shows what occurs at each signal during an External Data Memory Write Cycle.
FIGURE 31: EX TERNAL D A TA MEM ORY W RITE CYCLE
#PSEN
TYHLH
ALE
TLHLL
TLLYL
#WR
TAVLL
TQVWX
TLLAX
PORT 0
TWLWH
A0-A7
From Ri or DPL
TWHQX
TQVWH
DATA OUT
A0-A7
From PCL
INSTRL
IN
TAVYL
PORT 2
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
.
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37
VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Plastic Chip Carrier (PLCC)
VRS550
&
VRS560
L
E
GE
HE
Y
D
A2
HD
A1
A
TABLE 28: DIM ENSIONS OF PLCC-44 CHIP CARRIER
C
e
b1
b
GD
Note:
1. Dimensions D & E do not include interlead Flash.
2. Dimension B1 does not include dambar
protrusion/intrusion.
3. Controlling dimension: Inch
4. General appearance spec should be based on
final visual inspection spec.
Symbol
A
Al
A2
bl
b
C
D
E
e
GD
GE
HD
HE
L
y
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
Dimension in inch
Minimal/Maximal
-/0.185
0.020/0.145/0.155
0.026/0.032
0.016/0.022
0.008/0.014
0.648/0.658
0.648/0.658
0.050 BSC
0.590/0.630
0.590/0.630
0.680/0.700
0.680/0.700
0.090/0.110
-/0.004
/
Tel: (514) 871-2447
Dimension in mm
Minimal/Maximal
-/4.70
0.51/
3.68/3.94
0.66/0.81
0.41/0.56
0.20/0.36
16.46/16.71
16.46/16.71
1.27 BSC
14.99/16.00
14.99/16.00
17.27/17.78
17.27/17.78
2.29/2.79
-/0.10
/
http://www.goalsemi.com
38
VRS550 / VRS560
VERSA
Datasheet Rev 1.1
C
Quad Flat Package (QFP)
L
L1
S
S
VRS550
&
VRS560
2
D2 D1 D
R1
b
A2
Gage Plane
0.25mm
3
A1
E2
R2
A
E1
E
TABLE 29: DIM ENSIONS OF QFP-44 CHIP CARRIER
Symbol
e1
Seating Plane
e
Note:
1. Dimensions D1 and E1 do not include mold
protrusion.
2. Allowance protrusion is 0.25mm per side.
3. Dimensions D1 and E1 do not include mold
mismatch and are determined datum plane.
4. Dimension b does not include dambar
protrusion.
5. Allowance dambar protrusion shall be 0.08 mm
total in excess of the b dimension at maximum
material condition. Dambar cannot be located
on the lower radius of the lead foot.
C
A
Al
A2
b
c
D
D1
D2
E
E1
E2
e
L
L1
R1
R2
S
0
1
2
3
C
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
Dimension in in.
Minimal/Maximal
-/0.100
0.006/0.014
0.071 / 0.087
0.012/0.018
0.004 / 0.009
0.520 BSC
0.394 BSC
0.315
0.520 BSC
0.394 BSC
0.315
0.031 BSC
0.029 / 0.041
0.063
0.005/0.005/0.012
0.008/0˚/7˚
0˚/ 10˚ REF
7˚ REF
0.004
Tel: (514) 871-2447
Dimension in mm
Minimal/Maximal
-/2.55
0.15/0.35
1.80/2.20
0.30/0.45
0.09/0.20
13.20 BSC
10.00 BSC
8.00
13.20 BSC
10.00 BSC
8.00
0.80 BSC
0.73/1.03
1.60
0.13/0.13/0.30
0.20/as left
as left
as left
as left
0.10
http://www.goalsemi.com
39
VRS550 / VRS560
VERSA
Datasheet Rev 1.1
Ordering Information
Device Number Structure
VRSabc-X Y Z FF
Operating Frequency
25: 25MHz oscillator frequency
Temperature Range
I: Industrial ( -40°C to +85°C )
C: Commercial ( 0°C to +70°C )
Operating Voltage
A: 4.5V - 5.5V
L: 3.0V - 3.6V
Package Options
P: PLCC-44 pins
Q: QFP-44 pins
Product Number
550 - 8k Flash & 256 Bytes RAM
560 - 16k Flash & 256 Bytes RAM
Device Family
VRS: VERSA MCU
VRS550 Ordering Options
Device Number
VRS550-PAI25
VRS550-PLI25
VRS550-QAI25
VRS550-QLI25
Flash Size
8k
8k
8k
8k
RAM Size
256 Bytes
256 Bytes
256 Bytes
256 Bytes
Package Option
PLCC-44
PLCC-44
QFP-44
QFP-44
Voltage
4.5V to 5.5V
3.0V to 3.6V
4.5V to 5.5V
3.0V to 3.6V
Temperature
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Frequency
25MHz
25MHz
25MHz
25MHz
RAM Size
256 Bytes
256 Bytes
256 Bytes
256 Bytes
Package Option
PLCC-44
PLCC-44
QFP-44
QFP-44
Voltage
4.5V to 5.5V
3.0V to 3.6V
4.5V to 5.5V
3.0V to 3.6V
Temperature
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Frequency
25MHz
25MHz
25MHz
25MHz
VRS560 Ordering Options
Device Number
VRS560-PAI25
VRS560-PLI25
VRS560-QAI25
VRS560-QLI25
Flash Size
16k
16k
16k
16k
Disclaimers
Right to make change - Goal Semiconductor reserves the right to make changes to its products - including circuitry, software and services - without
notice at any time. C ustomers should obtain the most current and relevant information before placing orders.
Use in applications - Goal Semiconductor assumes no responsibility or liability for the use of any of its products, and conveys no license or title
under any patent, copyright or mask work right to these products and makes no representations or warranties that these products are free from
patent, copyright or mask work right infringement unless otherwise specified. Customers are responsible for product design and applications using
Goal Semiconductor parts. Goal Semiconductor assumes no liability for applications assistance or customer product design.
Life support – Goal Semiconductor products are not designed for use in life support systems or devices. Goal Semiconductor customers using or
selling Goal products for use in such applications do so at their own risk and agree to fully indemnify Goal Semiconductor for any damages resulting
from such applications.
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
Tel: (514) 871-2447
http://www.goalsemi.com
40