X51638 CPU Supervisor with 16Kb SPI EEPROM FEATURES DESCRIPTION • Extended Power-On Reset (800ms Nominal) • Selectable Watchdog Timer • Low Vcc Detection and Reset Assertion —Five Standard Reset Threshold Voltages —Re-program Low Vcc Reset Threshold Voltage using special programming sequence —Reset Signal Valid to Vcc=1V • Determine Watchdog or Low Voltage Reset with a Volatile Flag bit • Long Battery Life With Low Power Consumption —<50mA Max Standby Current, Watchdog On —<1mA Max Standby Current, Watchdog Off —<400mA Max Active Current during Read • 16Kbits of EEPROM • Built-in Inadvertent Write Protection —Power-Up/Power-Down Protection Circuitry —Protect 0, 1/4, 1/2 or all of EEPROM Array with Block LockTM Protection —In Circuit Programmable ROM Mode • 2MHz SPI Interface Modes (0,0 & 1,1) • Minimize EEPROM Programming Time —32 Byte Page Write Mode —Self-Timed Write Cycle —5ms Write Cycle Time (Typical) • 1.8V to 3.6V, 2.7V to 5.5V and 4.5V to 5.5V Power Supply Operation • Available Packages —14-Lead TSSOP, 8-Lead SOIC This device combines four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock™ Protect Serial EEPROM in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates a power on reset circuit which holds RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code. This device allows 800ms before releasing the controller. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time-out interval, the device activates the RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The X51638 low Vcc detection circuitry protects the user’s system from low voltage conditions, resetting the system when Vcc falls below the minimum Vcc trip point. RESET is asserted until Vcc returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds are available, however, Xicor’s unique circuits allow the thresold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. BLOCK DIAGRAM WATCHDOG TRANSITION DETECTOR WP WATCHDOG TIMER RESET PROTECT LOGIC RESET SI DATA SO REGISTER STATUS REGISTER DECODE & 4K BITS CONTROL CS/WDI LOGIC 4K BITS VCC THRESHOLD 8K BITS RESET LOGIC VCC EEPROM ARRAY COMMAND SCK RESET & WATCHDOG TIMEBASE POWER ON AND LOW VOLTAGE RESET + GENERATION VTRIP ÓXicor, Inc. 1999 Patents Pending 9900-3002.10 2/12/99 T0/C0/D0 - 1 Characteristics subject to change without notice X51638 PIN DESCRIPTION PIN (SOIC/PDIP) PIN TSSOP Name Function 1 1 CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power up, a HIGH to LOW transition on CS is required Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time-out period results in RESET going active. 2 2 SO Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. 5 8 SI Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. 6 9 SCK Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin. 3 6 WP Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting of the Watchdog Timer control and the memory write protect bits. 4 7 VSS Ground 8 14 VCC Supply Voltage 7 13 RESET 3-5,10-12 NC Reset Output. RESET is an active LOW open drain output which goes active whenever Vcc falls below the minimum Vcc sense level. It will remain active until Vcc rises above the minimum Vcc sense level for 800ms. RESET goes active if the Watchdog Timer is enabled and CS remains either HIGH or LOW longer than the selectable Watchdog time-out period. A falling edge of CS will reset the Watchdog Timer. RESET goes active on power up at 1V and remains active for 800ms after the power supply stabilizes. No internal connections PIN CONFIGURATION 14-LEAD TSSOP 8-LEAD SOIC/PDIP CS 1 X51638 8 V CC SO 2 7 RESET WP 3 6 SCK 4 5 SI VSS 2 CS 1 X51638 14 V CC SO 2 13 RESET NC 3 12 NC NC 4 11 NC NC 5 10 NC WP VSS 6 9 SCK 7 8 SI X51638 PRINCIPLES OF OPERATION To set the new VTRIP voltage, apply the desired VTRIP threshold to the Vcc pin and tie the CS/WDI pin and the WP pin HIGH. RESET and SO pins are left unconnected. Then apply the programming voltage Vp to both SCK and SI and pulse CS/WDI LOW then HIGH. Remove Vp and the sequence is complete. POWER ON RESET Application of power to the X51638 activates a Power On Reset Circuit. This circuit goes active at VCC sense level (VTRIP) and pulls the RESET pin LOW. This signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When Vcc exceeds the device VTRIP value for 800ms (nominal) the circuit releases RESET, allowing the processor to begin executing code. Figure 1. Set VTRIP Voltage CS Vp LOW VOLTAGE MONITORING SCK During operation, the X51638 monitors the VCC level and asserts RESET if supply voltage falls below a preset minimum VTRIP. The RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET signal remains active until the voltage drops below 1V. It also remains active until Vcc returns and exceeds VTRIP for 800ms. Vp SI Resetting the VTRIP Voltage This procedure sets the VTRIP to a “native” voltage level. For example, if the current VTRIP is 4.4V and the VTRIP is reset, the new VTRIP is something less than 1.7V. This procedure must be used to set the voltage to a lower value. WATCHDOG TIMER The Watchdog Timer circuit monitors the microprocessor activity by monitoring the WDI input. The microprocessor must toggle the CS/WDI pin periodically to prevent a RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog timeout period. The state of two nonvolatile control bits in the Status Register determine the watchdog timer period. The microprocessor can change these watchdog bits, or they may be “locked” by tying the WP pin LOW and setting the WPEN bit HIGH. To reset the VTRIP voltage, apply a voltage between 2.7 and 5.5V to the Vcc pin. Tie the CS/WDI pin, the WP pin, AND THE SCK pin HIGH. RESET and SO pins are left unconnected. Then apply the programming voltage Vp to the SI pin ONLY and pulse CS/WDI LOW then HIGH. Remove Vp and the sequence is complete. Figure 2. Reset VTRIP Voltage VCC THRESHOLD RESET PROCEDURE The X51638 is offered with one of several standard Vcc threshold (VTRIP) voltages. This value will not change over normal operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or for higher precision in the VTRIP value, the X51638 threshold may be adjusted. CS SCK Vcc Vp SI Setting the VTRIP Voltage This procedure sets the VTRIP to a higher voltage value. For example, if the current VTRIP is 4.4V and the new VTRIP is 4.6V, this procedure directly makes the change. If the new setting is lower than the current setting, then it is necessary to reset the trip point before setting the new value. 3 X51638 Figure 3. VTRIP Programming Sequence Flow Chart VTRIP Programming Execute Reset VTRIP Sequence Set Vcc = Vcc applied = Desired VTRIP New Vcc applied = Old Vcc applied + Error Execute Set VTRIP Sequence New Vcc applied = Old Vcc applied - Error Apply 5V to Vcc Execute Reset VTRIP Sequence Decrement Vcc (Vcc = Vcc - 50mV) NO RESET pin goes active? YES Error < 0 Measured VTRIP Desired VTRIP Error > 0 Error = 0 DONE Figure 4. Sample VTRIP Reset Circuit VP NC 4.7K 1 NC VTRIP + Adj. X51638 RESET 8 2 7 3 6 4 5 4.7K NC Program 10K 4 10K Reset VTRIP Test VTRIP Set VTRIP X51638 SPI SERIAL MEMORY Write Enable Latch The device contains a Write Enable Latch. This latch must be SET before a Write Operation is initiated. The WREN instruction will set the latch and the WRDI instruction will reset the latch (Figure 3). This latch is automatically reset upon a power-up condition and after the completion of a valid Write Cycle. The memory portion of the device is a CMOS Serial EEPROM array with Xicor’s Block LockTM Protection. The array is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Xicor’s proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. Status Register The RDSR instruction provides access to the Status Register. The Status Register may be read at any time, even during a Write Cycle. The Status Register is formatted as follows: The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. It contains an 8-bit instruction register that is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS must be LOW during the entire operation. 7 6 WPEN FLB All instructions (Table 1), addresses and data are transferred MSB first. Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off. 5 4 WD1 WD0 3 2 1 0 BL1 BL0 WEL WIP The Write-In-Progress (WIP) bit is a volatile, read only bit and indicates whether the device is busy with an internal nonvolatile write operation. The WIP bit is read using the RDSR instruction. When set to a “1”, a nonvolatile write operation is in progress. When set to a “0”, no write is in progress. Table 1. Instruction Set Instruction Name Instruction Format* Operation WREN 0000 0110 Set the Write Enable Latch (Enable Write Operations) SFLB 0000 0000 Set Flag Bit WRDI/RFLB 0000 0100 Reset the Write Enable Latch/Reset Flag Bit RSDR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register(Watchdog,BlockLock,WPEN & Flag Bits) READ 0000 0011 Read Data from Memory Array Beginning at Selected Address WRITE 0000 0010 Write Data to Memory Array Beginning at Selected Address *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first. Table 2. Block Protect Matrix WREN CMD STATUS REGISTER DEVICE PIN BLOCK BLOCK STATUS REGISTER UNPROTECTED BLOCK WPEN, BL0, BL1 WD0, WD1 WEL WPEN WP# PROTECTED BLOCK 0 X X Protected Protected Protected 1 1 0 Protected Writable Protected 1 0 X Protected Writable Writable 1 X 1 Protected Writable Writable 5 X51638 The Write Enable Latch (WEL) bit indicates the Status of the Write Enable Latch. When WEL=1, the latch is set HIGH and when WEL=0 the latch is reset LOW. The WEL bit is a volatile, read only bit. It can be set by the WREN instruction and can be reset by the WRDS instruction. Status Register Bits The Block Lock bits, BL0 and BL1, set the level of Block LockTM Protection. These nonvolatile bits are programmed using the WRSR instruction and allow the user to protect one quarter, one half, all or none of the EEPROM array. Any portion of the array that is Block Lock Protected can be read but not written. It will remain protected until the BL bits are altered to disable Block Lock Protection of that portion of memory. Status Register Bits BL0 X516x 0 0 None 0 1 $0600–$07FF 1 0 $0400–$07FF 1 1 $0000–$07FF WD0 0 0 1.4 Seconds 0 1 600 Milliseconds 1 0 400 Milliseconds 1 1 Disabled The FLAG bit shows the status of a volatile latch that can be set and reset by the system using the SFLB and RFLB instructions. The Flag bit is automatically reset upon power up. This flag can be used by the system to determine whether a reset occurs as a result of a watchdog time-out or power failure. Array Addresses Protected BL1 Watchdog Time-out (Typical) WD1 The nonvolatile WPEN bit is programmed using the WRSR instruction. This bit works in conjunction with the WP pin to provide an In-Circuit Programmable ROM function (Table 2). WP is LOW and WPEN bit programmed HIGH disables all Status Register Write Operations. In Circuit Programmable ROM Mode This mechanism protects the Block Lock and Watchdog bits from inadvertant corruption. The Watchdog Timer bits, WD0 and WD1, select the Watchdog Time-out Period. These nonvolatile bits are programmed with the WRSR instruction. In the locked state (Programmable ROM Mode) the WP pin is LOW and the nonvolatile bit WPEN is “1”. This mode disables nonvolatile writes to the device’s Status Register. Figure 5. Read EEPROM Array Sequence CS 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 SCK INSTRUCTION 16 BIT ADDRESS 15 14 13 SI 3 2 1 0 DATA OUT HIGH IMPEDANCE 7 SO MSB 6 6 5 4 3 2 1 0 X51638 Setting the WP pin LOW while WPEN is a “1” while an internal write cycle to the Status Register is in progress will not stop this write operation, but the operation disables subsequent write attempts to the Status Register. must then be taken HIGH. If the user continues the Write Operation without taking CS HIGH after issuing the WREN instruction, the Write Operation will be ignored. To write data to the EEPROM memory array, the user then issues the WRITE instruction followed by the 16 bit address and then the data to be written. Any unused address bits are specified to be “0’s”. The WRITE operation minimally takes 32 clocks. CS must go low and remain low for the duration of the operation. If the address counter reaches the end of a page and the clock continues, the counter will roll back to the first address of the page and overwrite any data that may have been previously written. When WP is HIGH, all functions, including nonvolatile writes to the Status Register operate normally. Setting the WPEN bit in the Status Register to “0” blocks the WP pin function, allowing writes to the Status Register when WP is HIGH or LOW. Setting the WPEN bit to “1” while the WP pin is LOW activates the Programmable ROM mode, thus requiring a change in the WP pin prior to subsequent Status Register changes. This allows manufacturing to install the device in a system with WP pin grounded and still be able to program the Status Register. Manufacturing can then load Configuration data, manufacturing time and other parameters into the EEPROM, then set the portion of memory to be protected by setting the Block Lock bits, and finally set the “OTP mode” by setting the WPEN bit. Data changes now require a hardware change. For the Page Write Operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed (Figure 4). To write to the Status Register, the WRSR instruction is followed by the data to be written (Figure 5). Data bits 0 and 1 must be “0” . Read Sequence When reading from the EEPROM memory array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 16-bit address. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS high. Refer to the Read EEPROM Array Sequence (Figure 1). While the write is in progress following a Status Register or EEPROM Sequence, the Status Register may be read to check the WIP bit. During this time the WIP bit will be high. OPERATIONAL NOTES The device powers-up in the following state: • The device is in the low power standby state. • A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. • SO pin is high impedance. • The Write Enable Latch is reset. • The Flag Bit is reset. • Reset Signal is active for tPURST. To read the Status Register, the CS line is first pulled low to select the device followed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the Status Register are shifted out on the SO line. Refer to the Read Status Register Sequence (Figure 2). Data Protection The following circuitry has been included to prevent inadvertent writes: • A WREN instruction must be issued to set the Write Enable Latch. • CS must come HIGH at the proper clock count in order to start a nonvolatile write cycle. Write Sequence Prior to any attempt to write data into the device, the “Write Enable” Latch (WEL) must first be set by issuing the WREN instruction (Figure 3). CS is first taken LOW, then the WREN instruction is clocked into the device. After all eight bits of the instruction are transmitted, CS 7 X51638 Figure 6. Read Status Register Sequence CS 0 1 2 3 4 5 6 7 8 9 10 7 6 5 11 12 13 14 SCK INSTRUCTION SI DATA OUT SO HIGH IMPEDANCE MSB Figure 7. Write Enable Latch Sequence CS 0 1 2 3 4 SCK SI SO HIGH IMPEDANCE 8 5 6 7 4 3 2 1 0 X51638 Figure 8. Write Sequence CS 0 1 2 3 4 5 6 7 8 9 15 14 10 20 21 22 23 24 25 26 1 0 7 6 5 27 28 29 30 31 1 0 SCK INSTRUCTION 16 BIT ADDRESS SI 13 3 DATA BYTE 1 2 4 3 2 CS 32 33 34 7 6 5 35 36 37 38 39 40 41 42 1 0 7 6 5 43 44 45 46 47 1 0 SCK DATA BYTE 2 SI 4 3 DAT A BYTE 3 2 4 3 2 DATA BYTE N 6 5 4 3 13 14 15 1 0 2 1 0 Figure 9. Status Register Write Sequence CS 0 1 2 3 4 5 6 7 8 9 10 7 6 5 11 12 SCK DATA BYTE INSTRUCTION SI SO 4 3 2 HIGH IMPEDANCE Symbol Table WAVEFORM 9 INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance X51638 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature under Bias ........................–65°C to +135°C Storage Temperature .............................–65°C to +150°C Voltage on any Pin with Respect to VSS....... –1.0V to +7V D.C. Output Current ....................................................5mA Lead Temperature (Soldering, 10 seconds)............ 300°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Commercial 0°C 70°C –1.8 Industrial –40°C +85°C –2.7 or -2.7A Voltage Option Supply Voltage 1.8V-3.6V 2.7V to 5.5V 4.5V-5.5V Blank or -4.5A D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Typ. Max. Units Test Conditions ICC1 VCC Write Current (Active) 5 mA SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO = Open ICC2 VCC Read Current (Active) 0.4 mA SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO = Open ISB1 VCC Standby Current WDT=OFF 1 µA ISB2 VCC Standby Current WDT=ON 50 µA ISB3 VCC Standby Current WDT=ON 20 µA ILI Input Leakage Current 0.1 10 µA VIN = VSS to VCC ILO Output Leakage Current 0.1 10 µA VOUT = VSS to VCC VIL(1) Input LOW Voltage –0.5 VCCx0.3 V VIH(1) Input HIGH Voltage VCCx0.7 VCC+0.5 V VOL1 Output LOW Voltage 0.4 V VCC > 3.3V, IOL = 2.1mA VOL2 Output LOW Voltage 0.4 V 2V < VCC £ 3.3V, IOL = 1mA VOL3 Output LOW Voltage 0.4 V VCC £ 2V, IOL = 0.5mA VOH1 Output HIGH Voltage VCC–0.8 V VCC > 3.3V, IOH = –1.0mA VOH2 Output HIGH Voltage VCC–0.4 V 2V < VCC £ 3.3V, IOH = –0.4mA VOH3 Output HIGH Voltage VCC–0.2 V VCC £ 2V, IOH = –0.25mA VOLS Reset Output LOW Voltage V IOL = 1mA 0.4 10 CS = VCC, VIN = VSS or VCC, VCC = 5.5V CS = VCC, VIN = VSS or VCC, VCC = 5.5V CS = VCC, VIN = VSS or VCC, VCC =3.6V X51638 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V. Symbol Test (2) Output Capacitance (SO, RESET) COUT (2) Input Capacitance (SCK, SI, CS, WP) CIN Notes: Max. Units Conditions 8 pF VOUT = 0V 6 pF VIN = 0V (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC 5V A.C. TEST CONDITIONS Input Pulse Levels 5V Input Rise and Fall Times 3.3KW 1.64KW SO OUTPUT 1.64KW Input and Output Timing Level RESET 100pF 30pF 11 VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 X51638 A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Serial Input Timing 1.8-3.6V Symbol Parameter 2.7-5.5V Min. Max. Min. Max. Units 0 1 0 2 MHz fSCK Clock Frequency tCYC Cycle Time 1000 500 ns tLEAD CS Lead Time 500 250 ns tLAG CS Lag Time 500 250 ns tWH Clock HIGH Time 400 200 ns tWL Clock LOW Time 400 250 ns tSU Data Setup Time 50 50 ns tH Data Hold Time 50 50 ns tRI(3) Input Rise Time 100 100 ns tFI(3) Input Fall Time 100 100 ns tCS CS Deselect Time tWC (4) 500 500 Write Cycle Time ns 10 10 ms Serial Input Timing tCS CS tLEAD tLAG SCK tSU SI tH tRI MSB IN t FI LSB IN HIGH IMPEDANCE SO 12 X51638 Serial Output Timing 1.8-3.6V Symbol Parameter 2.7-5.5V Min. Max. Min. Max. Units 0 1 0 2 MHz fSCK Clock Frequency tDIS Output Disable Time 250 250 ns tV Output Valid from Clock Low 400 250 ns tHO Output Hold Time tRO(3) Output Rise Time 100 100 ns tFO(3) Output Fall Time 100 100 ns Notes: 0 0 ns (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Serial Output Timing CS t CYC tWH t LAG SCK tV SO SI MSB OUT tHO MSB–1 OUT t WL tDIS LSB OUT ADDR LSB IN 13 X51638 Power-Up and Power-Down Timing VTRIP V TRIP VCC t PURST 0 Volts t PURST t F t RPD tR RESET RESET Output Timing Symbol Parameter Min. Typ. Max. Units 4.5 4.25 2.85 2.55 1.7 4.62 4.38 2.92 2.62 1.75 4.75 4.5 3.0 2.7 1.8 V VTRIP Reset Trip Point Voltage, X51638-4.5A Reset Trip Point Voltage, X51638 Reset Trip Point Voltage, X51638-2.7A Reset Trip Point Voltage, X51638-2.7 Reset Trip Point Voltage, X51638-1.8 VTH(5) VTRIP Hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) tPURST Power-up Reset Timeout tRPD(5) VCC Detect to Reset/Output tF(5) VCC Fall Time 100 ms tR(5) VCC Rise Time 100 ms VRVALID Reset Valid VCC 1 V Notes: 20 500 (5) This parameter is periodically sampled and not 100% tested. 14 800 mV 1400 ms 500 ns X51638 CS/WDI vs. RESET Timing CS/WDI t CST RESET t WDO t WDO t RST t RST RESET Output Timing (WD1 = 1, WD0 = 0) Symbol Parameter Min. Typ. Max. Units tWDO Watchdog Timeout Period 300 400 550 ms tCST CS Pulse Width to Reset the Watchdog 400 tRST Reset Timeout 200 400 600 ms Parameter Min. Typ. Max. Units tWDO Watchdog Timeout Period 450 600 800 ms tCST CS Pulse Width to Reset the Watchdog 400 tRST Reset Timeout 100 200 300 ms Min. Typ. Max. Units 1 1.4 2 sec ns RESET Output Timing (WD1 = 0, WD0 = 1) Symbol ns RESET Output Timing (WD1 = 0, WD0 = 0) Symbol Parameter tWDO Watchdog Timeout Period tCST CS Pulse Width to Reset the Watchdog 400 tRST Reset Timeout 100 15 ns 200 300 ms X51638 VTRIP Set Conditions tTHD Vcc VTrip tTSU tRP tP tVPS CS tVPH tVPH tVPS tVPO Vp SCK Vp tVPO SI VTRIP Reset Conditions tTHD Vcc VTrip tTSU tVPS CS SCK tRP tP tVPS tVP1 tVPH tVPO Vcc Vp tVPO SI 16 X51638 Table 3. VTRIP Programming Specifications: Vcc=1.7-5.5V; Temperature = 0oC to 70oC Parameter Description Min Max Units tVPS SCK VTRIP Program Voltage Setup time 1 ms tVPH SCK VTRIP Program Voltage Hold time 1 ms tP VTRIP Program Pulse Width 1 ms tTSU VTRIP Level Setup time 10 ms tTHD VTRIP Level Hold (stable) time 10 ms tWC VTRIP Write Cycle Time tRP VTRIP Program Cycle Recovery Period (Between successive programming cycles) 10 ms tVPO SCK VTRIP Program Voltage Off time before next cycle 0 ms Vp Programming Voltage 15 18 V VTRIP VTRIP Programed Voltage 1.7 5.0 V Vta VTRIP Programed Voltage accuracy (Vcc applied - VTRIP) -0.3 +0.3 V Vtr VTRIP Programed Voltage repeatability (Successive program operations.) -5 +5 mV 10 VTRIP Programming parameters are periodically sampled and are not 100% Tested. 17 ms X51638 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) PIN 1 INDEX PIN 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25) 0.050 (1.27) 0.010 (0.25) 0.020 (0.50) X 45° 0.050" TYPICAL 0.050" TYPICAL 0° – 8° 0.0075 (0.19) 0.010 (0.25) 0.250" 0.016 (0.410) 0.037 (0.937) FOOTPRINT NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 18 0.030" TYPICAL 8 PLACES X51638 14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V .025 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .193 (4.9) .200 (5.1) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15) .010 (.25) Gage Plane 0° – 8° Seating Plane .019 (.50) .029 (.75) Detail A (20X) .031 (.80) .041 (1.05) See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 19 X51638 Ordering Information Vcc Range 4.5-5.5V VTRIP Range 4.5-4.75 Package Operating Temperature Range PART NUMBER RESET (Active LOW) 8 pin PDIP 0oC - 70oC X51638P-4.5A o 8L SOIC 8 pin PDIP 4.5-5.5V 4.25-4.5 8L SOIC 2.7-5.5V 1.8-3.6V 2.85-3.0 2.55-2.7 1.7-1.8V 0 C - 70 C X51638S8-4.5A -40oC - 85oC X51638S8I-4.5A 0oC - 70oC X51638P 0oC - 70oC X51638S8 -40oC 14L TSSOP 2.7-5.5V o - 85oC 0°c - 70°C oC 0 8L SOIC - 70oC W X X51638V14 X51638S8-2.7A -40oC - 85oC X51638S8I-2.7A 14L TSSOP 0oC - 70oC X51638V14-2.7A 8L SOIC 0oC - 70oC X51638S8-2.7 o o 14L TSSOP 0 C - 70 C X51638V14-2.7 8L SOIC 0oC - 70oC X51638S8-1.8 14L TSSOP 0oC - 70oC X51638V14-1.8 Part Mark Information X51638 X51638S8I P = 8-Pin DIP Blank = 8-Lead SOIC V = 14 Lead TSSOP Blank = 5V ±10%, 0°C to +70°C, VTRIP=4.25-4.5 AL=5V±10%, 0°C to +70°C, VTRIP = 4.5-4.75 I = 5V ±10%, –40°C to +85°C, VTRIP=4.25-4.5 AM = 5V ±10%, –40°C to +85°C, VTRIP=4.5-4.75 F = 2.7V to 5.5V, 0°C to +70°C, VTRIP=2.55-2.7 AN = 2.7V to 5.5V, 0°C to +70°C, VTRIP=2.85-3.0 G = 2.7V to 5.5V, –40°C to +85°C, VTRIP=2.55-2.7 AP = 2.7V to 5.5V, –40°C to +85°C, VTRIP=2.85-3.0 AG = 1.8V to 3.6V, 0°C to +70°C, VTRIP=1.7-1.8 AH = 1.8V to 3.6V, –40°C to +85°C, VTRIP=1.7-1.8 20 X51638 LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 21