APPLICATION NOTE
A V A I L A B L E
AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135
Low Noise/Low Power/SPI Bus/256 Taps
X9250
Quad Digitally Controlled Potentiometers (XDCP™)
FEATURES
DESCRIPTION
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The X9250 integrates 4 digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated circuit.
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Four potentiometers in one package
256 resistor taps/pot–0.4% resolution
SPI serial interface
Wiper resistance, 40Ω typical @ VCC = 5V
Four nonvolatile data registers for each pot
Nonvolatile storage of wiper position
Standby current < 5µA max (total package)
Power supplies
—VCC = 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V
100KΩ, 50KΩ total pot resistance
High reliability
—Endurance – 100,000 data changes per bit per
register
—Register data retention – 100 years
24-lead SOIC, 24-lead TSSOP, 24-lead CSP (Chip
Scale Package)
Dual supply version of X9251
The digitally controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to
the wiper terminal through switches. The position of
the wiper on the array is controlled by the user through
the SPI bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and 4 nonvolatile Data Registers (DR0:DR3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array though the switches. Power
up recalls the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
VCC
VSS
V+
V-
Pot 0
R0 R1
R2 R3
HOLD
CS
SCK
SO
SI
A0
A1
Interface
and
Control
Circuitry
WP
VL0/RL0
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 2
VH2/RH2
VL2/RL2
VW0/RW0
VW2/RW2
VW1/RW1
VW3/RW3
8
Data
R0 R1
R2 R3
REV 1.1.5 1/31/03
VH0/RH0
Wiper
Counter
Register
(WCR)
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot1
VH1/RH1
VL1/RL1
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R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 3
VH3/RH3
VL3/RH3
Characteristics subject to change without notice.
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X9250
PIN DESCRIPTIONS
VW/RW (VW0/RW0–VW3/RW3)
Serial Output (SO)
SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9250.
The wiper pins are equivalent to the wiper terminal of
a mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
Analog Supplies (V+, V-)
The analog supplies V+, V- are the supply voltages for
the XDCP analog section.
PIN CONFIGURATION
Chip Select (CS)
When CS is HIGH, the X9250 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9250, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
SOIC/TSSOP
S0
1
24
HOLD
A0
2
23
SCK
VW3/RW3
3
22
VL2/RL2
VH3/RH3
4
21
VH2/RL2
VL3/RL3
5
20
VW2/RW2
19
V–
18
VSS
V+
6
VCC
7
VL0/RL0
8
17
VW1/RW1
VH0/RH0
9
16
VH1/RH1
VW0/RW0
10
15
VL1/RL1
CS
11
14
A1
WP
12
13
SI
1
A
Device Address (A0–A1)
The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9250. A maximum of 4 devices may occupy the
SPI serial bus.
B
C
D
E
F
Potentiometer Pins
X9250
CSP
2
3
R W0 CS
4
A 1 RL1
RL0 WP SI
RW1
VCC RH0 RH1 VSS
V+ RH3 RH2 VRL3 SO HOLD RW2
RW3 A0 SCK RL2
Top View–Bumps Down
VH/RH (VH0/RH0–VH3/RH3), VL/RL (VL0/RL0–VL3/RL3)
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer.
REV 1.1.5 1/31/03
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Characteristics subject to change without notice.
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X9250
PIN NAMES
Symbol
Description
SCK
Serial Clock
SI, SO
Serial Data
A0-A1
Device Address
VH0/RH0–VH3/RH3,
VL0/RL0–VL3/RL3
Potentiometer Pins
(terminal equivalent)
VW0/RW0–VW3/RW3
Potentiometer Pins
(wiper equivalent)
WP
Hardware Write Protection
V+,V-
Analog Supplies
VCC
System Supply Voltage
VSS
System Ground
NC
No Connection
Wiper Counter Register (WCR)
The X9250 contains four Wiper Counter Registers,
one for each XDCP potentiometer. The WCR is
equivalent to a serial-in, parallel-out register/counter
with its outputs decoded to select one of 256 switches
along its resistor array. The contents of the WCR can
be altered in four ways: it may be written directly by the
host via the write Wiper Counter Register instruction
(serial load); it may be written indirectly by transferring
the contents of one of four associated Data Registers
via the XFR Data Register or Global XFR Data
Register instructions (parallel load); it can be modified
one step at a time by the increment/decrement
instruction. Finally, it is loaded with the contents of its
Data Register zero (DR0) upon power-up.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9250 is powereddown. Although the register is automatically loaded
with the value in R0 upon power-up, this may be
different from the value present at power-down.
DEVICE DESCRIPTION
Serial Interface
The X9250 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9250 is comprised of four resistor arrays. Each
array contains 255 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (VH/RH and VL/RL inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(VW/RW) output. Within each individual array only one
switch may be turned on at a time.
Data Registers
Each potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonvolatile operation and will take
a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Data Register Detail
(MSB)
(LSB)
D7
D6
D5
D4
D3
D2
D1
D0
NV
NV
NV
NV
NV
NV
NV
NV
These switches are controlled by a Wiper Counter
Register (WCR). The 8 bits of the WCR are decoded
to select, and enable, one of 256 switches.
REV 1.1.5 1/31/03
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Characteristics subject to change without notice.
3 of 21
X9250
Figure 1. Detailed Potentiometer Block Diagram
(One of Four Arrays)
Serial Data Path
VH/RH
Serial
Bus
Input
From Interface
Circuitry
Register 0
8
Register 2
C
o
u
n
t
e
r
Register 1
8
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
Register 3
D
e
c
o
d
e
Inc/Dec
Logic
If WCR = 00[H] then VW/RW = VL/RL
UP/DN
If WCR = FF[H] then VW/RW = VH/RH
Modified SCK
UP/DN
VL/RL
CLK
VW/RW
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a write in process bit
(WIP). The WIP bit is read with a read status
command.
Figure 2. Identification Byte Format
INSTRUCTIONS
Instruction Byte
The next byte sent to the X9250 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the four pots and, when applicable,
they point to one of four associated registers. The
format is shown below in Figure 3.
Identification (ID) Byte
The first byte sent to the X9250 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9250 this is fixed as 0101[B] (refer to Figure 2).
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A0-A1 input pins.
The X9250 compares the serial data stream with the
address input state; a successful compare of both
address bits is required for the X9250 to successfully
continue the command sequence. The A0–A1 inputs
can be actively driven by CMOS input signals or tied to
VCC or VSS.
Device Type
Identifier
0
1
0
1
0
0
A1
A0
Device Address
Figure 3. Instruction Byte Format
Register
Select
I3
I2
I1
Instructions
I0
R1
R0
P1
P0
Pot Select
The remaining two bits in the slave byte must be set to 0.
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Characteristics subject to change without notice.
4 of 21
X9250
The four high order bits of the instruction byte specify
the operation. The next two bits (R1 and R0) select one
of the four registers that is to be acted upon when a
register oriented instruction is issued. The last two bits
(P1 and P0) selects which one of the four
potentiometers is to be affected by the instruction.
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte. These
instructions are:
– XFR Data Register to Wiper Counter Register—This
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.
– XFR Wiper Counter Register to Data Register—This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.
– Global XFR Data Register to Wiper Counter Register—
This transfers the contents of all specified Data Registers to the associated Wiper Counter Registers.
– Global XFR Wiper Counter Register to Data Register—
This transfers the contents of all Wiper Counter Registers to the specified associated Data Registers.
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper
to this action will be delayed by tWRL. A transfer from
the WCR (current wiper position), to a Data Register is
a write to nonvolatile memory and takes a minimum of
tWR to complete. The transfer can occur between one of
the four potentiometers and one of its associated
registers; or it may occur globally, where the transfer
occurs between all potentiometers and one associated
register.
REV 1.1.5 1/31/03
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9250; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register. These instructions are:
– Read Wiper Counter Register—read the current
wiper position of the selected pot,
– Write Wiper Counter Register—change current wiper
position of the selected pot,
– Read Data Register—read the contents of the
selected data register;
– Write Data Register—write a new value to the
selected data register.
– Read Status—This command returns the contents of
the WIP bit which indicates if the internal write cycle
is in progress.
The sequence of these operations is shown in Figure 5
and Figure 6.
The final command is Increment/Decrement. It is
different from the other commands, because it’s length
is indeterminate. Once the command is issued, the
master can clock the selected wiper up and/or down in
one resistor segment steps; thereby, providing a fine
tuning capability to the host. For each SCK clock pulse
(tHIGH) while SI is HIGH, the selected wiper will move
one resistor segment towards the VH/RH terminal.
Similarly, for each SCK clock pulse while SI is LOW, the
selected wiper will move one resistor segment towards
the VL/RL terminal. A detailed illustration of the sequence
and timing for this operation are shown in Figure 7 and
Figure 8.
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Characteristics subject to change without notice.
5 of 21
X9250
Figure 4. Two-Byte Instruction Sequence
CS
SCK
SI
0
1
0
1
0
0
A1
A0
I3
I2
I1
I0
R1 R0
P1 P0
Figure 5. Three-Byte Instruction Sequence (Write)
CS
SCL
SI
0
1
0
0
1
0
A1 A0
I3
I2
I1 I0
R1 R0 P1 P0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 6. Three-Byte Instruction Sequence (Read)
CS
SCL
SI
Don’t Care
0
1
0
0
1
0
A1 A0
I3
I2
I1 I0
R1 R0 P1 P0
S0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 7. Increment/Decrement Instruction Sequence
CS
SCK
SI
0
REV 1.1.5 1/31/03
1
0
1
0
0
A1 A0
I3
I2
I1
I0
0
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0
P1
P0
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
Characteristics subject to change without notice.
D
E
C
n
6 of 21
X9250
Figure 8. Increment/Decrement Timing Limits
tWRID
SCK
SI
Voltage Out
VW/RW
INC/DEC CMD Issued
Table 1. Instruction Set
Instruction
I3
I2
Instruction Set
I1
I0 R1 R0
P1
P0
Operation
Read Wiper Counter
Register
Write Wiper Counter
Register
Read Data Register
1
0
0
1
0
0
P1
P0
1
0
1
0
0
0
P1
P0
1
0
1
1
R1
R0
P1
P0
Write Data Register
1
1
0
0
R1
R0
P1
P0
XFR Data Register to
Wiper Counter Register
1
1
0
1
R1
R0
P1
P0
XFR Wiper Counter
Register to Data Register
1
1
1
0
R1
R0
P1
P0
Global XFR Data Register
to Wiper Counter Register
0
0
0
1
R1
R0
0
0
Global XFR Wiper Counter
Register to Data Register
1
0
0
0
R1
R0
0
0
Increment/Decrement
Wiper Counter Register
Read Status (WIP bit)
0
0
1
0
0
0
P1
P0
0
1
0
1
0
0
0
1
Read the contents of the Wiper Counter
Register pointed to by P1-P0
Write new value to the Wiper Counter
Register pointed to by P1-P0
Read the contents of the Data Register
pointed to by P1-P0 and R1–R0
Write new value to the Data Register pointed
to by P1-P0 and R1–R0
Transfer the contents of the Data Register
pointed to by R1–R0 to the Wiper Counter
Register pointed to by P1-P0
Transfer the contents of the Wiper Counter
Register pointed to by P1-P0 to the Register
pointed to by R1–R0
Transfer the contents of the Data Registers
pointed to by R1–R0 of all four pots to their
respective Wiper Counter Register
Transfer the contents of all Wiper Counter
Registers to their respective data Registers
pointed to by R1–R0 of all four pots
Enable Increment/decrement of the Wiper
Counter Register pointed to by P1-P0
Read the status of the internal write cycle,
by checking the WIP bit.
REV 1.1.5 1/31/03
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Characteristics subject to change without notice.
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X9250
Instruction Format
Notes: (1)
(2)
(2)
(3)
“A1 ~ A0”: stands for the device addresses sent by the master.
WPx refers to wiper position data in the Counter Register
“I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
“D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register(WCR)
device type
identifier
device
addresses
instruction
opcode
CS
Falling
Edge 0 1 0 1 0 0 A A 1
1 0
0
0
WCR
addresses
1
0
wiper position
(sent by X9250 on SO)
CS
W W W W W W W W Rising
P P
0
P P P P P P P P Edge
1 0
7 6 5 4 3 2 1 0
Write Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
CS
Falling
Edge 0 1 0 1 0 0 A A 1
1 0
0
1
WCR
addresses
0
0
Data Byte
(sent by Host on SI)
CS
W W W W W W W W Rising
P P
0
P P P P P P P P Edge
1 0
7 6 5 4 3 2 1 0
Read Data Register (DR)
device type
device
instruction DR and WCR
Data Byte
identifier
addresses
opcode
addresses
(sent by X9250 on SO)
CS
CS
Falling
Rising
W W W W W W W W
Edge 0 1 0 1 0 0 A A 1 0 1 1 R R P P P P P P P P P P Edge
1 0
1 0 1 0
7 6 5 4 3 2 1 0
Write Data Register (DR)
device type
device
identifier
addresses
instruction
opcode
DR and WCR
addresses
CS
Falling
Edge 0 1 0 1 0 0 A A 1 1 0 0 R
1 0
1
R
0
P
1
Data Byte
(sent by host on SI)
CS
W W W W W W W W Rising
P
P P P P P P P P Edge
0
7 6 5 4 3 2 1 0
HIGH-VOLTAGE
WRITE CYCLE
Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
device
instruction DR and WCR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 1 1 0 1 R R P P Edge
1 0
1 0 1 0
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Characteristics subject to change without notice.
8 of 21
X9250
Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
device
instruction DR and WCR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 1 1 1 0 R R P P Edge
1 0
1 0 1 0
HIGH-VOLTAGE
WRITE CYCLE
Increment/Decrement Wiper Counter Register (WCR)
device type
device
instruction
WCR
increment/decrement
CS
CS
identifier
addresses
opcode
addresses
(sent by master on SI)
Falling
Rising
Edge 0 1 0 1 0 0 A A 0 0 1 0 X X P P I/D I/D . . . . I/D I/D Edge
1 0
1 0
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
device
instruction
DR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 0 0 0 1 R R 0 0 Edge
1 0
1 0
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
device
instruction
DR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 1 0 0 0 R R 0 0 Edge
1 0
1 0
HIGH-VOLTAGE
WRITE CYCLE
Read Status
device type
device
instruction
Data Byte
identifier
addresses
opcode
(sent by X9250 on SO)
CS
CS
Falling
Rising
W
Edge 0 1 0 1 0 0 A A 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 I Edge
1 0
P
REV 1.1.5 1/31/03
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Characteristics subject to change without notice.
9 of 21
X9250
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias........................ –65 to +135°C
Storage temperature............................. –65 to +150°C
Voltage on SCK, SCL or any address input
with respect to VSS ................................. –1V to +7V
Voltage on V+ (referenced to VSS) .........................10V
Voltage on V- (referenced to VSS) ........................ -10V
(V+) – (V-) ..............................................................12V
Any VH/RH ...............................................................V+
Any VL/RL .................................................................VLead temperature (soldering, 10 seconds) ........ 300°C
IW (10 seconds) ................................................±15mA
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Device
Supply Voltage (VCC) Limits
Commercial
0°C
+70°C
X9250
5V ±10%
Industrial
–40°C
+85°C
X9250-2.7
2.7V to 5.5V
POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Max.
Unit
End to end resistance tolerance
±20
%
Power rating
50
mW
IW
Wiper current
±7.5
mA
RW
Wiper resistance
250
Ω
Vv+
Voltage on V+ pin
V
VvVTERM
Parameter
Min.
150
Voltage on V- pin
X9250
+4.5
+5.5
X9250-2.7
+2.7
+5.5
X9250
-5.5
-4.5
X9250-2.7
-5.5
-2.7
V-
V+
Voltage on any VH/RH or VL/RL pin
Noise
Resolution
(4)
Absolute linearity
Relative
Typ.
Temperature coefficient of RTOTAL
0.6
%
CH/CL/CW Potentiometer Capacitances
MI(3)
Vw(n)(actual)–Vw(n)(expected)
±0.6
MI(3)
Vw(n + 1)–[Vw(n) + MI]
ppm/°C
±20
10/10/25
Ref: 1kHz
±1
±300
Ratiometric Temperature
Coefficient
Wiper current = ± 1mA
V
dBV
linearity (2)
25°C, each pot
V
-120
(1)
Test Conditions
ppm/°C
pF
See Circuit #3
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/255 or (VH/RH–VL/RL)/255, single pot
(4) Individual array resolutions.
REV 1.1.5 1/31/03
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Characteristics subject to change without notice.
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X9250
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
ICC1
VCC supply current
(active)
400
µA
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
ICC2
VCC supply current
(nonvolatile write)
1
mA
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
ISB
VCC current (standby)
5
µA
SCK = SI = VSS, Addr. = VSS
ILI
Input leakage current
10
µA
VIN = VSS to VCC
VOUT = VSS to VCC
ILO
Output leakage current
10
µA
VIH
Input HIGH voltage
VCC x 0.7
VCC + 0.1
V
VIL
Input LOW voltage
–0.5
VCC x 0.3
V
VOL
Output LOW voltage
0.4
V
IOL = 3mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Unit
Minimum endurance
100,000
Data changes per bit per register
Data retention
100
Years
CAPACITANCE
Symbol
(5)
COUT
(5)
CIN
Test
Max.
Unit
Test Conditions
Output capacitance (SO)
8
pF
VOUT = 0V
Input capacitance (A0, A1, SI, and SCK, CS)
6
pF
VIN = 0V
POWER-UP TIMING
Symbol
(6)
(6)
tPUR
tPUW
(7)
tR VCC
Parameter
Min.
Max.
Unit
Power-up to initiation of read operation
1
ms
Power-up to initiation of write operation
5
ms
50
V/msec
VCC power up ramp rate
0.2
POWER UP AND DOWN REQUIREMENT
The are no restrictions on the sequencing of the bias supplies VCC, V+, and V- provided that all three supplies reach
their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than
V+ and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach
their final value. The VCC ramp rate spec is always in effect.
Notes: (5) This parameter is periodically sampled and not 100% tested
(6) tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific instruction can
be issued. These parameters are periodically sampled and not 100% tested.
(7) Sample tested only.
A.C. TEST CONDITIONS
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
REV 1.1.5 1/31/03
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Characteristics subject to change without notice.
11 of 21
X9250
Circuit #3 SPICE Macro Model
EQUIVALENT A.C. LOAD CIRCUIT
5V
2.7V
RTOTAL
RH
RL
CL
CH
CW
10pF
1533Ω
10pF
SDA Output
25pF
100pF
100pF
RW
AC TIMING
Symbol
Parameter
Min.
Max.
Unit
2.0
MHz
fSCK
SSI/SPI clock frequency
tCYC
SSI/SPI clock cycle time
500
ns
tWH
SSI/SPI clock high time
200
ns
tWL
SSI/SPI clock low time
200
ns
tLEAD
Lead time
250
ns
tLAG
Lag time
250
ns
tSU
SI, SCK, HOLD and CS input setup time
50
ns
tH
SI, SCK, HOLD and CS input hold time
75
ns
tRI
SI, SCK, HOLD and CS input rise time
tFI
SI, SCK, HOLD and CS input fall time
tDIS
SO output disable Time
0
2
µs
2
µs
500
ns
100
ns
tV
SO output valid time
tHO
SO output hold time
tRO
SO output rise time
50
ns
tFO
SO output fall time
50
ns
0
ns
tHOLD
HOLD time
400
ns
tHSU
HOLD setup time
100
ns
tHH
HOLD hold time
100
tHZ
HOLD low to output in high Z
100
ns
tLZ
HOLD high to output in low Z
100
ns
TI
Noise suppression time constant at SI, SCK, HOLD and CS inputs
TBD
ns
ns
CS deselect time
2
µs
tWPASU
WP, A0 and A1 setup time
0
ns
tWPAH
WP, A0 and A1 hold time
0
ns
tCS
REV 1.1.5 1/31/03
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Characteristics subject to change without notice.
12 of 21
X9250
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
tWR
High-voltage write cycle time (store instructions)
Typ.
Max.
Unit
5
10
ms
XDCP TIMING
Symbol
tWRPO
Parameter
Min.
Wiper response time after the third (last) power supply is stable
Max.
Unit
10
µs
tWRL
Wiper response time after instruction issued (all load instructions)
10
µs
tWRID
Wiper response time from an active SCL/SCK edge (increment/decrement instruction)
40
µs
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
TIMING DIAGRAMS
Input Timing
tCS
CS
SCK
...
tSU
SI
SO
REV 1.1.5 1/31/03
tLAG
tCYC
tLEAD
tH
MSB
tWL
tWH
...
tRI
tFI
LSB
High Impedance
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Characteristics subject to change without notice.
13 of 21
X9250
Output Timing
CS
SCK
...
tV
tDIS
...
MSB
SO
SI
tHO
LSB
ADDR
Hold Timing
CS
tHSU
tHH
SCK
...
tRO
tFO
SO
tHZ
tLZ
SI
tHOLD
HOLD
XDCP Timing (for all Load Instructions)
CS
SCK
...
tWRL
MSB
SI
...
LSB
VWx
SO
High Impedance
REV 1.1.5 1/31/03
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Characteristics subject to change without notice.
14 of 21
X9250
XDCP Timing (for Increment/Decrement Instruction)
CS
SCK
...
tWRID
...
VWx
SI
SO
ADDR
Inc/Dec
Inc/Dec
...
High Impedance
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
tWPASU
tWPAH
WP
A0
A1
REV 1.1.5 1/31/03
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Characteristics subject to change without notice.
15 of 21
X9250
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+VR
VR
VW/RW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
VS
Voltage Regulator
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
Offset Voltage Adjustment
R1
Comparator with Hysterisis
R2
VS
VS
–
+
VO
100KΩ
–
VO
+
}
}
TL072
R1
R2
10KΩ
10KΩ
+12V
REV 1.1.5 1/31/03
10KΩ
VUL = {R1/(R1+R2) VO(max)
VLL = {R1/(R1+R2) VO(min)
-12V
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Characteristics subject to change without notice.
16 of 21
X9250
Application Circuits (continued)
Attenuator
Filter
C
VS
+
R2
R1
VS
R
VO
+
VO
–
–
R3
R4
R2
R1 = R2 = R3 = R4 = 10kΩ
R1
GO = 1 + R2/R1
fc = 1/(2πRC)
VO = G V S
-1/2 ≤ G ≤ +1/2
R1
R2
}
}
Inverting Amplifier
Equivalent L-R Circuit
VS
R2
C1
–
VS
VO
+
+
–
R1
ZIN
VO = G VS
G = - R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
C
R2
–
+
R1
–
} RA
+
} RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
REV 1.1.5 1/31/03
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Characteristics subject to change without notice.
17 of 21
X9250
PACKAGING INFORMATION
24-Bump Chip Scale Package (CSP B24)
Package Outline Drawing
d
a
9250UA
YWW I
Lot#
f
j
A4
A3
A2
A1
B4
B3
B2
B1
C4
C3
C2
C1
D4
D3
D2
D1
E4
E3
E2
E1
F4
F3
F2
F1
m
e
k
l
Top View (Sample Marking)
b
Side View
Bottom View (Bumped Side)
e
c
Side View
Package Dimensions
Package Width
Package Length
Package Height
Body Thickness
Ball Height
Ball Diameter
Ball Pitch – Width
Ball Pitch – Length
Ball to Edge Spacing – Width
Ball to Edge Spacing – Length
REV 1.1.5 1/31/03
Ball Matrix:
Symbol
a
b
c
d
e
f
j
k
l
m
Min
2.771
4.549
0.644
0.444
0.200
0.300
0.626
1.015
Millimeters
Nominal
2.801
4.579
0.677
0.457
0.220
0.320
0.5
0.5
0.651
1.040
Max
2.831
4.609
0.710
0.470
0.240
0.340
A
4
RL1
3
2
1
RW0
A1
CS
B
RW1
SI
WP
RL0
C
VSS
RH1
RH0
VCC
D
V-
RH2
RH3
V+
E
RW2
HOLD
SO
RL3
F
RL2
SCK
A0
RW3
0.676
1.065
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Characteristics subject to change without notice.
18 of 21
X9250
PACKAGING INFORMATION
24-Lead Plastic, TSSOP, Package Code V24
.026 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.303 (7.70)
.311 (7.90)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.06)
.005 (.15)
.010 (.25)
Gage Plane
0°–8°
(4.16) (7.72)
Seating Plane
.020 (.50)
.030 (.75)
(1.78)
Detail A (20X)
(0.42)
(0.65)
.031 (.80)
.041 (1.05)
ALL MEASUREMENTS ARE TYPICAL
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.1.5 1/31/03
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Characteristics subject to change without notice.
19 of 21
X9250
PACKAGING INFORMATION
24-Lead Plastic, SOIC, Package Code S24
0.290 (7.37) 0.393 (10.00)
0.299 (7.60) 0.420 (10.65)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.50)
0.598 (15.20)
0.610 (15.49)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.050" Typical
0.010 (0.25)
X 45°
0.020 (0.50)
0.050"
Typical
0° – 8°
0.009 (0.22)
0.013 (0.33)
0.420"
0.015 (0.40)
0.050 (1.27)
FOOTPRINT
0.030" Typical
24 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.1.5 1/31/03
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Characteristics subject to change without notice.
20 of 21
X9250
Ordering Information
X9250
Y
P
T
V
VCC Limits
Blank = 5V ±10%
–2.7 = 2.7 to 5.5V
Device
Temperature Range
Blank = Commercial =0°C to +70°C
I = Industrial = –40°C to +85°C
Package
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP
B24 = 24-Lead CSP
Potentiometer Organization
T = 100KΩ
U= 50KΩ
S & V Package Marking
Line #1
Line #2
Line #3
Line #4
(Blank)
(Part Number)
(Date Code) (*)
(Blank)
LIMITED WARRANTY
= F 2.7V 0 to 70°C
G 2.7V -40 to +85°C
I 5V
-40 to +85°C
©Xicor, Inc. 2003 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
COPYRIGHTS AND TRADEMARKS
Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,
E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are
used for identification purposes only, and are trademarks or registered trademarks of their respective holders.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
REV 1.1.5 1/31/03
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Characteristics subject to change without notice.
21 of 21