XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE MAY 2007 REV. 1.4.1 GENERAL DESCRIPTION FEATURES The XR16L580 (L580) is a 2.25 to 5.5 volt Universal Asynchronous Receiver and Transmitter (UART) with 5 volt tolerant inputs and a reduced pin count. It is pin-to-pin and software compatible to industry standard 16C450, 16C550, ST16C580, ST16C650A and XR16C850 UARTs. It has 16 bytes of TX and RX FIFOs and is capable of operating up to serial data rate of 1 Mbps at 2.25 volt supply voltage. The internal registers is compatible to the 16C550 register set plus enhanced registers for additional features to support today’s high bandwidth data communication needs. The enhanced features include Intel or Motorola data bus interface to match your CPU interface, automatic hardware and software flow control to prevent data loss, selectable RX and TX trigger levels for more efficient interrupt service, wireless infrared (IrDA) encoder/decoder for wireless applications and a unique Power-Save mode to increase battery operating time. The device comes in the 48-TQFP and very small 32-QFN, 28-QFN and 24-QFN packages in industrial temperature range. APPLICATIONS • Handheld Terminals and Tablets • Handheld Computers • Wireless Portable Point-of-Sale Terminals • Cellular Phones DataPort • GPS Devices • Personal Digital Assistants Modules • Battery Operated Instruments • Smallest Full Featured UART • 2.25V to 5.5V Supply Voltage • 5V Tolerant Inputs (except XTAL1) • Intel/Motorola Bus Select • ’0 ns’ Address Hold Time (TAH and TADH) • Pin and Software Compatible to industry standard 16C450, 16C550, ST16C580, ST16C650A and XR16C850 in the 48-TQFP package. • 16-byte Transmit FIFO • 16-byte Receive FIFO with Errors Flags • Selectable RX and TX FIFO Trigger Levels • Automatic Hardware (RTS/CTS) Flow Control • Automatic Software (Xon/Xoff) Flow Control • Up to 3.125 Mbps Data Rate at 5V and 2 Mbps at 3.3V and 1 Mbps at 2.25V Operation with External Clock Input • Infrared (IrDA) Encoder/Decoder • Complete Modem Interface • Power-Save Mode to conserve battery power • Sleep Mode with Wake-up Interrupt • Small packages: 24-QFN (4x4x0.9mm), 28-QFN (5x5x0.9mm) and 32-QFN (5x5x0.9mm) • Compatible to standard 48-TQFP packages, without the following signals: IOR, IOW, CS1, CS2, TXRDY#, RXRDY#, RCLK, BAUDOUT#, OP1# and OP2# • Industrial Temperature Grade(-40 to +85oC) FIGURE 1. BLOCK DIAGRAM *5 V Tolerant Inputs (Except for XTAL1) PwrSave A2:A0 GND D7:D0 IOR# UART IOW# (R/W#) UART CS# INT (IRQ#) RESET (RESET#) 16/68# VCC (2.25 to 5.5 V) Intel or Motorola Data Bus Interface 16 Byte TX FIFO Regs IR TX & RX ENDEC BRG 16 Byte RX FIFO Crystal Osc/Buffer TX, RX, RTS#, CTS#, DTR#, DSR#, RI#, CD# XTAL1 XTAL2 GNugget_BLK Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 3 4 5 D5 D6 D7 RX TX NC A2 A1 A0 4 5 R/W# XTAL2 XTAL1 PwrSv CS# PwrSv 16/68# A2 A1 A0 IRQ# NC NC NC GND R/W# XTAL2 XTAL1 PwrSv CS# XTAL1 TX XTAL2 RX IOW# D7 GND D6 IOR# 21 20 19 18 17 16 15 14 22 13 23 28-pin QFN in 12 24 Motorola Bus 25 11 mode 26 10 27 9 28 8 1 2 3 4 5 6 7 D5 CTS# VCC D0 D1 D2 D3 D4 CS# TX RX D7 D6 NC CTS# RESET# DTR# RTS# IRQ# A0 A1 A2 GND CTS# RESET DTR# RTS# INT A0 A1 A2 VCC DSR# CD# RI# VCC D0 D1 D2 D3 3 RTS# Reset# NC A2 A1 A0 INT RTS# D5 21 20 19 18 17 16 15 14 22 13 23 12 24 28-pin QFN in 25 11 Intel Bus mode 26 10 27 9 28 8 1 2 3 4 5 6 7 16/68# CTS# VCC D0 D1 D2 D3 D4 2 GND GND Reset VCC 1 7 6 TX 2 D4 24 CS# RX 1 7 6 PwrSv D7 XTAL1 D6 XTAL2 D5 IOW# 8 16/68# D3 23 D4 24 18 17 16 15 14 13 VCC 19 12 D0 20 11 24-pin QFN in D1 21 10 Motorola Bus 9 D2 22 mode 8 D3 23 GND 16/68# 18 17 16 15 14 13 VCC 19 12 D0 20 11 D1 21 24-pin QFN in 10 9 D2 22 Intel Bus mode IRQ# Reset# IOR# A2 A1 A0 INT Reset FIGURE 2. PACKAGES AND PIN OUT (24, 28 AND 32-PIN QFN PACKAGES) 24 23 22 21 20 19 18 17 24 23 22 21 20 19 18 17 25 26 27 28 29 30 31 32 32-pin QFN in Intel Bus Mode 16 15 14 13 12 11 10 9 NC NC IOR# GND IOW# XTAL2 XTAL1 PwrSave DSR# CD# RI# VCC D0 D1 D2 D3 25 26 27 28 29 30 31 32 D4 16/68# D5 D6 D7 RX TX CS# 1 2 3 4 5 6 7 8 16/68# D5 D6 D7 RX TX CS# D4 1 2 3 4 5 6 7 8 32- pin QFN in Motorola Bus Mode VCC GND 2 16 15 14 13 12 11 10 9 NC NC NC GND R/W# XTAL2 XTAL1 PwrSave XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 NC RESET NC DTR# RTS# NC INT NC A0 A1 A2 NC NC RESET# NC DTR# RTS# NC IRQ# NC A0 A1 A2 NC FIGURE 3. PACKAGES AND PIN OUT (48-TQFP PACKAGE) 36 35 34 33 32 31 30 29 28 27 26 25 24 37 38 23 39 22 40 21 41 20 42 48-TQFP in Intel Bus Mode 43 44 19 18 17 45 16 46 15 47 14 48 1 2 3 4 5 6 7 8 13 9 10 11 12 NC NC NC NC NC IOR# GND NC IOW# XTAL2 XTAL1 PwrSave NC CTS# DSR# CD# RI# VCC D0 D1 D2 D3 D4 NC 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 23 39 22 40 21 41 42 43 44 20 48-TQFP in Motorola Bus Mode 19 18 17 45 16 46 15 47 48 1 14 2 3 4 5 6 7 8 13 9 10 11 12 NC NC NC NC NC NC GND NC R/W# XTAL2 XTAL1 PwrSave 16/68# D5 D6 D7 NC NC RX TX NC NC CS# NC 16/68# D5 D6 D7 NC NC RX TX NC NC CS# NC NC CTS# DSR# CD# RI# VCC D0 D1 D2 D3 D4 NC VCC GND ORDERING INFORMATION PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE DEVICE STATUS XR16L580IL24 24-Lead QFN -40°C to +85°C Active XR16L580IL28 28-Lead QFN -40°C to +85°C Active XR16L580IL 32-Lead QFN -40°C to +85°C Active XR16L580IM 48-Lead TQFP -40°C to +85°C Active 3 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 PIN DESCRIPTIONS Pin Descriptions NAME 24QFN PIN# 28QFN PIN# 32QFN PIN# 48TQFP TYPE PIN# DESCRIPTION DATA BUS INTERFACE A2 A1 A0 14 15 16 16 17 18 17 18 19 26 27 28 I D7 D6 D5 D4 D3 D2 D1 D0 4 3 2 24 23 22 21 20 4 3 2 28 27 26 25 24 5 4 3 1 32 31 30 29 4 3 2 47 46 45 44 43 I/O IOR# (NC) 13 13 14 19 I When 16/68# pin is at logic 1, the Intel bus interface is selected and this input becomes read strobe (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [A2:A0], puts the data byte on the data bus to allow the host processor to read it on the rising edge. When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input is not used. IOW# (R/W#) 11 11 12 16 I When 16/68# pin is at logic 1, it selects Intel bus interface and this input becomes write strobe (active low). The falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input becomes read (logic 1) and write (logic 0) signal. CS# 7 7 8 11 I This input is chip select (active low) to enable the device. INT (IRQ#) 17 19 20 30 Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A/B during a data bus transaction. Data bus lines [7:0] (bidirectional). O When 16/68# pin is at logic 1 for Intel bus interface, this output (OD) become the active high device interrupt output. The output state is defined by the user through the software setting of MCR[3]. INT is set to the active mode when MCR[3] is set to a logic 1. INT is set to the three state mode when MCR[3] is set to a logic 0. See MCR[3]. When 16/68# pin is at logic 0 for Motorola bus interface, this output becomes the active low device interrupt output (open drain). An external pull-up resistor is required for proper operation. MODEM OR SERIAL I/O INTERFACE TX 6 6 7 8 O UART Transmit Data or infrared encoder data. Standard transmit and receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be a logic 1 during reset or idle (no data). Infrared IrDA transmit and receive interface is enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the Infrared encoder/decoder interface is a logic 0. If it is not used, leave it unconnected. 4 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 Pin Descriptions NAME 24QFN PIN# 28QFN PIN# 32QFN PIN# RX 5 5 6 7 I UART Receive Data or infrared receive data. Normal receive data input must idle at logic 1 condition. The infrared receiver idles at logic 0. RTS# - 20 21 32 O UART Request-to-Send (active low) or general purpose output. This output must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1] and IER[6]. This pin is not available in the 24QFN package. CTS# - 22 24 38 I UART Clear-to-Send (active low) or general purpose input. It can be used for auto CTS flow control, see EFR[7], MSR[4] and IER[7]. This input should be connected to VCC when not used. This pin is not available in the 24-QFN package. DTR# - - 22 33 O UART Data-Terminal-Ready (active low) or general purpose output. This pin is not available in the 24-QFN and 28-QFN packages. DSR# - - 25 39 I UART Data-Set-Ready (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART. This pin is not available in the 24-QFN and 28-QFN packages. CD# - - 26 40 I UART Carrier-Detect (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART. This pin is not available in the 24-QFN and 28-QFN packages. RI# - - 27 41 I UART Ring-Indicator (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART. This pin is not available in the 24-QFN and 28-QFN packages. 48TQFP TYPE PIN# DESCRIPTION ANCILLARY SIGNALS XTAL1 9 9 10 14 I Crystal or external clock input. This input is not 5V tolerant. XTAL2 10 10 11 15 O Crystal or buffered clock output. This output may be use to drive a clock buffer which can drive other device(s). PwrSave 8 8 9 13 I Power-Save (active high). This feature isolates the L580’s data bus interface from the host preventing other bus activities that cause higher power drain during sleep mode. See Sleep Mode with Auto Wake-up and Power-Save Feature section for details. This pin has an internal pull-down resistor in the 48-TQFP package. The 32-QFN package does not have this pull-down resistor. 16/68# 1 1 2 1 I Intel or Motorola Bus Select. This pin has an internal pull-up resistor in the 48-TQFP package. The 32-QFN package does not have this resistor. When 16/68# pin is at logic 1, 16 or Intel Mode, the device will operate in the Intel bus type of interface. When 16/68# pin is at logic 0, 68 or Motorola mode, the device will operate in the Motorola bus type of interface. 5 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 Pin Descriptions 24QFN PIN# 28QFN PIN# 32QFN PIN# RESET (RESET#) 18 21 23 35 VCC 19 23 28 42 Pwr 2.25V to 5.5V power supply. All input pins, except XTAL1, are 5V tolerant. GND 12 12 13 18 Pwr Power supply common, ground. N/A Pwr The center pad on the backside of the QFN package is metallic and should be connected to GND on the PCB. The thermal pad size on the PCB should be the approximate size of this center pad and should be solder mask defined. The solder mask opening should be at least 0.0025" inwards from the edge of the PCB thermal pad. NAME GND NC Center Center Center Pad Pad Pad - 48TQFP TYPE PIN# 14, 15 15, 16 5, 6, 9, 10, 12, 17, 2025, 29, 31, 34, 36, 37, 48 I - DESCRIPTION When 16/68# pin is at logic 1 for Intel bus interface, this input becomes RESET (active high). When 16/68# pin is at logic 0 for Motorola bus interface, this input becomes RESET# (active low). A 40 ns minimum active pulse on this pin will reset the internal registers and all outputs of the UART. The UART transmitter output will be held at logic 1, the receiver input will be ignored and outputs are reset during reset period (see UART Reset Conditions). No Connects. Note that in Motorola mode, the IOR# pin becomes an NC pin. NOTE: Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain. 6 XR16L580 REV. 1.4.1 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE 1.0 PRODUCT DESCRIPTION The XR16L580 (L580) is an enhanced 16C550 Universal Asynchronous Receiver and Transmitter (UART). Its features set is compatible to the ST16C580 device and additionally offers Intel or Motorola data bus interface and Power-Save to isolate the data bus interface during Sleep mode. Hence, the L580 adds 2 more inputs: 16/ 68# and PwrSave pins. The XR16L580 can operate from 2.25V to 5.5V with 5 volt tolerant inputs. The configuration registers set is 16550 UART compatible for control, status and data transfer. Also, the L580 has 16-bytes of transmit and receive FIFOs, automatic RTS/CTS hardware flow control, automatic Xon/Xoff and special character software flow control, transmit and receive FIFO trigger levels, infrared encoder and decoder (IrDA ver 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4. The L580 is fabricated using an advanced CMOS process. Enhanced Features The L580 UART provides a solution that supports 16 bytes of transmit and receive FIFO memory. The L580 is designed to work with low supply voltage and high performance data communication systems, that require fast data processing time. Increased performance is realized in the L580 by the transmit and receive FIFOs, FIFO trigger level controls and automatic flow control mechanism. This allows the external processor to handle more networking tasks within a given time. This increases the service interval giving the external CPU additional time for other applications and reducing the overall UART interrupt servicing time. In addition, the L580 provides the Power-Save mode that drastically reduces the power consumption when the device is not used. The combination of the above greatly reduces the CPU’s bandwidth requirement, increases performance, and reduces power consumption. Data Bus Interface, Intel or Motorola Type The L580 provides a host interface that supports Intel or Motorola microprocessor (CPU) data bus interface. The Intel bus compatible interface allows direct interconnect to Intel compatible type of CPUs using IOR#, IOW# and CS# inputs for data bus operation. The Motorola bus compatible interface instead uses the R/W# and CS# signals for data bus transactions. See pin description section for details on all the control signals. The Intel and Motorola bus interface selection is made through the pin, 16/68#. Data Rate The L580 is capable of operation up to 3.125 Mbps at 5V, 2 Mbps at 3.3V and 1 Mbps at 2.5V supply with 16X internal sampling clock rate. The device can operate with an external 24 MHz crystal on pins XTAL1 and XTAL2, or external clock source of up to 50 MHz on XTAL1 pin. With a typical crystal of 14.7456 MHz, all standard data rates of up to 921.6 kbps can be generated. Internal Enhanced Register Sets The L580 UART has a set of enhanced registers providing control and monitoring functions. Interrupt enable/ disable and status, FIFO enable/disable, selectable TX and RX FIFO trigger levels, automatic hardware/ software flow control enable/disable, programmable baud rates, infrared encoder/decoder enable/disable, modem interface controls and status, sleep mode and Power-Save mode are all standard features. Following a power on reset or an external reset (and operating in 16 or Intel Mode), the registers defaults to the reset condition and its is compatible with previous generation of UARTs, 16C450, 16C550, 16C580, 16C650A and 16C850. 7 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The L580 data interface supports the Intel compatible types of CPUs and it is compatible to the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# or R/W# inputs. A typical data bus interconnection for Intel and Motorola mode is shown in Figure 4. FIGURE 4. XR16L580 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS D0 D1 D2 D3 D4 D5 D6 D7 VCC 16/68# D0 D1 D2 D3 D4 D5 D6 D7 TX RX DTR# A0 A1 A2 A0 A1 A2 Serial Interface of RS-232 or RS-422 RTS# CTS# IOR# IOR# IOW# IOW# UART_CS# CS# RI# UART_INT INT PwrSave UART_RESET VCC DSR# CD# RESET GND Intel Data Bus Interconnections D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A0 A1 A2 VCC IOR# R/W# IOW# UART_CS# CS# UART_IRQ# INT UART_RESET# RESET Motorola Data Bus Interconnections 8 VCC VCC PwrSave TX RX DTR# RTS# CTS# DSR# CD# RI# 16/68# GND Serial Interface of RS-232 or RS-422 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 2.2 5-Volt Tolerant Inputs The L580 can accept up to 5V inputs when operating at 3.3V or 2.5V. But note that if the L580 is operating at 2.5V, its VOH may not be high enough to meet the requirements of the VIH of a CPU or a serial transceiver that is operating at 5V. Note that the XTAL1 pin is not 5V tolerant when external clock supply is used. 2.3 Device Hardware Reset The RESET or RESET# input resets the internal registers and the serial interface outputs in both channels to their default state (see Table 11). An active pulse of longer than 40 ns duration will be required to activate the reset function in the device. 2.4 Device Identification and Revision The XR16L580 provides a Device Identification code and a Device Revision code to distinguish the part from other devices and revisions. To read the identification code from the part, it is required to set the baud rate generator registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x01 to indicate XR16L580 and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01 means revision A. 2.5 Internal Registers The L580 has a set of enhanced registers for control, monitoring and data loading and unloading. The configuration register set is compatible to those already available in the standard 16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers, (LSR/LCR), modem status and control registers (MSR/ MCR), programmable data rate (clock) divisor registers (DLL/DLM), and an user accessible Scratchpad register (SPR). Beyond the general 16C550 features and capabilities, the L580 offers enhanced feature registers (EFR, Xon1, Xoff 1, Xon1 and Xoff2) that provide automatic RTS and CTS hardware flow control and Xon/Xoff software flow control. All the register functions are discussed in full detail later in “Section 3.0, UART INTERNAL REGISTERS” on page 22. 2.6 DMA Mode The DMA Mode (a legacy term) refers to data block transfer operation. The DMA mode affects the state of the RXRDY# and TXRDY# output pins available in the original 16C550. These pins are not available in the XR16L580. The DMA Enable bit (FCR bit-3) does not have any function in this device and can be a ’0’ or a ’1’. 2.7 INT (IRQ#) Output The interrupt output changes according to the operating mode and enhanced features setup. Table 1 and Table 2 below summarize the operating behavior for the transmitter and receiver in the Intel and Motorola modes. Also see Figures 21 through 24. TABLE 1: INT (IRQ#) PIN OPERATION FOR TRANSMITTER FCR BIT-0 = 0 (FIFO DISABLED) FCR BIT-0 = 1 (FIFO ENABLED) INT Pin (16/68# = 1) 0 = one byte in THR 1 = THR empty 0 = FIFO above trigger level 1 = FIFO below trigger level or FIFO empty IRQ# Pin (16/68# = 0) 1 = one byte in THR 0 = THR empty 1 = FIFO above trigger level 0 = FIFO below trigger level or FIFO empty 9 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 TABLE 2: INT (IRQ#) PIN OPERATION FOR RECEIVER FCR BIT-0 = 0 (FIFO DISABLED) FCR BIT-0 = 1 (FIFO ENABLED) INT Pin (16/68# = 1) 0 = no data 1 = 1 byte 0 = FIFO below trigger level 1 = FIFO above trigger level IRQ# Pin (16/68# = 0) 1 = no data 0 = 1 byte 1 = FIFO below trigger level 0 = FIFO above trigger level 2.8 Crystal or External Clock Input The L580 includes an on-chip oscillator (XTAL1 and XTAL2) to generate a clock when a crystal is connected between the XTAL1 and XTAL2 pins of the device. Alternatively, an external clock can be supplied through the XTAL1 pin. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a system clock to the Baud Rate Generators (BRG) section. XTAL1 is the input to the oscillator or external clock input and XTAL2 pin is the bufferred output which can be used as a clock signal for other devices in the system. Please note that the input XTAL1 is not 5V tolerant and therefore, the maximum voltage at the pin should be VCC when an external clock is supplied. For programming details, see “Programmable Baud Rate Generator.” FIGURE 5. TYPICAL CRYSTAL CONNECTIONS XTAL1 XTAL2 R2 500K - 1M Y1 C1 22-47pF R1 0-120 (Optional) 1.8432 MHz to 24 MHz C2 22-47pF The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant, fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 5). When VCC = 5V, the onchip oscillator can operate with a crystal whose frequency is not greater than 24 MHz. On the other hand, the L580 can accept an external clock of up to 50MHz at XTAL1 pin, with a 2K ohms pull-up resistor on XTAL2 pin (as shown in Figure 6). This translates to a maximum of 3.125Mbps serial data rate at 5V. 10 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 FIGURE 6. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE E x te rn a l C lo c k vcc XTAL1 gnd VCC R1 2K XTAL2 For further reading on the oscillator circuit please see the Application Note DAN108 on the EXAR web site at http://www.exar.com. 2.9 Programmable Baud Rate Generator The L580 UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by a software bit (bit-7) in the MCR register. This bit selects the prescaler to divide the input crystal or external clock by a factor of 1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides this clock by a programmable divisor (via DLL and DLM registers) between 1 and (216 -1) to obtain a 16X sampling rate clock of the serial data rate. The sampling rate clock is used by the transmitter for data bit shifting and receiver for data sampling. The BRG divisor defaults to the maximum baud rate (DLL = 0x01 and DLM = 0x00) upon power up. FIGURE 7. BAUD RATE GENERATOR AND PRESCALER DLL and DLM Registers Prescaler Divide by 1 XTAL1 XTAL2 Crystal Osc/ Buffer MCR Bit-7=0 (default) Baud Rate Generator Logic Prescaler Divide by 4 16X Sampling Rate Clock to Transmitter MCR Bit-7=1 Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the operating data rate. Table 3 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling rate clock rate. When using a non-standard data rate crystal or external clock, the divisor value can be calculated for DLL/DLM with the following equation. divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16) 11 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 TABLE 3: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK OUTPUT Data Rate OUTPUT Data Rate DIVISOR FOR 16x DIVISOR FOR 16x MCR Bit-7=1 MCR Bit-7=0 Clock (Decimal) Clock (HEX) (DEFAULT) DLM PROGRAM VALUE (HEX) DLL PROGRAM VALUE (HEX) DATA RATE ERROR (%) 100 400 2304 900 09 00 0 600 2400 384 180 01 80 0 1200 4800 192 C0 00 C0 0 2400 9600 96 60 00 60 0 4800 19.2k 48 30 00 30 0 9600 38.4k 24 18 00 18 0 19.2k 76.8k 12 0C 00 0C 0 38.4k 153.6k 6 06 00 06 0 57.6k 230.4k 4 04 00 04 0 115.2k 460.8k 2 02 00 02 0 230.4k 921.6k 1 01 00 01 0 12 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 2.10 Transmitter The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in the Line Status Register (LSR bit-5 and bit-6). 2.10.1 Transmit Holding Register (THR) - Write Only The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data location. 2.10.2 Transmitter Operation in non-FIFO Mode The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty. FIGURE 8. TRANSMITTER OPERATION IN NON-FIFO MODE Data Byte 16X Clock Transmit Holding Register (THR) THR Interrupt (ISR bit-1) Enabled by IER bit-1 Transmit Shift Register (TSR) M S B L S B TXNOFIFO1 2.10.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by IER bit-1. The Transmitter Empty Flag (LSR bit-6) is set when both the TSR and the FIFO become empty. 13 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 FIGURE 9. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE Transmit Data Byte Transm it FIFO THR Interrupt (ISR bit-1): - W hen the TX FIFO falls below the programmed Trigger Level, and - W hen the TX FIFO becomes em pty. Auto CTS Flow Control (CTS# pin) FIFO is Enabled by FCR bit-0=1 Flow Control Characters (Xoff1,2 and Xon1,2 Reg.) Auto Software Flow Control 16X Clock Transm it Data Shift Register (TSR) T XF IF O 1 2.11 RECEIVER The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. On the falling edge of a start or a false start bit, an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start bit period should be at the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated as a start bit. Evaluating the start bit in this manner prevents the receiver from assembling a false character. Each of the data, parity and stop bits is sampled at the middle of the bit to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0. 2.11.1 Receive Holding Register (RHR) - Read-Only The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register. It provides the receive data interface to the host processor. The RHR register is part of the receive FIFO of 16 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data byte are immediately updated in the LSR bits 2-4. 14 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 FIGURE 10. RECEIVER OPERATION IN NON-FIFO MODE 16X Clock Receive Data Shift Register (RSR) Error Tags in LSR bits 4:2 Receive Data Byte and Errors Receive Data Holding Register (RHR) Data Bit Validation Receive Data Characters RHR Interrupt (ISR bit-2) RXFIFO1 FIGURE 11. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE 16X Clock Receive Data Shift Register (RSR) Data Bit Validation Example : RX FIFO trigger level selected at 8 bytes 16 bytes by 11-bit wide FIFO Error Tags (16-sets) Data falls to 4 Receive Data FIFO FIFO Trigger=8 Error Tags in LSR bits 4:2 Data fills to 14 Receive Data Byte and Errors Receive Data Characters RTS# re-asserts when data falls below the flow control trigger level to restart remote transmitter. Enable by EFR bit-6=1, MCR bit-1. RHR Interrupt (ISR bit-2) programmed for desired FIFO trigger level. FIFO is Enabled by FCR bit-0=1 RTS# de-asserts when data fills above the flow control trigger level to suspend remote transmitter. Enable by EFR bit-6=1, MCR bit-1. Receive Data RXFIFO1 15 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE 2.12 REV. 1.4.1 Auto RTS (Hardware) Flow Control This feature is not available in the 24-QFN package since it does not have the RTS# pin. Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control features is enabled to fit specific application requirement (see Figure 12): • Enable auto RTS flow control using EFR bit-6. • The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled). If using the Auto RTS interrupt: • Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1. 2.13 Auto RTS Hysteresis The L580 has a new feature that provides flow control trigger hysteresis while maintaining compatibility with the ST16C550 UART. With the Auto RTS function enabled, an interrupt is generated when the receive FIFO reaches the programmed RX trigger level. The RTS# pin will not be forced to a logic 1 (RTS off), until the receive FIFO reaches one trigger level above the programmed trigger level in the trigger table (Table 8). The RTS# pin will return to a logic 0 after the RX FIFO is unloaded to one trigger level lower than the programmed trigger level. This is described in Figure 12. Under the above described conditions, the L580 will continue to accept data until the receive FIFO gets full. The Auto RTS function is initiated when the RTS# output pin is asserted to a logic 0 (RTS On). 2.14 Auto CTS Flow Control This feature is not available in the 24-QFN package since it does not have the CTS# pin. Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific application requirement (see Figure 12): • Enable auto CTS flow control using EFR bit-7. If using the Auto CTS interrupt: • Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is reasserted (LOW), indicating more data may be sent. 16 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 FIGURE 12. AUTO RTS AND CTS FLOW CONTROL OPERATION (NOT AVAILABLE IN 24-QFN PACKAGE) Local UART UARTA Remote UART UARTB RXA Receiver FIFO Trigger Reached RTSA# Auto RTS Trigger Level Receiver FIFO Trigger Reached RTSB# Assert RTS# to Begin Transmission 1 ON Auto RTS Trigger Level 10 OFF ON 7 2 CTSB# Auto CTS Monitor RXB CTSA# Auto CTS Monitor Transmitter CTSB# TXA Transmitter RTSA# TXB ON 3 8 OFF 6 Suspend 11 ON TXB Data Starts 4 Restart 9 RXA FIFO INTA (RXA FIFO Interrupt) Receive RX FIFO Data Trigger Level 5 RTS High Threshold RTS Low Threshold 12 RX FIFO Trigger Level RTSCTS1 The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO (4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and continues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows (7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its transmit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9), UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB with RTSB# and CTSA# controlling the data flow. 17 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE 2.15 REV. 1.4.1 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled (See Table 10), the L580 compares one or two sequential receive data characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the L580 will halt transmission (TX) as soon as the current character has completed transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output pin will be activated. Following a suspension due to a match of the Xoff character, the L580 will monitor the receive data stream for a match to the Xon-1,2 character. If a match is found, the L580 will resume operation and clear the flags (ISR bit-4). Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/ Xoff characters (See Table 10) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected, the L580 compares two consecutive receive characters with two software flow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO. In the event that the receive buffer is overfilling and flow control needs to be executed, the L580 automatically sends an Xoff message (when enabled) via the serial TX output to the remote modem. The L580 sends the Xoff character(s) two-character-times (= time taken to send two characters at the programmed baud rate) after the receive FIFO crosses the programmed trigger level. To clear this condition, the L580 will transmit the programmed Xon character(s) as soon as receive FIFO is less than one trigger level below the programmed trigger level (see Table 8). The table below describes this. TABLE 4: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL RX TRIGGER LEVEL INT PIN ACTIVATION XOFF CHARACTER(S) SENT (CHARACTERS IN RX FIFO) XON CHARACTER(S) SENT (CHARACTERS IN RX FIFO) 1 1 1* 0 4 4 4* 1 8 8 8* 4 14 14 14* 8 * After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2 characters); for example, after 2.083ms has elapsed for 9600 baud and 8-bit word length, no parity and 1 stop bit setting. 2.16 Special Character Detect A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal incoming RX data. The L580 compares each incoming receive character with the programmed Xoff-2 data. If a match exists, the received data will be transferred to the RX FIFO and ISR bit-4 will be set to indicate detection of special character. Although the Internal Register Table shows Xon, Xoff Registers with eight bits of character information, the actual number of bits is dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also determines the number of bits that will be used for the special character comparison. Bit-0 in the Xon, Xoff Registers corresponds with the LSB bit for the receive character. 18 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 2.17 Infrared Mode The L580 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide HIGHpulse for each “0” bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED, hence reduces the power consumption. See Figure 13 below. The infrared encoder and decoder are enabled by setting MCR register bit-6 to a ‘1’. When the infrared feature is enabled, the transmit data output, TX, idles at logic zero level. Likewise, the RX input assumes an idle level of logic zero from a reset and power up, see Figure 13. Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin. Each time it senses a light pulse, it returns a logic 1 to the data bit stream. However, this is not true with some infrared modules on the market which indicate a logic 0 by a light pulse. So the L580 has a provision to invert the input polarity to accommodate this. In this case, the user can enable MCR bit-2 to invert the IR signal at the RX pin. FIGURE 13. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING TX Data 0 Stop Start Character Data Bits 1 0 1 0 1 0 1 1 0 Transmit IR Pulse (TX Pin) 1/2 Bit Time Bit Time 3/16 Bit Time IrEncoder-1 Receive IR Pulse (RX pin) Bit Time 1/16 Clock Delay 1 0 1 0 0 Data Bits 1 1 0 1 Stop 0 Start RX Data Character IRdecoder- 19 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE 2.18 REV. 1.4.1 Sleep Mode with Wake-Up Interrupt and Power-Save Feature The L580 supports low voltage system designs, hence, a sleep mode with wake-up interrupt and Power-Save feature is included to reduce power consumption when the device is not actively used. 2.18.1 Sleep Mode All of these conditions must be satisfied for the L580 to enter sleep mode: ■ no interrupts pending (ISR bit-0 = 1) ■ the 16-bit divisor programmed in DLM and DLL registers is a non-zero value ■ sleep mode is enabled (IER bit-4 = 1) ■ modem inputs are not toggling (MSR bits 0-3 = 0) ■ RX input pin is idling at a logic 1 The L580 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for no clock output as an indication that the device has entered the sleep mode. The L580 resumes normal operation by any of the following: ■ a receive data start bit transition (logic 1 to 0) at the RX input pin ■ a data byte is loaded to the transmitter, THR or FIFO ■ a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI# If the L580 is awakened by any one of the above conditions, it issues an interrupt as soon as the oscillator circuit is up and running and the device is ready to transmit/receive. This interrupt has the same encoding (bit0 of ISR register = 1) as "no interrupt pending" and will clear when the ISR register is read. This will show up in the ISR register only if no other interrupts are enabled. The L580 will return to the sleep mode automatically after all interrupting conditions have been serviced and cleared. If the L580 is awakened by the modem inputs, a read to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while an interrupt is pending. The L580 will stay in the sleep mode of operation until it is disabled by setting IER bit-4 to a logic 0. 2.18.2 Power-Save Feature If the address lines, data bus lines, IOW#, IOR#, CS# and modem input lines remain steady when the L580 is in sleep mode, the maximum current will be in the microamp range as specified in the DC Electrical Characteristics on page 37. If the input lines are floating or are toggling while the L580 is in sleep mode, the current can be up to 100 times more. If not using the Power-Save feature, an external buffer would be required to keep the address and data bus lines from toggling or floating to achieve the low current. But if the PowerSave feature is enabled (PwrSave pin connected to VCC), this will eliminate the need for an external buffer by internally isolating the address, data and control signals (see Figure 1 on page 1) from other bus activities that could cause wasteful power drain. The L580 enters Power-Save mode when this pin is connected to VCC and the L580 is in sleep mode (see Sleep Mode section above). Since Power-Save mode isolates the address, data and control signals, the device will wake-up only by: ■ a receive data start bit transition (logic 1 to 0) at the RX input pin or ■ a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD# or RI# The L580 will return to the Power-Save mode automatically after a read to the MSR (to reset the modem inputs) and all interrupting conditions have been serviced and cleared. The L580 will stay in the Power-Save mode of operation until it is disabled by setting IER bit-4 to a logic 0 and/or the Power-Save pin is connected to GND. 20 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 2.19 Internal Loopback The L580 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally including automatic hardware and software flow control. Figure 14 shows how the modem port signals are reconfigured. Transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input pins must be held to a logic 1 during loopback test else upon exiting the loopback test the UART may detect and report a false “break” signal. FIGURE 14. INTERNAL LOOP BACK VCC TX Transmit Shift Register (THR/FIFO) Receive Shift Register (RHR/FIFO) RX VCC RTS# RTS# Modem / General Purpose Control Logic Internal Data Bus Lines and Control Signals M CR bit-4=1 CTS# CTS# VCC DTR# DTR# DSR# DSR# OP1# RI# RI# OP2# CD# CD# 21 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 3.0 UART INTERNAL REGISTERS The L580 has a set of configuration registers selected by address lines A0, A1 and A2 with CS# asserted. The complete register set is shown on Table 5 and Table 6. TABLE 5: UART INTERNAL REGISTERS A2,A1,A0 ADDRESSES REGISTER READ/WRITE COMMENTS LCR[7] = 0 16C550 COMPATIBLE REGISTERS 0 0 0 RHR - Receive Holding Register THR - Transmit Holding Register Read-only Write-only 0 0 0 DLL - Div Latch Low Byte Read/Write 0 0 1 DLM - Div Latch High Byte Read/Write 0 0 0 DREV - Device Revision Code Read-only 0 0 1 DVID - Device Identification Code Read-only DLL, DLM = 0x00, LCR[7] = 1 0 0 1 IER - Interrupt Enable Register Read/Write LCR[7] = 0 0 1 0 ISR - Interrupt Status Register FCR - FIFO Control Register Read-only Write-only LCR ≠ 0xBF 0 1 1 LCR - Line Control Register Read/Write 1 0 0 MCR - Modem Control Register Read/Write 1 0 1 LSR - Line Status Register Reserved Read-only Write-only LCR[7] = 1 1 1 0 MSR - Modem Status Register Reserved Read-only Write-only 1 1 1 SPR - Scratchpad Register Read/Write LCR ≠ 0xBF LCR ≠ 0xBF ENHANCED REGISTERS 0 1 0 EFR - Enhanced Function Register Read/Write 1 0 0 Xon-1 - Xon Character 1 Read/Write 1 0 1 Xon-2 - Xon Character 2 Read/Write 1 1 0 Xoff-1 - Xoff Character 1 Read/Write 1 1 1 Xoff-2 - Xoff Character 2 Read/Write 22 LCR = 0xBF XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 . TABLE 6: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1 ADDRESS A2-A0 REG NAME READ/ WRITE BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 COMMENT 16C550 Compatible Registers 000 RHR RD Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 000 THR WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 001 IER RD/WR 0/ 0/ 0/ 0/ CTS Int. RTS Int. Enable Enable Xoff Int. Enable Sleep Mode Enable FIFOs FIFOs Enabled Enabled 0/ 0/ INT Source Bit-5 INT Source Bit-4 010 ISR RD Modem RX Line TX RX Stat. Int. Stat. Empty Data Enable Int. Int Int. Enable Enable Enable INT Source Bit-3 LCR[7]=0 INT INT INT Source Source Source Bit-2 Bit-1 Bit-0 LCR ≠ 0xBF 010 FCR WR RX FIFO RX FIFO Trigger Trigger 0/ 0/ TX FIFO TX FIFO Trigger Trigger 011 LCR RD/WR Divisor Enable Set TX Break Set Parity Even Parity 100 MCR RD/WR 0/ 0/ 0/ Internal Loopback Enable BRG Prescaler IR Mode XonAny ENable DMA Mode Enable TX FIFO Reset Parity Enable Stop Bits RX FIFO Reset FIFOs Enable Word Word Length Length Bit-1 Bit-0 INT Out- (OP1#) RTS# DTR# put Output Output Invert Control Control Enable IR RX (OP2#) 101 LSR RD RX FIFO Global Error THR & TSR Empty THR Empty RX Break RX Framing Error RX Parity Error RX Overrun Error RX LCR ≠ 0xBF Data Ready 110 MSR RD CD# Input RI# Input DSR# Input CTS# Input Delta CD# Delta RI# Delta DSR# Delta CTS# 111 SPR RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 LCR ≠ 0xBF LCR[7]=1 Baud Rate Generator Divisor 000 DLL RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 001 DLM RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 000 DREV RD Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 001 DVID RD 0 0 0 0 0 0 0 1 23 LCR[7]=1 DLL=0x00 DLM=0x00 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 TABLE 6: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1 ADDRESS A2-A0 REG NAME READ/ WRITE BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 MCR[7:5], MCR[2] Software Flow Cntl Bit-3 Software Flow Cntl Bit-2 Software Flow Cntl Bit-1 Software Flow Cntl Bit-0 COMMENT Enhanced Registers 010 EFR RD/WR Auto CTS Enable Auto RTS Enable Special Char Select Enable IER [7:4], ISR [5:4], FCR[5:4], 100 XON1 WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 101 XON2 WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 110 XOFF1 WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 111 XOFF2 WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 LCR=0XBF 4.0 INTERNAL REGISTER DESCRIPTIONS 4.1 Receive Holding Register (RHR) - Read- Only SEE”RECEIVER” ON PAGE 14. 4.2 Transmit Holding Register (THR) - Write-Only SEE”TRANSMITTER” ON PAGE 13. 4.3 Baud Rate Generator Divisors (DLL and DLM) - Read/Write The Baud Rate Generator (BRG) is a 16-bit counter that generates the data rate for the transmitter. The rate is programmed through registers DLL and DLM which are only accessible when LCR bit-7 is set to ‘1’. SEE”PROGRAMMABLE BAUD RATE GENERATOR” ON PAGE 11. 4.4 Interrupt Enable Register (IER) - Read/Write The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR). 4.4.1 IER versus Receive FIFO Interrupt Mode Operation When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts (see ISR bits 2 and 3) status will reflect the following: A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed trigger level. It will be cleared when the FIFO drops below the programmed trigger level. B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register status bit and the interrupt will be cleared when the FIFO drops below the trigger level. C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to the receive FIFO. It is reset when the FIFO is empty. 24 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 4.4.2 IER versus Receive/Transmit FIFO Polled Mode Operation When FCR bit-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16L580 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). A. LSR BIT-0 indicates there is data in RHR or RX FIFO. B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid. C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any. D. LSR BIT-5 indicates THR is empty. E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty. F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO. IER[0]: RHR Interrupt Enable The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when the receive FIFO has reached the programmed trigger level in the FIFO mode. • Logic 0 = Disable the receive data ready interrupt (default). • Logic 1 = Enable the receiver data ready interrupt. IER[1]: THR Interrupt Enable This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty in the nonFIFO mode or when data in the FIFO falls below the programmed trigger level in the FIFO mode. If the THR is empty when this bit is enabled, an interrupt will be generated. • Logic 0 = Disable Transmit Ready interrupt (default). • Logic 1 = Enable Transmit Ready interrupt. IER[2]: Receive Line Status Interrupt Enable If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when the character has been received. LSR bits 2-4 generate an interrupt when the character with errors is read out of the FIFO. • Logic 0 = Disable the receiver line status interrupt (default). • Logic 1 = Enable the receiver line status interrupt. IER[3]: Modem Status Interrupt Enable • Logic 0 = Disable the modem status register interrupt (default). • Logic 1 = Enable the modem status register interrupt. IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1) • Logic 0 = Disable Sleep Mode (default). • Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details. IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1) • Logic 0 = Disable the software flow control, receive Xoff interrupt. (default) • Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for details. 25 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1) This bit has no functionality in the 24-QFN package. • Logic 0 = Disable the RTS# interrupt (default). • Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition from low to high. IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1) This bit has no functionality in the 24-QFN package. • Logic 0 = Disable the CTS# interrupt (default). • Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from low to high. 4.5 Interrupt Status Register (ISR) - Read-Only The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source Table, Table 7, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources associated with each of these interrupt levels. 4.5.1 Interrupt Generation: • LSR is by any of the LSR bits 1, 2, 3 and 4. • RXRDY is by RX trigger level. • RXRDY Time-out is by a 4-char plus 12 bits delay timer. • TXRDY is by TX trigger level or TX FIFO empty. • MSR is by any of the MSR bits 0, 1, 2 and 3. • Receive Xoff/Special character is by detection of a Xoff or Special character. • CTS# is when its transmitter toggles the input pin (from low to high) during auto CTS flow control enabled by EFR bit-7. • RTS# is when its receiver toggles the output pin (from low to high) during auto RTS flow control enabled by EFR bit-6. • Wake-up Interrupt is when the device wakes up from sleep mode. See Sleep Mode section for more details. 4.5.2 Interrupt Clearing: • LSR interrupt is cleared by reading the LSR register (but FIFO error bit does not clear until the character(s) that generated the interrupt(s) is (are) read from the FIFO). • RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level. • RXRDY Time-out interrupt is cleared by reading the RHR register. • TXRDY interrupt is cleared by reading the ISR register or writing to the THR register. • MSR interrupt is cleared by reading the MSR register. • Xoff interrupt is cleared by reading the ISR or when Xon character(s) is received. • Special character interrupt is cleared by reading the ISR or after the next character is received. • RTS# and CTS# flow control interrupts are cleared by reading the MSR register. • Wake-up interrupt is cleared by reading the ISR register. 26 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 ] TABLE 7: INTERRUPT SOURCE AND PRIORITY LEVEL PRIORITY ISR REGISTER STATUS BITS SOURCE OF INTERRUPT LEVEL BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 1 0 0 0 1 1 0 LSR (Receiver Line Status Register) 2 0 0 1 1 0 0 RXRDY (Receive Data Time-out) 3 0 0 0 1 0 0 RXRDY (Received Data Ready) 4 0 0 0 0 1 0 TXRDY (Transmit Ready) 5 0 0 0 0 0 0 MSR (Modem Status Register) 6 0 1 0 0 0 0 RXRDY (Received Xoff or Special character) 7 1 0 0 0 0 0 CTS#, RTS# change of state - 0 0 0 0 0 1 None (default) or Wake-up Interrupt ISR[0]: Interrupt Status • Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine. • Logic 1 = No interrupt pending (default condition) or wake-up interrupt. The wake-up interrupt is issued when the L580 has been awakened from sleep mode. ISR[3:1]: Interrupt Status These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 7). ISR[5:4]: Interrupt Status These bits are enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match of the Xoff character(s). Note that once set to a logic 1, the ISR bit-4 will stay a logic 1 until a Xon character is received. ISR bit-5 indicates that CTS# or RTS# has changed state. ISR[7:6]: FIFO Enable Status These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are enabled. 4.6 FIFO Control Register (FCR) - Write-Only This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and select the DMA mode. The DMA, and FIFO modes are defined as follows: FCR[0]: TX and RX FIFO Enable • Logic 0 = Disable the transmit and receive FIFO (default). • Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are written or they will not be programmed. FCR[1]: RX FIFO Reset This bit is only active when FCR bit-0 is a ‘1’. • Logic 0 = No receive FIFO reset (default) • Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not cleared or altered). This bit will return to a logic 0 after resetting the FIFO. 27 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 FCR[2]: TX FIFO Reset This bit is only active when FCR bit-0 is a ‘1’. • Logic 0 = No transmit FIFO reset (default). • Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not cleared or altered). This bit will return to a logic 0 after resetting the FIFO. FCR[3]: DMA Mode Select (Legacy) This bit has no function and should be left at ’0’. FCR[5:4]: Transmit FIFO Trigger Select (’00’ = default, TX trigger level = 1) These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the FIFO did not get filled over the trigger level on last re-load. Table 8 below shows the selections. EFR bit-4 must be set to ‘1’ before these bits can be accessed. FCR[7:6]: Receive FIFO Trigger Select (’00’ = default, RX trigger level =1) These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the trigger level. Table 8 shows the selections. TABLE 8: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION FCR BIT-7 0 0 1 1 4.7 FCR BIT-6 FCR BIT-5 BIT-4 FCR 0 0 1 1 0 1 0 1 RECEIVE TRANSMIT TRIGGER LEVEL TRIGGER LEVEL 0 1 0 1 1 (default) 4 8 14 1 (default) 4 8 14 COMPATIBILITY 16C580 and 16L580 compatible. 16C550, 16C580, 16C554, 16C2550 and 16C2552 compatible Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. LCR[1:0]: TX and RX Word Length Select These two bits specify the word length to be transmitted or received. BIT-1 BIT-0 WORD LENGTH 0 0 5 (default) 0 1 6 1 0 7 1 1 8 28 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length. LENGTH STOP BIT LENGTH (BIT TIME(S)) 0 5,6,7,8 1 (default) 1 5 1-1/2 1 6,7,8 2 BIT-2 WORD LCR[3]: TX and RX Parity Select Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data integrity check. See Table 9 for parity selection summary below. • Logic 0 = No parity. • Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the data character received. LCR[4]: TX and RX Parity Select If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format. • Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The receiver must be programmed to check the same format (default). • Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The receiver must be programmed to check the same format. LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format. • LCR BIT-5 = logic 0, parity is not forced (default). • LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. • LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. TABLE 9: PARITY SELECTION LCR BIT-5 LCR BIT-4 LCR BIT-3 PARITY SELECTION X X 0 No parity 0 0 1 Odd parity 0 1 1 Even parity 1 0 1 Force parity to mark, “1” 1 1 1 Forced parity to space, “0” 29 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 LCR[6]: Transmit Break Enable When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a “space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0. • Logic 0 = No TX break condition (default). • Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line break condition. LCR[7]: Baud Rate Divisors Enable Baud rate generator divisor (DLL/DLM) enable. • Logic 0 = Data registers are selected (default). • Logic 1 = Divisor latch registers are selected. 4.8 Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs. MCR[0]: DTR# Output The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a general purpose output. This bit has no functionality in the 24-QFN and 28-QFN packages except in internal loopback mode. • Logic 0 = Force DTR# output to a logic 1 (default). • Logic 1 = Force DTR# output to a logic 0. MCR[1]: RTS# Output The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output. This bit has no functionality in the 24-QFN package except in internal loopback mode. • Logic 0 = Force RTS# output to a logic 1 (default). • Logic 1 = Force RTS# output to a logic 0. MCR[2]: Invert Infrared RX Data or OP1# (legacy term) If IrDA mode is enabled by setting MCR[6]=1 and if EFR[4] = 1, this bit acts as ’Invert Infrared RX data’ command. If EFR[4] = 0 or in internal loopback mode, this bit functions like the OP1# in the 16C550. • Logic 0 = Select RX input as active-low encoded IrDA data (if IrDA Mode is enabled by setting MCR[6] = 1 and EFR[4] = 1) (default). • Logic 1 = Select RX input as active-high encoded IrDA data (if MCR[6] = 1 and EFR[4] = 1). In this mode, this bit is write-only. In the Internal Loopback Mode, this bit controls the state of the modem input RI# bit in the MSR register as shown in Figure 14. MCR[3]: INT Output Enable or OP2# (legacy term) This bit enables and disables the operation of interrupt output, INT in the Intel mode. It has no function in the Motorola mode. • Logic 0 = INT output disabled (three state mode) (default). • Logic 1 = INT output enabled (active mode). In the Internal Loopback Mode, this bit functions like the OP2# in the 16C550 and is used to set the state of the modem input CD# bit in the MSR register. 30 XR16L580 REV. 1.4.1 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE MCR[4]: Internal Loopback Enable • Logic 0 = Disable loopback mode (default). • Logic 1 = Enable local loopback mode, see loopback section and Figure 14. MCR[5]: Xon-Any Enable • Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default). • Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation. The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and the L580 is programmed to use the Xon/Xoff flow control. MCR[6]: Infrared Encoder/Decoder Enable • Logic 0 = Enable the standard modem receive and transmit input/output interface (default). • Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface requirement. While in this mode, the infrared TX output will be a logic 0 during idle data conditions. MCR[7]: BRG Clock Prescaler Select • Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable Baud Rate Generator without further modification, i.e., divide by one (default). • Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and feeds it to the Programmable Baud Rate Generator, hence, data rates get reduced 4 times. 4.9 Line Status Register (LSR) - Read Only This register provides the status of data transfers between the UART and the host. LSR[0]: Receive Data Ready Indicator • Logic 0 = No data in receive holding register or FIFO (default). • Logic 1 = Data has been received and is saved in the receive holding register or FIFO. LSR[1]: Receiver Overrun Flag • Logic 0 = No overrun error (default). • Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into the FIFO, therefore the data in the FIFO is not corrupted by the error. LSR[2]: Receive Data Parity Error Flag • Logic 0 = No parity error (default). • Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect. This error is associated with the character available for reading in RHR. LSR[3]: Receive Data Framing Error Flag • Logic 0 = No framing error (default). • Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with the character available for reading in RHR. 31 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 LSR[4]: Receive Break Flag • Logic 0 = No break condition (default). • Logic 1 = The receiver received a break signal (RX was a logic 0 for at least one character frame time). In the FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX input returns to the idle condition, “mark” or logic 1. LSR[5]: Transmit Holding Register Empty Flag This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte. LSR[6]: THR and TSR Empty Flag This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and transmit shift register are both empty. LSR[7]: Receive FIFO Data Error Flag • Logic 0 = No FIFO error (default). • Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the RX FIFO. 4.10 Modem Status Register (MSR) - Read Only This register provides the current state of the modem interface input signals. Lower four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem changes state. These bits may be used for general purpose inputs when they are not used with modem signals. MSR[0]: Delta CTS# Input Flag • Logic 0 = No change on CTS# input (default). • Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3). MSR[1]: Delta DSR# Input Flag • Logic 0 = No change on DSR# input (default). • Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3). MSR[2]: Delta RI# Input Flag • Logic 0 = No change on RI# input (default). • Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3). MSR[3]: Delta CD# Input Flag • Logic 0 = No change on CD# input (default). • Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3). 32 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 MSR[4]: CTS Input Status CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto CTS (EFR bit-7). Auto CTS flow control allows starting and stopping of local data transmissions based on the modem CTS# signal. A logic 1 on the CTS# pin will stop UART transmitter as soon as the current character has finished transmission, and a logic 0 will resume data transmission. Normally MSR bit-4 bit is the compliment of the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The CTS# input may be used as a general purpose input when the modem interface is not used. MSR[5]: DSR Input Status DSR# (active high, logical 1). Normally this bit is the compliment of the DSR# input. In the loopback mode, this bit is equivalent to the DTR# bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is not used. MSR[6]: RI Input Status RI# (active high, logical 1). Normally this bit is the compliment of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the MCR register. The RI# input may be used as a general purpose input when the modem interface is not used. MSR[7]: CD Input Status CD# (active high, logical 1). Normally this bit is the compliment of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose input when the modem interface is not used. 4.11 Scratchpad Register (SPR) - Read/Write This is a 8-bit general purpose register for the user to store temporary data. The content of this register is preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle. 4.12 Baud Rate Generator Registers (DLL and DLM) - Read/Write The concatenation of the contents of DLM and DLL gives the 16-bit divisor value which is used to calculate the baud rate: • Baud Rate = (Clock Frequency / 16) / Divisor See MCR bit-7 and the baud rate table also. 4.13 Device Identification Register (DVID) - Read Only This register contains the device ID (0x01 for XR16L580). Prior to reading this register, DLL and DLM should be set to 0x00. 4.14 Device Revision Register (DREV) - Read Only This register contains the device revision information. For example, 0x01 means revision A. Prior to reading this register, DLL and DLM should be set to 0x00. 4.15 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive character software flow control selection (see Table 10). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting. EFR[3:0]: Software Flow Control Select Single character and dual sequential characters software flow control is supported. Combinations of software flow control can be selected by programming these bits. 33 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 TABLE 10: SOFTWARE FLOW CONTROL FUNCTIONS EFR BIT-3 CONT-3 EFR BIT-2 CONT-2 EFR BIT-1 CONT-1 EFR BIT-0 CONT-0 0 0 0 0 No TX and RX flow control (default and reset) 0 0 X X No transmit flow control 1 0 X X Transmit Xon1, Xoff1 0 1 X X Transmit Xon2, Xoff2 1 1 X X Transmit Xon1 and Xon2, Xoff1 and Xoff2 X X 0 0 No receive flow control X X 1 0 Receiver compares Xon1, Xoff1 X X 0 1 Receiver compares Xon2, Xoff2 1 0 1 1 Transmit Xon1, Xoff1 Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 0 1 1 1 Transmit Xon2, Xoff2 Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 1 1 1 1 Transmit Xon1 and Xon2, Xoff1 and Xoff2, Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 0 0 1 1 No transmit flow control, Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL EFR[4]: Enhanced Function Bits Enable Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 2, 5, 6 and 7 to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values. This feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it is recommended to leave it enabled, logic 1. • Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 2, 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 2, 5-7 are set to a logic 0 to be compatible with ST16C550 mode (default). • Logic 1 = Enables the above-mentioned register bits to be modified by the user. EFR[5]: Special Character Detect Enable • Logic 0 = Special Character Detect Disabled (default). • Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character interrupt, if enabled via IER bit-5. 34 XR16L580 REV. 1.4.1 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE EFR[6]: Auto RTS Flow Control Enable This bit has no functionality in the 24-QFN package. RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and RTS de-asserts to a logic 1 at one trigger level above the programmed trigger level. RTS# will return to a logic 0 when FIFO data falls below one trigger level below the programmed trigger level. The RTS# output must be asserted (logic 0) before the auto RTS can take effect. RTS# pin will function as a general purpose output when hardware flow control is disabled. • Logic 0 = Automatic RTS flow control is disabled (default). • Logic 1 = Enable Automatic RTS flow control. EFR[7]: Auto CTS Flow Control Enable This bit has no functionality in the 24-QFN package. Automatic CTS Flow Control. • Logic 0 = Automatic CTS flow control is disabled (default). • Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic 1. Data transmission resumes when CTS# returns to a logic 0. 4.16 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Write Only These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2. For more details, refer to “Section 2.15, Auto Xon/Xoff (Software) Flow Control” on page 18. 35 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE TABLE 11: UART RESET CONDITIONS FOR CHANNEL A AND B REGISTERS DLM and DLL RESET STATE Bits 15-0 = 0x0001. Resets upon power up only and not when only the Reset Pin is asserted. RHR Bits 7-0 = 0xXX THR Bits 7-0 = 0xXX IER Bits 7-0 = 0x00 FCR Bits 7-0 = 0x00 ISR Bits 7-0 = 0x01 LCR Bits 7-0 = 0x00 MCR Bits 7-0 = 0x00 LSR Bits 7-0 = 0x60 MSR Bits 3-0 = Logic 0 Bits 7-4 = Logic levels of the inputs inverted SPR Bits 7-0 = 0xFF EFR Bits 7-0 = 0x00 XON1 Bits 7-0 = 0x00 XON2 Bits 7-0 = 0x00 XOFF1 Bits 7-0 = 0x00 XOFF2 Bits 7-0 = 0x00 I/O SIGNALS TX RESET STATE Logic 1 RTS# Logic 1 (Not available in 24-QFN package) DTR# Logic 1 (Not available in 24-QFN and 28-QFN packages) INT Three-State Condition 36 REV. 1.4.1 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 ABSOLUTE MAXIMUM RATINGS Power Supply Range 7 Volts Voltage at Any Pin GND-0.3 V to 7 V Operating Temperature -40o to +85oC Storage Temperature -65o to +150oC Package Dissipation 500 mW TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) Thermal Resistance (48-TQFP) theta-ja =59oC/W, theta-jc = 16oC/W Thermal Resistance (32-QFN) theta-ja = 40oC/W, theta-jc = 13oC/W DC ELECTRICAL CHARACTERISTICS UNLESS OTHERWISE NOTED: TA=-40O TO +85OC, VCC=2.97 - 5.5V SYMBOL LIMITS 3.3V MIN MAX PARAMETER LIMITS 5.0V MIN MAX UNITS CONDITIONS VILCK Clock Input Low Level -0.3 0.6 -0.5 0.6 V VIHCK Clock Input High Level 2.4 VCC 3.0 VCC V VIL Input Low Voltage -0.3 0.8 -0.5 0.8 V VIH Input High Voltage 2.0 5.5 2.2 5.5 V VOL Output Low Voltage 0.4 V V IOL = 6 mA V V IOH = -6 mA 0.4 VOH Output High Voltage 2.4 2.0 IOL = 4 mA IOH = -1 mA IIL Input Low Leakage Current ±10 ±10 uA See Test 1A IIH Input High Leakage Current ±10 ±10 uA See Test 1B CIN Input Pin Capacitance 5 5 pF ICC Power Supply Current 2 3 mA ISLEEP/ IPWRSV Sleep / Power-Save Current (16 and 68 modes, QFN Packages) 15 30 uA See Test 2 ISLEEP/ IPWRSV Sleep / Power-Save Current (16 mode, 48-TQFP Package) 90 150 uA See Test 2 ISLEEP/ IPWRSV Sleep / Power-Save Current (68 mode, 48-TQFP Package) 180 300 uA See Test 2 37 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 DC ELECTRICAL CHARACTERISTICS UNLESS OTHERWISE NOTED: TA=-40O TO +85OC, VCC=1.62 - 2.75V SYMBOL PARAMETER LIMITS 1.8V MIN MAX LIMITS 2.5V MIN MAX UNITS VILCK Clock Input Low Level -0.3 0.6 -0.3 0.6 V VIHCK Clock Input High Level ?? VCC 1.8 VCC V CONDITIONS VIL Input Low Voltage -0.3 0.5 -0.3 0.5 V VIH Input High Voltage ?? 5.5 1.8 5.5 V VOL Output Low Voltage 0.4 V V IOL = 2 mA V V IOH = -400 uA ?? VOH Output High Voltage 1.8 ?? IOL = IOH = IIL Input Low Leakage Current ±10 ±10 uA See Test 1A IIH Input High Leakage Current ±10 ±10 uA See Test 1B CIN Input Pin Capacitance 5 5 pF ICC Power Supply Current 0.5 1 mA ISLEEP/ IPWRSV Sleep / Power-Save Current (16 and 68 modes, QFN Packages) 3 6 uA See Test 2 ISLEEP/ IPWRSV Sleep / Power-Save Current (16 mode, 48-TQFP Package) 30 65 uA See Test 2 ISLEEP/ IPWRSV Sleep / Power-Save Current (68 mode, 48-TQFP Package) 65 130 uA See Test 2 Test 1A: For 48-TQFP package only: The 16/68# pin has an internal pull-up resistor, so the input leakage current is -80uA max. Test 1B: For 48-TQFP package only: The PwrSave pin has an internal pull-down resistor, so the input leakage current is 80uA max. Test 2: The following inputs must remain steady at VCC or GND state to minimize sleep current: A0-A2, D0-D7, IOR#, IOW# (R/W#), CS# and all modem inputs. Also, RXA and RXB inputs must idle at logic 1 state while asleep. Floating inputs may result in sleep currents in the mA range. The 48-TQFP package has a higher current because of the internal pull-up and pull-down resistors on the 16/68# and PwrSave pins respectively. For Power-Save, the UART internally isolates all of these inputs (except the modem inputs, 16/68# and Reset pins) therefore eliminating any unnecessary external buffers to keep the inputs steady. SEE”POWER-SAVE FEATURE” ON PAGE 20. To achieve minimum power drain, the voltage at any of the inputs of the L580 should NOT be lower than its VCC supply. 38 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 AC ELECTRICAL CHARACTERISTICS UNLESS OTHERWISE NOTED: TA=-40O TO +85OC, VCC=2.97 - 5.5V, 70 PF LOAD WHERE APPLICABLE SYMBOL LIMITS 3.3 PARAMETER MIN - LIMITS 5.0 MAX MIN UNIT MAX Crystal Frequency 20 24 MHz OSC External Clock Frequency 33 50 MHz CLK External Clock Low/High Time 15 10 ns TAS Address Setup Time (16 Mode) 5 10 ns TAH Address Hold Time (16 Mode) 0 0 ns TCS Chip Select Width (16 Mode) 50 30 ns TRD IOR# Strobe Width (16 Mode) 50 30 ns TDY Read Cycle Delay (16 Mode) 50 30 ns TRDV Data Access Time (16 Mode) TDD Data Disable Time (16 Mode) 0 TWR IOW# Strobe Width (16 Mode) 50 30 ns TDY Write Cycle Delay (16 Mode) 50 30 ns TDS Data Setup Time (16 Mode) 15 12 ns TDH Data Hold Time (16 Mode) 3 5 ns 50 20 0 25 ns 20 ns TADS Address Setup (68 Mode) 5 10 ns TADH Address Hold (68 Mode) 0 0 ns TRWS R/W# Setup to CS# (68 Mode) 10 10 ns Read Data Access (68 mode) 50 25 TRDA Read Data Disable Time (68 mode) TWDS Write Data Setup (68 mode) 15 12 ns TWDH Write Data Hold (68 Mode) 3 5 ns TRWH CS# De-asserted to R/W# De-asserted (68 Mode) 10 10 ns TCSL CS# Width (68 Mode) 50 30 ns TCSD CS# Cycle Delay (68 Mode) 50 30 ns TWDO Delay From IOW# To Output 75 50 ns TMOD Delay To Set Interrupt From MODEM Input 75 50 ns TRSI Delay To Reset Interrupt From IOR# 75 50 ns TSSI Delay From Stop To Set Interrupt 1 1 Bclk TRRI Delay From IOR# To Reset Interrupt 75 50 ns TSI Delay From Stop To Interrupt 75 50 ns TINT Delay From Initial INT Reset To Transmit Start 24 Bclk TWRI Delay From IOW# To Reset Interrupt 50 ns TRST Reset Pulse Width 40 N Baud Rate Divisor 1 Bclk 20 ns TRDH 8 24 20 8 75 Baud Clock 40 216-1 1 16X of data rate 39 ns ns 216-1 Hz XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 AC ELECTRICAL CHARACTERISTICS UNLESS OTHERWISE NOTED: TA=-40O TO +85OC, VCC=1.62 - 2.75V, 70 PF LOAD WHERE APPLICABLE SYMBOL LIMITS 1.8 PARAMETER MIN - LIMITS 2.5 MAX MIN Crystal Frequency UNIT MAX 18 MHz OSC External Clock Frequency (with 2K pull-up on XTAL2) 12 24 MHz OSC External Clock Frequency (with XTAL2 floating) 2? 18 MHz CLK External Clock Low/High Time 20 ns TAS Address Setup Time (16 Mode) 5 ns TAH Address Hold Time (16 Mode) 0 ns TCS Chip Select Width (16 Mode) 100 ns TRD IOR# Strobe Width (16 Mode) 100 ns TDY Read Cycle Delay (16 Mode) 100 ns TRDV Data Access Time (16 Mode) TDD Data Disable Time (16 Mode) 0 TWR IOW# Strobe Width (16 Mode) 100 ns TDY Write Cycle Delay (16 Mode) 100 ns TDS Data Setup Time (16 Mode) 25 ns TDH Data Hold Time (16 Mode) 3 ns TADS Address Setup (68 Mode) 5 ns 0 75 ns 30 ns TADH Address Hold (68 Mode) 0 ns TRWS R/W# Setup to CS# (68 Mode) Read Data Access (68 mode) 10 75 ns TRDA TRDH Read Data Disable Time (68 mode) TWDS Write Data Setup (68 mode) 25 ns TWDH Write Data Hold (68 Mode) 3 ns TRWH CS# De-asserted to R/W# De-asserted (68 Mode) CS# Width (68 Mode) 10 100 ns TCSL TCSD CS# Cycle Delay (68 Mode) 100 ns TWDO Delay From IOW# To Output 150 ns TMOD Delay To Set Interrupt From MODEM Input 150 ns TRSI Delay To Reset Interrupt From IOR# 150 ns TSSI Delay From Stop To Set Interrupt 1 Bclk TRRI Delay From IOR# To Reset Interrupt 150 ns TSI Delay From Stop To Interrupt 150 ns TINT Delay From Initial INT Reset To Transmit Start 24 Bclk TWRI Delay From IOW# To Reset Interrupt 150 ns TRST Reset Pulse Width 40 N Baud Rate Divisor 1 Bclk ns 30 1 8 Baud Clock 24 8 1 16X of data rate 40 ns 40 216-1 ns ns 216-1 Hz XR16L580 REV. 1.4.1 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE FIGURE 15. CLOCK TIMING CLK CLK EXTERNAL CLOCK OSC FIGURE 16. MODEM INPUT/OUTPUT TIMING IOW# T WDO RTS# DTR# Change of state Change of state CD# CTS# DSR# Change of state Change of state T MOD T MOD Activ e INT Activ e Activ e T RSI Activ e IOR# Activ e Activ e T MOD Change of state RI# 41 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 FIGURE 17. 16 MODE (INTEL) DATA BUS READ TIMING A0A2 Valid Address Valid Address TAS TAS TAH TCS TAH TCS CS# TDY TRD TRD IOR# TDD TRDV TDD TRDV Valid Data D0-D7 Valid Data RDTm FIGURE 18. 16 MODE (INTEL) DATA BUS WRITE TIMING A0A2 Valid Address Valid Address TAS TAS TAH TCS TAH TCS CS# TDY TWR TWR IOW# TDS D0-D7 TDH Valid Data TDS TDH Valid Data 16Write 42 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 FIGURE 19. 68 MODE (MOTOROLA) DATA BUS READ TIMING A0-A2 Valid Address TADS TCSL Valid Address TADH CS# TCSD TRWS TRWH R/W# TRDH TRDA D0-D7 Valid Data Valid Data 68Read FIGURE 20. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING A0-A2 Valid Address TADS TCSL Valid Address TADH CS# TCSD TRWS TRWH R/W# TWDS D0-D7 T WDH Valid Data Valid Data 68Write 43 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 FIGURE 21. RECEIVE READY INTERRUPT TIMING [NON-FIFO MODE] RX Start Bit Stop Bit D0:D7 INT D0:D7 D0:D7 TSSR TSSR TSSR 1 Byte in RHR 1 Byte in RHR 1 Byte in RHR TRR TRR TRR IOR# (Reading data out of RHR) RXNFM FIGURE 22. TRANSMIT READY INTERRUPT TIMING [NON-FIFO MODE] TX (Unloading) IER[1] enabled Start Bit Stop Bit D0:D7 ISR is read D0:D7 D0:D7 ISR is read ISR is read INT* TWRI TWRI TSRT TWRI TSRT TSRT IOW# (Loading data into THR) TXNonFIFO *INT is cleared when the ISR is read or when data is loaded into the THR. 44 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 FIGURE 23. RECEIVE READY INTERRUPT TIMING [FIFO MODE] Start Bit RX S D0:D7 S D0:D7 T D0:D7 Stop Bit S D0:D7 T S D0:D7 T S D0:D7 T S D0:D7 T RX FIFO drops below RX Trigger Level TSSI INT TSSR RX FIFO fills up to RX Trigger Level or RX Data Timeout TRRI IOR# (Reading data out of RX FIFO) RXINTDMA# FIGURE 24. TRANSMIT READY INTERRUPT TIMING [FIFO MODE] TX FIFO Empty TX Start Bit Stop Bit S D0:D7 T IER[1] enabled Last Data Byte Transmitted T S D0:D7 T S D0:D7 T S D0:D7 T S D0:D7 T TSI ISR is read S D0:D7 T ISR is read INT* TX FIFO fills up to trigger level TWRI TX FIFO drops below trigger level IOW# (Loading data into FIFO) TX INT *INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level. 45 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm) D D1 36 25 24 37 D1 13 48 1 2 1 B e A2 C A α Seating Plane A1 L Note: The control dimension is the millimeter column INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.039 0.047 1.00 1.20 A1 0.002 0.006 0.05 0.15 A2 0.037 0.041 0.95 1.05 B 0.007 0.011 0.17 0.27 C 0.004 0.008 0.09 0.20 D 0.346 0.362 8.80 9.20 D1 0.272 0.280 6.90 7.10 e 0.020 BSC 0.50 BSC L 0.018 0.030 0.45 0.75 a 0× 7× 0× 7× 46 D XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 mm) Note: the actual center pad is metallic and the size (D2) is device-dependent with a typical tolerance of 0.3mm Note: The control dimension is in millimeter. INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.031 0.039 0.80 1.00 A1 0.000 0.002 0.00 0.05 A3 0.006 0.010 0.15 0.25 D 0.193 0.201 4.90 5.10 D2 0.138 0.150 3.50 3.80 b 0.007 0.012 0.18 0.30 e 0.0197 BSC 0.50 BSC L 0.012 0.020 0.35 0.45 k 0.008 - 0.20 - 47 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 PACKAGE DIMENSIONS (28 PIN QFN - 5 X 5 X 0.9 mm) Note: the actual center pad is metallic and the size (D2) is device-dependent with a typical tolerance of 0.3mm Note: The control dimension is in millimeter. INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.031 0.039 0.80 1.00 A1 0.000 0.002 0.00 0.05 A3 0.006 0.010 0.15 0.25 D 0.193 0.201 4.90 5.10 D2 0.138 0.150 3.50 3.80 b 0.007 0.012 0.18 0.30 e 0.0197 BSC 0.50 BSC L 0.014 0.018 0.35 0.45 k 0.008 - 0.20 - 48 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 PACKAGE DIMENSIONS (24 PIN QFN - 4 X 4 X 0.9 mm) Note: the actual center pad is metallic and the size (D2) is device-dependent with a typical tolerance of 0.3mm Note: The control dimension is in millimeter. INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.031 0.039 0.80 1.00 A1 0.000 0.002 0.00 0.05 A3 0.006 0.010 0.15 0.25 D 0.154 0.161 3.90 4.10 D2 0.098 0.110 2.50 2.80 b 0.007 0.012 0.18 0.30 e 0.0197 BSC 0.50 BSC L 0.014 0.018 0.35 0.45 k 0.008 - 0.20 - 49 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 REVISION HISTORY DATE REVISION DESCRIPTION November 2003 Rev 1.0.0 Final Datasheet. Updated DC and AC Electical Characteristics Tables. December 2003 Rev 1.1.0 Added missing 16 Mode (Intel) data bus read timing diagram. January 2004 Rev 1.2.0 Updated DC Electrical Characteristics to include ICC and Sleep/Power-Save current for final production devices of 48-TQFP and 32-QFN packages. October 2004 Rev 1.3.0 Corrected 32-QFN package dimension descriptions. Added GND center pad pin description. February 2005 Rev 1.3.1 Corrected 32-QFN pinout on page 2 (pinout with 16/68# pin connected to GND is for Motorola bus mode). August 2005 Rev 1.4.0 Added 28-QFN and 24-QFN packages. The modem pins DTR#, DSR#, RI# and CD# are not available in the 28-QFN package. The modem pins RTS#, CTS#, DTR#, DSR#, RI# and CD# are not available in the 24-QFN package. May 2007 Rev 1.4.1 Updated QFN package dimensions drawing to show minimum "k" parameter. NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2007 EXAR Corporation Datasheet May 2007. Send your UART technical inquiry with technical details to hotline: [email protected]. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 50 xr REV. 1.4.1 XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE TABLE OF CONTENTS GENERAL DESCRIPTION................................................................................................. 1 APPLICATIONS ............................................................................................................................................... 1 FEATURES ..................................................................................................................................................... 1 FIGURE 1. BLOCK DIAGRAM ............................................................................................................................................................. 1 FIGURE 2. PACKAGES AND PIN OUT (24, 28 AND 32-PIN QFN PACKAGES)........................................................................................ 2 FIGURE 3. PACKAGES AND PIN OUT (48-TQFP PACKAGE)................................................................................................................ 3 ORDERING INFORMATION ................................................................................................................................ 3 PIN DESCRIPTIONS ......................................................................................................... 4 1.0 PRODUCT DESCRIPTION .................................................................................................................... 7 2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................................ 8 2.1 CPU INTERFACE ............................................................................................................................................. 8 FIGURE 4. XR16L580 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS ............................................................................. 8 2.2 2.3 2.4 2.5 2.6 2.7 5-VOLT TOLERANT INPUTS ........................................................................................................................... DEVICE HARDWARE RESET .......................................................................................................................... DEVICE IDENTIFICATION AND REVISION .................................................................................................... INTERNAL REGISTERS ................................................................................................................................... DMA MODE ...................................................................................................................................................... INT (IRQ#) OUTPUT ......................................................................................................................................... 9 9 9 9 9 9 TABLE 1: INT (IRQ#) PIN OPERATION FOR TRANSMITTER ................................................................................................................. 9 TABLE 2: INT (IRQ#) PIN OPERATION FOR RECEIVER .................................................................................................................... 10 2.8 CRYSTAL OR EXTERNAL CLOCK INPUT ................................................................................................... 10 FIGURE 5. TYPICAL CRYSTAL CONNECTIONS ................................................................................................................................... 10 FIGURE 6. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE .......................................................................................... 11 2.9 PROGRAMMABLE BAUD RATE GENERATOR .......................................................................................... 11 FIGURE 7. BAUD RATE GENERATOR AND PRESCALER ..................................................................................................................... 11 TABLE 3: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK ...................................................................... 12 2.10 TRANSMITTER ............................................................................................................................................. 13 2.10.1 2.10.2 FIGURE 8. 2.10.3 FIGURE 9. TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY....................................................................................... 13 TRANSMITTER OPERATION IN NON-FIFO MODE ................................................................................................ 13 TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 13 TRANSMITTER OPERATION IN FIFO MODE ......................................................................................................... 13 TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ..................................................................................... 14 2.11 RECEIVER .................................................................................................................................................... 14 2.11.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .......................................................................................... 14 FIGURE 10. RECEIVER OPERATION IN NON-FIFO MODE .................................................................................................................. 15 FIGURE 11. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ....................................................................... 15 2.12 2.13 2.14 AUTO RTS (HARDWARE) FLOW CONTROL ............................................................................................ 16 AUTO RTS HYSTERESIS ........................................................................................................................... 16 AUTO CTS FLOW CONTROL ..................................................................................................................... 16 FIGURE 12. AUTO RTS AND CTS FLOW CONTROL OPERATION (NOT AVAILABLE IN 24-QFN PACKAGE)........................................... 17 2.15 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL .................................................................................. 18 TABLE 4: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ............................................................................................................... 18 2.16 SPECIAL CHARACTER DETECT ............................................................................................................... 18 2.17 INFRARED MODE ........................................................................................................................................ 19 FIGURE 13. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING .......................................................................... 19 2.18 SLEEP MODE WITH WAKE-UP INTERRUPT AND POWER-SAVE FEATURE ........................................ 20 2.18.1 SLEEP MODE ........................................................................................................................................................... 20 2.18.2 POWER-SAVE FEATURE ........................................................................................................................................ 20 2.19 INTERNAL LOOPBACK .............................................................................................................................. 21 FIGURE 14. INTERNAL LOOP BACK ................................................................................................................................................. 21 3.0 UART INTERNAL REGISTERS ........................................................................................................... 22 TABLE 5: UART INTERNAL REGISTERS.................................................................................................................................... 22 TABLE 6: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1.......................................... 23 4.0 INTERNAL REGISTER DESCRIPTIONS ............................................................................................ 24 4.1 4.2 4.3 4.4 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ............................................................................... TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................ BAUD RATE GENERATOR DIVISORS (DLL AND DLM) - READ/WRITE ................................................... INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ............................................................................. 24 24 24 24 4.4.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 24 I XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE xr REV. 1.4.1 4.4.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION ................................................................ 25 4.5 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 26 4.5.1 INTERRUPT GENERATION: ...................................................................................................................................... 26 4.5.2 INTERRUPT CLEARING: ........................................................................................................................................... 26 TABLE 7: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 27 4.6 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ...................................................................................... 27 TABLE 8: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION .............................................................................................. 28 4.7 LINE CONTROL REGISTER (LCR) - READ/WRITE ...................................................................................... 28 TABLE 9: PARITY SELECTION .......................................................................................................................................................... 29 4.8 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 4.9 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 4.10 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................. 4.11 SCRATCHPAD REGISTER (SPR) - READ/WRITE ..................................................................................... 4.12 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 4.13 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY .................................................................... 4.14 DEVICE REVISION REGISTER (DREV) - READ ONLY .............................................................................. 4.15 ENHANCED FEATURE REGISTER (EFR) ................................................................................................. 30 31 32 33 33 33 33 33 TABLE 10: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 34 4.16 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - WRITE ONLY ................ 35 TABLE 11: UART RESET CONDITIONS FOR CHANNEL A AND B............................................................................................ 36 ABSOLUTE MAXIMUM RATINGS...................................................................................37 TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 37 DC ELECTRICAL CHARACTERISTICS ..............................................................................................................37 DC ELECTRICAL CHARACTERISTICS ..............................................................................................................38 AC ELECTRICAL CHARACTERISTICS ..............................................................................................................39 Unless otherwise noted: TA=-40o to +85oC, Vcc=2.97 - 5.5V, 70 pF load where applicable ................................... 39 AC ELECTRICAL CHARACTERISTICS ..............................................................................................................40 Unless otherwise noted: TA=-40o to +85oC, Vcc=1.62 - 2.75V, 70 pF load where applicable ................................. 40 FIGURE 15. FIGURE 16. FIGURE 17. FIGURE 18. FIGURE 19. FIGURE 20. FIGURE 21. FIGURE 22. FIGURE 23. FIGURE 24. CLOCK TIMING ............................................................................................................................................................. 41 MODEM INPUT/OUTPUT TIMING .................................................................................................................................... 41 16 MODE (INTEL) DATA BUS READ TIMING ................................................................................................................... 42 16 MODE (INTEL) DATA BUS WRITE TIMING.................................................................................................................. 42 68 MODE (MOTOROLA) DATA BUS READ TIMING .......................................................................................................... 43 68 MODE (MOTOROLA) DATA BUS WRITE TIMING ......................................................................................................... 43 RECEIVE READY INTERRUPT TIMING [NON-FIFO MODE] ............................................................................................... 44 TRANSMIT READY INTERRUPT TIMING [NON-FIFO MODE] ............................................................................................. 44 RECEIVE READY INTERRUPT TIMING [FIFO MODE] ....................................................................................................... 45 TRANSMIT READY INTERRUPT TIMING [FIFO MODE] ..................................................................................................... 45 PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 MM)...............................................46 PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 MM)..............................................47 PACKAGE DIMENSIONS (28 PIN QFN - 5 X 5 X 0.9 MM)..............................................48 PACKAGE DIMENSIONS (24 PIN QFN - 4 X 4 X 0.9 MM)..............................................49 REVISION HISTORY.......................................................................................................................................50 TABLE OF CONTENTS ............................................................................................................ I II