YAMAHA YDA136

YDA136
D- 60
STEREO 60W-100W DIGITAL AUDIO POWER AMPLIFIER CONTROLLER
■Outline
YDA136 (D-60) is a high efficient and high output digital audio power amplifier controller IC.
By combining a general purpose PowerMOSFET (hereafter called PowerMOSFET) which is connected with YDA136
and BTL, it is able to compose a high efficient audio power amplifier such as 60Wx2ch (Supplied voltage=32V, RL=6Ω)
and 100Wx2ch (Supplied voltage=40V, RL=6Ω).
YDA136 has 24bit 192kHz (max) DAC and 6 to -73dB(1dB Step) of electron volumes in addition to a digital amplifier
controller, and supports a digital audio signal input. Furthermore, it also supports an analog audio signal input with DAC
bypasses.
YDA136 realizes a high-standing audio characteristic that is lower noise and distortion rate by performing an analog
feedback from PowerMOSFET output, and by using Yamaha’s unique modulation method.
YDA136 also equips a function (Over current detection function) which protects a circuit from a short of speaker output
terminal (after the LC filter) and a function (Supplied voltage detection function) which prevents a malfunction by
detecting a power supply falling.
Moreover, it has a function (Clock stop detection function) to protect a circuit by detecting a stop termination of PWM
carrier clock and a function (High-temperature detection function) to protect a circuit by detecting the unusual
high-temperature condition of it-self.
At last, by making three YDA136 to daisy-chain connection, the audio system of 6ch is easily realizable.
■Features
・High Output Power
100W (VBB=40V, RL=6Ω)
60W (VBB=32V, RL=6Ω)
・Low Distortion Rate(THD+N)
0.05% (Po=50W, 1kHz, RL=6Ω, at digital input)
0.03% (Po=50W, 1kHz, RL=6Ω, at analog input)
・High S/N Ratio
100dB (VBB=40V, A-filter, Gain=21.7+6dB, RL=6Ω,
at digital input
・Low Residual Noise
100µV (VBB=40V, Gain=21.7+6dB, at digital input)
70µV (VBB=40V, Gain=21.7+6dB, at analog input)
・Channel Separation
80dB (1kHz, Po=50W)
・ Supports 24bit Digital input and Analog input
・ Built-in 6 to -73dB(1dB Step) of electron volume
・ Multi-channel synchronous operation by switching
Master/Slave function.
・ Protect reset function
・ Hard mute function
・ Monophonic function
・ Unusual operation detection protection function
(Over current, Supplied voltage, Speaker terminal
short, Clock stop, Heat)
・ Pop noise rejection function at the time of
power-up
・ 100 pin plastic SQFP
Pin lead plating with Pd-free (YDA136-SZ)
YDA136 CATALOG
CATALOG No.:LSI-4DA136A20
2005.4
YDA136
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSSL
VREFL
VDDL
IBB
OML
OPL
FBPL
FBML
ITPL
ITML
OFCL1
OFCL2
OFCL3
DLYLL
OCPLL
ONPLU
ONPLD
VSSPL
ONMLD
ONMLU
VDDPL
N.C.
N.C.
N.C.
N.C.
■Terminal Configuration
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
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26
76
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80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VSSR
VREFR
VDDR
TEST
OMR
OPR
FBPR
FBMR
ITPR
ITMR
OFCR1
OFCR2
OFCR3
DLYLR
OCPLR
ONPRU
ONPRD
VSSPR
ONMRD
ONMRU
VDDPR
N.C.
N.C.
N.C.
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
AIL
AOL
N.C.
DVSS1
MUTEN
PROTN
PRSTN
CSN
VDI
VDO
MCLK
LRCLK
SCLK
SDIN
MCKIO
DVDD1
DET
MSSEL
MONO
DVDD2
XI
XO
DVSS2
AOR
AIR
<100pin SQFP Top View>
2
N.C.
N.C.
N.C.
VBSPL
OPMLD
OPMLU
VBBPL
OPPLU
OPPLD
VBB
OCPHL
DLYHL
DLYHR
OCPHR
VBS
OPPRD
OPPRU
VBBPR
OPMRU
OPMRD
VBSPR
N.C.
N.C.
N.C.
N.C.
YDA136
■Terminal Functions
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
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23
24
25
26
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30
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32
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39
40
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45
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47
48
49
50
Name
VSSR
VREFR
VDDR
TEST
OMR
OPR
FBPR
FBMR
ITPR
ITMR
OFCR1
OFCR2
OFCR3
DLYLR
OCPLR
ONPRU
ONPRD
VSSPR
ONMRD
ONMRU
VDDPR
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VBSPR
OPMRD
OPMRU
VBBPR
OPPRU
OPPRD
VBS
OCPHR
DLYHR
DLYHL
OCPHL
VBB
OPPLD
OPPLU
VBBPL
OPMLU
OPMLD
VBSPL
N.C.
N.C.
N.C.
I/O
PWR
AO
PWR
DI
AO
AO
AI
AI
AO
AO
AI
AI
AI
AI
AI
DO
DO
PWR
DO
DO
PWR
-
-
-
-
-
-
-
-
PWRH
DOH
DOH
PWRH
DOH
DOH
PWRH
AIH
AIH
AIH
AIH
PWRH
DOH
DOH
PWRH
DOH
DOH
PWRH
-
-
-
Function
Rch Analog Ground Terminal
Rch Reference Voltage Output Terminal
Rch Analog Power Terminal
Test Terminal: Usually, use it by “L” fixation.
Rch Electron Volume Output Terminal Inverted side
Rch Electron Volume Output Terminal Noninverted side
Rch Digital Amplifier Input Terminal
Noninverted side
Rch Digital Amplifier Input Terminal
Inverted side
Rch External Filter Element Connection Terminal Noninverted side
Rch External Filter Element Connection Terminal Inverted side
Hold to “H” level.
Hold to “L” level.
Hold to “L” level.
Rch Low-Side Driver Off-time Setting Terminal
Rch Low-Side Over Current Detection Terminal
Rch Low-Side Driver Output Terminal
Noninverted side (Pull-up)
Rch Low-Side Driver Output Terminal
Noninverted side (Pull-down)
Rch Low-Side Driver Ground Terminal
Rch Low-Side Driver Output Terminal
Inverted side (Pull-down)
Rch Low-Side Driver Output Terminal
Inverted side (Pull-up)
Rch Low-Side Driver Power Terminal
Non connection.
Non connection.
Non connection.
Non connection.
Non connection.
Non connection.
Non connection.
Non connection.
Rch High-Side Driver Power Terminal
Rch High-Side Driver Output Terminal
Inverted side (Pull-down)
Rch High-Side Driver Output Terminal
Inverted side (Pull-up)
Rch High-Side Driver Power Terminal
Rch High-Side Driver Output Terminal
Noninverted side (Pull-up)
Rch High-Side Driver Output Terminal
Noninverted side (Pull-down)
High-Side Common Circuit Power Terminal
Rch High-Side Over Current Detection Terminal
Rch High-Side Driver Off-time Setting Terminal
Lch High-Side Driver Off-time Setting Terminal
Lch High-Side Over Current Detection Terminal
High-Side Common Circuit Power Terminal
Lch High-Side Driver Output Terminal
Noninverted side (Pull-down)
Lch High-Side Driver Output Terminal
Noninverted side (Pull-up)
Lch High-Side Driver Power Terminal
Lch High-Side Driver Output Terminal
Inverted side (Pull-up)
Lch High-Side Driver Output Terminal
Inverted side (Pull-down)
Lch High-Side Driver Power Terminal
Non connection.
Non connection.
Non connection.
Note: DI: Digital Input Terminal, DO: Digital Output Terminal, DIO: Digital I/O Terminal, DOH:High-Side Digital Output Terminal
AI: Analog Input Terminal, AO: Analog Output Terminal, AIH:High-Side Analog Input Terminal
PWR:Low-Side Power Terminal, PWRH:High-Side Power Terminal
3
YDA136
No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
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68
69
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81
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94
95
96
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98
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100
Name
N.C.
N.C.
N.C.
N.C.
VDDPL
ONMLU
ONMLD
VSSPL
ONPLD
ONPLU
OCPLL
DLYLL
OFCL3
OFCL2
OFCL1
ITML
ITPL
FBML
FBPL
OPL
OML
IBB
VDDL
VREFL
VSSL
AIL
AOL
N.C.
DVSS1
MUTEN
PROTN
PRSTN
CSN
VDI
VDO
MCLK
LRCLK
SCLK
SDIN
MCKIO
DVDD1
DET
MSSEL
MONO
DVDD2
XI
XO
DVSS2
AOR
AIR
I/O
-
-
-
-
PWR
DO
DO
PWR
DO
DO
DO
AI
AI
AI
AI
AO
AO
AI
AI
AO
AO
AI
PWR
AO
PWR
AI
AO
-
PWR
DI
DO
DI
DI
DI
DO
DI
DI
DI
DI
DIO
PWR
DO
DI
DI
PWR
DI
DO
PWR
AO
AI
Function
Non connection.
Non connection.
Non connection.
Non connection.
Lch Low-Side Driver Power Terminal
Lch Low-Side Driver Output Terminal
Inverted side (Pull-up)
Lch Low-Side Driver Output Terminal
Inverted side (Pull-down)
Lch Low-Side Driver Ground Terminal
Lch Low-Side Driver Output Terminal
Noninverted side (Pull-down)
Lch Low-Side Driver Output Terminal
Noninverted side (Pull-up)
Lch Low-Side Over Current Detection Terminal
Lch Low-Side Driver Off-time Setting Terminal
Hold to “L” level.
Hold to “L” level.
Hold to “H” level.
Lch External Filter Elements Connection Terminal
Inverted side
Lch External Filter Elements Connection Terminal
Noninverted side
Lch Digital Amplifier Input Terminal
Inverted side
Lch Digital Amplifier Input Terminal
Noninverted side
Lch Electron Volume Output Terminal
Noninverted side
Lch Electron Volume Output Terminal
Inverted side
VBB Power-voltage Detection Terminal (Supplied-voltage feedback Terminal)
Lch Analog Power Terminal
Lch Reference Power-voltage Output Terminal
Lch Analog Ground Terminal
Lch Electron Volume Input Terminal
(Analog Signal Input Terminal)
Lch DAC Output Terminal
Non connection.
Digital Ground Terminal
Mute Control Terminal
Unusual Detection Output Terminal
(Open-drain)
Protect Reset Control Terminal
MPU Interface Chip-select Input Terminal
MPU Interface Serial Data Input Terminal
MPU Interface Serial Data Output Terminal
MPU Interface Serial Clock Input Terminal
DAC Interface Serial Word Clock Input Terminal
DAC Interface Serial Clock Input Terminal
DAC Interface Serial Data Input Terminal
Clock Input/Output Terminal
Digital Power Terminal
Startup Standby Time Setting Terminal
Slave mode/Master mode Change Terminal
Monophonic Control Terminal
CERALOCK Power Terminal
CERALOCK Connection Terminal
CERALOCK Connection Terminal
CERALOCK Ground Terminal
Rch DAC Output Terminal
Rch Electron Volume Input Terminal
(Analog Signal Input Terminal)
Note: DI: Digital Input Terminal, DO: Digital Output Terminal, DIO: Digital I/O Terminal, DOH:High-Side Digital Output Terminal
AI: Analog Input Terminal, AO: Analog Output Terminal, AIH:High-Side Analog Input Terminal
PWR:Low-Side Power Terminal, PWRH:High-Side Power Terminal
“CERALOCK” is the trademark of Murata Manufacturing Co., Ltd.
4
YDA136
■Block Diagram
5
YDA136
■Description of Block Functions
①
②
③
④
⑤
⑥
⑦
⑧
⑨
Stores the digital audio signal into DAC data register through a DAC interface.
Inputs into DAC through an over-sampling filter, and converts into an analog signal.
Performs a DC cut to DAC output data with the exterior capacitor of IC.
Performs a volume control and Differential signal conversion.
Performs a pulse width modulation
Negative feedbacks from the output of an external PowerMOSFET buffer.
Performs an Off-time delay control, and drives an external PowerMOSFET(Pch, Nch).
High current digital pulse signal is output from external PowerMOSFET (Pch, Nch)
The digital pulse signal is converted into audio signals by external LC filter and transmitted to speaker.
Stores the 7-bit volume data and control data into volume register and control register respectively through a MPU
interface.
Operation control circuit and protect circuit
Master clock generation circuit and carrier clock generation circuit
■Supply of Power
YDA136 needs to be supplied the following two kinds of power supplies, the object for Low-Side drivers (Analog
Circuit), and the object for High-Side drivers, in addition to a power stage power supply (VBB, VSS).
Be sure to use VDD power for Low-Side driver and VBS for High-Side driver.
6
YDA136
■Description of Terminals Functions
●Power Supply Terminal
Lo-Side Power Supply Terminal (VDD Power Supply)
DVDD1
Digital Power
DVDD2
CERALOCK Power
VDDL
Lch Analog Power
VDDR
Rch Analog Power
VDDPL
Lch Low-Side Driver Power
VDDPR
Rch Low-Side Driver Power
Lo-Side Ground Terminal (VSS Ground)
DVSS1
Digital Ground
DVSS2
CERALOCK Ground
VSSL
Lch Analog Ground
VSSR
Rch Analog Ground
VSSPL
Lch Low-Side Driver Ground
VSSPR
Rch Low-Side Driver Ground
High-Side Power Supply Terminal (VBB Power Supply)
VBB
High-Side Power
VBBPL
Lch High-Side Driver Power
VBBPR
Rch High-Side Driver Power
High-Side Power Supply Terminal (VBS Power Supply)
VBS
High-Side Power
VBSPL
Lch High-Side Driver Power
VBSPR
Rch High-Side Driver Power
●Control Terminal
MUTEN
PRSTN
PROTN
MONO
DET
TEST
Hard Mute Control Terminal
L: Hard mute mode
H: Normal mode
Protect Reset Control Terminal
L: Protect reset mode
H: Normal mode
Unusual Detection Output Terminal
L: Protect mode
Hi-Z: Normal mode
Since it is an OpenDrain output, be sure to pull-up by resistance.
Monophonic Control Terminal
L: Stereo mode
H: Monophonic mode
Start up Standby Time Setting Terminal
Sets up a Start up Standby Time (TWAIT) by connecting a capacitor into this terminal.
Test Terminal
Hold to “L” level.
7
YDA136
●Clock Terminal
XI
XO
MSSEL
MCKIO
CERALOCK Connection Terminal
Master mode: Connects a CERALOCK for 4.19MHz oscillation.
Slave mode: Fixes to “L.”
CERALOCK Connection Terminal
Master mode: Connects a CERALOCK for 4.19MHz oscillation.
Slave mode: Makes to “OPEN”.
Slave mode/ Master mode Selection Terminal
L: Master mode
H: Slave mode
4. 19MHz Clock I/O Terminal
Master mode: Clock Output
Slave mode: Clock Input
●Digital Interface Terminal
MPU Interface
CSN
MCLK
VDI
VDO
MPU
MPU
MPU
MPU
DAC Interface
LRCLK
SCLK
SDIN
DAC Interface Serial Word Clock Input
DAC Interface Serial Clock Input
DAC Interface Serial Data Input
Interface Chip-select Input
Interface Serial Clock Input
Interface Serial Data Input
Interface Serial Data Output
●Analog I/O Terminal
DAC Output Terminal
AOL
Lch DAC Output
AOR
Rch DAC Output
Be sure to make AOR to an OPEN state or to connect to VSS in Monophonic mode.
Electron Volume Input
AIL
Lch Volume Input Signal
AIR
Rch Volume Input Signal
Be sure to make AIR to an OPEN state or to connect to GND in Monophonic mode.
Electron Volume Output
OPL
Lch Electron Volume Output Terminal Noninverted side
OML
Lch Electron Volume Output Terminal Inverted side
OPR
Rch Electron Volume Output Terminal Noninverted side
OMR
Rch Electron Volume Output Terminal Inverted side
Be sure to make both OPR and OMR to a OPEN state or to connect to VSS in Monophonic mode.
8
YDA136
●Terminals for PWM modulation Circuits
FBPL
FBML
ITPL
ITML
DLYLL
DLYHL
Lch
Lch
Lch
Lch
Lch
Lch
Digital Amplifier Input
Noninverted side
Digital Amplifier Input
Inverted side
for External Filter Element Connection Noninverted side
for External Filter Element Connection Inverted side
Low-Side Driver Off-time Setting
High-Side Driver Off-time Setting
FBPR
FBMR
ITPR
ITMR
DLYLR
DLYHR
Rch
Rch
Rch
Rch
Rch
Rch
Digital Amplifier Input
Digital Amplifier Input
for External Filter Element Connection
for External Filter Element Connection
Low-Side Driver Off-time Setting
High-Side Driver Off-time Setting
Noninverted side
Inverted side
Noninverted side
Inverted side
Be sure to make each terminal of Rch to an OPEN state or to connect to VSS in Monophonic mode. In addition, as
for a High-side terminal, be sure to make it to an OPEN state and to connect to VBS.
●PowerMOSFET Drive Terminal
OPPLU
OPPLD
ONPLU
ONPLD
Lch High-Side Driver Output
Lch High-Side Driver Output
Lch Low-Side Driver Output
Lch Low-Side Driver Output
Noninverted side Pull-up
Noninverted side Pull-down
Noninverted side Pull-up
Noninverted side Pull-down
OPMLU
OPMLD
ONMLU
ONMLD
Lch High-Side Driver Output
Lch High-Side Driver Output
Lch Low-Side Driver Output
Lch Low-Side Driver Output
Inverted side Pull-up
Reversal side Pull-down
Inverted side Pull-up
Inverted side Pull-down
OPPRU
OPPRD
ONPRU
ONPRD
Rch High-Side Driver Output
Rch High-Side Driver Output
Rch Low-Side Driver Output
Rch Low-Side Driver Output
Noninverted side Pull-up
Noninverted side Pull-down
Noninverted side Pull-up
Noninverted side Pull-down
OPMRU
OPMRD
ONMRU
ONMRD
Rch High-Side Driver Output
Rch High-Side Driver Output
Rch Low-Side Driver Output
Rch Low-Side Driver Output
Noninverted side Pull-up
Noninverted side Pull-down
Noninverted side Pull-up
Noninverted side Pull-down
Low-Side Driver means the PowerMOSFET (Nch). High-Side Driver means the PowerMOSFET(Pch).
The through rate control of PowerMOSFET is performed by connecting a resistor between the pull-up side output
of a Low-Side driver and PowerMOSFET (Nch) and between the pull-down side of a High-Side driver and
PowerMOSFET (Pch).
9
YDA136
●Terminal for Protect Function
OCPHL
OCPLL
OCPHR
OCPLR
Lch High-Side Over Current Detection Terminal
Lch Low-Side Over Current Detection Terminal
Rch High-Side Over Current Detection Terminal
Rch Low-Side Over Current Detection Terminal
IBB
VBB Supplied Voltage Detection Terminal
This terminal operates also as a supplied voltage feedback terminal.
Be sure to input a specific voltage divided by a resistor VBB and VSS.
●VREF Terminal
VREFL
VREFR
Lch Reference Voltage Output Terminal
Be sure to connect a stabilization capacity.
Rch Reference Voltage Output Terminal
Be sure to connect a stabilization capacity.
●Test Terminal etc.
TEST
OFCL1
OFCR1
OFCL2
OFCR2
OFCL3
OFCR3
10
Hold to “L” level.
Hold to “H” level.
Hold to “H” level.
Hold to “L” level.
Hold to “L” level.
Hold to “L” level.
Hold to “L” level.
YDA136
■Terminal Condition in each Mode
●Operation Mode
YDA136 becomes an operation mode as the following table by the state in each input terminal.
Over Current
Detection
V(OCPLL) - VSS
V(OCPLR) - VSS
V(IBB)
VDD1 =
VBB - VBS
VDD2 =
VDD - VSS
Carrier Clock Frequency
Junction Temperature
Lch High-Side Driver Output
Lch Low-Side Driver Output
Rch High-Side Driver Output
Rch Low-Side Driver Output
-
-
-
-
-
< VIB
-
-
-
-
Hi-z H
L
H
L
-
-
-
-
-
-
< VVB
-
-
-
Hi-z H
L
H
L
-
-
-
-
-
-
-
< VVD
-
-
Hi-z H
L
H
L
L
-
-
-
-
> VIB
> VVB
> VVD
-
-
Hi-z H
L
H
L
H
-
-
-
-
↑
↑
↑
-
> Tmax
H
L
H
L
H
L
-
-
-
↑
↑
↑
-
< Tmax Hi-z H
L
H
L
H
H
-
> VOC1
-
↑
↑
↑
-
-
L
H
L
H
L
H
H
-
-
< VOC2
↑
↑
↑
-
-
L
H
L
H
L
↑
↑
↑
< FC1
< Tmax Hi-z H
L
H
L
PROTN Terminal Level
VBB - V(OCPHL)
VBB - V(OCPHR)
Over Current
Detection Mode
MONO Terminal Level
High temperature
Detection Mode
Hardware Mute
Mode
MUTEN Terminal Level
Protect Reset Mode
PRSTN Terminal Level
Low Voltage
Detection Mode
Power Detection
L
H
H
-
< VOC1
< VOC1
> VOC2
H
H
-
↑
↑
↑
↑
↑
> FC2
↑
Hi-z H
L
H
L
Stereo Mode
H
H
L
↑
↑
↑
↑
↑
> FC1
< FC2
↑
Hi-z
P
P
P
P
Monaural Mode
H
H
H
↑
↑
↑
↑
↑
↑
↑
Hi-z
P
P
*1
L
Clock Stop
Detection Mode
Note:
1)
2)
3)
4)
5)
“-“ means all input conditions.
“H” means “H” level, and “L” means “L” level. In addition, “P” means “Pulse oscillation condition”.
“*1” means indefinite state.
Rch over current detection terminal “OCPLR and OCPHR” can not be operated in Monophonic mode.
In the over current detection mode, the mode is continued even if it goes out of the over current condition.
The over current detection mode is canceled by protect reset mode.
6) All registers are initialized when VDD2 voltage (VDD-VSS) becomes below VVD in the low voltage
detection modes.
7) When YDA136 it-self heats higher than the unusual temperature (Tmax), it will become a high temperature
detection mode.
●Digital Audio Signal Input Mode / Analog Audio Signal Input Mode
YDA136 can input both Digital Audio Signal and Analog Audio Signal.
In case of input for the digital audio signal, be sure to connect DAC output terminal (AOL, AOR) and electron volume
input terminal (AIL, AIR) through capacitor for DC cut.
In addition, in case of input for the analog audio signal; be sure to connect an analog audio signal to electron volume input
terminal (AIL,AIR) through a capacitor for DC cut.
At this time, the output of DAC can be made into High-Z by setting the DAC input format of a control register as MODE8.
11
YDA136
■Functional Explanation of Operations
●Description of Registers
The volume register and the control register are allocated to address “0” and “1” in the register, respectively.
Each 14-bit register is mapped as follows.
Register Map
Bit
0
R1
R0
L6
L5
L4
L3
L2
L1
L0
Control Register
1
MOD0
FS1
FS0
T5
T4
T3
T2
T1
T0
D0
R2
D1
MOD1
D2
R3
D3
MOD2
D4
R4
D5
OSFN
D6
Volume Register
R6…R0 :Rch Volume Register
L6…L0 :Lch Volume Register
ZERO
:Volume Zero-cross Function Selection Register
CF
:Carrier Clock Frequency Selection Register
OSFN
:Over Sampling Filter Function Selection Register
MOD2…0 :DAC Input Format Selection Register
FS1…0 :Over Sampling Mode Selection Register
T5…T0 :(Reserved) Be held at “0.”
12
D7
R5
D8
CF
D9
R6
D13 D12 D11 D10
ZERO
Address
YDA136
●Volume Register
Volume Register L6
R6
vol=Mute
1
vol= 6dB
1
vol= 5dB
1
vol= 4dB
1
vol= 3dB
1
vol= 2dB
1
vol= 1dB
1
vol= 0dB
1
vol= -1dB
1
vol= -2dB
1
vol= -3dB
1
vol= -4dB
1
vol= -5dB
1
vol= -6dB
1
vol= -7dB
1
vol= -8dB
1
vol= -9dB
1
vol= -10dB
1
vol= -11dB
1
vol= -12dB
1
vol= -13dB
1
vol= -14dB
1
vol= -15dB
1
vol= -16dB
1
vol= -17dB
1
vol= -18dB
1
vol= -19dB
1
vol= -20dB
1
vol= -21dB
1
vol= -22dB
1
vol= -23dB
1
vol= -24dB
1
vol= -25dB
1
vol= -26dB
1
vol= -27dB
1
vol= -28dB
1
vol= -29dB
1
vol= -30dB
1
vol= -31dB
1
vol= -32dB
1
vol= -33dB
1
vol= -34dB
1
vol= -35dB
1
vol= -36dB
1
vol= -37dB
1
vol= -38dB
1
vol= -39dB
1
vol= -40dB
1
vol= -41dB
1
vol= -42dB
1
vol= -43dB
1
vol= -44dB
1
vol= -45dB
1
vol= -46dB
1
vol= -47dB
1
vol= -48dB
1
vol= -49dB
1
vol= -50dB
1
vol= -51dB
1
vol= -52dB
1
vol= -53dB
1
vol= -54dB
1
vol= -55dB
1
vol= -56dB
1
L5
R5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
L4
R4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
L3
R3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
L2
R2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
L1
R1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
L0
R0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Volume Register L6
R6
vol= -57dB
0
vol= -58dB
0
vol= -59dB
0
vol= -60dB
0
vol= -61dB
0
vol= -62dB
0
vol= -63dB
0
vol= -64dB
0
vol= -65dB
0
vol= -66dB
0
vol= -67dB
0
vol= -68dB
0
vol= -69dB
0
vol= -70dB
0
vol= -71dB
0
vol= -72dB
0
vol= -73dB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
vol=Mute
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
L5
R5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
L4
R4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
L3
R3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
L2
R2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
L1
R1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
L0
R0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
13
YDA136
T0
*
*
T1
*
*
T2
MOD0
*
*
T3
MOD1
*
*
T4
MOD2
*
*
T5
OSFN
0
1
FS0
CF
Zero-cross Function Termination
Zero-cross Function Operation
FS1
Control Register
ZERO
●Volume Zero-cross Function Selection
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
After a rewrite of register, be sure to cancel mute after waiting for TZERO.
T2
T1
T0
*
*
T3
*
*
T4
MOD1
*
*
T5
MOD2
0
1
FS0
OSFN
*
*
FS1
CF
Carrier Frequency=524kHz
Carrier Frequency=466kHz
MOD0
Control Register
ZERO
●Carrier Clock Frequency Selection
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
After rewrite of register, be sure to cancel mute after waiting for TCF.
T0
*
*
T1
*
*
T2
MOD0
*
*
T3
MOD1
0
1
T4
MOD2
*
*
T5
OSFN
*
*
FS0
CF
Over Sampling Filter Operation
Over Sampling Filter Termination
FS1
Control Register
ZERO
●Over Sampling Filter Function Selection
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
After a rewrite of register, be sure to cancel mute after waiting for TOSFN.
T2
T1
T0
0
0
1
1
0
0
1
1
T3
0
0
0
0
1
1
1
1
T4
MOD1
*
*
*
*
*
*
*
*
T5
MOD2
*
*
*
*
*
*
*
*
FS0
OSFN
*
*
*
*
*
*
*
*
FS1
CF
MODE1
MODE2
MODE3
MODE4
MODE5
MODE6
MODE7
MODE8
MOD0
Control Register
ZERO
●DAC Input Format Selection
0
1
0
1
0
1
0
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
After a rewrite of register, be sure to cancel mute after waiting for TMOD.
Control Register
ZERO
CF
OSFN
MOD2
MOD1
MOD0
FS1
FS0
T5
T4
T3
T2
T1
T0
●Over Sampling Mode Selection
4x Mode
2x Mode
1x Mode
Auto Mode
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0
0
1
1
0
1
0
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
After a rewrite of register, be sure to cancel mute after waiting for TFS.
14
YDA136
■MPU Interface Function
By using the following three terminals “CSN, MCLK, and VDI”, data is written into Volume register and Control register.
In case of writing data in the Control register, be sure to set mute to Volume register in advance. After a write of Control
register or after the given time (TZERO, TCF, TOSFN, TMOD, and TFS), be sure to cancel mute condition.
●Input Format
Please input the data of each 14-bit register into a VDI terminal in MSB first following address bits. The data input from
VDI terminal is taken into internal shift register at the rising edge of MCLK terminal when CSN terminal is “L.” The data
input into shift register is written into the register of the appointed address at the rising edge of CSN terminal.
All the values of registers after a power up are set to “0.”
After a power supply starting, the MPU interface works after passing over a serial access prohibition time (TPUP).
Be sure to perform a power supply staring first, and then perform a write of the data to a register after a serial access
prohibition time (TPUP).
CSN
MCLK
VDI
A1
A0
VDO
D1[13] D1[12] D1[11] D1[10] D1[9]
D0[13] D0[12] D0[11] D0[10] D0[9]
D1[2]
D0[2]
D1[1] D1[0]
D0[1] D0[0]
A1
Here, A1 and D1 [13:0] indicates a register to update and data. In addition, A0 and D0 [13:0] indicates a data input into
VDI terminal before 16-clock.
●Daisy-chain
Multiple Daisy-chain connections for multi-channel system are available in YDA136. For example, 6ch system can be
realized by connecting three YDA136 with Daisy-chain connection.
By connecting a VDO terminal of first YDA136 to VDI terminal of the second YDA136; and then, connecting a VDO
output of second YDA136 to a VDI terminal of the third YDA136, it becomes available to control those three YDA136
simultaneously without a complex addressing.
The data in which it overflowed from the internal 15-bit shift register among the data inputted into each VDI terminal of
YDA136 is output from a VDO terminal synchronizing with falling edge of a MCLK terminal.
By setting CSN terminal to “L” during the number of YDA136×15-clock which daisy-chain connection was made, an
input data is taken into each shift register of YDA136.
Then, writing is simultaneously performed to a volume register (control register) from the shift register of all YDA136
connected to the daisy-chain by setting the CSN terminal of YDA136 to “H.”
VDI
VDO
CSN
YDA136_B
VDI
VDO
MCLK
CSN
YDA136_A
MCLK
MCLK and CSN are connected 3 chips in common.
MCLK
CSN
MPU
YDA136_C
VDI
VDO
15
YDA136
■DAC Function
YDA136 has a 24-bit×2ch of DAC.
The DAC supports the following eight kinds of sampling frequencies (Fs), and it has an over sampling filter corresponding
to each sampling frequencies.
32kHz、44.1kHz、48kHz、64kHz、88.4kHz、96kHz、176.4kHz、192kHz
The output full-scale of this DAC is 1Vrms.
●DAC Interface
Be sure to input a digital audio signal from the following three terminals, SDIN, LRCLK, and SCLK.
DAC interface of YDA136 supports the seven DAC input formats.
Be sure to set up control registers, MOD2, MOD1, and MOD0, and then select a DAC input format to use.
When using the YDA136 as Digital Audio Signal mode, be sure not to stop a SCLK signal except when electronic volume
is mute, protection reset mode, or hard mute mode.
DAC Input Format
MODE1(16bit) MODE2(20bit) MODE3(24bit)
SCLK
SDIN
LSB
MSB
LRCLK
LSB
MSB
Right channel
Left channel
A SDIN bit is sampled by the rising edge of SCLK.
When LRCLK is “H”, be sure to input data for Left channel by right justified.
When LRCLK is “L”, be sure to input data for Right channel by right justified.
SDIN data is written into a DAC data register by the rising edge of LRCLK.
64-clock for one-word.
MODE4(16bit) MODE5(20bit) MODE6(24bit)
SCLK
SDIN
X
LRCLK
MSB
LSB
X
Left channel
MSB
LSB
Right channel
A SDIN bit is sampled by the rising edge of SCLK.
When LRCLK is “L”, be sure to input data for Left channel in left justified with a vacant bit.
When LRCLK is “H”, be sure to input data for Right channel in left justified with a vacant bit.
SDIN data is written into a DAC data register by the falling edge of LRCLK.
64-clock for one-word.
MODE7
SCLK
SDIN
LRCLK
LSB
MSB
Left channel
LSB
MSB
Right channel
A SDIN bit is sampled by the rising edge of SCLK.
When LRCLK is “H”, be sure to input data for Left channel by right justified.
When LRCLK is “L”, be sure to input data for Right channel by right justified.
SDIN data is written into a DAC data register by the rising edge of LRCLK.
64-clock for one-word.
MODE8
Analog Audio Signal Input Mode
16
YDA136
●Over Sampling Filter
Be sure to set up the Over Sampling mode according to a sampling frequency (Fs) of audio signals to input.
Over sampling filter mode can be set up by FS1 and FS0 in the control register.
In addition, an over sampling filter can be bypassed by the setting of control register OSF.
When Fs is 32kHz, 44.1kHz or 48kHz
:Sets up to the 4x mode.
When Fs is 64kHz, 88.2kHz, or 96kHz
:Sets up to the 2x mode.
When Fs is 176.4kHz or 192kHz
:Sets up to the 1x mode.
When it is set as Auto mode, the above mentioned over sampling modes are set up by detecting a sampling frequency (Fs)
of audio signal which was input.
■Volume Function
YDA136 has the electronic volume which can be set up in the range from +6dB to -73dB by 1dB step.
By inputting an analog signal from AIL (AIR) terminal, and attenuating with the set up volume value, this electronic
volume outputs a differential analog signal from an OPL (OPR) terminal and OML (OMR) terminal.
Non-inverted signal from OPL (OPR) terminal and inverted signal from OML (OMR) terminal is output.
The maximum input level is 1Vrms and the maximum output level is 1Vrms.
Be sure to set a volume value to a volume register through a MPU serial data interface.
Moreover, in order to suppress the noise at the time of volume value change, a mode (Zero-cross mode) which changes a
volume value when an output signal carries out a zero-cross, is provided as an option.
●Volume Register
D [13:7] of a volume register shows the volume value of R channels, and D [6:0] shows the volume value of L channels.
"1111111" and from "0101110" to "0000000" becomes mute among each volume value.
At this time, a DAC output signal turns into a non-signal irrespective of an input.
●Zero-cross Mode
This is the volume change mode, which reduces the noise generated at the time of change of the volume value of electronic
volume.
When this mode is selected, the volume value is changed under the following conditions.
・ At the time of an audio signal carries out a Zero-cross
・ After the volume change is set up
・ After the volume value setting time (TZEROWAIT)
When not selected, the volume is changed regardless of the input after the volume setting.
By ZERO of a control register, Zero-cross mode can be set.
17
YDA136
■Digital Amplifier Function
YDA136 has a 2-channel differential analog signal input digital amplifier controller.
This digital amplifier controller consists of High-Side and Low-Side PowerMOSFET drivers and a PWM circuit.
By combining the two sets of Pch/Nch PowerMOSFET in each channel, a digital amplifier (60W to 100W) can be
configured.
To each PowerMOSFET driver, it is possible to set up an off-time individually, and it can be set as the optimal driver
according to PowerMOSFET to be used.
AM intermodulation can be performed with AM reception interference reduction function.
Moreover, it can be optimized to the digital amplifier which has a lower distortion by adding a filter element to a PWM
circuit.
●Gain Setup Method
The gain of digital amplifier can be set up by external resistance (RE1 to RE4).
The gain of digital amplifier can be calculated with the following formula.
⎛ RE1 ⋅ RE 2 + RE 2 ⋅ RE 3 + RE1 ⋅ RE 3 ⎞
⎟⎟
Av(dB ) = 20 ⋅ log⎜⎜
RE 2 ⋅ (RE 4 + 400Ω)
⎝
⎠
However, be sure to set RE4 as more than 10kΩ according to the capability of a built-in operational amplifier.
●Characteristic Improvement by External Filter Element Connection
Although it is possible to realize high performance digital amplifier by the PWM circuit, by adding resistor and a capacitor
between DBPL(FBPR) and ITPL (ITPR), and between FBML (FBMR) and ITML (ITMR), it is possible to optimize a
circuit further and to improve distortion rate.
18
YDA136
●Clock Input
YDA136 operates synchronizing with 4.19MHz clock.
Be sure to connect a 4.16MHz CERALOCK or to supply a clock to YDA136 from the outside.
Be sure to always supply a clock except protection reset mode and hard mute mode.
When using a CERALOCK, be sure to set MSSEL terminal to “L” and to set YDA136 to a master mode.
In case of supplying a clock from the outside, be sure to set MSSL terminal to “H” and to set YDA136 to a slave mode.
Master mode
Be sure to set MSSEL terminal to “L.”
Connects CELALOCK to XI and XO terminal.
Be sure to set the oscillation frequency to 4.19MHz.
At this time, a master clock (4.19MHz) is output from a MCKIO terminal.
Slave mode
Be sure to set MSSEL terminal to “H.”
Be sure to input a master clock (4.19MHz) into a MCKIO terminal.
At this time, be sure to set XI terminal to “L” and set XO terminal to open state.
When making a multi channel amplifier by using multiple YDA136, a system with little interference between channels can
be constituted by using one YDA136 in master mode, and using the remainder in slave mode as shown in the following
figure.
●AM Reception Interference Reduction Function
YDA136 outputs the pulse made by modulating the career clock, which is made by dividing the input master clock.
In order to reduce cross talk caused by the coincidence between harmonics of the output pulse and AM radio frequency,
YDA136 has the changing (frequency hopping) function of two carrier clock frequencies.
A carrier clock frequency can be chosen by the control register CF.
●Off-time Setup Function
Off time delay (Typical)
200
180
160
140
Off time[ns]
A setup of an off-time is individually possible for YDA136
to the High-Side driver and Low-Side driver of Lch and each
Rch.
Off-time adjustment of the Low-Side driver of Lch and each
Rch is possible by the capacitor that is connected to a
DLYLL terminal and a DLYLR terminal.
Moreover, off-time adjustment of the High-Side driver of
Lch and each Rch is possible by the capacitor connected to a
DLYHL terminal and a DLYHR terminal.
Relation between capacitance value of the capacitor and the
relation of an off-time is shown in the figure.
(Under characteristic adjustment)
120
100
80
60
40
20
0
0pF
50pF
100pF
150pF
Capacitor value
19
YDA136
●IBB Terminal Setting
In the PWM circuit, the IBB terminal is used and VBB power supply voltage is
feedbacked. Simultaneously, under voltage detection of VBB power supply voltage is
performed by monitoring the voltage of the terminal.
After making 1.5V by dividing VBB voltage with resistors, an then be sure to input it
into IBB terminal.
Set for the voltage of the IBB terminal not to become 1.6V or more even if the VBB
voltage moves.
In the case of VBB=40V Example
of a resistance setting
VBB
910kΩ
IBB
36kΩ
●PowerMOSFET Drive Function
Since it is BTL connection digital amplifier, external connection of two sets per channel of Pch and Nch PowerMOSFET is
made.
A High-Side driver output is connected to Pch PowerMOSFET, and a Low-Side driver output is connected to Nch
PowerMOSFET as shown below.
Non-inverted side Pch PowerMOSFET :Be sure to connect to OPPLU and OPPLD (OPPRU,OPPRD).
(High-Side Driver Output)
Non-inverted side Nch PowerMOSFET :Be sure to connect to ONPLU and ONPLD (ONPRU,ONPRD).
(Low-Side Driver Output)
Inverted side Pch PowerMOSFET
:Be sure to connect to OPMLU and OPMLD (OPMRU,OPMRD).
(High-Side Driver Output)
Inverted side Nch PowerMOSFET
:Be sure to connect to ONMLU and ONMLD (ONMRU,ONMRD)
(Low-Side Driver Output)
There are two output terminals to one PowerMOSFET, and they mean the pull-up output and the pull-down output,
respectively.
By connecting gate resistor (RG) between each driver output and PowerMOSFET, slew-rate of both pull-up and pull-down
side separately.
In the example of peripheral circuit connection, resistor (RG) of 20Ω is connected with the pull-down side output of Pch
PowerMOSFET and the pull-up side output of Nch PowerMOSFET.
VBB
VBB
High-Side Driver
P
OPPLU
OPPLD
OPMLU
OPMLD
OPPRU
OPPRD
OPMRU
OPMRD
P
P
P
Low-Side Driver
Analog Circuit
N
ONPLU
ONPLD
ONMLU
ONMLD
ONPRU
ONPRD
ONMRU
ONMRD
N
N
N
RG
YDA136
VSS
VSS
In addition, total amount of electric charges (Qg) of gates in PowerMOSFET, which is used by connecting to YDA136,
should be 20nC or less (Vgs=5V).
20
YDA136
■Protect Function
●Over Current Detection Function
YDA136 has a function to perform an over current protection by detecting a voltage drop of the current detection resistor
connected to the source side of PowerMOSFET.
When the voltage of an over-current detection terminal fulfills the following conditions, it judges that it is in an over-current
condition, and becomes over-current detection mode, and then a circuit is protected.
Voltage to be monitored
Low-Side over-current detection terminal (OCPLL, OCPLR) Voltage
High-Side over-current detection terminal(OCPHL, OCPHR) Voltage and VBB Potential difference
Over-current detection
mode threshold
< VOC2
> VOC1
In the example of peripheral circuit connection, the following four over-current conditions are detected, and then it becomes
an over-current detection mode.
・ A condition in which signals after LC filter and VSS power supply is shorted.
・ A condition in which signals after LC filter of non-inverted side and signals after LC filter of inverted side is
shorted.
・ A condition in which one side of a speaker was connected to LC filter, and another side of a speaker is shorted to
the VSS power supply.
In over-current detection mode, PROTN terminal is set to “L”, simultaneously it turns off all PowerMOSFET (hard mute)
and protects a circuit.
After it is made to over-current detection mode, even if an over-current condition is canceled, it is not canceled but is held
as it is.
Over-current detection mode can be canceled by intercepting a power supply or setting a PRSTN terminal to “L” at once.
●Power Detection Function
YDA136 monitors the following three kinds voltage.
When which voltage is less than regular voltage, it becomes low voltage detection mode.
Voltage to be monitored
IBB Terminal Voltage(It is proportional to the
voltage between VBB and VSS)
VDD1 (Voltage between VBB and VBS)
VDD2 (Voltage between VDD and VSS)
Constant Voltage Detection Mode Threshold
VIB2
VVB2
VVD2
Here, since the IBB terminal has input the signal which divided VBB voltage, the IBB terminal will act as the monitor of
the VBB voltage.
Hard mute is operated in low voltage detection mode.
Among these, all registers are reset when VDD2 voltage is less than threshold voltage (VVD2).
Then, when three kinds of power supply voltage rises and a low voltage detection mode threshold is exceeded altogether,
the low voltage detection mode is canceled and a hard mute is also canceled after starting standby time (TWAIT).
●Starting Standby Time Setup
Starting standby time (TWAIT) can be set up by connecting a capacitor to the DET terminal of YDA136.
Be sure to set up to usually be set to TWAIT>=600msec for internal initialization of YDA136.
The value of starting standby time (TWAIT) and capacity (CDET) of and the capacitor linked to a DET terminal serves as the
following relations.
TWAIT = 60(kΩ)×CDET(F)
In the case of the capacity value (10μF) of the capacitor in the example of peripheral circuit connection, TWAIT is set to
600msec.
21
YDA136
●Clock Stop Detection Function
YDA136 becomes clock stop detection mode, when a career clock frequency exceeds a maximum (FC1) of operation or it is
less than a minimum (FC1).
Hard mute is carried out in clock stop detection mode.
If a career clock frequency enters within normal limits, clock stop detection mode will be canceled and hard mute will be
canceled.
●High Temperature Detection Function
YDA136 is acting as the internal monitor of the temperature of YDA136 self, and when it becomes an unusual temperature
exceeding Tjmax, it serves as high temperature detection mode.
In high temperature detection mode, a PROTN terminal is set to "L" at the same time it carries out hard mute.
Then, a PROTN terminal is set to "H" at the same time it cancels high temperature detection mode and cancels hard mute,
when temperature falls and it becomes a normal range.
●Self-recovery function
By connecting a PROTN terminal and a PRSTN terminal, when a PROTN terminal is set to "L" by over-current detection
and high temperature detection, it can be set as fixed time protection reset mode, and hard mute release (automatic return)
can be carried out after starting standby time (TWAIT).
22
YDA136
■Control Function
●Hard Mute Function
YDA136 serves as hard mute mode, when a MUTEN terminal is "L."
In hard mute mode, they are all PowerMOSFETs. It turns off (hard mute).
Hard mute will be canceled if a MUTEN terminal is set to "H."
Rewriting of all registers is possible for during a hard mute mode period.
●Protect Reset Function
YDA136 serves as protection reset mode, when a PRSTN terminal is "L."
A PROTN terminal is set to "H" in protection reset mode.
Hard mute is carried out simultaneously, the circuit which operates inside IC is minimized, and consumption current is
reduced.
After canceling protection reset mode, using a PRSTN terminal as "H", after starting standby time (TWAIT), hard mute is
canceled and a start of operation is carried out.
Rewriting of all registers is possible for during a hard mute mode period.
Moreover, a register is by protection reset mode. is not carried out.
●Monophonic Function
YDA136 serves as monophonic mode, when a MONO terminal is “H.”
In monophonic mode, only Lch outputs an audio signal, and all the circuits related to Rch is stopped.
Moreover, it becomes stereo mode when a MONO terminal is “L.”
In monophonic mode, the over-current detection function by the OCPLR terminal and the PCPHR terminal does not
operate.
Please perform the change in monophonic mode and stereo mode at the time of interception of a power supply.
The change in the monophonic mode by the MONO terminal at the time of power supply impression and stereo mode is
forbidden.
■Typical Voltage
Since a VREFL terminal and a VREFR terminal output 1/2*VDD2 voltage respectively, be sure to connect and stabilize a
capacitor.
■Initialization / Power-down
●System Initialization
All registers are initialized when VDD2 voltage (VDD-VSS) becomes less than VVD in low voltage detection modes.
The initial value of each register is “0.”
●Power-down
At the time of power interception, be sure to intercept a power after set it as a hard mute mode.
23
YDA136
■Example of System Composition
●Example of peripheral circuit connection
24
YDA136
■Electrical Characteristics
●Absolute Maximum Rating
Item
VBB Power Supply Voltage
VBS Power Supply Voltage
VDD Power Supply Voltage
High-Side Input Terminal Voltage Range*1)
Low-Side Input Terminal Voltage Range
Welding Temperature
Storage Temperature Range
*1)
Symbol
VBB
VBS
VDD
VIN1
VIN2
Tjmax
TSTG
Min
-0.3
VBB-7.0
-0.3
VBS-0.3
-0.3
Max
50
VBB+0.3
7.0
VBB+0.3
VDD+0.3
125
125
–50
Unit
V
V
V
V
V
ºC
ºC
The voltage range to DLYHL, DLYHR, OCPHL, and OCPHR are indicated.
●Recommended Operation Condition
Item
VBB Power Supply Voltage
VBS Power Supply Voltage
VDD Power Supply Voltage
Speaker Impedance
Operation Ambient Temperature
Symbol
VBB
VBS
VDD
RL
Ta
Min
20
VBB-4.75
4.75
4
-40
Typ
VBB-5.0
5.0
6
25
Max
50
VBB-5.25
5.25
85
Unit
V
V
V
Ω
ºC
●DC Characteristics (Adjust Condition:VDD=5.0V, VBB=40V, Ta=-40 to 85℃)
Item
High-Side Driver H Level Output Voltage (IOH=-100mA)
High-Side Driver L Level Output Voltage (IOL=+100mA)
Low-Side Driver H Level Output Voltage (IOH=-100mA)
Low-Side Driver L Level Output Voltage (IOL=+100mA)
XO Terminal H Level Output Voltage (IOH=-80µA)
XO Terminal L Level Output Voltage (IOL=+1.6mA)
MCKIO Terminal H Level Output Voltage (IOH=-80µA)
MCKIO Terminal L Level Output Voltage (IOL=+1.6mA)
PROTN Terminal L Level Output Voltage (IOL=+1.6mA)
Digital Terminal H Level Input Voltage
Digital Terminal L Level Input Voltage
MCKIO, MSSEL Terminal H Level Input Voltage
MCKIO, MSSELTerminal H Level Input Voltage
IBB Terminal Power Detection Threshold Voltage (Start)
High-Side Driver power
Power Detection Threshold Voltage (Start)
High-Side Driver power
Power Detection Threshold Voltage (CO)
Low-Side Driver power
Power Detection Threshold Voltage (Start)
Low-Side Driver power
Power Detection Threshold Voltage (CO)
High-Side Over-current Detection Thrshol Voltage
Low-Side Over-current Detection Thrshol Voltage
Low-Side Over-current Detection Thrshol Voltage
VREFL, VREFR Terminal Output Voltage
Stereo Mode VBB Power Consumption ( No-Signal)
Stereo Mode High-Side Power Consumption (No-Signal)
Stereo Mode Low-Side Power Consumption (No-Signal)
Mute Mode VBB Power Consumption
Mute Mode High-Side Power Consumption
Mute Mode Low-Side Power Consumption
Protection Reset Mode VBB Power Consumption
Protection Reset Mode High-Side Power Consumption
Protection Reset Low-Side Power Consumption
Symbol
VOHPD
VOLPD
VOHND
VOLND
VOHXO
VOLXO
VOHMC
VOLMC
VOLPR
VIH
VIL
VIHMC
VILMC
VIB1
VVB1
Min
VBB-0.4
Typ
Max
VBS+0.4
VDD-0.4
0.4
VDD-0.4
0.4
VDD-0.4
0.4
0.4
2.2
0.8
0.7×VDD
0.75
4.0
0.3×VDD
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VVB2
3.8
V
VVD1
4.0
V
VVD2
3.8
V
VOC1
VOC1
VOC2
VREF
IBB
ID1
ID2
IBBM
ID1M
ID2M
IBBP
ID1P
ID2P
1.25
1.25
0.6
2.5
3
35
50
3
6
28
3
6
10
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
25
YDA136
●AC Characteristic (Adjust Condition:VDD=5.0V, VDDH=5.0V, VBB=40V, Ta=-40 to 85℃)
Item
SCLK Frequency
SCLK High Time
SCLK Low Time
SDIN Input Setup Time
SDIN Input Hold Time
LRCK Setup Time
LRCK Hold Time
MCLK Frequency
MCLK High Time
MCLK Low Time
VDI Input Setup Time
VDI Input Hold Time
CSN Setup Time
CSN Hold Time
VDO Output Delay ( to MCLK Edge) (CL=20pF)
Symbol
1/TSCLK
TSCLKH
TSCLKL
TSDINS
TSDINH
TLRCKS
TLRCKH
FMCLK
TMCLKH
TMCLKL
TVDIS
TVDIH
TCSNS
TCSNH
TVDOMCLK
Min
Typ
*1)
Max
40
40
20
20
30
30
6.25
80
80
20
20
30
30
60
*1) 1/TSCLK=64Fs(Fs=32 to 192kHz)
LRCLK
TLRCKS
TSDINS
TSCLKL
TLRCKH
TMCLKL
TCSNH
SCLK
TSCLKH
TSDINH
SDIN
CSN
TCSNS
TVDIS
MCLK
TMCLKH
TVDIH
VDI
TVDOMCLK
VDO
26
Unit
MHz
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
YDA136
●Audio Characteristic
(Measurement Condition:VDD=5.0V, VDDH=5.0V, VBB=40V, Ta=25℃, Fs=48kHz, Volume=0dB、
100W Specifications (Gain=22.6dB+6dB), filter is as example of peripheral circuit connection, Speaker
Impedance=6Ω)
Item
Distortion (Input=1kHz, Output=50W, at Digital Input)
Distortion (Input=1kHz, Output=50W、at Analog Input)
Residual Noise (Gain=22.6+6dB)
Signal-Noise Ratio (A-filter, Gain=22.6+6dB)
Channel Separation (Input=1kHz, Output=50W)
Symbol
THD+N
THD+N
Vn
SNR
CS
Min
Typ
0.05
0.03
100
100
80
Max
Unit
dB
dB
µV
dB
dB
Note) All the values of audio characteristics were obtained by using our evaluation circumstance.
The characteristics may vary according to the Power MOSFET, coils, capacitors and pattern layout that are used
in the system.
●Timing Rules and Regulations
Item
Operation Standby Time (CDET=10µF)
Standby Time after a write of ZERO register
Standby Time after a write of CF register
Standby Time after a write of OSFN register
Standby Time after a write of MOD register
Standby Time after a write of FS register
Symbol
TWAIT
TZERO
TCF
TOSFN
TMOD
TFS
Min
Typ
0.6
Max
10
10
10
10
10
Unit
s
ms
ms
ms
ms
ms
27
YDA136
■Typical characteristics examples
Power vs THD+N (RL=6Ω)
Analog Input non-Regulated power supply
Power vs THD+N (RL=6Ω)
Analog Input Regulated power supply
10
10
Lch
Rch
Lch
Rch
1
THD+N(%)
THD+N(%)
1
0.1
0.1
0.01
0.01
0.001
0.0001
0.001
0.01
0.1
1
Output Power(W)
10
100
0.001
0.0001
1000
RL = 6Ω VBB = 40V VBS = 35V VDD = 5V
Freq = 1kHz Filter : <20kHz
PowerMOSFET : 2SJ545, 2SK2933(RENESAS)
0.001
0.01
0.1
1
Output Power(W)
10
100
1000
RL = 6Ω VBB = 40V VBS = 35V VDD = 5V
Freq = 1kHz Filter : <20kHz
PowerMOSFET : 2SJ545, 2SK2933(RENESAS)
Power vs THD+N (RL=6Ω)
Digital Input Regulated power supply
THD+N(%)
10
Lch
Rch
1
0.1
0.01
0.0001
0.001
0.01
0.1
1
Output Power(W)
10
100
1000
RL = 6Ω VBB = 40V VBS = 35V VDD = 5V
Freq = 1kHz(Fs = 48kHz 16bit ×4) Filter : <20kHz
PowerMOSFET : 2SJ545, 2SK2933(RENESAS)
Frequency Characteristic(RL=6Ω)
Analog Input
Frequency Characteristics(RL=6Ω)
Digital Input
0.0
(dBV)
(dBV)
0.0
Lch
Rch
-1.0
-2.0
-2.0
10
100
1000
Frequency(Hz)
10000
VBB = 40V VBS = 35V VDD = 5V Half Power
Lo = 15uH Co = 0.39uF RL = 6Ω
PowerMOSFET : 2SJ545, 2SK2933(RENESAS)
28
Lch
Rch
-1.0
100000
10
100
1000
Frequency(Hz)
10000
VBB = 40V VBS = 35V VDD = 5V Half Power
Lo = 15uH Co = 0.39uF RL = 6Ω
PowerMOSFET : 2SJ545, 2SK2933(RENESAS)
100000
YDA136
Signal Frequency vs Channel Separation
PSRR (VBB Power supply)
-40
-45
Rch->Lch
Lch->Rch
PSRR(dB)
(dB)
-60
-65
-70
-75
-80
-85
-90
-95
-100
Lch
Rch
-50
-55
-60
-65
10
100
1000
Frequency(Hz)
10000
10
100000
100
RL = 6Ω VBB = 40V VBS = 35V VDD = 5V Half Power
Analog Input Freq = 1kHz
PowerMOSFET : 2SJ545, 2SK2933(RENESAS)
Efficiency(%)
Efficiency(%)
90
85
80
75
70
65
60
55
50
RL=6Ω
RL=4Ω
RL=8Ω
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Output Power(W)
Output Power(W)
VBB = 40V VBS = 35V VDD = 5V
Freq = 1kHz(Fs = 48kHz 16bit ×4)
PowerMOSFET : 2SJ545, 2SK2933(RENESAS)
VBB = 40V VBS = 35V VDD = 5V
Freq = 1kHz(Fs = 48kHz 16bit ×4)
PowerMOSFET : 2SJ532, 2SK2934(RENESAS)
Output Noise Spectrum Digital Input Mode
Output Noise Spectrum Analog Input Mode
0
0
-20
-20
Lch
Rch
-40
Lch
Rch
-40
-60
-60
(dBV)
(dBV)
100000
Efficiency vs Power
2SJ532, 2SK2934(RENESAS)
RL=6Ω
RL=4Ω
RL=8Ω
0
10000
VBB = 40V±100mVrms VBS = 35V VDD = 5V RL = 6Ω
Analog Input Freq = 1kHz
PowerMOSFET : 2SJ545, 2SK2933(RENESAS)
Efficiency vs Power
2SJ545, 2SK2933(RENESAS)
90
85
80
75
70
65
60
55
50
1000
Signal frequency added to power supply (Hz)
-80
-100
-80
-100
-120
-120
-140
-140
-160
-160
10
100
1000
Frequency(Hz)
10000
RL = 6Ω VBB = 40V VBS = 35V VDD = 5V
MOSFET : 2SJ545, 2SK2933(RENESAS)
PowerMOSFET : 2SJ545, 2SK2933(RENESAS)
100000
10
100
1000
Frequency(Hz)
10000
100000
RL = 6Ω VBB = 40V VBS = 35V VDD = 5V
MOSFET : 2SJ545, 2SK2933(RENESAS)
PowerMOSFET : 2SJ545, 2SK2933(RENESAS)
29
YDA136
■Package Outline
30
YDA136
MEMO
31
YDA136
Notice
The specifications of this product are subject to improvement changes without prior notice.