ZILOG Z51F0410HCX

Z8051 Series 8-Bit Microcontrollers
Z51F0410
Product Specification
PS029502-0212
PRELIMINARY
Copyright ©2012 Zilog®, Inc. All rights reserved.
www.zilog.com
Z51F0410
Product Specification
ii
Warning: DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS.
LIFE SUPPORT POLICY
ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
Document Disclaimer
©2012 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications,
or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES
NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE
INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO
DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED
IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED
HEREIN OR OTHERWISE. The information contained within this document has been verified according
to the general principles of electrical and mechanical engineering.
Z8051 is a trademark or registered trademark of Zilog, Inc. All other product or service names are the
property of their respective owners.
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Z51F0410
Product Specification
iii
Revision History
Each instance in this document’s revision history reflects a change from its previous edition. For more details, refer to the corresponding page(s) or appropriate links furnished in
the table below.
Revision
Level
Description
Page
Feb
2012
02
Removed references to SOP, PDIP packages.
All
Jan
2012
01
Original Zilog issue.
All
Date
PS029502-0212
PRELIMINARY
Revision History
Z51F0410
Product Specification
Table of Contents
1. OVERVIEW .................................................................................................................................... 11
1.1 Description ............................................................................................................................... 11
1.2 Features ................................................................................................................................... 11
1.3 Ordering Information ................................................................................................................ 12
1.3.1 Part Number Suffix Designation ........................................................................................ 13
1.4 Development Tools .................................................................................................................. 13
1.4.1 Compiler ........................................................................................................................... 13
1.4.2 OCD Emulator and Debugger ........................................................................................... 13
1.5 Block Diagram .......................................................................................................................... 15
1.6 PIN Assignment ....................................................................................................................... 16
1.7 Package Diagram ..................................................................................................................... 17
1.8 Reconfigurable Pin Description ................................................................................................ 18
1.8.1 USART Pin Location Switch Mode .................................................................................... 18
1.8.2 I2C Pin Location Switch Mode .......................................................................................... 18
1.8.3 External Interrupt Pin Location Switch Mode ..................................................................... 19
1.8.4 Buzzer Out Pin Location Switch Mode .............................................................................. 20
1.8.5 TIMER Pin Location Switch Mode ..................................................................................... 21
1.9 Code Encryption (Super Lock) ................................................................................................. 21
1.10 Port Structure ......................................................................................................................... 23
1.10.1 General Purpose I/O Port................................................................................................ 23
1.10.2 External Interrupt I/O Port ............................................................................................... 24
1.11 Port Structure Diagram (detail view) ....................................................................................... 25
1.11.1 P0[0] Port Structure ........................................................................................................ 25
1.11.2 P0[1] Port Structure ........................................................................................................ 26
1.11.3 P0[2] Port Structure ........................................................................................................ 27
1.11.4 P0[3] Port Structure ........................................................................................................ 29
1.11.5 P0[4] Port Structure ........................................................................................................ 31
1.11.6 P0[5] Port Structure ........................................................................................................ 33
1.11.7 P0[6]/P0[7] Port Structure ............................................................................................... 35
1.12 Electrical Characteristics ........................................................................................................ 36
1.12.1 Absolute Maximum Ratings ............................................................................................ 36
1.12.2 Recommended Operating Conditions ............................................................................. 36
1.12.3 A/D Converter Characteristics ......................................................................................... 36
1.12.4 Voltage Dropout Converter Characteristics ..................................................................... 37
1.12.5 Power-On Reset Characteristics ..................................................................................... 37
1.12.6 Brown Out Detector Characteristics ................................................................................ 38
1.12.7 Internal 8Mhz, 128Khz RC Oscillator Characteristics ..................................................... 38
1.12.8 Analog Comparator Characteristics ................................................................................ 38
1.12.9 DC Characteristics .......................................................................................................... 39
1.12.10 AC Characteristics ........................................................................................................ 40
1.12.11 Typical Characteristics .................................................................................................. 40
2. Functional Description .................................................................................................................... 42
2.1 Memory .................................................................................................................................... 42
2.1.1 Program Memory .............................................................................................................. 42
2.1.2 Data Memory .................................................................................................................... 42
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2.1.3 EEPROM Data Memory .................................................................................................... 44
2.2 SFR Map .................................................................................................................................. 45
2.2.1 SFR Map Summary .......................................................................................................... 45
2.2.2 SFR Map ........................................................................................................................... 46
2.2.3 Compiler Compatible SFR ................................................................................................ 49
2.3 I/O Port..................................................................................................................................... 51
2.3.1 I/O Ports............................................................................................................................ 51
2.3.2 Port Register ..................................................................................................................... 51
2.3.3 P0 Port .............................................................................................................................. 52
3. Interrupt Controller ......................................................................................................................... 56
3.1 Overview .................................................................................................................................. 56
3.2 External Interrupt ...................................................................................................................... 56
3.3 Block Diagram .......................................................................................................................... 58
3.4 Interrupt Vector Table............................................................................................................... 59
3.5 Interrupt Sequence ................................................................................................................... 59
3.6 Effective Timing after Controlling Interrupt bit ........................................................................... 61
3.7 Multi Interrupt ........................................................................................................................... 61
3.8 Interrupt Enable Accept Timing ................................................................................................ 63
3.9 Interrupt Service Routine Address ............................................................................................ 63
3.10 Saving/Restore General-Purpose Registers ........................................................................... 63
3.11 Interrupt Timing ...................................................................................................................... 64
3.12 Interrupt Register Overview .................................................................................................... 64
3.12.1 Interrupt Enable Register (IE, IE1, IE2, IE3) .................................................................... 64
3.12.2 Interrupt Priority Register (IP, IP1) .................................................................................. 64
3.12.3 External Interrupt Flag Register (EIFLAG) ...................................................................... 65
3.12.4 External Interrupt Edge Register (EIEDGE) .................................................................... 65
3.12.5 External Interrupt Polarity Register (EIPOLA) ................................................................. 65
3.12.6 External Interrupt Enable Register (EIENAB) .................................................................. 65
3.12.7 Register Map................................................................................................................... 65
3.13 Interrupt Register Description ................................................................................................. 65
3.13.1 Register description for Interrupt ..................................................................................... 65
4. Peripheral Hardware....................................................................................................................... 69
4.1 Clock Generator ....................................................................................................................... 69
4.1.1 Overview ........................................................................................................................... 69
4.1.2 Block Diagram................................................................................................................... 69
4.1.3 Register Map..................................................................................................................... 70
4.1.4 Clock Generator Register description ............................................................................... 70
4.1.5 Register description for Clock Generator .......................................................................... 70
4.2 BIT ........................................................................................................................................... 72
4.2.1 Overview ........................................................................................................................... 72
4.2.2 Block Diagram................................................................................................................... 72
4.2.3 Register Map..................................................................................................................... 72
4.2.4 Bit Interval Timer Register description .............................................................................. 73
4.2.5 Register description for Bit Interval Timer ......................................................................... 73
4.3 WDT ......................................................................................................................................... 74
4.3.1 Overview ........................................................................................................................... 74
4.3.2 Block Diagram................................................................................................................... 74
4.3.3 Register Map..................................................................................................................... 74
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4.3.4 Watch Dog Timer Register description .............................................................................. 75
4.3.5 Register description for Watch Dog Timer......................................................................... 75
4.3.6 WDT Interrupt Timing Waveform....................................................................................... 76
4.4 WT ........................................................................................................................................... 77
4.4.1 Overview ........................................................................................................................... 77
4.4.2 Block Diagram................................................................................................................... 77
4.4.3 Register Map..................................................................................................................... 77
4.4.4 Watch Timer Register description ..................................................................................... 77
4.4.5 Register description for Watch Timer ................................................................................ 78
4.5 Timer/PWM .............................................................................................................................. 80
4.5.1 8-bit Timer/Event Counter 0, 1 .......................................................................................... 80
4.5.2 16-Bit Timer 4 ................................................................................................................... 92
4.6 USART ..................................................................................................................................... 96
4.6.1 Overview ........................................................................................................................... 96
4.6.2 Block Diagram................................................................................................................... 97
4.6.3 Clock Generation .............................................................................................................. 98
4.6.4 External Clock (XCK) ........................................................................................................ 99
4.6.5 Synchronous mode operation ........................................................................................... 99
4.6.6 Data format ....................................................................................................................... 99
4.6.7 Priority bit ........................................................................................................................ 100
4.6.8 USART Transmitter ......................................................................................................... 100
4.6.9 USART Receiver ............................................................................................................. 101
4.6.10 SPI Mode ...................................................................................................................... 104
4.6.11 Register Map................................................................................................................. 106
4.6.12 USART Register description ......................................................................................... 107
4.6.13 Register description for USART .................................................................................... 107
4.6.14 Baud Rate setting (example) ......................................................................................... 110
4.7 I2C ......................................................................................................................................... 112
4.7.1 Overview ......................................................................................................................... 112
4.7.2 Block Diagram................................................................................................................. 112
4.7.3 I2C Bit Transfer ............................................................................................................... 112
4.7.4 START / REPEATED START / STOP ............................................................................. 113
4.7.5 DATA TRANSFER .......................................................................................................... 113
4.7.6 ACKNOWLEDGE ............................................................................................................ 114
4.7.7 SYNCHRONIZATION / ARBITRATION........................................................................... 114
4.7.8 OPERATION ................................................................................................................... 115
4.7.9 Register Map................................................................................................................... 123
4.7.10 I2C Register description ................................................................................................ 123
4.7.11 Register description for I2C ........................................................................................... 123
4.8 12-Bit A/D Converter .............................................................................................................. 126
4.8.1 Overview ......................................................................................................................... 126
4.8.2 Block Diagram................................................................................................................. 127
4.8.3 ADC Operation................................................................................................................ 128
4.8.4 Register Map................................................................................................................... 129
4.8.5 ADC Register description ................................................................................................ 129
4.8.6 Register description for ADC ........................................................................................... 129
4.9 Analog Comparator ................................................................................................................ 132
4.9.1 Overview ......................................................................................................................... 132
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4.9.2 Block Diagram................................................................................................................. 132
4.9.3 IN/OUT signal description ............................................................................................... 132
4.9.4 Register Map................................................................................................................... 133
4.9.5 Analog Comparator Register description......................................................................... 133
4.9.6 Register description for Analog Comparator ................................................................... 133
4.10 Buzzer Driver ....................................................................................................................... 134
4.10.1 Overview ....................................................................................................................... 134
4.10.2 Block Diagram............................................................................................................... 135
4.10.3 Register Map................................................................................................................. 135
4.10.4 Buzzer Driver Register description ................................................................................ 135
4.10.5 Register description for Buzzer Driver ........................................................................... 135
5. Power Down Operation ................................................................................................................ 137
5.1 Overview ................................................................................................................................ 137
5.2 Peripheral Operation In IDLE/STOP Mode ............................................................................. 137
5.3 IDLE mode ............................................................................................................................. 137
5.4 STOP mode ........................................................................................................................... 139
5.5 Release Operation of STOP1, 2 Mode ................................................................................... 140
5.5.1 Register Map................................................................................................................... 140
5.5.2 Power Down Operation Register description ................................................................... 141
5.5.3 Register description for Power Down Operation.............................................................. 141
6. RESET ......................................................................................................................................... 142
6.1 Overview ................................................................................................................................ 142
6.2 Reset source .......................................................................................................................... 142
6.3 Block Diagram ........................................................................................................................ 142
6.4 RESET Noise Canceller ......................................................................................................... 142
6.5 Power ON RESET .................................................................................................................. 143
6.6 External RESETB Input .......................................................................................................... 145
6.7 Brown Out Detector Processor ............................................................................................... 146
6.7.1 Register Map................................................................................................................... 148
6.7.2 Reset Operation Register description ............................................................................. 148
6.7.3 Register description for Reset Operation ........................................................................ 148
7. On-chip Debug System ................................................................................................................ 150
7.1 Overview ................................................................................................................................ 150
7.1.1 Description ...................................................................................................................... 150
7.1.2 Feature ........................................................................................................................... 150
7.2 Two-pin external interface ...................................................................................................... 151
7.2.1 Basic transmission packet............................................................................................... 151
7.2.2 Packet transmission timing ............................................................................................. 152
7.2.3 Connection of transmission ............................................................................................. 153
8. Memory Programming .................................................................................................................. 155
8.1 Overview ................................................................................................................................ 155
8.1.1 Description ...................................................................................................................... 155
8.1.2 Features.......................................................................................................................... 155
8.2 Flash and EEPROM Control and status register .................................................................... 155
8.2.1 Register Map................................................................................................................... 155
8.2.2 Register description for Flash and EEPROM .................................................................. 156
8.3 Memory map .......................................................................................................................... 160
8.3.1 Flash Memory Map ......................................................................................................... 160
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8.3.2 Data EEPROM Memory Map .......................................................................................... 161
8.4 Serial In-System Program Mode ............................................................................................ 162
8.4.1 Flash operation ............................................................................................................... 162
8.4.2 Data EEPROM operation ................................................................................................ 166
8.4.3 Summary of Flash and Data EEPROM Program/Erase Mode ........................................ 168
8.5 Parallel Mode ......................................................................................................................... 169
8.5.1 Overview ......................................................................................................................... 169
8.5.2 Parallel Mode instruction format ...................................................................................... 170
8.5.3 Parallel Mode timing diagram .......................................................................................... 171
8.6 Mode entrance method of ISP and byte-parallel mode ........................................................... 171
8.6.1 Mode entrance method for ISP ....................................................................................... 171
8.6.2 Mode entrance of Byte-parallel ....................................................................................... 172
8.7 Security .................................................................................................................................. 173
9. Configure option ........................................................................................................................... 174
9.1 Configure option Control Register .......................................................................................... 174
9.2 Serial ID ................................................................................................................................. 175
10. APPENDIX ................................................................................................................................. 176
10.1 Instruction Table ................................................................................................................... 176
10.2 Instructions on how to use the input port. ............................................................................. 179
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List of Figures
Figure 1.1 OCD Debugger and Pin Configuration............................................................................... 14
Figure 1.2 Top Abstract Block Diagram .............................................................................................. 15
Figure 1.3 10-SSOP PIN Assignment Diagram of Z51F0410HCX ...................................................... 16
Figure 1.7 10-SSOP Package Diagram .............................................................................................. 17
Figure 1.8 USART Pin Location : USART_PINMODE=0 .................................................................... 18
Figure 1.9 USART Pin Location : USART_PINMODE=1 .................................................................... 18
Figure 1.10 I2C Pin Location : I2C_PINMODE=0 ............................................................................... 19
Figure 1.11 I2C Pin Location : I2C_PINMODE=1 ............................................................................... 19
Figure 1.12 External INT Pin Location : EINT_PINMODE=0 .............................................................. 20
Figure 1.13 External INT Pin Location : EINT_PINMODE=1 .............................................................. 20
Figure 1.14 Buzzer Out Pin Location : BUZO_PINMODE=0 .............................................................. 20
Figure 1.15 Buzzer Out Pin Location : BUZO_PINMODE=1 .............................................................. 21
Figure 1.16 Timer Out Pin Location : TMR_PINMODE=0................................................................... 21
Figure 1.17 Timer Out Pin Location : TMR_PINMODE=1................................................................... 21
Figure 1.18 Super Lock Enabled Encryption/Decryption Diagram ...................................................... 22
Figure 1.19 General Purpose I/O Port ................................................................................................ 23
Figure 1.20 External Interrupt I/O Port................................................................................................ 24
Figure 1.21 XIN(SUBXIN) / AN0 /RXD /P0[0] Port Structure .............................................................. 25
Figure 1.22 XOUT(SUBXOUT) / AN1 / INT1 / TXD / P0[1] Port Structure .......................................... 26
Figure 1.23 RESETB / AN2 / ACK / P0[2] Port Structure .................................................................... 27
Figure 1.24 P0[3] / INT0 / SS / EC0 / AN3 / ACOUT Port Structure ................................................... 29
Figure 1.25 P0[4]/SCL/T0O/AN4/AC-/Avref Port Diagram .................................................................. 31
Figure 1.26 P0[5]/SDA/PWM1O/BUZ/AN5/AC+ Port Structure .......................................................... 33
Figure 1.27 P0[6] / AN6, P0[7] / AN7 Port Structure ........................................................................... 35
Figure 1.28 AC Timing ....................................................................................................................... 40
Figure 2.1 Program memory ............................................................................................................... 42
Figure 2.2 Data memory map ............................................................................................................. 43
Figure 2.3 Lower 128 bytes RAM ....................................................................................................... 44
Figure 2.4 Debounce Function ........................................................................................................... 55
Figure 3.1 External Interrupt Description ............................................................................................ 57
Figure 3.2 Block Diagram of Interrupt ................................................................................................. 58
Figure 3.3 Interrupt Vector Address Table .......................................................................................... 60
Figure 3.4 Effective Timing of Interrupt Enable Register ................................................................... 61
Figure 3.5 Effective Timing of Interrupt Flag Register ......................................................................... 61
Figure 3.6 Execution of Multi Interrupt ................................................................................................ 62
Figure 3.7 Interrupt Response Timing Diagram .................................................................................. 63
Figure 3.8 Correspondence between vector Table address and the entry address of ISP ................. 63
Figure 3.9 Saving/Restore Process Diagram & Sample Source ......................................................... 63
Figure 3.10 Timing chart of Interrupt Acceptance and Interrupt Return Instruction ............................. 64
Figure 4.1 Clock Generator Block Diagram ........................................................................................ 69
Figure 4.2 BIT Block Diagram ............................................................................................................ 72
Figure 4.3 WDT Block Diagram .......................................................................................................... 74
Figure 4.4 WDT Interrupt Timing Waveform ....................................................................................... 76
Figure 4.5 Watch Timer Block Diagram .............................................................................................. 77
Figure 4.6 8 Bit Timer/Event Counter0, 1 Block Diagram ................................................................... 81
Figure 4.7 Timer/Event Counter0, 1 Example ..................................................................................... 82
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Figure 4.8 Operation Example of Timer/Event Counter0, 1 ................................................................ 82
Figure 4.9 16 Bit Timer/Event Counter0, 1 Block Diagram ................................................................. 83
Figure 4.10 8-bit Capture Mode for Timer0, 1..................................................................................... 84
Figure 4.11 Input Capture Mode Operation of Timer 0, 1 ................................................................... 85
Figure 4.12 Express Timer Overflow in Capture Mode ....................................................................... 85
Figure 4.13 16-bit Capture Mode of Timer 0, 1 ................................................................................... 86
Figure 4.14 PWM Mode...................................................................................................................... 87
Figure 4.15 Example of PWM at 4MHz .............................................................................................. 87
Figure 4.16 Example of Changing the Period in Absolute Duty Cycle at 4Mhz ................................... 88
Figure 4.17 Timer4 16-bit Mode Block Diagram ................................................................................. 93
Figure 4.18 USART Block Diagram .................................................................................................... 97
Figure 4.19 Clock Generation Block Diagram..................................................................................... 98
Figure 4.20 Synchronous Mode XCKn Timing. ................................................................................... 99
Figure 4.21 frame format .................................................................................................................. 100
Figure 4.22 Start Bit Sampling .......................................................................................................... 103
Figure 4.23 Sampling of Data and Parity Bit ..................................................................................... 104
Figure 4.24 Stop Bit Sampling and Next Start Bit Sampling ............................................................. 104
Figure 4.25 SPI Clock Formats when UCPHA=0.............................................................................. 105
Figure 4.26 SPI Clock Formats when UCPHA=1.............................................................................. 106
Figure 4.27 I2C Block Diagram ........................................................................................................ 112
Figure 4.28 Bit Transfer on the I2C-Bus ........................................................................................... 113
Figure 4.29 START and STOP Condition ......................................................................................... 113
Figure 4.30 Data Transfer on the I2C-Bus ........................................................................................ 114
Figure 4.31 Acknowledge on the I2C-Bus ........................................................................................ 114
Figure 4.32 Clock Synchronization during Arbitration Procedure ...................................................... 115
Figure 4.33 Arbitration Procedure of Two Masters ........................................................................... 115
Figure 4.34 Formats and States in the Master Transmitter Mode ..................................................... 117
Figure 4.35 Formats and States in the Master Receiver Mode ......................................................... 119
Figure 4.36 Formats and States in the Slave Transmitter Mode ....................................................... 121
Figure 4.37 Formats and States in the Slave Receiver Mode ........................................................... 123
Figure 4.38 ADC Block Diagram....................................................................................................... 127
Figure 4.39 A/D Analog Input Pin Connecting Capacitor .................................................................. 127
Figure 4.40 A/D Power(AVDD) Pin Connecting Capacitor ................................................................ 127
Figure 4.41 ADC Operation for Align bit ........................................................................................... 128
Figure 4.42 A/D Converter Operation Flow....................................................................................... 128
Figure 4.43 Analog Comparator Block Diagram ............................................................................... 132
Figure 5.1 IDLE Mode Release Timing by External Interrupt ............................................................ 138
Figure 5.2 STOP Mode Release Timing by External Interrupt .......................................................... 139
Figure 5.3 STOP1, 2 Mode Release Flow ........................................................................................ 140
Figure 6.1 RESET Block Diagram .................................................................................................... 142
Figure 6.2 Reset noise canceller time diagram ................................................................................. 143
Figure 6.3 Fast VDD rising time........................................................................................................ 143
Figure 6.4 Internal RESET Release Timing On Power-Up ............................................................... 143
Figure 6.5 Configuration timing when Power-on ............................................................................... 144
Figure 6.6 Boot Process Wave Form ................................................................................................ 145
Figure 6.7 Timing Diagram after RESET .......................................................................................... 146
Figure 6.8 Oscillator generating waveform example ......................................................................... 146
Figure 6.9 Block Diagram of BOD .................................................................................................... 147
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Figure 6.10 Internal Reset at the power fail situation ........................................................................ 148
Figure 6.11 Configuration timing when BOD RESET........................................................................ 148
Figure 7.1 Block Diagram of On-chip Debug System ....................................................................... 150
Figure 7.2 10-bit transmission packet ............................................................................................... 151
Figure 7.3 Data transfer on the twin bus ........................................................................................... 152
Figure 7.4 Bit transfer on the serial bus ............................................................................................ 152
Figure 7.5 Start and stop condition ................................................................................................... 152
Figure 7.6 Acknowledge on the serial bus ........................................................................................ 153
Figure 7.7 Clock synchronization during wait procedure .................................................................. 153
Figure 7.8 Connection of transmission ............................................................................................. 154
Figure 8.1 Flash Memory Map .......................................................................................................... 160
Figure 8.2 Address configuration of Flash memory .......................................................................... 160
Figure 8.3 Data EEPROM memory map........................................................................................... 161
Figure 8.4 Address configuration of data EEPROM.......................................................................... 161
Figure 8.5 The sequence of page program and erase of Flash memory .......................................... 162
Figure 8.6 The sequence of bulk erase of Flash memory ................................................................. 163
Figure 8.7 Pin diagram for parallel programming .............................................................................. 169
Figure 8.8 Parallel Byte Read Timing of Program Memory ............................................................... 171
Figure 8.9 Parallel Byte Write Timing of Program Memory ............................................................... 171
Figure 8.10 ISP mode ..................................................................................................................... 172
Figure 8.11 Byte-parallel mode (10pin package only)....................................................................... 172
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List of Tables
Table 1.1 Ordering Information of the Z51F0410 MCU....................................................................... 12
Table 1.2 Absolute Maximum Ratings ................................................................................................ 36
Table 1.3 Recommended Operation Conditions ................................................................................. 36
Table 1.4 A/D Converter Characteristics ............................................................................................ 36
Table 1.5 Voltage Dropout Converter Characteristics......................................................................... 37
Table 1.6 Power-On Reset Characteristics......................................................................................... 37
Table 1.7 Brown Out Detector Characteristics.................................................................................... 38
Table 1.8 Internal 8Mhz RC Oscillator Characteristics ....................................................................... 38
Table 1.9 Internal 128Khz RC Oscillator Characteristics .................................................................... 38
Table 1.10 DC Electrical Characteristics ............................................................................................ 38
Table 1.11 AC Characteristics ............................................................................................................ 39
Table 1.12 DC Characteristics ............................................................................................................ 39
Table 1.13 AC Characteristics ............................................................................................................ 40
Table 2.1 SFR Map Summary ............................................................................................................ 45
Table 2.2 SFR Map ............................................................................................................................ 46
Table 2.3 Register map ...................................................................................................................... 52
Table 3.1 Interrupt Group Priority Level .............................................................................................. 56
Table 3.2 Interrupt Vector Address Table ........................................................................................... 59
Table 3.3 Register Map ...................................................................................................................... 65
Table 4.1 SSCR Register Map ........................................................................................................... 70
Table 4.2 BIT Register Map ................................................................................................................ 72
Table 4.3 WDT Register Map ............................................................................................................. 74
Table 4.4 WT Register Map ................................................................................................................ 77
Table 4.5 Operating Modes of Timer .................................................................................................. 80
Table 4.6 PWM Frequency vs. Resolution at 8 Mhz ........................................................................... 86
Table 4.7 Timer Register Map ............................................................................................................ 88
Table 4-8 Register Map ...................................................................................................................... 93
Table 4.9 Equations for Calculating Baud Rate Register Setting ........................................................ 98
Table 4.10 CPOL Functionality ......................................................................................................... 105
Table 4.11 USART Register Map ..................................................................................................... 106
Table 4.12 Examples of UBAUD Settings for Commonly Used Oscillator Frequencies .................... 110
Table 4.13 Examples of UBAUD Settings for Commonly Used Oscillator Frequencies (continued) . 111
Table 4.14 Examples of UBAUD Settings for Commonly Used Oscillator Frequencies (continued) . 111
Table 4.15 I2C Register Map ............................................................................................................ 123
Table 4.16 ADC Register Map .......................................................................................................... 129
Table 4.17 Analog Comparator Register Map .................................................................................. 133
Table 5.1 Peripheral Operation during Power Down Mode. .............................................................. 137
Table 5.2 PCON Register Map ......................................................................................................... 140
Table 6.1 Reset state ....................................................................................................................... 142
Table 6.2 Boot Process Description ................................................................................................. 145
Table 6.3 BOD Register Map ........................................................................................................... 148
Table 8-1 Flash and EEPROM Register Map ................................................................................... 155
Table 8-2 Flash and Data EEPROM Operation Mode ...................................................................... 168
Table 8-3 The selection of memory type by ADDRH[7:4] ................................................................. 169
Table 8-4 Parallel mode instruction format ....................................................................................... 170
Table 8-5 Control Pin Description ..................................................................................................... 171
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Table 8-6 Security policy using lock-bits ........................................................................................... 173
Table 9-1 Summary of SID ............................................................................................................... 175
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Z51F0410
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 12-BIT A/D CONVERTER
1. OVERVIEW
1.1 Description
The Z51F0410 MCU is advanced CMOS 8-bit microcontroller with 4K bytes of Flash. This is powerful
microcontroller which provides a highly flexible and cost effective solution to many embedded control
applications. This provides the following features : 4K bytes of Flash, 256 bytes of RAM, 256 bytes of
Data EEPROM, general purpose I/O, 8/16-bit timer/counter, watchdog timer, watch timer, USART,
BUZZER, I2C, on-chip POR, 12-bit A/D converter, analog comparator, 10-bit PWM output, on-chip
oscillator and clock circuitry. The Z51F0410 MCU also supports power saving modes to reduce power
consumption.
Device Name
Flash
RAM
ADC
I/O PORT
Package
Z51F0410
4K bytes
256 bytes
8 channel
8
10 SSOP
1.2 Features
• Timer/ Counter
• CPU
- 8 Bit CISC Core (8051 Compatible,2 clock
per cycle)
• 4K Bytes On-chip Flash
- 8Bit×2ch(16Bit×1ch)
- 16bit x 1ch
• 10-bit PWM (Using Timer1)
- Endurance : 10,000 times
- 10Bitx1ch
- Retention : 10 years
• Watch Dog Timer
- Code Encryption (Super Lock)
• Watch Timer
• 256 Bytes SRAM
• USART
• 256 Bytes Data EEPROM
• BUZZER
- mapped in XDATA region
• I2C
- Endurance : 100,000 times
• 12 Bit A/D Converter
- Retention : 10 years
- 8 Input channels
• General Purpose I/O
• Analog Comparator
- 8 Ports (P0[7:0])
- On Chip Analog Comparator with ACOUT
• One Basic Interval Timer
• Interrupt Sources
-Reset Release Time - 16ms, 32ms, 64ms
Configurable
PS029502-0212
- External (2)
PRELIMINARY
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Z51F0410
Product Specification
- Pin Change Interrupt(P0) (1)
• Reconfigurable Secondary Pin Function
- USART (2)
• Minimum Instruction Execution Time
- Timer (3)
- 250ns (@8MHz, NOP Instruction)
- I2C (1)
• Power down mode
- ADC (1)
- IDLE, STOP1, STOP2 mode
- ACOM (1)
• Sub-Active mode
- WDT (1)
- System used external 32.768KHz crystal or
system used internal 128KHz oscillator
- WT (1)
• Operating Frequency
- BIT (1)
- 1MHz ~ 8MHz
- Data EEPROM(1)
• Operating Voltage
• On-Chip RC-Oscillator
- 1.8V ~ 5.5V (@ 1~8MHz)
- 8MHz(±1%) @ 25℃
- 2.2V ~ 5.5V (@ 1~8Mhz, Using Comparator)
- 128KHz(±50%)
• Operating Temperature : -40 ~ +85℃
• Power On Reset
• Package Type
- 1.4V
• Programmable Brown-Out Detector
- 10-pin SSOP
- Pb free package
- 4 level Selectable
1.3 Ordering Information
Table 1.1 Ordering Information of the Z51F0410 MCU
Device Name
ROM Size
RAM Size
EEPROM Size
Package
Z51F0410HCX
4K bytes Flash
256 bytes
256 bytes
10SSOP
PS029502-0212
PRELIMINARY
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Z51F0410
Product Specification
1.3.1
Part Number Suffix Designation
Zilog part numbers consist of a number of components, as indicated in the following example.
Example: Part number Z51F0410HCX is an 8-bit MCU with 4 KB of Flash memory and 256 bytes of
RAM in a 10-pin SSOP package and operating within a –40°C to +85°C temperature range. In
accordance with RoHS standards, this device has been built using lead-free solder.
Z51
F
04
10
H
C
X
Temperature Range
X = –40°C to +85°C
Pin Count
C = 10 pins
Package
H = SSOP
Device Type
Flash Memory Size
04 = 4 KB Flash
Flash Memory
F = General-Purpose Flash
Device Family
Z51 = Z8051 8-Bit Core MCU
1.4 Development Tools
1.4.1 Compiler
Zilog does not provide any compiler for the Z51F0410 MCU. But the CPU core of the Z51F0410 MCU
is Mentor 8051, you can use all kinds of third party’s standard 8051 compiler like Keil C Compiler,
Open Source SDCC (Small Device C Compiler) .. These compilers’ output debug information can be
integrated with our OCD emulator and debugger. Refer to OCD manual for more details.
1.4.2 OCD Emulator and Debugger
The OCD (On Chip Debug) emulator supports Zilog’s 8051 series MCU emulation. The OCD interface
uses two wires interfacing between PC and MCU which is attached to user’s system. The OCD can
read or change the value of MCU’s internal memory and I/O peripherals. And also the OCD controls
MCU’s internal debugging logic, it means OCD controls emulation, step run, monitoring, etc.
The OCD debugger program works on Microsoft-Windows NT, 2000, XP, Vista(32-bit) operating
system.
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Z51F0410
Product Specification
If you want to see details more, please refer to OCD debugger manual. You can download debugger
S/W and manual from out web-site.
The connection pins between PC and MCU is as follows:
SCLK (P0[3] of Z51F0410)
SDATA (P0[5] of Z51F0410)
OCD connector diagram: Connect OCD and user system
1
2
User VCC
3
4
User GND
5
6
SCLK
7
8
SDATA
9
10
Figure 1.1 OCD Debugger and Pin Configuration
Note: P0[3] is pulled-up by external resistor to avoid malfunction when power is on.
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Product Specification
1.5 Block Diagram
P03/DSCL
P07/AN7
P06/AN6
P05/AN5
AVref/P04/AN4
P03/AN3
P02/AN2
P01/AN1
P00/AN0
P03/EC0
P05/T1(PWM1)
On –Chip
Debug
12-BIT
ADC
P0
PORT
EEPROM
(256B)
TIMER
&
PWM
RAM
(256B)
BIT
FLASH
(4K byte)
P01/INT0
P04/INT1
P07~P00
M8051
CORE
Decryption
P04/T0O
P05/DSDA
INTERRUP
CONTROLLER
WDT
WT
Power on
Reset
P05/AC+
P04/ACP03/ACOUT
Analog
Comparator
P05/BUZO
BUZZER
Brown Out
Detector
SUBXIN/P00
INT-RC OSC
128kHz ( 50%)
P03/SS
P02/ACK
P01/TXD
P00/RXD
P05/SDA
P04/SCL
INT-RC OSC
8MHz ( 1%)
SUBXOUT/P01
CLOCK/
SYSTEM
CON
USART
I2C
XIN/P00
XOUT/P01
RESETB/P02
Voltage
Down
Convertor
VDD
VSS
Figure 1.2 Top Abstract Block Diagram
Note) P01, P02, P03 pin are programmable or configure option selectable.
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Product Specification
1.6 PIN Assignment
※Pin priority high
※Pin priority high
1
XIN(SUBXIN) / AN0 / RXD / P00
2
XOUT(SUBXOUT) / AN1 / INT1 / TXD / P01
3
RESETB / AN2 / ACK / P02
4
AN6 / P06
5
C
H
0
1
4
0
F
1
5
Z
VDD
10 VSS
9
P05 / SDA / PWM1O / BUZ / AN5 / AC+ / (DSDA)
8
P04 / SCL / T0O / AN4 / AC- / AVref
7
P03 / INT0 / SS / EC0 / AN3 / ACOUT / (DSCL)
6
P07 / AN7
Figure 1.3 10-SSOP PIN Assignment Diagram of Z51F0410HCX
NOTE)
- If 8 PIN PKG, Pin 5 and 6 are removed in 10 PIN PKG.
- On On-Chip Debugging, ISP uses P0[3], P0[5] pin as DSCL, DSDA.
- P00, P01,P02,P06 pin priority is high from left to right. P05, P04,P03,P07 pin priority is high from right to left.
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Z51F0410
Product Specification
1.7 Package Diagram
Figure 1.4 10-SSOP Package Diagram
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Product Specification
1.8 Reconfigurable Pin Description
1.8.1 USART Pin Location Switch Mode
※Pin priority high
※Pin priority high
1
XIN(SUBXIN) / AN0 / RXD / P00
2
XOUT(SUBXOUT) / AN1 / INT1 / TXD / P01
3
RESETB / AN2 / ACK / P02
4
AN6 / P06
5
C
H
0
1
4
0
F
1
5
Z
VDD
10 VSS
9
P05 / SDA / PWM1O / BUZ / AN5 / AC+ / (DSDA)
8
P04 / SCL / T0O / AN4 / AC- / AVref
7
P03 / INT0 / SS / EC0 / AN3 / ACOUT / (DSCL)
6
P07 / AN7
Figure 1.5 USART Pin Location : USART_PINMODE=0
※Pin priority high
※Pin priority high
1
XIN(SUBXIN) / AN0 / P00
2
XOUT(SUBXOUT) / AN1 / INT1 / P01
3
RESETB / AN2 / ACK / P02
4
AN6 / RXD / P06
5
C
H
0
1
4
0
F
1
5
Z
VDD
10 VSS
9
P05 / SDA / PWM1O / BUZ / AN5 / AC+ / (DSDA)
8
P04 / SCL / T0O / AN4 / AC- / AVref
7
P03 / INT0 / SS / EC0 / AN3 / ACOUT / (DSCL)
6
P07 / TXD / AN7
Figure 1.6 USART Pin Location : USART_PINMODE=1
1.8.2 I2C Pin Location Switch Mode
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Product Specification
※Pin priority high
※Pin priority high
1
XIN(SUBXIN) / AN0 / RXD / P00
2
XOUT(SUBXOUT) / AN1 / INT1 / TXD / P01
3
RESETB / AN2 / ACK / P02
4
AN6 / P06
5
C
H
0
1
4
0
F
1
5
Z
VDD
10 VSS
9
P05 / SDA / PWM1O / BUZ / AN5 / AC+ / (DSDA)
8
P04 / SCL / T0O / AN4 / AC- / AVref
7
P03 / INT0 / SS / EC0 / AN3 / ACOUT / (DSCL)
6
P07 / AN7
Figure 1.7 I2C Pin Location : I2C_PINMODE=0
※Pin priority high
※Pin priority high
1
XIN(SXIN) / AN0 / RXD / P00
2
XOUT(SXOUT) / AN1 / INT1 / TXD / P01
3
RESETB / AN2 / ACK / P02
4
AN6 / SCL / P06
5
C
H
0
1
4
0
F
1
5
Z
VDD
10 VSS
9
P05 / PWM1O / BUZ / AN5 / AC+ / (DSDA)
8
P04 / T0O / AN4 / AC- / AVref
7
P03 / INT0 / SS / EC0 / AN3 / ACOUT / (DSCL)
6
P07 / SDA / AN7
Figure 1.8 I2C Pin Location : I2C_PINMODE=1
1.8.3 External Interrupt Pin Location Switch Mode
※Pin priority high
※Pin priority high
1
XIN(SUBXIN) / AN0 / RXD / P00
2
XOUT(SUBXOUT) / AN1 / INT1 / TXD / P01
3
RESETB / AN2 / ACK / P02
4
AN6 / P06
PS029502-0212
5
C
H
0
1
4
0
F
1
5
Z
VDD
10 VSS
9
P05 / SDA / PWM1O / BUZ / AN5 / AC+ / (DSDA)
8
P04 / SCL / T0O / AN4 / AC- / AVref
7
P03 / INT0 / SS / EC0 / AN3 / ACOUT / (DSCL)
6
P07 / AN7
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Z51F0410
Product Specification
Figure 1.9 External INT Pin Location : EINT_PINMODE=0
※Pin priority high
※Pin priority high
1
XIN(SUBXIN) / AN0 / RXD / P00
2
XOUT(SUBXOUT) / AN1 / TXD / P01
3
RESETB / AN2 / ACK / P02
4
AN6 / INT1 / P06
5
C
H
0
1
4
0
F
1
5
Z
VDD
10 VSS
9
P05 / SDA / PWM1O / BUZ / AN5 / AC+ / (DSDA)
8
P04 / SCL / T0O / AN4 / AC- / AVref
7
P03 / SS / EC0 / AN3 / ACOUT / (DSCL)
6
P07 / INT0 / AN7
Figure 1.10 External INT Pin Location : EINT_PINMODE=1
1.8.4 Buzzer Out Pin Location Switch Mode
※Pin priority high
※Pin priority high
1
XIN(SUBXIN) / AN0 / RXD / P00
2
XOUT(SUBXOUT) / AN1 / INT1 / TXD / P01
3
RESETB / AN2 / ACK / P02
4
AN6 / P06
5
C
H
0
1
4
0
F
1
5
Z
VDD
10 VSS
9
P05 / SDA / PWM1O / BUZ / AN5 / AC+ / (DSDA)
8
P04 / SCL / T0O / AN4 / AC- / AVref
7
P03 / INT0 / SS / EC0 / AN3 / ACOUT / (DSCL)
6
P07 / AN7
Figure 1.11 Buzzer Out Pin Location : BUZO_PINMODE=0
※Pin priority high
※Pin priority high
1
XIN(SUBXIN) / AN0 / RXD / P00
2
XOUT(SUBXOUT) / AN1 / INT1 / TXD / P01
3
RESETB / AN2 / ACK / P02
4
AN6 / BUZ / P06
PS029502-0212
5
C
H
0
1
4
0
F
1
5
Z
VDD
10 VSS
9
P05 / SDA / PWM1O / AN5 / AC+ / (DSDA)
8
P04 / SCL / T0O / AN4 / AC- / AVref
7
P03 / INT0 / SS / EC0 / AN3 / ACOUT / (DSCL)
6
P07 / AN7
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Product Specification
Figure 1.12 Buzzer Out Pin Location : BUZO_PINMODE=1
1.8.5 TIMER Pin Location Switch Mode
※Pin priority high
※Pin priority high
1
XIN(SUBXIN) / AN0 / RXD / P00
2
XOUT(SUBXOUT) / AN1 / INT1 / TXD / P01
3
RESETB / AN2 / ACK / P02
4
AN6 / P06
5
X
C
H
0
1
4
0
F
1
5
Z
VDD
10 VSS
9
P05 / SDA / PWM1O / BUZ / AN5 / AC+ / (DSDA)
8
P04 / SCL / T0O / AN4 / AC- / AVref
7
P03 / INT0 / SS / EC0 / AN3 / ACOUT / (DSCL)
6
P07 / AN7
Figure 1.13 Timer Out Pin Location : TMR_PINMODE=0
※Pin priority high
※Pin priority high
1
XIN(SXIN) / AN0 / RXD / P00
2
XOUT(SXOUT) / AN1 / INT1 / TXD / P01
3
RESETB / AN2 / ACK / EC0 / P02
4
AN6 / PWM1O / P06
5
C
H
0
1
4
0
F
1
5
Z
VDD
10 VSS
9
P05 / SDA / BUZ / AN5 / AC+ / (DSDA)
8
P04 / SCL / AN4 / AC- / AVref
7
P03 / INT0 / SS / AN3 / ACOUT / (DSCL)
6
P07 / T0O / AN7
Figure 1.14 Timer Out Pin Location : TMR_PINMODE=1
1.9 Code Encryption (Super Lock)
Basically user code data will be programmed with raw data in Flash area. Although code data read
mode is protected with lock mode, its contents are vulnerable for several codes hooking method. We
provide the code encryption method to secure the user code data. The original user code will be
scrambled with user seed key value (private key). The scrambled data is programmed in flash area.
The fetched code during CPU operation will be decoded with the user key in configuration area.
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Product Specification
Core Bus
Config Option
User Key
User Key
00011010
10101101
00000000
11100111
11110010
01001101
00110000
Original Code
Encryption
10101011
Decryption
Flash /
EEPROM
Download
Scrambled Code
Figure 1.15 Super Lock Enabled Encryption/Decryption Diagram
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Product Specification
1.10 Port Structure
1.10.1 General Purpose I/O Port
LevelShift ( 1.8V to ExtVDD)
LevelShift (ExtVDD to 1.8V)
VDD
PULL-UP
REGISTER
OPEN DRAIN
REGISTER
DATA
REGISTER
VDD
0
PAD
MUX
SUB-FUNC DATA OUTPUT
VDD
1
SUB-FUNC ENABLE
SUB-FUNC DIRECTION
0
MUX
DIRECTION
REGISTER
1
R(400Ω)
PORTx INPUT
1
MUX
0
PADx Data INPUT
0
MUX
1
SUB-FUNC
DATA INPUT
Q
CMOS or
SchmittLevel
Input
D
r
CP
DEBOUNCE
CLK
DEBOUNCE
ENABLE
ANALOG CHANNEL
ENABLE
ANALOG INPUT
ANALOG INPUT
(without Resistor)
Figure 1.16 General Purpose I/O Port
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1.10.2 External Interrupt I/O Port
LevelShift ( 1.8V to ExtVDD)
LevelShift (ExtVDD to 1.8V)
VDD
PULL-UP
REGISTER
OPEN DRAIN
REGISTER
VDD
DATA
REGISTER
VDD
0
PAD
MUX
SUB-FUNC DATA OUTPUT
1
SUB-FUNC ENABLE
SUB-FUNC DIRECTION
0
MUX
DIRECTION
REGISTER
1
R(200Ω)
0
VDD
MUX
EXTERNAL
INTERRUPT
1
INTERRUPT
ENABLE
r
EDGE
REG
PORTx INPUT
R(200Ω)
D
Q
POLARITY
REG
CP
FLAG
CLEAR
1
MUX
0
PADx Data INPUT
0
MUX
1
SUB-FUNC
DATA INPUT
Q
CMOS or
SchmittLevel
Input
D
r
CP
DEBOUNCE
CLK
DEBOUNCE
ENABLE
ANALOG CHANNEL
ENABLE
ANALOG INPUT
Figure 1.17 External Interrupt I/O Port
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Product Specification
1.11 Port Structure Diagram (detail view)
1.11.1 P0[0] Port Structure
VDD
Pull-up Enable
VDD
Open-Drain
Output data
TXD_OUT
Output
0
XIN(SUBXIN)
/
AN0 / RXD(TXD) /
P00
1
RXD_OUT_EN
Direction
P0DA_OEB
P0RDA_OEB
Input
Data
1
0
LPF
PAD DATA
RXD_IN_EN
Secondary
Input
RXD
NC20NS
PCI_EN[0]
PCI_IN[0]
AN0
Analog
Input
AN0_EN (from PSR)
XIN_EN (from Config)
XIN(SUBXIN)
Figure 1.18 XIN(SUBXIN) / AN0 /RXD /P0[0] Port Structure
The pull-up resister is directly controlled by the pull-up register bit regardless of current port direction.
The open-drain control is also by open-drain register. On open-drain mode, the push-pull drives just
N-MOS. When the direction is output (value 1), the output PAD voltage is controlled by push-pull
driver for the current output data. The secondary input or analog channel selection bit disable the
output direction regardless of the current direction register. The secondary input RXD_EN, PCI_EN[0]
enables the input data path continuously. On normal read mode (non secondary mode), the input data
path is only enabled during the CPU OEB (active low). When the analog channel (AN0) is enabled,
the first input gate from the PAD is disabled (highest priority) to prevent the input leakage current for
the floating voltage status. The XIN function disables all analog channels and secondary input/output.
At read operation, the input data is selected by PAD direction register. If its value is ‘1’, it reads the
current output register value. Otherwise, it reads the current PAD voltage directly (just during OEB
active). In addition, always the current PAD voltage is read by PAD DATA register.
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1.11.2 P0[1] Port Structure
VDD
Pull-up Enable
VDD
Open-Drain
Output Data
TXD
Output
0
XOUT(SUBXOUT)
/ AN1 / INT1 /
TXD(RXD) / P01
1
TXD_OUT_EN
Direction
P0DA_OEB
P0RDA_OEB
Input
Data
1
0
LPF
PAD DATA
PCI_EN[1]
PCI_IN[1]
EXT_INT1
Secondary
Input
EXT_INT1_EN
TXD_IN_EN
RXD
NC20NS
AN1
AN1_EN
Analog
Input
XOUT_EN (from Config)
XOUT(SUBXOUT)
Figure 1.19 XOUT(SUBXOUT) / AN1 / INT1 / TXD / P0[1] Port Structure
The Figure 1.19 shows a brief diagram of P0[1] port structure. The pull-up resister is directly
controlled by the pull-up register bit regardless of current port direction. The open-drain control is also
by open-drain register. On open-drain mode, the push-pull drives just N-MOS. When the direction is
output (value 1), the output PAD voltage is controlled by push-pull driver for the current output data.
The secondary input or analog channel selection bit disable the output direction regardless of the
current direction register. The secondary input INT1_EN, PCI_EN[1] enables the input data path
continuously. On normal read mode (non secondary mode), the input data path is only enabled during
the CPU OEB (active low). When the analog channel (AN1) is enabled, the first input gate from the
PAD is disabled (highest priority) to prevent the input leakage current for the floating voltage status.
The XOUT function disables all analog channels and secondary input/output. At read operation, the
input data is selected by PAD direction register. If its value is ‘1’, it reads the current output register
value. Otherwise, it reads the current PAD voltage directly (just during OEB active). In addition,
always the current PAD voltage is read by PAD DATA register.
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Product Specification
1.11.3 P0[2] Port Structure
RESETB_EN
(from Config)
VDD
Pull-up Enable
VDD
Open-Drain
Output Data
Output
ACK_OUT
0
1
RESETB / AN2 /
ACK / P0[2]
ACK_OUT_EN
Direction
P0DA_OEB
P0RDA_OEB
Input
Data
1
0
LPF
PAD DATA
PCI_EN[2]
PCI_IN[2]
Secondary
Input
ACK_IN_EN
ACK_IN
RESETB_EN
RESETB
Analog
Input
AN2
AN2_EN
Figure 1.20 RESETB / AN2 / ACK / P0[2] Port Structure
If the RESETB_EN (from config data) is 1, the input secondary data path is enabled with the highest
priority level and it automatically enables the pull-up function regardless of pull-up register value.
The analog channel selection bit enables the path of the AN2 and disable normal logic data path to
prevent the input gate leakage current. When the direction register value is 0, the input data is always
external PAD voltage.
The pull-up resister is directly controlled by the pull-up register bit regardless of current port direction.
The open-drain control is also by open-drain register. On open-drain mode, the push-pull drives just
N-MOS. When the direction is output (value 1), the output PAD voltage is controlled by push-pull
driver for the current output data. The secondary input or analog channel selection bit disable the
output direction regardless of the current direction register. The secondary input ACK_IN_EN,
PCI_EN[2] enable the input data path continuously. On normal read mode (non secondary mode), the
input data path is only enabled during the CPU OEB (active low). When the analog channel (AN2) is
enabled, the first input gate from the PAD except of RESET enabled is disabled (highest priority) to
prevent the input leakage current for the floating voltage status. At read operation, the input data is
selected by PAD direction register. If its value is ‘1’, it reads the current output register value.
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Product Specification
Otherwise, it reads the current PAD voltage directly (just during OEB active). In addition, always the
current PAD voltage is read by PAD DATA register.
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1.11.4 P0[3] Port Structure
Pull-up Enable
VDD
OCD_EN
VDD
Open-Drain
Output Data
0
0
SS_OUT
Output
1
P03 / INT0 / SS /
EC0 / AN3 /
ACOUT / (DSCL)
1
SS_OUT_EN
ACO_OUT
ACO_OUT_EN
Direction
P0DA_OEB
P0RDA_OEB
Input
Data
1
0
LPF
PAD DATA
PCI_EN[3]
PCI_IN[3]
SS_IN_EN
SS
Secondary
Input
INT0_EN
INT0
NC20NS
EC0_EN
EC0
Analog
Input
NC20NS
AN3
AN3_EN
Figure 1.21 P0[3] / INT0 / SS / EC0 / AN3 / ACOUT Port Structure
The pull-up resister is directly controlled by the pull-up register bit regardless of current port direction.
The open-drain control is also by open-drain register. On open-drain mode, the push-pull drives just
N-MOS. The OCD mode enable the Open-drain Output regardless of the Open-Drain Register value.
When the direction is output (value 1), the output PAD voltage is controlled by push-pull driver for the
current output data. The secondary input or analog channel selection bit disable the output direction
regardless of the current direction register. The secondary input SS_EN, INT0_EN, EC0_EN,
PCI_EN[3] enable the input data path continuously. On normal read mode (non secondary mode), the
input data path is only enabled during the CPU OEB (active low). When the analog channel (AN3) is
enabled, the first input gate from the PAD is disabled (highest priority) to prevent the input leakage
current for the floating voltage status. At read operation, the input data is selected by PAD direction
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Z51F0410
Product Specification
register. If its value is ‘1’, it reads the current output register value. Otherwise, it reads the current
PAD voltage directly (just during OEB active). In addition, always the current PAD voltage is read by
PAD DATA register.
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1.11.5 P0[4] Port Structure
Pull-up Enable
VDD
I2C_EN
PIN_MODE0
VDD
Open-Drain
Output Data
SCL_OUT
T0O
Output
0
1
0
P04 / SCL / T0O /
AN4 / AC- / AVref
1
I2C_EN
T0O_EN
Direction
P0DA_OEB
P0RDA_OEB
Input
Data
1
0
LPF
PAD DATA
I2C_EN
Secondary
Input
SCL_IN
PCI_EN[4]
PCI_IN[4]
AN4
AN4_EN
Analog
Input
ACAC- EN
AVREF
AVREF_EN
Figure 1.22 P0[4]/SCL/T0O/AN4/AC-/Avref Port Diagram
The pull-up resister is directly controlled by the pull-up register bit regardless of current port direction.
The open-drain control is also by open-drain register. On open-drain mode, the push-pull drives just
N-MOS. The I2C Mode enable the Open-drain Output regardless of the Open-Drain Register value.
When the direction is output (value 1), the output PAD voltage is controlled by push-pull driver for the
current output data. The secondary input or analog channel selection bit disable the output direction
regardless of the current direction register. The secondary input SCL_IN_EN, PCI_EN[4] enables the
input data path continuously. On normal read mode (non secondary mode), the input data path is only
enabled during the CPU OEB (active low). When the analog channel (AN4,AC-) is enabled, the first
input gate from the PAD is disabled (highest priority) to prevent the input leakage current for the
floating voltage status. The AVREF function disables all analog channels and secondary
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Z51F0410
Product Specification
input/output.At read operation, the input data is selected by PAD direction register. If its value is ‘1’, it
reads the current output register value. Otherwise, it reads the current PAD voltage directly (just
during OEB active). In addition, always the current PAD voltage is read by PAD DATA register.
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Z51F0410
Product Specification
1.11.6 P0[5] Port Structure
Pull-up Enable
VDD
OCD_EN
I2C_EN
PIN_MODE0
VDD
Open-Drain
Output Data
Output
SDA_OUT
PWM1O
BUZO
I2C_EN
PWM1O_EN
BUZO_EN
0
1
0
1
P0[5]/SDA/PWM1
O/BUZ/AN5/AC+
0
1
Direction
P0DA_OEB
Input
P0RDA_OEB
Data
1
0
LPF
PAD DATA
I2C_EN
Secondary
Input
SDA_IN
PCI_EN[5]
PCI_IN[5]
AN5
AN5_EN
Analog
Input
AC+
AC+ EN
Figure 1.23 P0[5]/SDA/PWM1O/BUZ/AN5/AC+ Port Structure
The pull-up resister is directly controlled by the pull-up register bit regardless of current port direction.
The open-drain control is also by open-drain register. On open-drain mode, the push-pull drive just NMOS. The I2C Mode and OCD Mode enable the Open-drain Output regardless of the Open-Drain
Register value. When the direction is output (value 1), the output PAD voltage is controlled by pushpull driver for the current output data. The secondary input or analog channel selection bit disable the
output direction regardless of the current direction register. The secondary input SDA_IN_EN,
PCI_EN[5] enables the input data path continuously. On normal read mode (non secondary mode),
the input data path is only enabled during the CPU OEB (active low). When the analog channel (AN5)
is enabled, the first input gate from the PAD is disabled (highest priority) to prevent the input leakage
current for the floating voltage status. The AC+ function disables all analog channels and secondary
input/output. At read operation, the input data is selected by PAD direction register. If its value is ‘1’, it
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Z51F0410
Product Specification
reads the current output register value. Otherwise, it reads the current PAD voltage directly (just
during OEB active). In addition, always the current PAD voltage is read by PAD DATA register.
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Z51F0410
Product Specification
1.11.7 P0[6]/P0[7] Port Structure
FUSE_PKG8
(from Config)
VDD
Pull-up Enable
VDD
Open-Drain
Output
Output Data
Direction
R0[6]/AN6
P0[7]/AN7
P0DA_OEB
P0RDA_OEB
Input
Data
1
0
PAD DATA
LPF
PCI_EN[6]/PCI_EN[7]
Secondary
Analog
Input
PCI_IN[6]/PCI_IN[7]
AN6/AN7
AN6_EN/AN7_EN
Figure 1.24 P0[6] / AN6, P0[7] / AN7 Port Structure
The analog channel selection bit enables the path of the AN6/AN7 and disable normal logic data path
to prevent the input gate leakage current. When the direction register value is 0, the input data is
always external PAD voltage.
The pull-up resister is directly controlled by the pull-up register bit regardless of current port direction.
The open-drain control is also by open-drain register. On open-drain mode, the push-pull drives just
N-MOS. When the direction is output (value 1), the output PAD voltage is controlled by push-pull
driver for the current output data. The secondary input PCI_EN[6]/PCI_EN[7] enable the input data
path continuously. On normal read mode (non secondary mode), the input data path is only enabled
during the CPU OEB (active low). When the analog channel (AN6/AN7) is enabled, the first input gate
from the PAD is disabled (highest priority) to prevent the input leakage current for the floating voltage
status. At read operation, the input data is selected by PAD direction register. If its value is ‘1’, it reads
the current output register value. Otherwise, it reads the current PAD voltage directly (just during OEB
active). In addition, always the current PAD voltage is read by PAD DATA register.
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Product Specification
1.12 Electrical Characteristics
1.12.1 Absolute Maximum Ratings
Table 1.2 Absolute Maximum Ratings
Parameter
Supply Voltage
Normal Voltage Pin
Total Power Dissipation
Storage Temperature
Symbol
Rating
Unit
VDD
-0.3~+6.5
V
VSS
-0.3~+0.3
V
VI
-0.3~VDD+0.3
V
VO
-0.3~VDD+0.3
V
IOH
10
mA
∑IOH
80
mA
IOL
20
mA
∑IOL
160
mA
PT
600
mW
TSTG
-45~+125
℃
Note) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at any other conditions beyond those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
1.12.2 Recommended Operating Conditions
Table 1.3 Recommended Operation Conditions
Parameter
Symbol
Supply Voltage
Operating Temperature
Operating Frequency
Condition
MIN
TYP
MAX
Unit
1.8
-
5.5
V
VDD=1.8~5.5V
-40
-
85
℃
fXIN
1
-
8
MHz
fSUB
-
32.768
-
KHz
Internal RC-OSC
-
8
-
MHz
fXIN=1.0~8MHz
VDD
fSUB=32.768KHz
TOPR
FOPR
1.12.3 A/D Converter Characteristics
(TA=-40℃ ~ +85℃, VDD=AVDD=1.8V ~ 5.5V, VSS=0V)
Table 1.4 A/D Converter Characteristics
Parameter
Symbol
Resolution
Condition
MIN
TYP
MAX
Unit
-
-
12
-
bits
Total Accuracy
-
Integral Linear Error
INL
Differential
Error
DLE
Linearity
AVDD=VDD=5.12
V
fXIN=4MHz
±3(Avref
base)
lsb
-
-
±3
lsb
-
-
±2
lsb
Zero Offset Error
ZOE
-
±3
lsb
Full Scale Error
FSE
-
±3
lsb
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Product Specification
60
-
cycl
e
-
VSS
-
AVDD=VD
D
V
AVDD
-
-
*AVDD=V
DD
-
V
AVREF
-
2.0
-
AVREF=A
VDD
V
AVSS
-
-
VSS
-
V
AVDD=VDD=5.12
V
-
-
10
uA
-
1
3
mA
-
-
1
uA
tCON
Analog Input Voltage
VAN
Analog
Voltage
Power
Analog
Voltage
Reference
Analog
Voltage
Ground
Analog Input Leakage
Current
ADC
Current
12bit conversion
-
Conversion Time
IDD
Operating
SIDD
Max 3MHz
AVDD=VDD=5.12
V
1.12.4 Voltage Dropout Converter Characteristics
Table 1.5 Voltage Dropout Converter Characteristics
Parameter
Symbol
Condition
MIN
TYP
MAX
Unit
Operating Voltage
-
1.8
-
5.5
V
Operating Temperature
-
-40
-
+85
℃
Regulation Voltage
-
1.62
1.8
1.98
V
Drop-out Voltage
-
-
-
0.02
V
RUN/IDLE
-
10
-
mA
SUB-ACTIVE
-
1
-
mA
STOP1
-
50
-
uA
STOP2
-
10
-
uA
IDD1
RUN/IDLE
-
-
1
mA
IDD2
SUB-ACTIVE
-
-
0.1
mA
SIDD1
STOP1
-
-
5
uA
SIDD2
STOP2
-
-
0.1
uA
TRAN1
SUB to RUN
-
-
1
uS
TRAN2
STOP to RUN
-
-
Current Drivability
Operating Current
Drivability Transition Time
Note) -STOP1: WDT running - STOP2: WDT disable
1.12.5 Power-On Reset Characteristics
Table 1.6 Power-On Reset Characteristics
Parameter
Symbol
Condition
MIN
TYP
MAX
Unit
Operating Voltage
-
VSS
-
5.5
V
Operating Temperature
-
-40
-
+85
℃
RESET Release Level
Operating Current
PS029502-0212
-
1.3
1.4
1.5
V
IDD
-
-
-
10
uA
SIDD
-
-
-
1
uA
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Z51F0410
Product Specification
1.12.6 Brown Out Detector Characteristics
Table 1.7 Brown Out Detector Characteristics
Parameter
Symbol
Condition
MIN
TYP
MAX
Unit
Operating Voltage
-
VSS
-
5.5
V
Operating Temperature
-
-40
-
+85
℃
-
4.1
4.3
4.4
V
-
3.4
3.6
3.7
V
-
2.4
2.5
2.6
V
Detection Level
-
1.5
1.6
1.7
V
-
-
50
-
mV
IDD
-
-
-
50
uA
SIDD
-
-
-
1
uA
Hysteresis
Operating Current
1.12.7 Internal 8Mhz, 128Khz RC Oscillator Characteristics
Table 1.8 Internal 8Mhz RC Oscillator Characteristics
Parameter
Condition
Operating Voltage
MIN
TYP
MAX
Unit
1.62
1.8
3.3
V
85
℃
Operating Temp.
TBD
-40
Clock Freq.
25℃
7.92
8
8.08
MHz
Operating Current
Average Current
140
170
200
uA
Table 1.9 Internal 128Khz RC Oscillator Characteristics
Condition
Operating Voltage
MIN
TYP
MAX
Unit
1.62
1.8
5.5
V
85
℃
Operating Temp.
TBD
-40
Clock Freq.
TBD
-
128
-
KHz
Operating Current
Average Current
15
20
40
uA
1.12.8 Analog Comparator Characteristics
Table 1.10 DC Electrical Characteristics
LIMITS
SYMBOL
IL
PARAMETER
Input
current
PS029502-0212
leakage
TEST CONDITION
VDDEXT=5V,
Vin=1/2VDDEXT
PRELIMINARY
Temp= -40 °C to 85 °C
MIN
TYP
MAX
-50
-
50
UNIT
nA
38
Z51F0410
Product Specification
Input offset voltage
VDDEXT=5V, Vin=1/2VDD
IOP
Operating current
COMP_EN=H
1
mA
IPD
Power
current
COMP_EN=L
1
uA
down
10
-
±mV
Voffset
40
Table 1.11 AC Characteristics
LIMITS
SYMBOL
PARAMETER
Comparator
Response time
VRT
TEST CONDITION
CL= 50pF, VDDEXT=5V
Temp=-40 °C to 85 °C
UNIT
MIN
TYP
MAX
-
-
500
ns
1.12.9 DC Characteristics
(VDD =1.8~5.5V, VSS =0V, fXIN=10.0MHz, TA=-40~+85℃)
Table 1.12 DC Characteristics
Parameter
Input Low Voltage
Symbol
VIL1
Condition
RESETB (External Reset Active)
P0
VIL2
Input High Voltage
VIH1
RESETB (External Reset Active)
P0
MIN
TYP
MAX
Unit
-0.5
-
0.2VDD
V
-0.5
-
0.2VDD
V
0.8VDD
-
VDD+0.5
V
VIH2
-
0.7VDD
-
VDD+0.5
V
Output Low Voltage
VOL1
P0 (IOL=10mA, VDD=4.5V)
-
-
1
V
Output High Voltage
VOH1
P0 (IOH=-8.57mA, VDD=4.5V)
3.5
-
-
V
Input High Leakage
Current
IIH
P0,
1
uA
Input Low Leakage
Current
IIL
P0
-1
RPU
P0(VDD=5.0V)
20
-
62
kΩ
IDD1
Run Mode, fXIN=8MHz@5V
-
-
10
mA
IDD2
Sleep Mode, fXIN=8MHz@5V
-
-
5
mA
IDD3
Sub Active Mode,
fXIN=32.768KHz@5V
-
-
500
uA
IDD4
STOP1 Mode,WDT Active@5V
-
-
110
uA
IDD5
STOP2 Mode,WDT Disable@5V
-
-
10
uA
Pull-Up Resister
Power
Current
Supply
uA
Note) STOP1: WDT running STOP2: WDT disable
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Product Specification
1.12.10 AC Characteristics
(VDD=5.0V±10%, VSS=0V, TA=-40~+85℃)
Table 1.13 AC Characteristics
Parameter
Symbol
PIN
Operating Frequency
fMCP
XIN
1
System Clock Cycle Time
tSYS
-
125
Oscillation Stabilization Time (8MHz)
tMST1
XIN, XOUT
-
External Clock “H” or “L” Pulse Width
tCPW
XIN
90
External Clock Transition Time
MIN
TYP
MAX
Unit
-
8
MHz
-
1000
ns
-
10
ms
-
-
ns
tRCP,tFCP
XIN
-
-
10
ns
tIW
INT0~INT1
2
-
-
tSYS
RESETB Input Pulse “L” Width
tRST
RESETB
8
-
-
tSYS
External Counter Input “H” or “L” Pulse
Width
tECW
EC0
2
-
-
tSYS
tREC,tFEC
EC0
-
-
20
ns
Interrupt Input Width
Event Counter Transition Time
1/fMCP
tCPW
tCPW
0.9VDD
XIN
0.1VDD
tRCP
tFCP
tIW
INT0
INT1
tIW
0.8VDD
0.2VDD
tRST
RESETB
0.2VDD
tECW
tECW
EC0
0.8VDD
0.2VDD
tREC
tFEC
Figure 1.25 AC Timing
1.12.11 Typical Characteristics
These graphs and tables provided in this section are for design guidance only and are not tested or
guaranteed. In some graphs or tables the data presented are outside specified operating range (e.g.
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Z51F0410
Product Specification
outside specified VDD range). This is for information only and devices are guaranteed to operate
properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different
lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min”
represents (mean + 3σ) and (mean - 3σ) respectively where σ is standard deviation.
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2. Functional Description
2.1 Memory
The Z51F0410 MCU addresses two separate address memory stores: Program memory and Data
memory. The logical separation of Program and Data memory allows Data memory to be assessed by
8-bit addresses, which can be more quickly stored and manipulated by 8-bit CPU. Nevertheless, 16bit Data memory addresses can also be generated through the DPTR register.
Program memory can only be read, not written to. There can be up to 64K bytes of Program
memory. In the Z51F0410 Flash version of these devices the 4K bytes of Program memory are
provided on-chip. Data memory can be read and written to up to 256 bytes internal memory (DATA)
including the stack area.
2.1.1 Program Memory
A 16-bit program counter is capable of addressing up to 64K bytes, but this device has just 4K bytes
program memory space.
Figure 2.1 shows a map of the lower part of the program memory. After reset, the CPU begins
execution from location 0000H. Each interrupt is assigned a fixed location in program memory. The
interrupt causes the CPU to jump to that location, where it commences execution of the service
routine. External interrupt 0, for example, is assigned to location 000BH. If external interrupt 0 is going
to be used, its service routine must begin at location 000BH. If the interrupt is not going to be used, its
service location is available as general purpose program memory. If an interrupt service routine is
short enough (as is often the case in control applications), it can reside entirely within that 8 byte
interval. Longer service routines can use a jump instruction to skip over subsequent interrupt
locations, if other interrupts are in use.
FFFFH
0FFFH
4KBytes
0000H
-
Figure
2.1 Program
memory
User Function Mode: 4KBytes Included
Interrupt
Vector Region
-
Nonvolatile and reprogramming memory: Flash memory based on EEPROM cell
2.1.2 Data Memory
Figure 2.2 shows the internal Data memory space available.
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Product Specification
FFh
80h
7Fh
FFh
Upper
128 Bytes
Special Function
Registers
Internal RAM
128 Bytes
(Direct Addressing)
(Indirect
Addressing)
80h
Lower
128 Bytes
Internal RAM
(Direct or Indirect
Addressing)
00h
Figure
Data
memory
mapare generally referred to as the lower
The internal memory space is divided
into 2.2
three
blocks,
which
128, upper 128, and SFR space.
Internal Data memory addresses are always one byte wide, which implies an address space of only
256 bytes. However, the addressing modes for internal RAM can in fact accommodate 384 bytes,
using a simple trick. Direct addresses higher than 7FH access one memory space and indirect
addresses higher than 7FH access a different memory space. Thus Figure 2.2 shows the upper 128
and SFR space occupying the same block of addresses, 80H through FFH, although they are
physically separate entities.
The lower 128 bytes of RAM are present in all 8051 devices as mapped in Figure 2.3. The lowest 32
bytes are grouped into 4 banks of 8 registers. Program instructions call out these registers as R0
through R7. Two bits in the Program Status Word select which register bank is in use. This allows
more efficient used of code space, since register instructions are shorter than instructions that use
direct addressing.
The next 16 bytes above the register banks form a block of bit-addressable memory space. The
8051 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area
can be directly addressed by these instructions. The bit addresses in this area are 00H through 7FH.
All of the bytes in the lower 128 can be accessed by either direct or indirect addressing. The upper
128 bytes RAM can only be accessed by indirect addressing. These spaces are used for user RAM
and stack pointer.
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Product Specification
7F 7E 7D 7C 7B 7A 79 78
77 76 75 74 73 72 71 70
7FH
6F 6E 6D 6C 6B 6A 69 68
67 66 65 64 63 62 61 60
5F 5E 5D 5C 5B 5A 59 58
57 56 55 54 53 52 51 50
General
register
80 bytes
purpose
4F 4E 4D 4C 4B 4A 49 48
47 46 45 44 43 42 41 40
3F 3E 3D 3C 3B 3A 39 38
37 36 35 34 33 32 31 30
2F 2E 2D 2C 2B 2A 29 28
30H
2FH
27 26 25 24 23 22 21 20
1F 1E 1D 1C 1B 1A 19 18
16 bytes
20H
1FH
8 bytes
8 bytes
8 bytes
17 16 15 14 13 12 11 10
Bit addressable
(128bits)
18H
17H
10H
0FH
08H
07H
8 bytes
0F 0E 0D 0C 0B 0A 09 08
Register bank 3
(8 bytes)
07 06 05 04 03 02 01 00
Register bank 2
(8 bytes)
R7
Register bank 1
(8 bytes)
R6
Register bank 0
(8 bytes)
R4
00H
R5
R3
R2
R1
R0
Figure 2.3 Lower 128 bytes RAM
2.1.3 EEPROM Data Memory
The Z51F0410 MCU features 256 bytes EEPROM Data memory. This area has no relation with
RAM/Flash. It can read and write through SFR with 8-bit unit.
For more information about EEPROM Data memory, see EEPROM section
PS029502-0212
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Z51F0410
Product Specification
2.2 SFR Map
2.2.1 SFR Map Summary
-
Reserved
M8051 Compatible
Table 2.1 SFR Map Summary
0H/8H(1)
1H/9H
2H/AH
3H/BH
4H/CH
5H/DH
6H/EH
7H/FH
F8H
IP1
FUSE_
CONF2
FUSE_
CAL2
FUSE_
CAL1
FUSE_
CAL0
FUSE_
CONF1
TEST_B
TEST_A
F0H
B
-
FEARL
FEARM
FEARH
FEDR
-
FUSE_CA
L3
E8H
-
ACCSR
FEMR
FECR
FESR
FETCR
UKEY0
UKEY1
E0H
ACC
-
UCTRL1
UCTRL2
UCTRL3
USTAT
UBAUD
UDATA
D8H
-
-
I2CMR
I2CSR
I2CSCLLR
I2CSCLH
R
I2CSDAH
R
I2CDR
D0H
PSW
FKEY0
FKEY1-
USEED1
USEED0
SIDA
SIDD
I2CAR
C8H
-
-
T4H
T4CR
T4L
C0H
P0DB
P0PC
-
-
-
-
B8H
IP
-
-
-
-
-
-
-
B0H
-
-
T0CR
T0
T1CR
T1DR
T1
T1PWHR
A8H
IE
IE1
IE2
IE3
EIFLAG
EIEDGE
EIPOLA
EIENAB
A0H
PSR1
P0OD
EO
-
-
-
-
-
98H
P0IO
ADCM
ADCRH
ADCRL
WTMR
WTR
PSR0
90H
-
-
PINMCR
-
-
-
BUZCR
TFLG
88H
P0PD
P0PU
SCCR
BCCR
BITR
WDTMR
WDTR
BUZDR
80H
P0
SP
DPL
DPH
BODR
PCON
Note: 1) These registers are bit-addressable
PS029502-0212
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Z51F0410
Product Specification
2.2.2 SFR Map
Table 2.2 SFR Map
Address
Function
Symbol
R/W
@Reset
7
6
5
4
3
2
1
0
80H
Port 0 Data Register
P0
R/W
0
0
0
0
0
0
0
0
81H
Stack Pointer
SP
R/W
0
0
0
0
0
1
1
1
82H
Data Pointer Register Low
DPL
R/W
0
0
0
0
0
0
0
0
83H
Data Pointer Register High
DPH
R/W
0
0
0
0
0
0
0
0
84H
Reserved
84H
Reserved
86H
BOD Control Register
BODR
R/W
1
0
0
0
0
0
0
1
87H
Power Control Register
PCON
R/W
0
0
0
0
0
0
0
0
88H
Port0 PAD Data Register
P0PD
R
-
-
-
-
-
-
-
-
89H
Port 0 Pull-up
Option Register
P0PU
R/W
0
0
0
0
0
0
0
0
8AH
System
Register
SCCR
R/W
0
0
0
0
0
1
0
0
8BH
BIT Clock Control Register
BCCR
R/W
0
-
-
-
0
1
0
1
8CH
Basic Interval Timer Register
BITR
R/W
0
0
0
0
0
0
0
0
8DH
Watch Dog
Register
WDTMR
R/W
0
0
0
0
0
0
0
0
WDTR
W
1
1
1
1
1
1
1
1
Resistor
Clock
Control
Timer
Mode
Watch Dog Timer Register
8EH
Watch Dog Timer Counter
Register
WDTCR
R
0
0
0
0
0
0
0
0
8FH
Buzzer Data Register
BUZDR
R/W
1
1
1
1
1
1
1
1
90H
Reserved
-
-
-
-
-
-
-
-
-
-
91H
Reserved
-
-
-
-
-
-
-
-
92H
Pin Mux Control Register
93H
94H
-
-
PINMCR
R/W
-
-
-
0
0
0
0
0
Reserved
-
-
-
-
-
-
-
-
-
-
Reserved
-
-
-
-
-
-
-
-
-
-
95H
Reserved
96H
Buzzer Control Register
-
-
-
-
-
-
-
-
-
-
BUZCR
R/W
-
-
-
-
-
0
0
0
97H
TIMER 0,1,4 Interrupt Flag
Register
TFLG
R/W
-
0
0
0
-
-
-
-
98H
Port 0 Direction Register
P0IO
R/W
0
0
0
0
0
0
0
0
99H
Reserved
-
-
-
-
-
-
-
-
-
-
9AH
A/D
Converter
Register
ADCM
R/W
1
0
0
0
1
1
1
1
9BH
A/D Converter Result High
Register
ADCRH
R
X
X
X
X
X
X
X
X
9CH
A/D Converter Result Low
Register
ADCRL
R/W
0
1
0
0
-
-
X
X
9DH
Watch Timer Mode Register
WTMR
R/W
0
-
-
0
0
0
0
0
WTR
W
0
1
1
1
1
1
1
1
9EH
Watch
Register
WTCR
R
0
0
0
0
0
0
0
0
Mode
Watch Timer Register
PS029502-0212
Timer
Counter
PRELIMINARY
46
Z51F0410
Product Specification
9FH
Port Selection Register0
PSR0
R/W
0
0
0
0
0
0
0
0
A0H
Port Selection Register1
PSR1
R/W
0
0
0
0
0
0
0
0
A1H
Port 0 Open Drain Register
P0OD
R/W
0
0
0
0
0
0
0
0
A2H
Reserved
-
-
-
-
-
-
-
-
-
-
A3H
Reserved
-
-
-
-
-
-
-
-
-
-
A4H
Reserved
-
-
-
-
-
-
-
-
-
-
A5H
Reserved
-
-
-
-
-
-
-
-
-
-
A6H
Reserved
-
-
-
-
-
-
-
-
-
-
A7H
Reserved
-
-
-
-
-
-
-
-
-
-
A8H
Interrupt Enable Register 0
IE
R/W
0
0
0
0
0
0
0
0
A9H
Interrupt Enable Register 1
IE1
R/W
0
0
0
0
0
0
0
0
AAH
Interrupt Enable Register 2
IE2
R/W
0
0
0
0
0
0
0
0
ABH
Interrupt Enable Register 3
IE3
R/W
0
0
0
0
0
0
0
0
ACH
External
Register
Interrupt
Flag
EIFLAG
R/W
-
-
-
-
0
0
0
0
ADH
External
Register
Interrupt
Edge
EIEDGE
R/W
-
-
-
-
0
0
0
0
AEH
External Interrupt
Register
EIPOLA
W
-
-
-
-
0
0
0
0
AFH
External
Register
EIENAB
R/W
-
-
-
-
0
0
0
0
B0H
Reserved
-
-
-
-
-
-
-
-
-
-
B1H
Reserved
-
-
-
-
-
-
-
-
-
-
B2H
Timer 0
Register
T0CR
R/W
0
0
0
0
0
0
0
0
T0
R
0
0
0
0
0
0
0
0
T0DR
W
1
1
1
1
1
1
1
1
CDR0
R
0
0
0
0
0
0
0
0
T1CR
R/W
0
0
0
0
0
0
0
0
T1DR
W
1
1
1
1
1
1
1
1
T1PPR
W
1
1
1
1
1
1
1
1
T1
R
0
0
0
0
0
0
0
0
Timer 1 RWM Duty Register
T1PDR
R/W
1
1
1
1
1
1
1
1
Timer
1
Register
Capture
CDR1
R
0
0
0
0
0
0
0
0
B7H
Timer
1
Register
PWM
Control
T1PWHR
R/W
0
0
0
0
0
0
0
0
B8H
Interrupt Priority
Register 0
Control
IP
R/W
0
0
0
0
0
0
0
0
B9H
Reserved
-
-
-
-
-
-
-
-
-
-
BAH
Reserved
-
-
-
-
-
-
-
-
-
-
Polarity
Interrupt
Mode
Enable
Control
Timer 0 Register
B3H
B4H
Timer 0 Data Register
Timer
0
Register
Capture
Timer 1
Register
Mode
Data
Control
Timer 1 Data Register
B5H
Timer
1
Register
PWM
Period
Timer 1 Register
B6H
Data
BBH
Reserved
-
-
-
-
-
-
-
-
-
-
BCH
Reserved
-
-
-
-
-
-
-
-
-
-
BDH
Reserved
-
-
-
-
-
-
-
-
-
-
PS029502-0212
PRELIMINARY
47
Z51F0410
Product Specification
BEH
Reserved
-
-
-
-
-
-
-
-
-
-
BFH
Reserved
-
-
-
-
-
-
-
-
-
-
C0H
Port 0 Debounce Register
P0DB
R/W
0
0
0
0
0
0
0
0
C1H
Port 0 Pin Change Interrupt
P0PC
R/W
0
0
0
0
0
0
0
0
C2H
Reserved
-
-
-
-
-
-
-
-
-
-
C3H
Reserved
-
-
-
-
-
-
-
-
-
-
C4H
Reserved
-
-
-
-
-
-
-
-
-
-
C5H
Reserved
-
-
-
-
-
-
-
-
-
-
C6H
Reserved
-
-
-
-
-
-
-
-
-
C7H
Reserved
-
-
-
-
-
-
-
-
-
C8H
Reserved
-
-
-
-
-
-
-
-
-
-
C9H
Reserved
-
-
-
-
-
-
-
-
-
-
CAH
Reserved
-
-
-
-
-
-
-
-
-
CBH
Reserved
-
-
-
-
-
-
-
-
-
CCH
Reserved
-
-
-
-
-
-
-
-
-
CDH
Timer 4 Data High Register
T4H
R
0
0
0
0
0
0
0
0
CEH
Timer 4 Mode Control Register
T4CR
R/W
0
0
0
0
0
0
0
0
CFH
Timer 4 Data Low Register
T4L
R/W
0
0
0
0
0
0
0
0
D0H
Program
Register
PSW
R/W
0
0
0
0
0
0
0
0
D1H
Authetification FAB Key
AUTH_FKEY0
R/W
0
0
0
0
0
0
0
0
D2H
Authetification FAB Key
AUTH_FKEY1
R/W
0
0
0
0
0
0
0
0
D3H
USER SEED0[7:0]
USEED0
R/W
0
0
0
0
0
0
0
0
D4H
USER_SEED1[15:8]
USEED1
R/W
0
0
0
0
0
0
0
0
D5H
SID Access Addresss
SIDA
R
-
-
-
-
-
-
-
-
D6H
Current SID Data Value
SIDD
R
-
-
-
-
-
-
-
-
D7H
I2C Slave Address Register
I2CAR
R/W
0
0
0
0
0
0
0
0
D8H
Reserved
-
-
-
-
-
-
-
-
-
-
D9H
Reserved
-
-
-
-
-
-
-
-
-
-
DAH
I2C Mode Control Register
I2CMR
R/W
0
0
0
0
0
0
0
0
Status
Word
DBH
I2C Status Register
I2CSR
R
0
0
0
0
0
0
0
0
DCH
I2C SCL Low Period Register
I2CSCLLR
R/W
0
0
1
1
1
1
1
1
DDH
I2C
SCL
Register
I2CSCLHR
R/W
0
0
1
1
1
1
1
1
DEH
I2C SDA Hold Time Register
I2CSDAHR
R/W
0
0
0
0
0
0
1
1
DFH
I2C Data Register
I2CDR
R/W
1
1
1
1
1
1
1
1
E0H
Accumulator Register
ACC
R/W
0
0
0
0
0
0
0
0
High
Period
E1H
Reserved
-
-
-
-
-
-
-
-
-
-
E2H
USART Control Register 1
UCTRL1
R/W
0
0
0
0
0
0
0
0
E3H
USART Control Register 2
UCTRL2
R/W
0
0
0
0
0
0
0
0
E4H
USART Control Register 3
UCTRL3
R/W
0
0
0
0
0
0
0
0
E5H
USART Status Register
USTAT
R/W
1
0
0
0
-
0
0
0
E6H
USART
Baud
Generation Register
UBAUD
R/W
1
1
1
1
1
1
1
1
E7H
USART Data Register
UDATA
R/W
1
1
1
1
1
1
1
1
PS029502-0212
Rate
PRELIMINARY
48
Z51F0410
Product Specification
E8H
Reserved
-
-
-
-
-
-
-
-
-
-
E9H
Analog Comparator Control
& Status Register
ACCSR
R/W
0
0
0
0
0
0
0
0
EAH
Flash and EEPROM Mode
Register
FEMR
R/W
0
0
0
0
0
0
0
0
EBH
Flash and EEPROM Control
Register
FECR
R/W
0
0
0
0
0
0
1
1
ECH
Flash and EEPROM Status
Register
FESR
R/W
1
0
0
0
0
0
0
0
EDH
Flash and EEPROM Timer
Control Register
FETCR
R/W
0
0
0
0
0
0
0
0
EEH
Authetification Key LSB
AUTH_UKEY
0
R/W
0
0
0
0
0
0
0
0
EFH
Authetification Key MSB
AUTH_UKEY
1
R/W
0
0
0
0
0
0
0
0
F0H
B Register
B
R/W
0
0
0
0
0
0
0
0
F1H
Reserved
-
-
-
-
-
-
-
-
-
-
F2H
Flash and EEPROM Address
Low Register
FEARL
W
0
0
0
0
0
0
0
0
F3H
Flash and EEPROM Address
Middle Register
FEARM
W
0
0
0
0
0
0
0
0
F4H
Flash and EEPROM Address
High Register
FEARH
W
0
0
0
0
0
0
0
0
F5H
Flash and EEPROM Data
Register
FEDR
R/W
0
0
0
0
0
0
0
0
F6H
Reserved
-
-
-
-
-
-
-
-
-
-
F7H
VDC Trimming for RCOSC
128Khz
FUSE_CAL3
R/W
0
0
0
0
0
0
0
0
F8H
Interrupt Priority
Register 1
IP1
R/W
0
0
0
0
0
0
0
0
F9H
Configuration Option 1
FUSE_CONF
2
R/W
-
-
-
-
-
-
-
0
FAH
BGR and BOD Calibration
Data
FUSE_CAL2
R/W
0
0
0
0
0
0
0
0
FBH
INTOSC Calibration Data
FUSE_CAL1
R/W
1
0
0
0
0
0
0
0
FCH
VDC Trimming for INTOSC
8Mhz
FUSE_CAL0
R/W
0
0
0
0
0
0
0
0
FDH
Configuration Option 0
FUSE_CONF
1
R/W
-
-
-
0
0
0
0
0
FEH
Function Test Register B
TEST_B
R/W
0
0
0
0
0
0
0
0
FFH
Function Test Register A
TEST_A
R/W
0
0
0
0
0
0
0
1
Control
2.2.3 Compiler Compatible SFR
ACC (Accumulator) : E0H
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
ACC
R/W
PS029502-0212
R/W
R/W
R/W
PRELIMINARY
49
Z51F0410
Product Specification
Initial value : 00H
ACC
Accumulator
B (B Register) : F0H
7
6
5
4
R/W
R/W
R/W
R/W
3
2
1
R/W
R/W
R/W
3
2
1
R/W
R/W
R/W
3
2
1
R/W
R/W
R/W
3
2
1
R/W
R/W
R/W
0
B
B
R/W
Initial value : 00H
B Register
SP (Stack Pointer) : 81H
7
6
5
4
0
SP
R/W
R/W
R/W
SP
R/W
R/W
Initial value : 07H
Stack Pointer
DPL (Data Pointer Low Byte) : 82H
7
6
5
4
0
DPL
R/W
R/W
R/W
DPL
R/W
R/W
Initial value : 00H
Data Pointer Low Byte
DPH (Data Pointer High Byte) : 83H
7
6
5
4
R/W
R/W
R/W
R/W
0
DPH
DPH
R/W
Initial value : 00H
Data Pointer High Byte
PSW (Program Status Word) : D0H
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS0
OV
F1
P
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PS029502-0212
CY
Carry Flag
AC
Auxiliary Carry Flag
F0
General Purpose User-Definable Flag
R/W
Initial value : 00H
RS1
Register Bank Select bit 1
RS0
Register Bank Select bit 0
OV
Overflow Flag
F1
User-Definable Flag
P
Parity Flag. Set/cleared by hardware each instruction cycle to
indicate an odd/even number of ‘1’ bits in the accumulator
PRELIMINARY
50
Z51F0410
Product Specification
2.3 I/O Port
2.3.1 I/O Ports
The Z51F0410 MCU features one I/O ports (P0). Each port can be easily configured by software as
I/O pin, internal pull up and open drain pin to meet various system configurations and design
requirements. Also P0 includes function that can generate interrupt according to change of state of
the pin.
2.3.2 Port Register
2.3.2.1 Data Register (P0)
Data Register is a bidirectional I/O port. If ports are configured as output ports, data can be written to
the corresponding bit of the P0. If ports are configured as input ports, the data can be read from the
corresponding bit of the P0.
2.3.2.2 Direction Register (P0IO)
Each I/O pin can independently used as an input or an output through the P0IO register. Bits cleared
in this read/write register will select the corresponding pin in P0 to become an input, setting a bit sets
the pin to output. All bits are cleared by a system reset.
2.3.2.3 Pull-up Resistor Selection Register (P0PU)
The on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up resistor selection
register (P0PU). The pull-up register selection controls the pull-up resister enable/disable of each port.
When the corresponding bit is 1, the pull-up resister of the pin is enabled. When 0, the pull-up resister
is disabled. All bits are cleared by a system reset.
2.3.2.4 Open-drain Selection Register (P0OD)
There is internally open-drain selection register (P0OD) in P0. The open-drain selection register
controls the open-drain enable/disable of each port. Ports become push-pull by a system reset. You
should connect an external resistor in open-drain output mode.
2.3.2.5 Debounce Enable Register (P0DB)
P0 support debounce function. Debounce time of each ports has 1us, but if P0[2] uses external reset
function, it has 3us debounce time. (except P0[2], other port initialization state is OFF)
2.3.2.6 Pin Change Interrupt Enable Register (P0PC)
The P0 can support Pin Change Interrupt function. Pin Change Interrupts PCI will trigger if any
PS029502-0212
PRELIMINARY
51
Z51F0410
Product Specification
enabled P0[7:0] pin toggles. The P0PC Register control which pins contribute to the pin change
interrupts.
2.3.2.7 Pin Mux Control Register (PINMCR)
In the 10pin PKG, The secondary pin muxing function is added for pin efficiency.
2.3.2.8 Pin PAD Data Register (P0PD)
It is used to read directly PAD data regardless of port direction.
2.3.2.9 PORT Selection Register0(PSR0, PSR1)
ADC Channel Selection (PSR0), and Comparator Output Selection (PSR1) disables the logic input
gate to prevent the leakage current.
2.3.2.10 Register Map
Table 2.3 Register map
Name
Address
Dir
Default
Description
P0
80H
R/W
00H
P0 Data Register
P0IO
98H
R/W
00H
P0 Direction Register
P0PU
89H
R/W
00H
P0 Pull-up Resistor Selection Register
P0OD
A1H
R/W
00H
P0 Open-drain Selection Register
P0DB
C0H
R/W
00H
P0 Debounce Enable Register
P0PC
C1H
R/W
00H
P0 Pin Change Interrupt Enable Register
P0PD
88H
R/W
00H
P0 PAD Data Register
PINMCR
92H
R/W
00H
Pin Mux Control Register
2.3.3 P0 Port
2.3.3.1 P0 Port Description
P0 is 8-bit I/O port. P0 control registers consist of Data register (P0), direction register (P0IO),
debounce enable register (P0DB, P2DB), pull-up register selection register (P0PU), open-drain
selection register (P0OD).
2.3.3.2 Register description for P0
P0 (P0 Data Register) : 80H
7
6
5
4
3
2
1
0
P07
P06
P05
P04
P03
P02
P01
P00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PS029502-0212
PRELIMINARY
52
Z51F0410
Product Specification
Initial value : 00H
P0[7:0]
I/O Data
P0IO (P0 Direction Register) : 98H
7
6
5
4
3
2
1
0
P07IO
P06IO
P05IO
P04IO
P03IO
P02IO
P01IO
P00IO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P0IO[7:0]
R/W
Initial value : 00H
P0 data I/O direction.
0
Input
1
Output
P0PU (P0 Pull-up Resistor Selection Register) : 89H
7
6
5
4
3
2
1
0
P07PU
P06PU
P05PU
P04PU
P03PU
P02PU
P01PU
P00PU
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P0PU[7:0]
R/W
Initial value : 00H
Configure pull-up resistor of P0 port
0
disable
1
enable
P0OD (P0 Open-drain Selection Register) : A1H
7
6
5
4
3
2
1
0
P07OD
P06OD
P05OD
P04OD
P03OD
P02OD
P01OD
P00OD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P0OD[7:0]
R/W
Initial value : 00H
Configure open-drain of P0 port
0
disable
1
enable
P0DB (P0 Debounce Enable Register) : C0H
7
6
5
4
3
2
1
0
P07DB
P06DB
P05DB
P04DB
P03DB
P02DB
P01DB
P00DB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P0DB[7:0]
R/W
Initial value : 00H
Configure debounce of P0 port
0
disable
1
enable
P0PC (P0 Pin Change Interrupt Enable Register) : C1H
7
6
5
4
3
2
1
0
P07PC
P06PC
P05PC
P04PC
P03PC
P02PC
P01PC
P00PC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PS029502-0212
PRELIMINARY
R/W
Initial value : 00H
53
Z51F0410
Product Specification
P0PC[7:0]
Configure Pin Change Interrupt of P0 port
0
disable
1
enable
PSR0 (ADC Pin Selection Register) : 9FH
7
6
5
4
3
2
1
0
AIN07_EN
AIN06_EN
AIN05_EN
AIN04_EN
AIN03_EN
AIN02_EN
AIN01_EN
AIN00_EN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PSR0[7:0]
R/W
Initial value : 00H
ADC Channel Selection (Disable logic input gate)
0
disable
1
enable
PSR1 (Comparator Pin Selection Register) : A0H
7
6
5
4
3
2
1
0
ACO_EN
R/W
Initial value : 00H
PSR1[0]
Analog Comparator Output Enable (Disable logic input gate)
0
disable
1
enable
P0PD (P0 PAD Data Register) : 88H
7
6
5
4
3
2
1
0
P0PD7
P0PD 6
P0PD 5
P0PD 4
P0PD 3
P0PD 2
P0PD 1
P0PD 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
3
2
1
0
XINT_CFG
P0PD[7:0]
R/W
Initial value : 00H
PAD input data
PINMCR ( Pin Mux Control Register) : 92H
7
6
5
4
-
-
-
TMR_CFG
BUZ_CFG
I2C_CFG
USART_CF
G
-
-
-
R/W
R/W
R/W
R/W
TR_CFG
BUZZER Pin Control Mode
I2C_CFG
I2C Pin Control Mode
XINT_CFG
PS029502-0212
Timer Pin Control Mode
BUZ_CFG
USART_CFG
R/W
Initial value : 00H
USART Pin Control Mode
External Interrupt Pin Control Mode
PRELIMINARY
54
Z51F0410
Product Specification
Min. 5 clock counting
External Port
Pin Signal
DBCLK
Port Data
Figure 2.4 Debounce Function
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Z51F0410
Product Specification
3. Interrupt Controller
3.1 Overview
The Z51F0410 MCU supports up to 15 interrupt sources. The interrupts have separate enable
register bits associated with them, allowing software control. They can also have four levels of priority
assigned to them. The nonmaskable interrupt source is always enabled with a higher priority than any
other interrupt source, and is not controllable by software. The interrupt controller has following
features:
- receive the request from 24 interrupt source
- 6 group priority
- 4 priority levels
- Multi Interrupt possibility
- If the requests of different priority levels are received simultaneously, the request of higher
priority level is serviced
- Each interrupt source can control by EA bit and each IEx bit
- Interrupt latency: 5–8 machine cycles in single interrupt system
The nonmaskable interrupt is always enabled. The maskable interrupts are enabled through four pair
of interrupt enable registers (IE, IE1, IE2, IE3). Bits of IE, IE1, IE2, IE3 register each individually
enable/disable a particular interrupt source. Overall control is provided by bit 7 of IE (EA). When EA is
set to ‘0’, all interrupts are disabled: when EA is set to ‘1’, interrupts are individually enabled or
disabled through the other bits of the interrupt enable registers. The Z51F0410 MCU supports a fourlevel priority scheme. Each maskable interrupt is individually assigned to one of four priority levels by
writing to IP or IP1.
External interrupt default mode is level-trigger basically but if needed, it is able to change edgetrigger mode. Table 3.1 shows the Interrupt Group Priority Level that is available for sharing interrupt
priority. Priority sets two bit which is to IP and IP1 register about group. Interrupt service routine
services higher priority. If two requests of different priority levels are received simultaneously, the
request of higher priority level is serviced. If the request of same or lower priority level is received, that
request is not serviced.
Table 3.1 Interrupt Group Priority Level
Interrupt
Group
Highest
Lowest
0 (Bit0)
Interrupt0
Interrupt6
Interrupt12
Interrupt18
1 (Bit0)
Interrupt1
Interrupt7
Interrupt13
Interrupt19
2 (Bit0)
Interrupt2
Interrupt8
Interrupt14
Interrupt20
3 (Bit0)
Interrupt3
Interrupt9
Interrupt15
Interrupt21
4 (Bit0)
Interrupt4
Interrupt10
Interrupt16
Interrupt22
5 (Bit0)
Interrupt5
Interrupt11
Interrupt17
Interrupt23
Highest
Lowest
3.2 External Interrupt
The external interrupt on INT0, INT1 pins receive various interrupt request depending on the edge
selection register EIEDGE (External Interrupt Edge register) and EIPOLA (External Interrupt Polarity
register) as shown in Figure 3.1. Also each external interrupt source has control setting bits. The
PS029502-0212
PRELIMINARY
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Z51F0410
Product Specification
EIFLAG (External interrupt flag register) register provides the status of external interrupts.
INT0
Pi
FLAG0
INT1
I t
t
FLAG1
INT2
I t
t
2
INT1
Pi
2
EIEDGE, EIPOLA
[ADH]External Interrupt Edge Register
[AEH]External
Interrupt
Polarity
Figure 3.1 External Interrupt Description
PS029502-0212
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Z51F0410
Product Specification
3.3 Block Diagram
IEDS0
IE[A8H]
IP[B8H]
IP1[F8H]
0
0
EIFLAG.0[ACH]
INT0
FLAG0
INT1
FLAG1
1
EIFLAG.1[ACH]
1
2
2
-
2
3
FLAG2
Reser
d
Reser
d
0
1
3
-
3
4
FLAG3
4
4
5
PCI
PCI
5
5
0
Priority High
1
2
3
4
5
IE1[A9H]
6
INT6
Reserved
6
INT7
7
8
USTAT.6 [E5H]
TXC
UART Tx
RXC
Reserved
INT11
7
8
INT8
UART Rx
6
7
8
9
9
USTAT.5 [E5H]
9
10
10
-
10
11
11
11
6
7
8
9
10
11
Release
Stop/Sleep
IE2[AAH]
I2CSR.6 [DBH]
2-Wire
Interface
Timer 0
12
TEND
12
T0IF
13
T1ISR[7:2] [C4H]
Timer 1
INT15
Reserved
INT16
13
14
T1IF
Reserved
12
13
14
14
15
15
15
16
16
16
17
Timer4
T4IF
17
17
12
13
14
EA(IE.7[A8H])
15
16
17
IE3[ABH]
ADCM.4[9AH]
ADC
18
AFLAG
Comparator
CMPIF
WT
WTIFR
WDT
WDTMR
18
19
WTMR.4[9DH]
20
EEPROM
ROMI
F
20
21
21
BITF.7[8BH]
BCCR
19
20
WTMR.0[8DH]
BIT
18
19
21
22
22
22
23
23
23
18
19
20
21
22
23
Priority Low
Figure 3.2 Block Diagram of Interrupt
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Z51F0410
Product Specification
3.4 Interrupt Vector Table
The interrupt controller supports 24 interrupt sources as shown in the Table 3.2 below. When
interrupt becomes service, long call instruction (LCALL) is executed in the vector address. Interrupt
request 24 has a decided priority order.
Table 3.2 Interrupt Vector Address Table
Interrupt Source
Symbol
Hardware Reset
RESETB
External Interrupt 0
External Interrupt 1
Pin Change Interrupt (P0)
UART Rx
UART Tx
I2C
T0
T1
T4
ADC
Analog Comparator
WT
WDT
BIT
EEPROM
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
INT8
INT9
INT10
INT11
INT12
INT13
INT14
INT15
INT16
INT17
INT18
INT19
INT20
INT21
INT22
INT23
Interrupt
Enable Bit
Polarity
Mask
Vector Address
0
0
NonMaskable
0000H
IE0.0
IE0.1
IE0.2
IE0.3
IE0.4
IE0.5
IE1.0
IE1.1
IE1.2
IE1.3
IE1.4
IE1.5
IE2.0
IE2.1
IE2.2
IE2.3
IE2.4
IE2.5
IE3.0
IE3.1
IE3.2
IE3.3
IE3.4
IE3.5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
0003H
000BH
0013H
001BH
0023H
002BH
0033H
003BH
0043H
004BH
0053H
005BH
0063H
006BH
0073H
007BH
0083H
008BH
0093H
009BH
00A3H
00ABH
00B3H
00BBH
For maskable interrupt execution, first EA bit must set ‘1’ and specific interrupt source must set ‘1’ by
writing a ‘1’ to associated bit in the IEx. If interrupt request is received, specific interrupt request flag
set ‘1’. And it remains ‘1’ until CPU accepts interrupt. After that, interrupt request flag will be cleared
automatically.
3.5 Interrupt Sequence
An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to ‘0’ by a
reset or an instruction. Interrupt acceptance always generates at last cycle of the instruction. So
instead of fetching the current instruction, CPU executes internally LCALL instruction and saves the
PC stack. For the interrupt service routine, the interrupt controller gives the address of LJMP
instruction to CPU. After finishing the current instruction, at the next instruction to go interrupt service
routine needs 3–9 machine cycle and the interrupt service task is terminated upon execution of an
interrupt return instruction [RETI]. After generating interrupt, to go to interrupt service routine, the
following process is progressed
PS029502-0212
PRELIMINARY
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Z51F0410
Product Specification
1
IE.EA Flag  1
IEx.y  1
2
Program Counter low Byte
SP  SP + 1
M(SP)  (PCL)
Saves PC value in order to continue
process again after executing ISR
3
Program Counter high Byte
SP  SP + 1
M(SP)  (PCH)
4
Interrupt Vector Address occurrence
(Interrupt Vector Address)
5
ISR(Interrupt Service Routine) move, execute
6
Return from ISR
RETI
7
Program Counter high Byte recovery
(PCL)  (SP-1)
8
Program Counter low Byte recovery
(PCL)  (SP-1)
9
Main Program execution
Figure 3.3 Interrupt Vector Address Table
PS029502-0212
PRELIMINARY
60
Z51F0410
Product Specification
3.6 Effective Timing after Controlling Interrupt bit
Case a) Control Interrupt Enable Register (IE, IE1, IE2, IE3)
Interrupt Enable Register
command
Next Instruction
After executing IE set/clear, enable
register is effective.
Next Instruction
Figure 3.4 Effective Timing of Interrupt Enable Register
Case b) Interrupt flag Register
Interrupt Flag Register
Command
Next Instruction
After executing next instruction,
interrupt flag result is effective.
Next Instruction
Figure 3.5 Effective Timing of Interrupt Flag Register
3.7 Multi Interrupt
If two requests of different priority levels are received simultaneously, the request of higher priority
level is serviced. If requests of the interrupt are received at the same time simultaneously, an interrupt
polling sequence determines by hardware which request is serviced. However, multiple processing
through software for special features is possible.
PS029502-0212
PRELIMINARY
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Z51F0410
Product Specification
Main Program
Service
INT1 ISR
INT0 ISR
Enable INT0
Disable others
EA
Occur
INT1 Interrupt
Occur
INT0 Interrupt
Enable INT0
Enable others
RETI
RETI
Figure 3.6 Execution of Multi Interrupt
Following example is shown to service INT0 routine during INT1 routine in Figure 3.6. In this
example, INT0 interrupt priority is higher than INT1 interrupt priority. If some interrupt is lower than
INT1 priority, it can’t service its interrupt routine.
Example) Software Multi Interrupt:
INT1:
MOV
IE, #81H
; Enable INT0 only
MOV
IE1, #00H
; Disable other
MOV
IE, #0FFH
; Enable all Interrupts
MOV
IE1, #0FFH
:
RETI
PS029502-0212
PRELIMINARY
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Z51F0410
Product Specification
3.8 Interrupt Enable Accept Timing
Max. 4 Machine Cycle
4 Machine Cycle
System
Clock
Interrupt
goes
Active
Interrupt
Latched
Interrupt Processing
: LCALL & LJMP
Interrupt Routine
Figure 3.7 Interrupt Response Timing Diagram
3.9 Interrupt Service Routine Address
Basic Interval Timer
Vector Table Address
Basic Interval Timer
Service Routine Address
00B3H
01H
0125H
0EH
00B4H
25H
0126H
2EH
Figure 3.8 Correspondence between vector Table address and the entry address of ISP
3.10 Saving/Restore General-Purpose Registers
INTxx : PUSH
PUSH
PUSH
PUSH
PUSH
·
·
PSW
DPL
DPH
B
Main Task
Interrupt
Service Task
ACC
Saving
Register
Interrupt_Processing:
∙
∙
POP
POP
POP
POP
POP
RETI
Restoring
Register
ACC
B
DPH
DPL
PSW
Figure 3.9 Saving/Restore Process Diagram & Sample Source
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Z51F0410
Product Specification
3.11 Interrupt Timing
Interrupt sampled here
CLP2
CLP1
CLP2
C1P1
C1P2
C2P1
C2P2
SCLK
INT_SRC
INTR_ACK
LAST_CYC
INTR_LCALL
8-Bit interrupt Vector
INT_VEC
{8’h00, INT_VEC}
PROGA
Figure 3.10 Timing chart of Interrupt Acceptance and Interrupt Return Instruction
Interrupt source sampled at last cycle of the command. When sampling interrupt source, it is decided
to low 8-bit of interrupt vector. M8051W core makes interrupt acknowledge at first cycle of command,
executes long call to jump interrupt routine as INT_VEC.
Note) command cycle C?P?: L=Last cycle, 1=1st cycle or 1st phase, 2=2nd cycle or 2nd phase
3.12 Interrupt Register Overview
3.12.1 Interrupt Enable Register (IE, IE1, IE2, IE3)
Interrupt enable register consists of Global interrupt control bit (EA) and peripheral interrupt control
bits. Totally 24 peripheral are able to control interrupt.
3.12.2 Interrupt Priority Register (IP, IP1)
The 24 interrupt divides 6 groups which have each 4 interrupt sources. A group can decide 4 levels
interrupt priority using interrupt priority register. Level 3 is the high priority, while level 0 is the low
priority. Initially, IP, IP1 reset value is ‘0’. At that initialization, low interrupt number has a higher
priority than high interrupt number. If decided the priority, low interrupt number has a higher priority
than high interrupt number in that group.
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Z51F0410
Product Specification
3.12.3 External Interrupt Flag Register (EIFLAG)
The external interrupt flag register is set to ‘1’ when the external interrupt generating condition is
satisfied. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be
cleared by writing a ‘0’ to it.
3.12.4 External Interrupt Edge Register (EIEDGE)
The External interrupt edge register determines which type of edge or level sensitive interrupt.
Initially, default value is level. For level, write ‘0’ to related bit. For edge, write ‘1’ to related bit.
3.12.5 External Interrupt Polarity Register (EIPOLA)
According to EIEDGE register, the external interrupt polarity (EIPOLA) register has a different
meaning. If EIEDGE is level type, EIPOLA is able to have Low/High level value. If EIEGDE is edge
type, EIPOLA is able to have rising/falling edge value.
3.12.6 External Interrupt Enable Register (EIENAB)
When the external interrupt enable register is written to ‘1’, the corresponding external pin interrupt is
enabled. The EIEDGE and EIPOLA register defines whether the external interrupt is activated on
rising or falling edge or level sensed.
3.12.7 Register Map
Table 3.3 Register Map
Name
Address
Dir
Default
Description
IE
A8H
R/W
00H
Interrupt Enable Register
IE1
A9H
R/W
00H
Interrupt Enable Register 1
IE2
AAH
R/W
00H
Interrupt Enable Register 2
IE3
ABH
R/W
00H
Interrupt Enable Register 3
IP
B8H
R/W
00H
Interrupt Polarity Register
IP1
F8H
R/W
00H
Interrupt Polarity Register 1
EIFLAG
ACH
R/W
00H
External Interrupt Flag Register
EIEDGE
ADH
R/W
00H
External Interrupt Edge Register
EIPOLA
AEH
R/W
00H
External Interrupt Polarity Register
EIENAB
AFH
R/W
00H
External Interrupt Enable Register
3.13 Interrupt Register Description
The Interrupt Register is used for controlling interrupt functions. Also it has External interrupt control
registers. The interrupt register consists of Interrupt Enable Register (IE), Interrupt Enable Register 1
(IE1), Interrupt Enable Register 2 (IE2) and Interrupt Enable Register 3 (IE3). For external interrupt, it
consists of External Interrupt Flag Register (EIFLAG), External Interrupt Edge Register (EIEDGE),
External Interrupt Polarity Register (EIPOLA) and External Interrupt Enable Register (EIENAB).
3.13.1 Register description for Interrupt
IE (Interrupt Enable Register) : A8H
7
PS029502-0212
6
5
4
3
PRELIMINARY
2
1
0
65
Z51F0410
Product Specification
EA
-
INT5E
-
-
INT2E
INT1E
R/W
R
R/W-
R/
R
R/W
R/W
EA
R/
Initial value : 00H
Enable or disable all interrupt bits
INT5E
INT2E
INT1E
0
All Interrupt disable
1
All Interrupt enable
Enable or disable Pin Change Interrupt
0
disable
1
enable
Enable or disable External Interrupt 1
0
disable
1
enable
Enable or disable External Interrupt 0
0
disable
1
enable
IE1 (Interrupt Enable Register 1) : A9H
7
6
5
4
3
2
1
0
-
-
-
INT10E-
INT9E
-
-
-
R
R
R/ -
R/W
R/W
R
R
INT10E
INT9E
R
Initial value : 00H
Enable or disable UART Tx Interrupt
0
disable
1
enable
Enable or disable UART Rx Interrupt
0
disable
1
enable
IE2 (Interrupt Enable Register 2) : AAH
7
6
5
4
3
2
1
0
-
-
INT17E
-
-
INT14E
INT13E
INT12E
R
R
R/W-
R
R
R/W
R/W
INT17E
INT14E
INT13E
INT12E
PS029502-0212
R/W
Initial value : 00H
Enable or disable Timer 4 interrupt
0
disable
1
enable
1
enable
Enable or disable Timer 1 Interrupt
0
disable
1
enable
Enable or disable Timer 0 Interrupt
0
disable
1
enable
Enable or disable I2C Interrupt
0
disable
1
enable
PRELIMINARY
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Z51F0410
Product Specification
IE3 (Interrupt Enable Register 3) : ABH
7
6
5
4
3
2
1
0
-
-
INT23E
INT22E-
INT21E
INT20E
INT19E
INT18E
R
R
R/W-
R/W
R/W
R/W
R/W
INT23E
INT22E
INT21E
INT20E
INT19E
INT18E
R/W
Initial value : 00H
Enable or disable EEPROM Interrupt
0
disable
1
enable
Enable or disable BIT Interrupt
0
disable
1
enable
Enable or disable WDT Interrupt
0
disable
1
enable
Enable or disable WT Interrupt
0
disable
1
enable
Enable or disable Analog Comparator Interrupt
0
disable
1
enable
Enable or disable ADC Interrupt
0
disable
1
enable
IP (Interrupt Priority Register) : B8H
7
6
5
4
3
2
1
0
-
-
IP5
IP4
IP3
IP2
IP1
R
R
R/W-
R/W
R/W
R/W
R/W
IP0
5
4
3
2
1
0
IP10
R/W
Initial value : 00H
IP1 (Interrupt Priority Register 1) : F8H
7
6
-
-
IP15
IP14
IP13
IP12
IP11
R
R
R/W-
R/W
R/W
R/W
R/W
IP[5:0],
IP1[5:0]
R/W
Initial value : 00H
Select Interrupt Group Priority
IP1x
IPx
Description
0
0
level 0 (lowest)
0
1
level 1
1
0
level 2
1
1
level 3 (highest)
EIFLAG (External Interrupt Flag Register) : ACH
7
6
5
4
3
2
1
0
-
-
-
-
-
-
FLAG1
FLAG0
R
R
R-
R
R
R
R/W
R/W
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PRELIMINARY
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Z51F0410
Product Specification
Initial value : 00H
FLAG[1:0]
If External Interrupt is occurred, the flag becomes ‘1’. The flag can
be cleared by writing a ‘0’ to bit
0
External Interrupt not occurred
1
External Interrupt occurred
EIEDGE (External Interrupt Edge Register) : ADH
7
6
5
4
3
2
1
0
-
-
-
-
-
-
EDGE1
EDGE0
R/W-
R/W-
R/W-
R/W
R/W
R/W
R/W
EDGE[1:0]
R/W
Initial value : 00H
Determines which type of edge or level sensitive interrupt may occ
ur.
0
Level (default)
1
Edge
EIPOLA (External Interrupt Polarity Register) : AEH
7
6
5
4
3
2
1
0
POLA0
-
-
-
-
-
-
POLA1
R/W
R/W
R/W-
R/W
R/W
R/W
R/W
POLA[1:0]
R/W
Initial value : 00H
According to EIEDGE, External interrupt polarity register has a
different means. If EIEDGE is level type, external interrupt polarity is
able to have Low/High level value. If EIEGDE is edge type, external
interrupt polarity is able to have rising/ falling edge value.
Level case:
0
When High level, Interrupt occurred (default)
1
When Low level, Interrupt occurred
Edge case:
0
When Rising edge, Interrupt occurred (default)
1
When Falling edge, Interrupt occurred
EIENAB (External Interrupt Enable Register) : AFH
7
6
5
4
3
2
1
0
-
-
-
-
-
-
ENAB1
ENAB0
R/W-
R/W-
R/W-
R/W
R/W
R/W
R/W
ENAB[1:0]
PS029502-0212
R/W
Initial value : 00H
Control External Interrupt
0
disable (default)
1
enable
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Z51F0410
Product Specification
4. Peripheral Hardware
4.1 Clock Generator
4.1.1 Overview
As shown in Figure 4.1, the clock generator produces the basic clock pulses which provide the
system clock to be supplied to the CPU and the peripheral hardware. It contains main-frequency clock
oscillator. The system clock operation can be easily obtained by attaching a crystal between the XIN
and XOUT pin, respectively. The system clock can also be obtained from the external oscillator. In
this case, it is necessary to put the external clock signal into the XIN pin and open the XOUT pin. The
default system clock is INT-RC Oscillator and the default division rate is one. In order to stabilize
system internally, use 128 KHz ring-oscillator (±50%) for BIT and WDT.
- Calibrated Internal RC Oscillator (8 MHz / ±1%)
. INT-RC OSC/1 (Default system clock)
. INT-RC OSC/2 (4 MHz)
. INT-RC OSC/4 (2 MHz)
. INT-RC OSC/8 (1 MHz)
- Crystal Oscillator (1~8 MHz)
- Sub-Clock Crystal Oscillator (32.768 KHz)
- Internal Ring-Oscillator (128 KHz / ±50%)
4.1.2 Block Diagram
PDOWN
XIN
XOUT
Main
OSC
fXIN
DCLK
fSUB
SUBXIN
SUBXOUT
SUB
OSC
WT
fRingRC
fINTRC
1/1
1/2
Divider 1/4
System
ClockGen.
Clock
Change
1/8
INT-RC
OSC
(8MHz)
Ring-OSC
(128KHz)
SCLK
(Core, System,
Peripherals)
System
Clock
Masking Control
BIT
Overflow
PDOWN
BIT
WDT
WONS
Figure 4.1 Clock Generator Block Diagram
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Z51F0410
Product Specification
4.1.3 Register Map
Table 4.1 SSCR Register Map
Name
SCCR
Address
Dir
8AH
Default
R/W
Description
04H
System and Clock Control Register
4.1.4 Clock Generator Register description
The Clock Generation Register uses clock control for system operation. The clock generation
consists of System and Clock register.
4.1.5 Register description for Clock Generator
SCCR (System and Clock Control Register) : 8AH
7
6
5
4
3
2
1
0
WONS
DIV1
DIV0
CBYS
ISTOP
XSTOP
CS1
CS0
R/W
R/W
R/W-
R/W
R/W
R/W
R/W
WONS
DIV[1:0]
CBYS
ISTOP
XSTOP
CS[1:0]
Control the operation of WDT RC-Oscillation during stop mode
0
WDTRC-Oscillator is disabled at stop mode (=STOP2)
1
WDTRC-Oscillator is enabled at stop mode (=STOP1)
When using fINTRC as system clock, determine division rate.
Note) when using fINTRC as system clock, only division rate come
into effect.
Note) To change by software, CBYS set to ‘1’
DIV1
DIV0
description
0
0
fINTRC/1 (8MHz)
0
1
fINTRC/2 (4MHz)
1
0
fINTRC/4 (2MHz)
1
1
fINTRC/8 (1MHz)
Control the scheme of clock change. If this bit set to ‘0’, clock
change is controlled by hardware. But if this set to ‘1’, clock change
is controlled by software. Ex) when setting CS[1:0], if CBYS bit set
to ‘0’, it is not changed right now, CPU goes to STOP mode and
then when wake-up, it applies to clock change.
Note) when clear this bit, keep other bits in SCCR
0
Clock changed by hardware during stop mode (default)
1
Clock changed by software. After clock is changed, it
should be cleared for low power.
Control the operation of INT-RC Oscillation
Note) when CBYS=’1’, It is applied
0
RC-Oscillation enable (default)
1
RC-Oscillation disable
Control the operation of X-Tal Oscillation
Note1) when CBYS=’1’, It is applied
Note2) if XINENA bit in FUSE_CONF to ‘0’, XSTOP is fixed to ‘1’
0
X-Tal Oscillation enable
1
X-Tal Oscillation disable (default)
Determine System Clock
Note) by CBYS bit, reflection point is decided
CS1
PS029502-0212
R/W
Initial value : 04H
CS0
description
PRELIMINARY
70
Z51F0410
Product Specification
PS029502-0212
0
0
fINTRC INTRC (8 MHz)
0
1
fXIN External Main Clock (1~8 MHz)
1
0
fSUB (32.768 KHz)
1
1
fRingRC (128KHz, ±50%)
PRELIMINARY
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Z51F0410
Product Specification
4.2 BIT
4.2.1 Overview
The Z51F0410 MCU features one 8-bit Basic Interval Timer that is free-run and can’t stop. Block
diagram is shown in Figure 4.2. In addition, the Basic Interval Timer generates the time base for
watchdog timer counting. It also provides a Basic interval timer interrupt (BITF).
The Z51F0410 MCU has these Basic Interval Timer (BIT) features:
- During Power On, BIT gives a stable clock generation time
- On exiting Stop mode, BIT gives a stable clock generation time
- As clock function, time interrupt occurrence
4.2.2 Block Diagram
& BITR[7:0]
& BITR[6:0]
& BITR[5:0]
& BITR[4:0]
& BITR[3:0]
& BITR[2:0]
& BITR[1:0]
& BITR[0]
Internal RingOSC (128KHz/
±50%)
BIT Interrupt
BITR
(8-BIT
COUNTER)
DIV
BCK[2:0]
BITR[7]
BITR[6]
BITR[5]
BITR[4]
BITR[3]
BITR[2]
BITR[1]
BITR[0]
BIT_OUT
(WDT clock source)
Figure 4.2 BIT Block Diagram
4.2.3 Register Map
Table 4.2 BIT Register Map
Name
Address
Dir
Default
Description
BCCR
8BH
R/W
05H
BIT Clock Control Register
BITR
8CH
R
00H
Basic Interval Timer Register
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4.2.4 Bit Interval Timer Register description
The Bit Interval Timer Register consists of BIT Clock control register (BCCR) and Basic Interval
Timer register (BITR). If BCLR bit set to ‘1’, BITR becomes ‘0’ and then counts up. After 1 machine
cycle, BCLR bit is cleared as ‘0’ automatically.
4.2.5 Register description for Bit Interval Timer
BCCR (BIT Clock Control Register) : 8BH
7
6
5
4
3
2
1
0
BCK0
BITF
-
-
-
BCLR
BCK2
BCK1
R/W
R
R
R
R/W
R/W
R/W
R/W
Initial value : 05H
When BIT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’
to this bit.
BITF
BCLR
BCK[2:0]
0
no generation
1
generation
If BCLK Bit is written to ‘1’, BIT Counter is cleared as ‘0’
0
Free Running
1
Clear Counter
Select BIT overflow period (BIT Clock=4 KHz)
BCK2
BCK1
BCK0
0
0
0
0.5msec (BIT Clock * 2)
0
0
1
1msec
0
1
0
2msec
0
1
1
4msec
1
0
0
8msec
1
0
1
16msec (default)
1
1
0
32msec
1
1
1
64msec
BITR (Basic Interval Timer Register) : 8CH
7
6
5
4
3
2
1
0
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
R
R
R
R
R
R
R
BIT[7:0]
PS029502-0212
R
Initial value : 00H
BIT Counter
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Z51F0410
Product Specification
4.3 WDT
4.3.1 Overview
The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or
the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting
malfunction can be selected either a reset CPU or an interrupt request. When the watchdog timer is
not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed
intervals. It is possible to use free running 8-bit timer mode (WDTRSON=’0’) or watch dog timer mode
(WDTRSON=’1’) as setting WDTMR[6] bit. If writing WDTMR[5] to ‘1’, WDT counter value is cleared
and counts up. After 1 machine cycle, this bit has ‘0’ automatically. The watchdog timer consists of 8bit binary counter and the watchdog timer data register. When the value of 8-bit binary counter is
equal to the 8 bits of WDTR, the interrupt request flag is generated. This can be used as Watchdog
timer interrupt or reset the CPU in accordance with the bit WDTRSON.
The clock source of Watch Dog Timer is BIT overflow output. The interval of watchdog timer interrupt
is decided by BIT overflow period and WDTR set value. The equation is as below
WDT Interrupt Interval = (BIT Interrupt Interval) X (WDTR Value+1)
4.3.2 Block Diagram
BIT Overflow
Watchdog Timer
Counter Register
1/2, 1/4, 1/8
Clear
To Reset
Circuit
WDTCR
WDTEN
[8EH]
WDTIFR
WCKDIV[1:0]
Watchdog Timer
Register
Clear
INT_ACK
WDTIF
WDTR
[8EH]
WDTCL
WDTRSON
WDTMR
Figure 4.3 WDT Block Diagram
4.3.3 Register Map
Table 4.3 WDT Register Map
Name
Address
Dir
Default
Description
WDTR
8EH
W
FFH
Watch Dog Timer Register
WDTCR
8EH
R
00H
Watch Dog Timer Counter Register
WDTMR
8DH
R/W
00H
Watch Dog Timer Mode Register
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4.3.4 Watch Dog Timer Register description
The Watch dog timer (WDT) Register consists of Watch Dog Timer Register (WDTR), Watch Dog
Timer Counter Register (WDTCR) and Watch Dog Timer Mode Register (WDTMR).
4.3.5 Register description for Watch Dog Timer
WDTR (Watch Dog Timer Register:Write Case) : 8EH
7
6
5
4
3
2
1
0
WDTR7
WDTR 6
WDTR 5
WDTR 4
WDTR 3
WDTR 2
WDTR 1
WDTR 0
W
W
W
W
W
W
W
W
Initial value : FFH
WDTR[7:0]
Set a period
WDT Interrupt Interval=(BIT Interrupt Interval) x(WDTR Value+1)
Note) To guarantee proper operation, the data should be greater than 01H.
WDTCR (Watch Dog Timer Counter Register:Read Case) : 8EH
7
6
5
4
3
2
1
0
WDTCR 7
WDTCR 6
WDTCR 5
WDTCR 4
WDTCR 3
WDTCR 2
WDTCR 1
WDTCR 0
R
R
R
R
R
R
R
WDTCR[7:0]
R
Initial value : 00H
WDT Counter
WDTMR (Watch Dog Timer Mode Register) : 8DH
7
6
5
4
3
2
1
0
WDTEN
WDTRSON
WDTCL
WCKDIV1
WCKDIV0
-
-
WDTIFR
R/W
R/W
R/W
R/W
R/W
-
-
WDTEN
WDTRSON
WDTCL
R/W
Initial value : 00H
Control WDT operation
0
disable
1
enable
Control WDT Reset operation
0
Free Running 8-bit timer
1
Watch Dog Timer Reset ON
Clear WDT Counter
0
Free Run
1
Clear WDT Counter (auto clear after 1 Cycle)
WCKDIV[1:0] WDT Clock Division Selection
WDTIFR
PS029502-0212
00
Default No Divided
01
WDT Clock = BIT Clock / 2
10
WDT Clock = BIT Clock / 4
11
WDT Clock = BIT Clock / 8
When WDT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write
‘0’ to this bit or auto clear by INT_ACK signal.
0
WDT Interrupt no generation
1
WDT Interrupt generation
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4.3.6 WDT Interrupt Timing Waveform
Source Clock
BIT Overflow
WDTCR[7:0]
0
1
2
3
0
1
2
3
0
1
2
Counter Clear
WDTR[7:0]
WDTIF
Interrupt
n
3
WDTCL
Occur
WDTR  0000_0011b
Match
Detect
WDTRESETB
RESET
Figure 4.4 WDT Interrupt Timing Waveform
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Z51F0410
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4.4 WT
4.4.1 Overview
The watch timer has the function for RTC (Real Time Clock) operation. It is generally used for RTC
design. The internal structure of the watch timer consists of the clock source select circuit, timer
counter circuit, output select circuit and watch timer mode register. To operate the watch timer,
determine the input clock source, output interval and set WTEN to ‘1’ in watch timer mode register
(WTMR). It is able to execute simultaneously or individually. To stop or reset WT, clear the WTEN bit
in WTMR register. Even if CPU is STOP mode, sub clock is able to be alive so WT can continue the
operation. The watch timer counter circuits may be composed of 21-bit counter which is low 14-bit
with binary counter and high 7-bit with auto reload counter in order to raise resolution. In WTR, it can
control WT clear and set Interval value at write time, and it can read 7-bit WT counter value at read
time.
4.4.2 Block Diagram
fSUB
(32.768kHz)
P
r
e
s
c
a
l
e
r
fx
÷64
fWCK / 214
14Bit
Binary Counter
fWCK
MUX
÷128
Timer Counter
(7bit auto reload counter)
÷256
fWCK / 214 x (7bit WTR Value +1)
7
fWCK/214
13
fWCK/2
MUX
WTIFR
WTIF
fWCK/212
Clear
WTMR
WTEN
-
-
WTIFR
WTIN1
WTIN0 WTCK1 WTCK0
2
INT_ACK
WTR
WTR Write
WTCL
WTR6
WTR5
WTR4
WTR2
WTR2
WTR1
WTR0
WTCR
WTR Read
-
WTCR6 WTCR5 WTCR4 WTCR2 WTCR2 WTCR1 WTCR0
Figure 4.5 Watch Timer Block Diagram
4.4.3 Register Map
Table 4.4 WT Register Map
Name
WTMR
Address
9DH
Dir
R/W
Default
Description
00H
Watch Timer Mode Register
WTR
9EH
W
7FH
Watch Timer Register
WTCR
9EH
R
00H
Watch Timer Counter Register
4.4.4 Watch Timer Register description
The watch timer register (WT) consists of Watch Timer Mode Register (WTMR), Watch Timer
Counter Register (WTCR) and Watch Timer Register (WTR). As WTMR is 6-bit writable/readable
PS029502-0212
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Z51F0410
Product Specification
register, WTMR can control the clock source (WTCK), interrupt interval (WTIN) and function
enable/disable (WTEN). Also there is WT interrupt flag bit (WTIFR).
4.4.5 Register description for Watch Timer
WTMR (Watch Timer Mode Register) : 9DH
7
6
5
4
3
2
1
0
WTEN
-
-
WTIFR
WTIN1
WTIN0
WTCK1
WTCK0
R/W
-
-
R/W
R/W
R/W
R/W
WTEN
WTIFR
WTIN[1:0]
WTCK[1:0]
R/W
Initial value :0 0H
Control Watch Timer
0
disable
1
enable
When WT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’
to this bit or auto clear by INT_ACK signal.
0
WT Interrupt no generation
1
WT Interrupt generation
Determine interrupt interval
WTIN1
WTIN0
description
0
0
fwck/2^11
0
1
fwck/2^13
1
0
fwck/2^14
1
1
fwck/2^14 x (7bit WT Value)
Determine Source Clock
WTCK1
WTCK0
description
0
0
fsub
0
1
fx/256
1
0
fx/128
1
1
fx/64
Remark: fx– Main system clock oscillation frequency
fsub- Sub clock oscillation frequency
fwck- selected Watch Timer clock
WTR (Watch Timer Register:Write Case) : 9EH
7
6
5
4
3
2
1
0
WTCL
WTR 6
WTR 5
WTR 4
WTR 3
WTR 2
WTR 1
WTR 0
W
W
W
W
W
W
W
WTCL
WTR[6:0]
W
Initial value : 7FH
Clear WT Counter
0
Free Run
1
Clear WT Counter (auto clear after 1 Cycle)
Set WT period
WT Interrupt Interval=(fwck/2^14) x(7bit WT Value+1)
Note) To guarantee proper operation, it is greater than 01H to write WTR.
WTCR (Watch Timer Counter Register:Read Case) : 9EH
7
6
5
4
3
2
1
0
WTCR 6
WTCR 5
WTCR 4
WTCR 3
WTCR 2
WTCR 1
WTCR 0
PS029502-0212
PRELIMINARY
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Z51F0410
Product Specification
-
R
R
WTCR[6:0]
PS029502-0212
R
R
R
R
R
Initial value : 00H
WT Counter
PRELIMINARY
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Z51F0410
Product Specification
4.5 Timer/PWM
4.5.1 8-bit Timer/Event Counter 0, 1
4.5.1.1 Overview
Timer 0 and timer 1 can be used either two 8-bit timer/counter or one 16-bit timer/counter with
combine them. Each 8-bit timer/event counter module has multiplexer, 8-bit timer data register, 8-bit
counter register, mode register, input capture register, comparator. For PWM, it has PWM register
(T1PPR, T1PDR, T1PWHR).
It has seven operating modes:
-
8 Bit Timer/Counter Mode
-
8 Bit Capture Mode
-
8 Bit Compare Output Mode
-
16 Bit Timer/Counter Mode
-
16 Bit Capture Mode
-
16 Bit Compare Output Mode
-
PWM Mode
The timer/counter can be clocked by an internal or external clock source (external EC0). The clock
source is selected by clock select logic which is controlled by the clock select (T0CK[2:0], T1CK[1:0]).
- TIMER0 clock source : fX/2, 4, 16, 64, 256, 1024, 4096, EC0
- TIMER1 clock source : fX/1, 2, 16, T0CK
In the capture mode, by INT0, INT1, the data is captured into Input Capture Register. The Timer 0
outputs the compare result to T0 port in 8/16-bit mode. Also the timer 1 outputs the result T1 port in
the timer mode and the PWM wave form to PWM1 in the PWM mode.
Table 4.5 Operating Modes of Timer
16 Bit
CAP0
CAP1
PWM1E
T0CK[2:0]
T1CK[1:0]
T0/1_PE
Timer 0
Timer 1
0
0
0
0
XXX
XX
00
8 Bit Timer
8 Bit Timer
0
0
1
0
111
XX
00
8 Bit Event Counter
8 Bit Capture
0
1
0
0
XXX
XX
01
8 Bit Capture
8 Bit Compare Output
0
0
0
1
XXX
XX
11
8 Bit Timer/Counter
10 Bit PWM
1
0
0
0
XXX
11
00
16 Bit Timer
1
0
0
0
111
11
00
16 Bit Event Counter
1
1
1
0
XXX
11
00
16 Bit Capture
1
0
0
0
XXX
11
01
16 Bit Compare Output
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Z51F0410
Product Specification
4.5.1.2 8-Bit Timer/Counter Mode
The 8-bit Timer/Counter Mode is selected by control registers as shown in Figure 4.6.
T0CR
T1CR
T0EN
T0PE
CAP0
T0CK2
T0CK1
T0CK0
T0CN
T0ST
1
X
0
X
X
X
X
X
POL
16BIT
PWM1E
CAP1
T1CK1
T1CK0
T1CN
T1ST
X
0
0
0
X
X
X
X
EC0
T0CN
÷2
fx
P
r
e
s
c
a
l
e
r
ADDRESS
:
B2H
INITIAL VALUE : 0000_0000B
ADDRESS
:
B4H
INITIAL VALUE : 0000_0000B
T0ST
8-bit Timer0 Counter
÷4
÷16
Clear
MUX
T0(8Bit)
÷64
÷256
[B3H]
÷1024
T0IF
÷4096
[B3H]
Timer0
Interrupt
Comparator
3
T0DR(8Bit)
T0CK[2:0]
F/F
P04/T0
8-bit Timer0 Data Register
T1CN
T1ST
8-bit Timer1 Counter
÷1
÷2
Clear
MUX
T1(8Bit)
÷16
[B6H]
T1IF
2
T1CK[1:0]
[B5H]
Timer1
Interrupt
Comparator
T1DR(8Bit)
F/F
P05/T1
8-bit Timer1 Data Register
Figure 4.6 8 Bit Timer/Event Counter0, 1 Block Diagram
The two 8-bit timers have each counter and data register. The counter register is increased by
internal or external clock input. The timer 0 can use the input clock with 2, 4, 16, 64, 256, 1024, 4096
prescaler division rates (T0CK[2:0]). The timer 1 can use the input clock with 1, 2, 16 and timer 0
overflow clock (T1CK[1:0]). When the value of T0, 1 value and the value of T0DR, T1DR are
respectively identical in Timer 0, 1, the interrupt of timer 0, 1 occurs. The external clock (EC0) counts
up the timer at the rising edge. If EC0 is selected from T0CK[2:0], EC0 port becomes input port. The
timer 1 can’t use the external EC0 clock.
PS029502-0212
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Z51F0410
Product Specification
Match with T0DR/T1DR
n
T0DR/T1DR
Value
n-1
n-2
Count Pulse Period
PCP
6
Up-count
5
4
3
2
1
0
TIME
Interrupt Period
= PCP x (n+1)
Timer 0, 1
(T0IF, T1IF)
Interrupt
Interrupt
Occurs
Interrupt
Occurs
Interrupt
Occurs
Figure 4.7 Timer/Event Counter0, 1 Example
T0DR/T1DR
Value
Disable
Enable
Clear&Start
STOP
Up-count
TIME
Timer 0, 1
(T0IF, T1IF)
Interrupt
T0ST, T1ST
Start&Stop
Interrupt
Occurs
Interrupt
Occurs
T0ST,T1ST = 1
T0ST,T1ST = 1
T0ST,T1ST = 0
T0CN, T1CN
Control
count
T0CN,T1CN = 1
T0CN,T1CN = 1
T0CN,T1CN = 0
Figure 4.8 Operation Example of Timer/Event Counter0, 1
4.5.1.3 16-Bit Timer/Counter Mode
The timer register is being run with all 16bits. A 16-bit timer/counter register T0, T1 are incremented
from 0000H to FFFFH until it matches T0DR, T1DR and then resets to 0000H. The match output
generates the Timer 0 interrupt ( no timer 1 interrupt). The clock source is selected from T0CK[2:0]
and T1CK[1:0] must set 11b and 16BIT bit must set to ‘1’. The timer 0 is LSB 8-bit, the timer 1 is MSB
8-bit. The 16-bit mode setting is shown as Figure 4.9.
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Z51F0410
Product Specification
T0CR
T1CR
T0EN
T0PE
CAP0
T0CK2
T0CK1
T0CK0
T0CN
T0ST
1
X
0
X
X
X
X
X
POL
16BIT
PWM1E
CAP1
T1CK1
T1CK0
T1CN
T1ST
X
1
0
0
1
1
X
X
EC0
T0CN
÷2
fx
P
r
e
s
c
a
l
e
r
ADDRESS
:
B2H
INITIAL VALUE : 0000_0000B
ADDRESS
:
B4H
INITIAL VALUE : 0000_0000B
T0ST
16-bit Counter
÷4
÷16
T0
(8Bit)
MUX
÷64
÷256
[B3H]
T1
(8Bit)
Clear
[B6H]
÷1024
T0IF
÷4096
[B3H]
3
T0CK[2:0]
T0DR
(8Bit)
Timer0
Interrupt
Comparator
T1DR
(8Bit)
[B5H]
F/F
P04/T0
PIN
16-bit Data Register
Figure 4.9 16 Bit Timer/Event Counter0, 1 Block Diagram
Note: Do not set T0DR to 0x00 in 16-bit mode. If T0DR is set to 0x00, Timer interrupt or count
match occur after T1DR+0x01. If you set T0DR to be 0x00, T1DR must have one fewer number of
count than the number of count which you want.
Example: If T1DR=0x01 and T0DR=0x00, counter match occurs when T1=0x02 and T0=0x00.
4.5.1.4 8-Bit Capture Mode
The timer 0, 1 capture mode is set by CAP0, CAP1 as ‘1’. The clock source can use the
internal/external clock. Basically, it has the same function of the 8-bit timer/counter mode and the
interrupt occurs at T0, T1 and T0DR, T1DR matching time, respectively. The capture result is loaded
into CDR0, CDR1. The T0, T1 value is automatically cleared by hardware and restarts counter.
This timer interrupt in capture mode is very useful when the pulse width of captured signal is wider
than the maximum period of timer.
As the EIEDGE and EIPOLA register setting, the external interrupt INT0, INT1 function is chosen.
The CDR0, T0 and T0DR are in same address. In the capture mode, reading operation is read the
CDR0, not T0DR because path is opened to the CDR0. The CDR1 has the same function.
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T0CR
T1CR
T0EN
T0PE
CAP0
T0CK2
T0CK1
T0CK0
T0CN
T0ST
1
X
1
X
X
X
X
X
POL
16BIT
PWM1E
CAP1
T1CK1
T1CK0
T1CN
T1ST
X
0
0
1
X
X
X
X
EC0
T0CN
fx
ADDRESS
:
B4H
INITIAL VALUE : 0000_0000B
T0ST
÷2
P
r
e
s
c
a
l
e
r
ADDRESS
:
B2H
INITIAL VALUE : 0000_0000B
8-bit Timer0 Counter
÷4
Clear
÷16
MUX
T0(8Bit)
÷64
÷256
Timer0
Interrupt
[B3H]
Clear
÷1024
T0IF
÷4096
[B3H]
3
[B3H] Comparator
CDR0
(8Bit)
T0CK[2:0]
T0DR
(8Bit)
EIEDGE.0
8-bit Timer0 Data Register
INT0
INT0
Interrupt
INT0IF
T1CN
T1ST
8-bit Timer1 Counter
÷1
÷2
Clear
T1(8Bit)
MUX
÷16
Timer1
Interrupt
[B6H]
Clear
T1IF
2
T1CK[1:0]
[B6H]
CDR1
(8Bit)
[B5H] Comparator
T1DR
(8Bit)
EIEDGE.1
8-bit Timer1 Data Register
INT1IF
INT1
INT1
Interrupt
Figure 4.10 8-bit Capture Mode for Timer0, 1
PS029502-0212
PRELIMINARY
84
Z51F0410
Product Specification
CDR0, CDR1 Load
n
T0/T1 Value
n-1
n-2
Count Pulse Period
PCP
6
Up-count
5
4
3
2
1
0
TIME
Ext. INT0,1 PIN
Interrupt
Request
(INT0F,INT1F)
Interrupt Interval Period
Figure 4.11 Input Capture Mode Operation of Timer 0, 1
FFH
FFH
XXH
T0, T1
YYH
00H
00H
00H
00H
00H
Interrupt
Request
(T0IF,T1IF)
Ext. INT0,1 PIN
Interrupt
Request
(INT0F,INT1F)
Interrupt Interval Period = FFH+01H+FFH+01H+YYH +01H
Figure 4.12 Express Timer Overflow in Capture Mode
4.5.1.5 16-Bit Capture Mode
The 16-bit capture mode is the same operation as 8-bit capture mode, except that the timer register
uses 16 bits.
The clock source is selected from T0CK[2:0] and T1CK[1:0] must set 11b and 16BIT0 bit must set to
‘1’. The 16-bit mode setting is shown as Figure 4.13.
PS029502-0212
PRELIMINARY
85
Z51F0410
Product Specification
T0CR
T1CR
T0EN
T0PE
CAP0
T0CK2
T0CK1
T0CK0
T0CN
T0ST
1
X
1
X
X
X
X
X
POL
16BIT
PWM1E
CAP1
T1CK1
T1CK0
T1CN
T1ST
X
1
0
1
1
1
X
X
EC0
T0CN
fx
ADDRESS
:
CAH
INITIAL VALUE : 0000_0000B
T0ST
÷2
P
r
e
s
c
a
l
e
r
ADDRESS
:
C6H
INITIAL VALUE : 0000_0000B
16-bit Counter
[B6H:B3H]
÷4
÷16
MUX
T1(8Bit) MSB
T0(8Bit) LSB
Clear
÷64
÷256
Timer0
Interrupt
Clear
÷1024
T0IF
÷4096
Comparator
3
T1DR(8Bit)
+T0DR(8Bit)
CDR1(8Bit)
+CDR0(8BIT)
T0CK[2:0]
EIEDGE.0
[B6H:B3H]
16-bit Data Register
INT0
[B5H:B3H]
INT0IF
INT0
Interrupt
Figure 4.13 16-bit Capture Mode of Timer 0, 1
4.5.1.6 PWM Mode
The timer 1 has a PWM (Pulse Width Modulation) function. In PWM mode, the T1/PWM1 output pin
outputs up to 10-bit resolution PWM output. This pin should be configured as a PWM output by set
T1_PE to ‘1’. The period of the PWM output is determined by the T1PPR (PWM period register) +
T1PWHR[3:2] + T1PWHR[1:0]
PWM Period = [ T1PWHR[3:2]T1PPR ] X Source Clock
PWM Duty = [ T1PWHR[1:0] T1PDR ] X Source Clock
Table 4.6 PWM Frequency vs. Resolution at 8 Mhz
Resolution
Frequency
T1CK[1:0]=00 (125ns)
T1CK[1:0]=01 (250ns)
T1CK[1:0]=10 (2us)
10 Bit
7.8KHz
3.9KHz
0.49KHz
9 Bit
15.6KHz
7.8KHz
0.98KHz
8 Bit
31.2KHz
15.6KHz
1.95KHz
7 Bit
62.4KHz
31.2KHz
3.91KHz
The POL bit of T1CR register decides the polarity of duty cycle. If the duty value is set same to the
period value, the PWM output is determined by the bit POL (1: High, 0: Low). And if the duty value is
set to "00H", the PWM output is determined by the bit POL (1: Low, 0: High).
PS029502-0212
PRELIMINARY
86
Z51F0410
Product Specification
T1CR
T1PWHR
POL
16BIT
PWM1E
CAP1
T1CK1
T1CK0
T1CN
T1ST
X
0
1
0
X
X
X
X
T1_PE
-
-
-
1
-
-
-
ADDRESS
:
B4H
INITIAL VALUE : 0000_0000B
ADDRESS
:
B7H
INITIAL VALUE : 0---_0000B
PW1H3 PW1H2 PW1H1 PW1H0
X
X
X
Period High
X
Duty High
8-bit Timer3 PWM Period Register
T1PPR
(8 Bit)
T1PHR[1:0]
T1_PE
[B7H]
T1ST
fx
P
r
e
s
c
a
l
e
r
S
T1CN
÷1
PWM1
Comparator
÷2
÷16
Q
MUX
2 Bit
R
Clear
T1
(8 Bit)
POL
[B6H]
8-bit Timer3
Counter + 2-bit
2
T1CK[1:0]
Comparator
T0 Clock
Source
T1PDR
(8 Bit)
Slave
[B6H]
T1PHR[7:6]
T1PDR
(8 Bit)
Master
[B6H]
Figure 4.14 PWM Mode
Source Clock
(fX)
T1
00
01
02
03
04
7F
80
81
82
3FF
00
01
02
T1/PWM1
POL = 1
T1/PWM1
POL = 0
Duty Cycle(1+80H)X250ns = 32.25us
Period Cycle(1+3FFH)X250ns = 256us  3.9kHz
PW1H3
T1CR[1:0] = 00H(fXIN)
T1PWHR
=
03H
T1PPR = FFH
T1PDR = 80H
PW1H2
T1PPR(8 Bit)
1
1
FFH
PW1H1
PW1H0
T1PDR(8 Bit)
0
0
80H
Figure 4.15 Example of PWM at 4MHz
PS029502-0212
PRELIMINARY
87
Z51F0410
Product Specification
T1CR[1:0] = 10H(2us)
T1PWHR
=
00H
T1PPR = 0EH
T1PDR = 05H
Write 0AH to T1PPR
Source Clock
(fX)
T1
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 00 01 02 03 04 05 06 07 08 09 0A 00 01 02 03 04 05 06
T1/PWM
POL = 1
Duty Cycle
(1+05H)X2us = 12us
Duty Cycle
(1+05H)X2us = 12us
Period Cycle
(1+0EH)X2us = 32us  31.25kHz
Duty Cycle
(1+05H)X2us = 12us
Period Cycle
(1+0AH)X2us = 22us  45.5kHz
Figure 4.16 Example of Changing the Period in Absolute Duty Cycle at 4Mhz
4.5.1.7 8-Bit (16-Bit) Compare Output Mode
If the T1 (T0+T1) value and the T1DR (T0DR+T1DR) value are matched, T1/PWM1 port outputs.
The output is 50:50 of duty square wave, the frequency is following
f
COMP

Oscillator Frequency
2  Prescaler Value  (TDR  1)
To export the compare output as T1/PWM1, the T1_PE bit in the T1PWHR register must set to ‘1’.
4.5.1.8 Register Map
Table 4.7 Timer Register Map
Name
Address
Dir
Default
Description
T0CR
B2H
R/W
00H
Timer 0 Mode Control Register
T0
B3H
R
00H
Timer 0 Register
T0DR
B3H
W
FFH
Timer 0 Data Register
CDR0
B3H
R
00H
Capture 0 Data Register
T1CR
B4H
R/W
00H
Timer 1 Mode Control Register
T1DR
B5H
W
FFH
Timer 1 Data Register
T1PPR
B5H
W
FFH
Timer 1 PWM Period Register
T1
B6H
R
00H
Timer 1 Register
T1PDR
B6H
R/W
00H
Timer 1 PWM Duty Register
CDR1
B6H
R
00H
Capture 1 Data Register
T1PWHR
B7H
W
00H
Timer 1 PWM High Register
PS029502-0212
PRELIMINARY
88
Z51F0410
Product Specification
4.5.1.9 Timer/Counter 0, 1 Register description
The Timer/Counter 0, 1 Register consists of Timer 0 Mode Control Register (T0CR), Timer 0
Register (T0), Timer 0 Data Register (T0DR), Capture 0 Data Register (CDR0), Timer 1 Mode Control
Register (T1CR), Timer 1 Data Register (T1DR), Timer 1 PWM Period Register (T1PPR), Timer 1
Register (T1), Timer 1 PWM Duty Register (T1PPR), Capture 1 Data Register (CDR1) and Timer 1
PWM High Register (T1PWHR).
4.5.1.10 Register description for Timer/Counter 0, 1
T0CR (Timer 0 Mode Control Register) : B2H
7
6
5
4
3
2
1
0
T0EN
T0_PE
CAP0
T0CK2
T0CK1
T0CK0
T0CN
T0ST
R/W
R/W
R/W
R/W
R/W
R/W
R/W
T0EN
T0_PE
CAP0
T0CK[2:0]
T0CN
T0ST
PS029502-0212
R/W
Initial value : 00H
Control Timer 0
0
Timer 0 disable
1
Timer 0 enable
Control Timer 0 Output port
0
Timer 0 Output disable
1
Timer 0 Output enable
Control Timer 0 operation mode
0
Timer/Counter mode
1
Capture mode
Select Timer 0 clock source. Fx is main system clock frequency
T0CK2
T0CK1
T0CK0
Description
0
0
0
fx/2
0
0
1
fx/2^2
0
1
0
fx/2^4
0
1
1
fx/2^6
1
0
0
fx/2^8
1
0
1
fx/2^10
1
1
0
fx/2^12
1
1
1
External Clock (EC0)
Control Timer 0 Count pause/continue
0
Temporary count stop
1
Continue count
Control Timer 0 start/stop
0
Counter stop
1
Clear counter and start
PRELIMINARY
89
Z51F0410
Product Specification
T0 (Timer 0 Register: Read Case) : B3H
7
6
5
4
3
2
1
0
T07
T06
T05
T04
T03
T02
T01
T00
R
R
R
R
R
R
R
T0[7:0]
R
Initial value : 00H
T0 Counter data
T0DR (Timer 0 Data Register: Write Case) : B3H
7
6
5
4
3
2
1
0
T0D7
T0D6
T0D5
T0D4
T0D3
T0D2
T0D1
T0D0
W
W
W
W
W
W
W
W
Initial value : FFH
T0D[7:0]
T0 Compare data
CDR0 (Capture 0 Data Register: Read Case) : B3H
7
6
5
4
3
2
1
0
CDR07
CDR06
CDR05
CDR04
CDR03
CDR02
CDR01
CDR00
R
R
R
R
R
R
R
CDR0[7:0]
R
Initial value : 00H
T0 Capture data
T1CR (Timer 1 Mode Count Register) : B4H
7
6
5
4
3
2
1
0
POL
16BIT
PWM1E
CAP1
T1CK1
T1CK0
T1CN
T1ST
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POL
16BIT
PWM1E
CAP1
T1CK[1:0]
PS029502-0212
R/W
Initial value : 00H
Configure PWM polarity
0
Negative (Duty Match: Clear)
1
Positive (Duty Match: Set)
Select Timer 1 8/16Bit
0
8 Bit
1
16 Bit
Control PWM enable
0
PWM disable
1
PWM enable
Control Timer 1 mode
0
Timer/Counter mode
1
Capture mode
Select clock source of Timer 1. Fx is the frequency of main
system.
T1CK1
T1CK0
description
0
0
fx
0
1
fx/2
1
0
fx/2^4
PRELIMINARY
90
Z51F0410
Product Specification
1
T1CN
1
Use Timer 0 Clock
Control Timer 1 Count pause/continue
T1ST
0
Temporary count stop
1
Continue count
Control Timer 1 start/stop
0
Counter stop
1
Clear counter and start
T1DR (Timer 1 Data Register: Write Case) : B5H
7
6
5
4
3
2
1
0
T1D7
T1D6
T1D5
T1D4
T1D3
T1D2
T1D1
T1D0
W
W
W
W
W
W
W
W
Initial value : FFH
T1D[7:0]
T1 Compare data
T1PPR (Timer 1 PWM Period Register: Write Case) : B5H
7
6
5
4
3
2
1
0
T1PP7
T1PP6
T1PP5
T1PP4
T1PP3
T1PP2
T1PP1
T1PP0
W
W
W
W
W
W
W
W
Initial value : FFH
T1PP[7:0]
T1 PWM Period data
T1 (Timer 1 Register: Read Case) : B6H
7
6
5
4
3
2
1
0
T17
T16
T15
T14
T13
T12
T11
T10
R
R
R
R
R
R
R
T1[7:0]
R
Initial value : 00H
T1 Counter Period data
T1PDR (Timer 1 PWM Duty Register) : B6H
7
6
5
4
3
2
1
0
T1PD7
T1PD6
T1PD5
T1PD4
T1PD3
T1PD2
T1PD1
T1PD0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
T1PD[7:0]
R/W
Initial value : 00H
T1 PWM Duty data
Note) only write, when PWM1E ‘1’
CDR1 (Capture 1 Data Register: Read Case) : B6H
7
6
5
4
3
2
1
0
CDR17
CDR16
CDR15
CDR14
CDR13
CDR12
CDR11
CDR10
R
R
R
R
R
R
R
CDR1[7:0]
PS029502-0212
R
Initial value : 00H
T1 Capture data
PRELIMINARY
91
Z51F0410
Product Specification
T1PWHR (Timer 1 PWM High Register) : B7H
7
6
5
4
3
2
1
0
T1_PE
-
-
-
PW1H3
PW1H2
PW1H1
PW1H0
W
-
-
-
W
W
W
T1_PE
W
Initial value : 00H
Control Timer 1 Output port operation
Note) only writable Bit. Be careful
0
Timer 1 Output disable
1
Timer 1 Output enable
PW1H[3:2]
PWM period High value (Bit [9:8])
PW1H[1:0]
PWM duty High value (Bit [9:8])
PERIOD:
DUTY:
PW1H3
PW1H1
PW1H2
PW1H0
T1PPR[7:0]
T1PDR[7:0]
TFLG (Timer Interrupt Flag Register) : 97H
7
6
5
4
3
2
1
0
-
-
T1IF
T0IF
-
-
-
-
-
-
R/W
R/W
-
-
-
T1IF
Timer1 Interrupt Flag
T0IF
Timer0 Interrupt Flag
Initial value : 00H
4.5.2 16-Bit Timer 4
4.5.2.1 Overview
The 16-bit timer 4 consists of Multiplexer, Timer Data Register High/Low, Timer Register High/Low,
Timer Mode Control Register. It is able to use internal 16-bit timer/ counter without a port output
function.
The 16-bit timer 4 is able to use the divided clock of the main clock selected from prescaler output.
PS029502-0212
PRELIMINARY
92
Z51F0410
Product Specification
4.5.2.2 16 Bit Timer/Counter Mode
T4CR
T4EN
-
-
T4CK2
T4CK1
T4CK0
T4CN
T4ST
1
-
-
X
X
X
X
X
÷2
P
r
e
s
c
a
l
e
r
fx
ADDRESS
:
CEH
INITIAL VALUE : 0--0_0000B
T4ST
T4CN
÷4
16-bit Timer4 Counter
÷8
T4H
(8Bit)
÷16
MUX
÷64
÷256
Clear
T4L
(8Bit)
[CFH]
[CDH]
÷1024
T4IF
÷2048
Timer4
Interrupt
Comparator
T4HDR
(8Bit)
3
T4CK[2:0]
[CDH]
T4LDR
(8Bit)
[CFH]
16-bit Timer4 Data Register
Figure 4.17 Timer4 16-bit Mode Block Diagram
4.5.2.3 Register Map
Table 4-8 Register Map
Name
Address
Dir
Default
Description
T4CR
0xCE
R/W
0H
Timer 4 Mode Control Register
T4L
0xCF
R
0H
Timer 4 Low Register
T4LDR
0xCF
W
FFH
Timer 4 Low Data Register
T4H
0xCD
R
0H
Timer 4 High Register
T4HDR
0xCD
R/W
0H
Timer 4 High Data Register
4.5.2.4 Timer 4 Register description
The timer 4 register consists of Timer 4 Mode Control Register (T4CR), Timer 4 Low Register (T4L),
Timer 4 Low Data Register (T4LDR), Timer 4 High Register (T4H), Timer 4 High Data Register
(T4HDR).
4.5.2.5 Register description for Timer 4
T4CR (Timer 4 Mode Control Register) : CEH
7
6
5
4
3
2
1
0
T4EN
-
-
T4CK2
T4CK1
T4CK0
T4CN
T4ST
PS029502-0212
PRELIMINARY
93
Z51F0410
Product Specification
R/W
-
T4EN
T4CK[2:0]
R/W
T4ST
R/W
R/W
R/W
Initial value : 00H
Control Timer 4 operation
0
Timer 4 disable
1
Timer 4 enable
Select Timer 4 clock source. fx is main system clock frequency
T4CK2
T4CN
R/W
T4CK1
T4CK0
Description
0
0
0
fx/2
0
0
1
fx/4
0
1
0
fx/8
0
1
1
fx/16
1
0
0
fx/64
1
0
1
fx/256
1
1
0
fx/1024
1
1
1
fx/2048
Control Timer 4 Count pause/continue
0
Temporary count stop
1
Continue count
Control Timer 4 start/stop
0
Counter stop
1
Clear Counter and start
T4L (Timer 4 Low Register: Read Case) : CFH
7
6
5
4
3
2
1
0
T4L7
T4L6
T4L5
T4L4
T4L3
T4L2
T4L1
T4L0
R
R
R
R
R
R
R
T4L[7:0]
R
Initial value : 00H
T4L Counter
T4LDR (Timer 4 Low Data Register: Write Case) : CFH
7
6
5
4
3
2
1
0
T4LD7
T4LD6
T4LD5
T4LD4
T4LD3
T4LD2
T4LD1
T4LD0
W
W
W
W
W
W
W
W
Initial value : FFH
T4LD[7:0]
T4L Compare
T4H (Timer 4 High Register: Read Case) : CDH
7
6
5
4
3
2
1
0
T4H7
T4H6
T4H5
T4H4
T4H3
T4H2
T4H1
T4H0
R
R
R
R
R
R
R
2
1
T4H[7:0]
R
Initial value : 00H
T4H Counter Period
T4HDR (Timer 4 High Data Register: Write Case) : CDH
7
PS029502-0212
6
5
4
3
PRELIMINARY
0
94
Z51F0410
Product Specification
T4HD7
T4HD6
T4HD5
T4HD4
T4HD3
T4HD2
T4HD1
T4HD0
W
W
W
W
W
W
W
W
Initial value : FFH
T4HD[7:0]
T4H Compare
TFLG (Timer Interrupt Flag Register) : 97H
7
6
5
4
3
2
1
0
-
T4IF
-
-
-
-
-
-
-
R/W
-
-
-
-
-
T4IF
PS029502-0212
Initial value : 00H
Timer4 Interrupt Flag
PRELIMINARY
95
Z51F0410
Product Specification
4.6 USART
4.6.1 Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly
flexible serial communication device. The main features are listed below.
- Full Duplex Operation (Independent Serial Receive and Transmit Registers)
- Asynchronous or Synchronous Operation
- Master or Slave Clocked Synchronous and SPI Operation
- Supports all four SPI Modes of Operation (Mode 0, 1, 2, 3)
- LSB First or MSB First Data Transfer @SPI mode
- High Resolution Baud Rate Generator
- Supports Serial Frames with 5,6,7,8, or 9 Data Bits and 1 or 2 Stop Bits
- Odd or Even Parity Generation and Parity Check Supported by Hardware
- Data OverRun Detection
- Framing Error Detection
- Digital Low Pass Filter
- Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
- Double Speed Asynchronous Communication Mode
USART has three main parts of Clock Generator, Transmitter and Receiver. The Clock Generation
logic consists of synchronization logic for external clock input used by synchronous or SPI slave
operation, and the baud rate generator for asynchronous or master (synchronous or SPI) operation.
The Transmitter consists of a single write buffer, a serial shift register, parity generator and control
logic for handling different serial frame formats. The write buffer allows a continuous transfer of data
without any delay between frames. The receiver is the most complex part of the USART module due
to its clock and data recovery units. The recovery unit is used for asynchronous data reception. In
addition to the recovery unit, the Receiver includes a parity checker, a shift register, a two level
receive FIFO (UDATAn) and control logic. The Receiver supports the same frame formats as the
Transmitter and can detect Frame Error, Data OverRun and Parity Errors.
PS029502-0212
PRELIMINARY
96
Z51F0410
Product Specification
4.6.2 Block Diagram
UBAUD
SCLK
Baud Rate Generator
Master
Clock Sync
Logic
XCK
Control
XCK
UMSEL[1:0]
RXC
RXD/
MISO
M
U
X
M
U
X
Rx Interrupt
Rx
Control
Clock
Recovery
Data
Recovery
Receive Shift Register
(RXSR)
DOR/PE/FE
Checker
UDATA[0]
(Rx)
M
U
X
UMSEL1&UMSEL0
Master
Stop bit
Generator
D
E
P
TXD/
MOSI
D
E
P
UMSEL0
Transmit Shift Register
(TXSR)
M
U
X
B
u
s
L
i
n
e
Parity
Generator
M
U
X
Tx
Control
UDATA[1]
(Rx)
UPM0
I
n
t
e
r
n
a
l
UPM1
UDATA(Tx)
SS
Control
SS
TXC
Rx Interrupt
UMSEL1 UMSEL0
UPM1
UPM0
UCTRL2
UDRIE
RXCIE
WAKEIE
TXE
RXE
USARTEN
U2X
ADDRESS
:
E3H
INITIAL VALUE : 0000_0000B
UCTRL3
MASTER LOOPS DISXCK
SPISS
-
USBS
TX8
RX8
ADDRESS
:
E4H
INITIAL VALUE : 0000_-000B
UDRE
WAKE
SOFTRST
DOR
FE
PE
ADDRESS
:
E5H
INITIAL VALUE : 1000_0000B
USTAT
TXCIE
TXC
RXC
USIZE2 USIZE1 USIZE0 UCPOL
ADDRESS
:
E2H
INITIAL VALUE : 0000_0000B
UCTRL1
Figure 4.18 USART Block Diagram
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4.6.3 Clock Generation
UBAUD
U2X
fSCLK
Prescaling
Up-Counter
(UBAUD+1)
/8
/2
SCLK
M
U
X
M
U
X
txclk
MASTER
Sync Register
Edge
Detector
M
U
X
UMSEL0
UCPOL
XCK
/2
M
U
X
rxclk
Figure 4.19 Clock Generation Block Diagram
Clock generation 부는 transmitter & receiver 에 사용되는 기준 Clock 을 생성합니다
The Clock generation logic generates the base clock for the Transmitter and Receiver. The USART
supports four modes of clock operation and those are Normal Asynchronous, Double Speed
Asynchronous, Master Synchronous and Slave Synchronous. The clock generation scheme for
Master SPI and Slave SPI mode is the same as Master Synchronous and Slave Synchronous
operation mode. The UMSELn bit in UCTRL1 register selects between asynchronous and
synchronous operation. Asynchronous Double Speed mode is controlled by the U2X bit in the
UCTRL2 register. The MASTER bit in UCTRL2 register controls whether the clock source is internal
(Master mode, output port) or external (Slave mode, input port). The XCK pin is only active when the
USART operates in Synchronous or SPI mode.
Table below contains equations for calculating the baud rate (in bps).
Table 4.9 Equations for Calculating Baud Rate Register Setting
Operating Mode
Equation for Calculating Baud Rate
Asynchronous Normal Mode (U2X=0)
Baud Rate
fSCLK
16 UBAUD
Asynchronous Double Speed Mode (U2X=1)
Baud Rate
fSCLK
8 UBAUD 1
Synchronous or SPI Master Mode
Baud Rate
fSCLK
2 UBAUD 1
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4.6.4 External Clock (XCK)
External clocking is used by the synchronous or spi slave modes of operation.
External clock input from the XCK pin is sampled by a synchronization logic to remove meta-stability.
The output from the synchronization logic must then pass through an edge detector before it can be
used by the Transmitter and Receiver. This process introduces a two CPU clock period delay and
therefore the maximum frequency of the external XCK pin is limited by the following equation.
fXCK
fSCLK
4
where fXCK is the frequency of XCK and fSCLK is the frequency of main system clock (SCLK).
4.6.5 Synchronous mode operation
When synchronous or spi mode is used, the XCK pin will be used as either clock input (slave) or
clock output (master). The dependency between the clock edges and data sampling or data change is
the same. The basic principle is that data input on RXD (MISO in spi mode) pin is sampled at the
opposite XCK clock edge of the edge in the data output on TXD (MOSI in spi mode) pin is changed.
The UCPOL bit in UCTRL1 register selects which XCK clock edge is used for data sampling and
which is used for data change. As shown in the figure below, when UCPOL is zero the data will be
changed at rising XCK edge and sampled at falling XCK edge.
UCPOL = 1
XCK
TXD/RXD
Sample
UCPOL = 0
XCK
TXD/RXD
Sample
Figure 4.20 Synchronous Mode XCKn Timing.
4.6.6 Data format
A serial frame is defined to be one character of data bits with synchronization bits (start and stop
bits), and optionally a parity bit for error checking.
The USART supports all 30 combinations of the following as valid frame formats.
- 1 start bit
- 5, 6, 7, 8 or 9 data bits
- no, even or odd parity bit
- 1 or 2 stop bits
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A frame starts with the start bit followed by the least significant data bit (LSB). Then the next data
bits, up to a total of nine, are succeeding, ending with the most significant bit (MSB). If enabled the
parity bit is inserted after the data bits, before the stop bits. A high to low transition on data pin is
considered as start bit. When a complete frame is transmitted, it can be directly followed by a new
frame, or the communication line can be set to an idle state. The idle means high state of data pin.
The next figure shows the possible combinations of the frame formats. Bits inside brackets are
optional.
1 data frame
Idle
St
D0
D1
D2
D3
D4
[D5]
[D6]
[D7]
[D8]
[P]
Sp1
[Sp2
]
Idle / St
Character
bits
Figure 4.21 frame format
1 data frame consists of the following bits
•
Idle
No communication on communication line (TxD/RxD)
•
St
Start bit (Low)
•
Dn
Data bits (0~8)
•
Parity bit ------------ Even parity, Odd parity, No parity
•
Stop bit(s) ---------- 1 bit or 2 bits
The frame format used by the USART is set by the USIZE[2:0], UPM[1:0] and USBS bits in UCTRL1
register. The Transmitter and Receiver use the same setting.
4.6.7 Priority bit
The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result
of the exclusive-or is inverted. The parity bit is located between the MSB and first stop bit of a serial
frame.
Peven = Dn-1 ^ … ^ D3 ^ D2 ^ D1 ^ D0 ^ 0
Podd = Dn-1 ^ … ^ D3 ^ D2 ^ D1 ^ D0 ^ 1
Peven : Parity bit using even parity
Podd : Parity bit using odd parity
Dn
: Data bit n of the character
4.6.8 USART Transmitter
The USART Transmitter is enabled by setting the TXE bit in UCTRL1 register. When the Transmitter
is enabled, the normal port operation of the TXD pin is overridden by the serial output pin of USART.
The baud-rate, operation mode and frame format must be setup once before doing any transmissions.
If synchronous or spi operation is used, the clock on the XCK pin will be overridden and used as
transmission clock. If USART operates in spi mode, SS pin is used as SS input pin in slave mode or
can be configured as SS output pin in master mode. This can be done by setting SPISS bit in
UCTRL3 register.
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Note: In Tx mode, the length of start bit can be shorter than one or two clock of the lengh of the other
data bits.
4.6.8.1 Sending Tx data
A data transmission is initiated by loading the transmit buffer (UDATA register I/O location) with the
data to be transmitted. The data written in transmit buffer is moved to the shift register when the shift
register is ready to send a new frame. The shift register is loaded with the new data if it is in idle state
or immediately after the last stop bit of the previous frame is transmitted. When the shift register is
loaded with new data, it will transfer one complete frame at the settings of control registers. If the 9-bit
characters are used in asynchronous or synchronous operation mode (USIZE[2:0]=7), the ninth bit
must be written to the TX8 bit in UCTRL3 register before loading transmit buffer (UDATA register).
4.6.8.2 Transmitter flag and interrupt
The USART Transmitter has 2 flags which indicate its state. One is USART Data Register Empty
(UDRE) and the other is Transmit Complete (TXC). Both flags can be interrupt sources.
UDRE flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the
transmit buffer is empty and cleared when the transmit buffer contains data to be transmitted that has
not yet been moved into the shift register. And also this flag can be cleared by writing ‘0’ to this bit
position. Writing ‘1’ to this bit position is prevented.
When the Data Register Empty Interrupt Enable (UDRIE) bit in UCTRL2 register is set and the
Global Interrupt is enabled, USART Data Register Empty Interrupt is generated while UDRE flag is
set.
The Transmit Complete (TXC) flag bit is set when the entire frame in the transmit shift register has
been shifted out and there are no more data in the transmit buffer. The TXC flag is automatically
cleared when the Transmit Complete Interrupt service routine is executed, or it can be cleared by
writing ‘0’ to TXC bit in UCTRL2 register.
When the Transmit Complete Interrupt Enable (TXCIE) bit in UCTRL2 register is set and the Global
Interrupt is enabled, USART Transmit Complete Interrupt is generated while TXC flag is set.
4.6.8.3 Parity Generator
The Parity Generator calculates the parity bit for the sending serial frame data. When parity bit is
enabled (UPM[1]=1), the transmitter control logic inserts the parity bit between the MSB and the first
stop bit of the sending frame.
4.6.8.4 Disabling Transmitter
Disabling the Transmitter by clearing the TXE bit will not become effective until ongoing transmission
is completed. When the Transmitter is disabled, the TXD pin is used as normal General Purpose I/O
(GPIO) or primary function pin.
4.6.9 USART Receiver
The USART Receiver is enabled by setting the RXE bit in the UCTRL1 register. When the Receiver
is enabled, the normal pin operation of the RXD pin is overridden by the USART as the serial input pin
of the Receiver. The baud-rate, mode of operation and frame format must be set before serial
reception. If synchronous or spi operation is used, the clock on the XCK pin will be used as transfer
clock. If USART operates in spi mode, SS pin is used as SS input pin in slave mode or can be
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configured as SS output pin in master mode. This can be done by setting SPISS bit in UCTRL3
register.
4.6.9.1 Receiving Rx data
When USART is in synchronous or asynchronous operation mode, the Receiver starts data
reception when it detects a valid start bit (LOW) on RXD pin. Each bit after start bit is sampled at predefined baud-rate (asynchronous) or sampling edge of XCK (synchronous), and shifted into the
receive shift register until the first stop bit of a frame is received. Even if there’s 2nd stop bit in the
frame, the 2nd stop bit is ignored by the Receiver. That is, receiving the first stop bit means that a
complete serial frame is present in the receiver shift register and contents of the shift register are to
be moved into the receive buffer. The receive buffer is read by reading the UDATA register.
If 9-bit characters are used (USIZE[2:0] = 7) the ninth bit is stored in the RX8 bit position in the
UCTRL3 register. The 9th bit must be read from the RX8 bit before reading the low 8 bits from the
UDATA register. Likewise, the error flags FE, DOR, PE must be read before reading the data from
UDATA register. This is because the error flags are stored in the same FIFO position of the receive
buffer.
4.6.9.2 Receiver flag and interrupt
The USART Receiver has one flag that indicates the Receiver state.
The Receive Complete (RXC) flag indicates whether there are unread data present in the receive
buffer. This flag is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty. If the Receiver is disabled (RXE=0), the receiver buffer is flushed and the RXC flag is
cleared.
When the Receive Complete Interrupt Enable (RXCIE) bit in the UCTRL2 register is set and Global
Interrupt is enabled, the USART Receiver Complete Interrupt is generated while RXC flag is set.
The USART Receiver has three error flags which are Frame Error (FE), Data OverRun (DOR) and
Parity Error (PE). These error flags can be read from the USTAT register. As data received are stored
in the 2-level receive buffer, these error flags are also stored in the same position of receive buffer.
So, before reading received data from UDATA register, read the USTAT register first which contains
error flags.
The Frame Error (FE) flag indicates the state of the first stop bit. The FE flag is zero when the stop
bit was correctly detected as one, and the FE flag is one when the stop bit was incorrect, ie detected
as zero. This flag can be used for detecting out-of-sync conditions between data frames.
The Data OverRun (DOR) flag indicates data loss due to a receive buffer full condition. A DOR
occurs when the receive buffer is full, and another new data is present in the receive shift register
which are to be stored into the receive buffer. After the DOR flag is set, all the incoming data are lost.
To prevent data loss or clear this flag, read the receive buffer.
The Parity Error (PE) flag indicates that the frame in the receive buffer had a Parity Error when
received. If Parity Check function is not enabled (UPM[1]=0), the PE bit is always read zero.
Note) The error flags related to receive operation are not used when USART is in spi mode.
4.6.9.3 Parity Checker
If Parity Bit is enabled (UPM[1]=1), the Parity Checker calculates the parity of the data bits in
incoming frame and compares the result with the parity bit from the received serial frame.
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4.6.9.4 Disabling Receiver
In contrast to Transmitter, disabling the Receiver by clearing RXE bit makes the Receiver inactive
immediately. When the Receiver is disabled the Receiver flushes the receive buffer and the remaining
data in the buffer is all reset. The RXD pin is not overridden the function of USART, so RXD pin
becomes normal GPIO or primary function pin.
4.6.9.5 Asynchronous Data Reception
To receive asynchronous data frame, the USART includes a clock and data recovery unit. The Clock
Recovery logic is used for synchronizing the internally generated baud-rate clock to the incoming
asynchronous serial frame on the RXD pin.
The Data recovery logic samples and low pass filters the incoming bits, and this removes the noise
of RXD pin.
The next figure illustrates the sampling process of the start bit of an incoming frame. The sampling
rate is 16 times the baud-rate for normal mode, and 8 times the baud rate for Double Speed mode
(U2X=1). The horizontal arrows show the synchronization variation due to the asynchronous sampling
process. Note that larger time variation is shown when using the Double Speed mode.
START
RxD
IDLE
BIT0
Sample
(U2X = 0)
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
Sample
(U2X = 1)
0
1
2
3
4
5
6
7
8
1
2
Figure 4.22
Start Bit
Sampling
When the Receiver is enabled (RXE=1),
the clock
recovery
logic tries to find a high to low transition
on the RXD line, the start bit condition. After detecting high to low transition on RXD line, the clock
recovery logic uses samples 8,9, and 10 for Normal mode, and samples 4, 5, and 6 for Double Speed
mode to decide if a valid start bit is received. If more than 2 samples have logical low level, it is
considered that a valid start bit is detected and the internally generated clock is synchronized to the
incoming data frame. And the data recovery can begin. The synchronization process is repeated for
each start bit.
As described above, when the Receiver clock is synchronized to the start bit, the data recovery can
begin. Data recovery process is almost similar to the clock recovery process. The data recovery logic
samples 16 times for each incoming bits for Normal mode and 8 times for Double Speed mode. And
uses sample 8, 9, and 10 to decide data value for Normal mode, samples 4, 5, and 6 for Double
Speed mode. If more than 2 samples have low levels, the received bit is considered to a logic 0 and
more than 2 samples have high levels, the received bit is considered to a logic 1. The data recovery
process is then repeated until a complete frame is received including the first stop bit. The decided bit
value is stored in the receive shift register in order. Note that the Receiver only uses the first stop bit
of a frame. Internally, after receiving the first stop bit, the Receiver is in idle state and waiting to find
start bit.
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BIT n
RxD
Sample
(U2X = 0)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
Sample
(U2X = 1)
1
2
4
3
5
6
7
8
1
Figurebit4.23
Data
and recovery
Parity Bit process. That is, if 2 or more
The process for detecting stop
is Sampling
like clock ofand
data
samples of 3 center values have high level, correct stop bit is detected, else a Frame Error flag is set.
After deciding first stop bit whether a valid stop bit is received or not, the Receiver goes idle state and
monitors the RXD line to check a valid high to low transition is detected (start bit detection).
STOP 1
RxD
(A)
(B)
(C)
Sample
(U2X = 0)
1
2
3
4
5
6
7
8
9
10
11
12
13
Sample
(U2X = 1)
1
2
3
4
5
6
7
Figure 4.24 Stop Bit Sampling and Next Start Bit Sampling
4.6.10 SPI Mode
The USART can be set to operate in industrial standard SPI compliant mode. The SPI mode has the
following features.
-
Full duplex, three-wire synchronous data transfer
-
Master or Slave operation
-
Supports all four SPI modes of operation (mode0, 1, 2, and 3)
-
Selectable LSB first or MSB first data transfer
-
Double buffered transmit and receive
-
Programmable transmit bit rate
When SPI mode is enabled (UMSEL[1:0]=3), the Slave Select (SS) pin becomes active low input in
slave mode operation, or can be output in master mode operation if SPISS bit is set.
Note that during SPI mode of operation, the pin RXD is renamed as MISO and TXD is renamed as
MOSI for compatibility to other SPI devices.
4.6.10.1 SPI Clock formats and timing
To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the
USART has a clock polarity bit (UCPOL) and a clock phase control bit (UCPHA) to select one of four
clock formats for data transfers. UCPOL selectively insert an inverter in series with the clock. UCPHA
chooses between two different clock phase relationships between the clock and data. Note that
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UCPHA and UCPOL bits in UCTRL1 register have different meanings according to the UMSEL[1:0]
bits which decides the operating mode of USART.
Table below shows four combinations of UCPOL and UCPHA for SPI mode 0, 1, 2, and 3.
Table 4.10 CPOL Functionality
SPI Mode
UCPOL
UCPHA
Leading Edge
Trailing Edge
0
0
0
Sample (Rising)
Setup (Falling)
1
0
1
Setup (Rising)
Sample (Falling)
2
1
0
Sample (Falling)
Setup (Rising)
3
1
1
Setup (Falling)
Sample (Rising)
XCK
(UCPOL=0)
XCK
(UCPOL=1)
SAMPLE
MOSI
MSB First
LSB First
BIT7
BIT0
BIT6
BIT1
…
…
BIT2
BIT5
BIT1
BIT6
BIT0
BIT7
MISO
/SS OUT
(MASTER)
/SS IN
(SLAVE)
SPI Clock
Formats
when
When UCPHA=0, the slaveFigure
begins4.25
to drive
its MISO
output
withUCPHA=0
the first data bit value when SS goes
to active low. The first XCK edge causes both the master and the slave to sample the data bit value
on their MISO and MOSI inputs, respectively. At the second XCK edge, the USART shifts the second
data bit value out to the MOSI and MISO outputs of the master and slave, respectively. Unlike the
case of UCPHA=1, when UCPHA=0, the slave’s SS input must go to its inactive high level between
transfers. This is because the slave can prepare the first data bit when it detects falling edge of SS
input.
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XCK
(UCPOL=0)
XCK
(UCPOL=1)
SAMPLE
MOSI
MSB First
LSB First
BIT7
BIT0
BIT6
BIT1
…
…
BIT2
BIT5
BIT1
BIT6
BIT0
BIT7
MISO
/SS OUT
(MASTER)
/SS IN
(SLAVE)
Figure 4.26 SPI Clock Formats when UCPHA=1
When UCPHA=1, the slave begins to drive its MISO output when SS goes active low, but the data
is not defined until the first XCK edge. The first XCK edge shifts the first bit of data from the shifter
onto the MOSI output of the master and the MISO output of the slave. The next XCK edge causes
both the master and slave to sample the data bit value on their MISO and MOSI inputs, respectively.
At the third XCK edge, the USART shifts the second data bit value out to the MOSI and MISO output
of the master and slave respectively. When UCPHA=1, the slave’s SS input is not required to go to its
inactive high level between transfers.
Because the SPI logic reuses the USART resources, SPI mode of operation is similar to that of
synchronous or asynchronous operation. An SPI transfer is initiated by checking for the USART Data
Register Empty flag (UDRE=1) and then writing a byte of data to the UDATA Register. In master
mode of operation, even if transmission is not enabled (TXE=0), writing data to the UDATA register is
necessary because the clock XCK is generated from transmitter block.
4.6.11 Register Map
Table 4.11 USART Register Map
Name
Address
Dir
Default
Description
UCTRL1
E2H
R/W
00H
USART Control 1 Register
UCTRL2
E3H
R/W
00H
USART Control 2 Register
UCTRL3
E4H
R/W
00H
USART Control 3 Register
USTAT
E5H
R
80H
USART Status Register
UBAUD
E6H
R/W
FFH
USART Baud Rate Generation Register
UDATA
E7H
R/W
FFH
USART Data Register
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4.6.12 USART Register description
USART module consists of USART Control 1 Register (UCTRL1), USART Control 2 Register
(UCTRL2), USART Control 3 Register (UCTRL3), USART Status Register (USTAT), USART Data
Register (UDATA), and USART Baud Rate Generation Register (UBAUD).
4.6.13 Register description for USART
UCTRL1 (USART Control 1 Register) : E2H
7
6
5
4
3
2
1
0
UMSEL1
UMSEL0
UPM1
UPM0
USIZE2
USIZE1
UDORD
USIZE0
UCPHA
UCPOL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
UMSEL[1:0]
Selects operation mode of USART.
UMSEL1
UMSEL0
Operation Mode
0
0
Asynchronous Mode (Uart)
0
1
Synchronous Mode
1
0
Reserved
1
1
SPI Mode
UPM[1:0]
USIZE[2:0]
UDORD
UCPOL
UCPHA
PS029502-0212
R/W
Initial value : 00H
Selects Parity Generation and Check methods
UPM1
UPM0
0
0
Parity
No Parity
0
1
Reserved
1
0
Even Parity
1
1
Odd Parity
When in asynchronous or synchronous mode of operation, selects the
length of data bits in frame.
USIZE2
USIZE1
USIZE0
Data Length
0
0
0
5 bit
0
0
1
6 bit
0
1
0
7 bit
0
1
1
8 bit
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
9 bit
This bit is in the same bit position with USIZE1. In SPI mode, when set to
one the MSB of the data byte is transmitted first. When set to zero the
LSB of the data byte is transmitted first.
0
LSB First
1
MSB First
Selects polarity of XCK in synchronous or spi mode
0
TXD change @Rising Edge, RXD change @Falling Edge
1
TXD change @ Falling Edge, RXD change @ Rising Edge
This bit is in the same bit position with USIZE0. In SPI mode, along
with UCPOL bit, selects one of two clock formats for different kinds
of synchronous serial peripherals. Leading edge means first XCK
edge and trailing edge means 2nd or last clock edge of XCK in one
XCK pulse. And Sample means detecting of incoming receive bit,
Setup means preparing transmit data.
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UCPOL
UCPHA
Leading Edge
Trailing Edge
0
0
Sample (Rising)
Setup (Falling)
0
1
Setup (Rising)
Sample (Falling)
1
0
Sample (Falling)
Setup (Rising)
1
1
Setup (Falling)
Sample (Rising)
UCTRL2 (USART Control 2 Register) : E3H
7
6
5
4
3
2
1
0
UDRIE
TXCIE
RXCIE
WAKEIE
TXE
RXE
USARTEN
U2X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
UDRIE
TXCIE
RXCIE
WAKEIE
TXE
R/W
Initial value : 00H
Interrupt enable bit for USART Data Register Empty.
0
Interrupt from UDRE is inhibited (use polling)
1
When UDRE is set, request an interrupt
Interrupt enable bit for Transmit Complete.
0
Interrupt from TXC is inhibited (use polling)
1
When TXC is set, request an interrupt
Interrupt enable bit for Receive Complete
0
Interrupt from RXC is inhibited (use polling)
1
When RXC is set, request an interrupt
Interrupt enable bit for Asynchronous Wake in STOP mode. When device
is in stop mode, if RXD goes to LOW level an interrupt can be requested
to wake-up system.
0
Interrupt from Wake is inhibited
1
When WAKE is set, request an interrupt
Enables the transmitter unit.
RXE
0
Transmitter is disabled
1
Transmitter is enabled
Enables the receiver unit.
USARTEN
0
Receiver is disabled
1
Receiver is enabled
Activate USART module by supplying clock.
0
USART is disabled (clock is halted)
1
USART is enabled
This bit only has effect for the asynchronous operation and selects
receiver sampling rate.
U2X
0
Normal asynchronous operation
1
Double Speed asynchronous operation
UCTRL3 (USART Control 3 Register) : E4H
7
6
5
4
3
2
MASTER
LOOPS
DISXCK
SPISS
-
R/W
R/W
R/W
R/W
-
MASTER
PS029502-0212
1
0
USBS
TX8
RX8
R/W
R/W
R/W
Initial value : 00H
Selects master or slave in SPI or Synchronous mode operation and
controls the direction of XCK pin.
0
Slave mode operation and XCK is input pin.
1
Master mode operation and XCK is output pin
PRELIMINARY
108
Z51F0410
Product Specification
LOOPS
DISXCK
SPISS
USBS
Controls the Loop Back mode of USART, for test mode
0
Normal operation
1
Loop Back mode
In Synchronous mode of operation, selects the waveform of XCK output.
0
XCK is free-running while USART is enabled in synchronous
master mode.
1
XCK is active while any frame is on transferring.
Controls the functionality of SS pin in master SPI mode.
0
SS pin is normal GPIO or other primary function
1
SS output to other slave device
Selects the length of stop bit in Asynchronous or Synchronous mode of
operation.
0
1 Stop Bit
1
2 Stop Bit
The ninth bit of data frame in Asynchronous or Synchronous mode of
operation. Write this bit first before loading the UDATA register.
TX8
0
MSB (9th bit) to be transmitted is ‘0’
1
MSB (9 bit) to be transmitted is ‘1’
th
The ninth bit of data frame in Asynchronous or Synchronous mode of
operation. Read this bit first before reading the receive buffer.
RX8
0
MSB (9th bit) received is ‘0’
1
MSB (9th bit) received is ‘1’
USTAT (USART Status Register) : E5H
7
6
5
4
3
2
1
0
UDRE
TXC
RXC
WAKE
SOFTRST
DOR
FE
PE
R/W
R/W
R/W
R/W
R/W
R
R
UDRE
TXC
RXC
WAKE
SOFTRST
PS029502-0212
R
Initial value : 80H
The UDRE flag indicates if the transmit buffer (UDATA) is ready to
receive new data. If UDRE is ‘1’, the buffer is empty and ready to be
written. This flag can generate a UDRE interrupt.
0
Transmit buffer is not empty.
1
Transmit buffer is empty.
This flag is set when the entire frame in the transmit shift register has
been shifted out and there is no new data currently present in the
transmit buffer. This flag is automatically cleared when the interrupt
service routine of a TXC interrupt is executed. This flag can generate a
TXC interrupt.
0
Transmission is ongoing.
1
Transmit buffer is empty and the data in transmit shift register
are shifted out completely.
This flag is set when there are unread data in the receive buffer and
cleared when all the data in the receive buffer are read. The RXC flag
can be used to generate a RXC interrupt.
0
There is no data unread in the receive buffer
1
There are more than 1 data in the receive buffer
This flag is set when the RX pin is detected low while the CPU is in stop
mode. This flag can be used to generate a WAKE interrupt. This bit is set
only when in asynchronous mode of operation.
0
No WAKE interrupt is generated.
1
WAKE interrupt is generated
This is an internal reset and only has effect on USART. Writing ‘1’ to this
PRELIMINARY
109
Z51F0410
Product Specification
bit initializes the internal logic of USART and is auto cleared.
0
No operation
1
Reset USART
This bit is set if a Data OverRun occurs. While this bit is set, the incoming
data frame is ignored. This flag is valid until the receive buffer is read.
DOR
0
No Data OverRun
1
Data OverRun detected
This bit is set if the first stop bit of next character in the receive buffer is
detected as ‘0’. This bit is valid until the receive buffer is read.
FE
0
No Frame Error
1
Frame Error detected
This bit is set if the next character in the receive buffer has a Parity Error
when received while Parity Checking is enabled. This bit is valid until the
receive buffer is read.
PE
0
No Parity Error
1
Parity Error detected
UBAUD (USART Baud-Rate Generation Register) : E6H
7
6
5
4
3
2
1
0
UBAUD7
UBAUD 6
UBAUD 5
UBAUD 4
UBAUD 3
UBAUD 2
UBAUD 1
UBAUD 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : FFH
UBAUD [7:0]
The value in this register is used to generate internal baud rate in
asynchronous mode or to generate XCK clock in synchronous or spi
mode. To prevent malfunction, do not write ‘0’ in asynchronous
mode, and do not write ‘0’ or ‘1’ in synchronous or spi mode.
UDATA (USART Data Register) : E7H
7
6
5
4
3
2
1
0
UDATA7
UDATA6
UDATA 5
UDATA 4
UDATA 3
UDATA 2
UDATA 1
UDATA 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : FFH
UDATA [7:0]
The USART Transmit Buffer and Receive Buffer share the same I/O
address with this DATA register. The Transmit Data Buffer is the
destination for data written to the UDATA register. Reading the
UDATA register returns the contents of the Receive Buffer.
Write this register only when the UDRE flag is set. In spi or
synchronous master mode, write this register even if TX is not
enabled to generate clock, XCK.
4.6.14 Baud Rate setting (example)
Table 4.12 Examples of UBAUD Settings for Commonly Used Oscillator Frequencies
fOSC=1.00MHz
Baud
Rate
U2X=0
fOSC=1.8432MHz
U2X=1
U2X=0
fOSC=2.00MHz
U2X=1
U2X=0
U2X=1
UBAUD
ERROR
UBAUD
ERROR
UBAUD
ERROR
UBAUD
ERROR
UBAUD
ERROR
UBAUD
ERROR
2400
25
0.2%
51
0.2%
47
0.0%
95
0.0%
51
0.2%
103
0.2%
4800
12
0.2%
25
0.2%
23
0.0%
47
0.0%
25
0.2%
51
0.2%
9600
6
-7.0%
12
0.2%
11
0.0%
23
0.0%
12
0.2%
25
0.2%
14.4K
3
8.5%
8
-3.5%
7
0.0%
15
0.0%
8
-3.5%
16
2.1%
PS029502-0212
PRELIMINARY
110
Z51F0410
Product Specification
19.2K
2
8.5%
6
-7.0%
5
0.0%
11
0.0%
6
-7.0%
12
0.2%
28.8K
1
8.5%
3
8.5%
3
0.0%
7
0.0%
3
8.5%
8
-3.5%
38.4K
1
-18.6%
2
8.5%
2
0.0%
5
0.0%
2
8.5%
6
-7.0%
57.6K
-
-
1
8.5%
1
-25.0%
3
0.0%
1
8.5%
3
8.5%
76.8K
-
-
1
-18.6%
1
0.0%
2
0.0%
1
-18.6%
2
8.5%
115.2K
-
-
-
-
-
-
1
0.0%
-
-
1
8.5%
230.4K
-
-
-
-
-
-
-
-
-
-
-
-
Table 4.13 Examples of UBAUD Settings for Commonly Used Oscillator Frequencies (continued)
fOSC=3.6864MHz
Baud
Rate
U2X=0
fOSC=4.00MHz
U2X=1
U2X=0
fOSC=7.3728MHz
U2X=1
U2X=0
U2X=1
UBAUD
ERROR
UBAUD
ERROR
UBAUD
ERROR
UBAUD
ERROR
UBAUD
ERROR
UBAUD
2400
95
0.0%
191
0.0%
103
0.2%
207
0.2%
191
0.0%
-
ERROR
-
4800
47
0.0%
95
0.0%
51
0.2%
103
0.2%
95
0.0%
191
0.0%
0.0%
9600
23
0.0%
47
0.0%
25
0.2%
51
0.2%
47
0.0%
95
14.4K
15
0.0%
31
0.0%
16
2.1%
34
-0.8%
31
0.0%
63
0.0%
19.2K
11
0.0%
23
0.0%
12
0.2%
25
0.2%
23
0.0%
47
0.0%
28.8K
7
0.0%
15
0.0%
8
-3.5%
16
2.1%
15
0.0%
31
0.0%
38.4K
5
0.0%
11
0.0%
6
-7.0%
12
0.2%
11
0.0%
23
0.0%
57.6K
3
0.0%
7
0.0%
3
8.5%
8
-3.5%
7
0.0%
15
0.0%
0.0%
76.8K
2
0.0%
5
0.0%
2
8.5%
6
-7.0%
5
0.0%
11
115.2K
1
0.0%
3
0.0%
1
8.5%
3
8.5%
3
0.0%
7
0.0%
230.4K
-
-
1
0.0%
-
-
1
8.5%
1
0.0%
3
0.0%
250K
-
-
1
-7.8%
-
-
1
0.0%
1
-7.8%
3
-7.8%
0.5M
-
-
-
-
-
-
-
-
-
-
1
-7.8%
Table 4.14 Examples of UBAUD Settings for Commonly Used Oscillator Frequencies (continued)
fOSC=8.00MHz
Baud
Rate
U2X=0
fOSC=11.0592MHz
U2X=1
U2X=0
fOSC=14.7456MHz
U2X=1
U2X=0
U2X=1
UBAUD
ERROR
UBAUD
ERROR
UBAUD
ERROR
UBAUD
ERROR
UBAUD
ERROR
UBAUD
2400
207
0.2%
-
-
-
-
-
-
-
-
-
ERROR
-
4800
103
0.2%
207
0.2%
143
0.0%
-
-
191
0.0%
-
-
9600
51
0.2%
103
0.2%
71
0.0%
143
0.0%
95
0.0%
191
0.0%
14.4K
34
-0.8%
68
0.6%
47
0.0%
95
0.0%
63
0.0%
127
0.0%
19.2K
25
0.2%
51
0.2%
35
0.0%
71
0.0%
47
0.0%
95
0.0%
28.8K
16
2.1%
34
-0.8%
23
0.0%
47
0.0%
31
0.0%
63
0.0%
38.4K
12
0.2%
25
0.2%
17
0.0%
35
0.0%
23
0.0%
47
0.0%
57.6K
8
-3.5%
16
2.1%
11
0.0%
23
0.0%
15
0.0%
31
0.0%
0.0%
76.8K
6
-7.0%
12
0.2%
8
0.0%
17
0.0%
11
0.0%
23
115.2K
3
8.5%
8
-3.5%
5
0.0%
11
0.0%
7
0.0%
15
0.0%
230.4K
1
8.5%
3
8.5%
2
0.0%
5
0.0%
3
0.0%
7
0.0%
250K
1
0.0%
3
0.0%
2
-7.8%
5
-7.8%
3
-7.8%
6
5.3%
0.5M
-
-
1
0.0%
-
-
2
-7.8%
1
-7.8%
3
-7.8%
1M
-
-
-
-
-
-
-
-
-
-
1
-7.8%
PS029502-0212
PRELIMINARY
111
Z51F0410
Product Specification
4.7 I2C
4.7.1 Overview
The I2C is one of industrial standard serial communication protocols, and which uses 2 bus lines
Serial Data Line (SDA) and Serial Clock Line (SCL) to exchange data. Because both SDA and SCL
lines are open-drain output, each line needs pull-up resistor. The features are as shown below.
-
Compatible with I2C bus standard
-
Multi-master operation
-
Up to 400 KHz data transfer speed
-
7 bit address
-
Both master and slave operation
-
Bus busy detection
4.7.2 Block Diagram
Slave Address Register
(SVADR)
Debounce
enable
SDA
Noise
Canceller
(debounce)
SDAIN
1
0
SDAOUT
F/F
8-bit Shift Register
(SHFTR)
SDA
Out Controller
Data Out Register
(I2CDR)
Debounce
enable
SCL High Period Register
(I2CSCLHR)
SCLIN
SCL
Noise
Canceller
(debounce)
SCL
Out Controller
1
0
SCL Low Period Register
(I2CSCLLR)
I
n
t
e
r
n
a
l
B
u
s
L
i
n
e
SDA Hold Time Register
(I2CDAHR)
SCLOUT
Figure 4.27 I2C Block Diagram
4.7.3 I2C Bit Transfer
The data on the SDA line must be stable during HIGH period of the clock, SCL. The HIGH or LOW
state of the data line can only change when the clock signal on the SCL line is LOW. The exceptions
are START(S), repeated START(Sr) and STOP(P) condition where data line changes when clock line
is high.
PS029502-0212
PRELIMINARY
112
Z51F0410
Product Specification
SDA
SCL
Data line Stable:
Data valid
exept S, Sr, P
Change of Data
allowed
Figure 4.28 Bit Transfer on the I2C-Bus
4.7.4 START / REPEATED START / STOP
One master can issue a START (S) condition to notice other devices connected to the SCL, SDA
lines that it will use the bus. A STOP (P) condition is generated by the master to release the bus lines
so that other devices can use it.
A high to low transition on the SDA line while SCL is high defines a START (S) condition.
A low to high transition on the SDA line while SCL is high defines a STOP (P) condition.
START and STOP conditions are always generated by the master. The bus is considered to be
busy after START condition. The bus is considered to be free again after STOP condition, ie, the bus
is busy between START and STOP condition. If a repeated START condition (Sr) is generated
instead of STOP condition, the bus stays busy. So, the START and repeated START conditions are
functionally identical.
SDA
SCL
S
P
START Condition
STOP Condition
Figure 4.29 START and STOP Condition
4.7.5 DATA TRANSFER
Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted
per transfer is unlimited. Each byte has to be followed by an acknowledge bit. Data is transferred with
the most significant bit (MSB) first. If a slave can’t receive or transmit another complete byte of data
until it has performed some other function, it can hold the clock line SCL LOW to force the master into
a wait state. Data transfer then continues when the slave is ready for another byte of data and
releases clock line SCL.
PS029502-0212
PRELIMINARY
113
Z51F0410
Product Specification
P
SDA
MSB
Acknowledgement
Signal form Slave
Byte Complete,
Interrupt within Device
SCL
S
or
Sr
1
9
Acknowledgement
Signal form Slave
Sr
Clock line held low while
interrupts are served.
1
ACK
9
Sr
or
P
ACK
START or Repeated
START Condition
STOP or Repeated
START Condition
Figure 4.30 Data Transfer on the I2C-Bus
4.7.6 ACKNOWLEDGE
The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA
line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the
acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse.
When a slave is addressed by a master (Address Packet), and if it is unable to receive or transmit
because it’s performing some real time function, the data line must be left HIGH by the slave. And
also, when a slave addressed by a master is unable to receive more data bits, the slave receiver must
release the SDA line (Data Packet). The master can then generate either a STOP condition to abort
the transfer, or a repeated START condition to start a new transfer.
If a master receiver is involved in a transfer, it must signal the end of data to the slave transmitter by
not generating an acknowledge on the last byte that was clocked out of the slave. The slave
transmitter must release the data line to allow the master to generate a STOP or repeated START
condition.
Data Output
By Transmitter
NACK
Data Output
By Receiver
ACK
SCL From MASTER
1
2
8
9
Clock pulse for ACK
Figure 4.31 Acknowledge on the I2C-Bus
4.7.7 SYNCHRONIZATION / ARBITRATION
Clock synchronization is performed using the wired-AND connection of I2C interfaces to the SCL
line. This means that a HIGH to LOW transition on the SCL line will cause the devices concerned to
start counting off their LOW period and it will hold the SCL line in that state until the clock HIGH state
is reached. However the LOW to HIGH transition of this clock may not change the state of the SCL
line if another clock is still within its LOW period. In this way, a synchronized SCL clock is generated
with its LOW period determined by the device with the longest clock LOW period, and its HIGH period
determined by the one with the shortest clock HIGH period.
A master may start a transfer only if the bus is free. Two or more masters may generate a START
condition. Arbitration takes place on the SDA line, while the SCL line is at the HIGH level, in such a
way that the master which transmits a HIGH level, while another master is transmitting a LOW level
PS029502-0212
PRELIMINARY
114
Z51F0410
Product Specification
will switch off its DATA output state because the level on the bus doesn’t correspond to its own level.
Arbitration continues for many bits until a winning master gets the ownership of I2C bus. Its first stage
is comparison of the address bits.
Wait High
Counting
Start High
Counting
Fast Device
SCLOUT
High Counter
Reset
Low Device
SCLOUT
SCL
Figure 4.32 Clock Synchronization during Arbitration Procedure
Arbitration Process
not adaped
Device 1 loses
Arbitration
Device1 outputs
High
Device1
DataOut
Device2
DataOut
SDA on BUS
SCL on BUS
S
Figure 4.33 Arbitration Procedure of Two Masters
4.7.8 OPERATION
The I2C is byte-oriented and interrupt based. Interrupts are issued after all bus events except for a
transmission of a START condition. Because the I2C is interrupt based, the application software is
free to carry on other operations during a I2C byte transfer.
Note that when a I2C interrupt is generated, IIF flag in I2CMR register is set, it is cleared by writing
an arbitrary value to I2CSR. When I2C interrupt occurs, the SCL line is hold LOW until writing any
value to I2CSR. When the IIF flag is set, the I2CSR contains a value indicating the current state of the
I2C bus. According to the value in I2CSR, software can decide what to do next.
I2C can operate in 4 modes by configuring master/slave, transmitter/receiver. The operating mode
is configured by a winning master. A more detailed explanation follows below.
PS029502-0212
PRELIMINARY
115
Z51F0410
Product Specification
4.7.8.1 Master Transmitter
To operate I2C in master transmitter, follow the recommended steps below.
1. Enable I2C by setting IICEN bit in I2CMR. This provides main clock to the peripheral.
2. Load SLA+W into the I2CDR where SLA is address of slave device and W is transfer
direction from the viewpoint of the master. For master transmitter, W is ‘0’. Note that I2CDR is
used for both address and data.
3. Configure baud rate by writing desired value to both I2CSCLLR and I2CSCLHR for the Low
and High period of SCL line.
4. Configure the I2CSDAHR to decide when SDA changes value from falling edge of SCL. If
SDA should change in the middle of SCL LOW period, load half the value of I2CSCLLR to the
I2CSDAHR.
5. Set the START bit in I2CMR. This transmits a START condition. And also configure how to
handle interrupt and ACK signal. When the START bit is set, 8-bit data in I2CDR is
transmitted out according to the baud-rate.
6. This is ACK signal processing stage for address packet transmitted by master. When 7-bit
address and 1-bit transfer direction is transmitted to target slave device, the master can know
whether the slave acknowledged or not in the 9th high period of SCL. If the master gains bus
mastership, I2C generates GCALL interrupt regardless of the reception of ACK from the slave
device. When I2C loses bus mastership during arbitration process, the MLOST bit in I2CSR is
set, and I2C waits in idle state or can be operate as an addressed slave. To operate as a
slave when the MLSOT bit in I2CSR is set, the ACKEN bit in I2CMR must be set and the
received 7-bit address must equal to the SLA bits in I2CSAR. In this case I2C operates as a
slave transmitter or a slave receiver (go to appropriate section). In this stage, I2C holds the
SCL LOW. This is because to decide whether I2C continues serial transfer or stops
communication. The following steps continue assuming that I2C does not lose mastership
during first data transfer.
I2C (Master) can choose one of the following cases regardless of the reception of ACK signal
from slave.
1) Master receives ACK signal from slave, so continues data transfer because slave can
receive more data from master. In this case, load data to transmit to I2CDR.
2) Master stops data transfer even if it receives ACK signal from slave. In this case, set the
STOP bit in I2CMR.
3) Master transmits repeated START condition with not checking ACK signal. In this case,
load SLA+R/W into the I2CDR and set START bit in I2CMR.
After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In
case of 1), move to step 7. In case of 2), move to step 9 to handle STOP interrupt. In case of
3), move to step 6 after transmitting the data in I2CDR and if transfer direction bit is ‘1’ go to
master receiver section.
7. 1-Byte of data is being transmitted. During data transfer, bus arbitration continues.
8. This is ACK signal processing stage for data packet transmitted by master. I2C holds the SCL
LOW. When I2C loses bus mastership while transmitting data arbitrating other masters, the
MLOST bit in I2CSR is set. If then, I2C waits in idle state. When the data in I2CDR is
transmitted completely, I2C generates TEND interrupt.
I2C can choose one of the following cases regardless of the reception of ACK signal from
slave.
1) Master receives ACK signal from slave, so continues data transfer because slave can
receive more data from master. In this case, load data to transmit to I2CDR.
2) Master stops data transfer even if it receives ACK signal from slave. In this case, set the
STOP bit in I2CMR.
3) Master transmits repeated START condition with not checking ACK signal. In this case,
load SLA+R/W into the I2CDR and set the START bit in I2CMR.
PS029502-0212
PRELIMINARY
116
Z51F0410
Product Specification
After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In
case of 1), move to step 7. In case of 2), move to step 9 to handle STOP interrupt. In case of
3), move to step 6 after transmitting the data in I2CDR, and if transfer direction bit is ‘1’ go to
master receiver section.
9. This is the final step for master transmitter function of I2C, handling STOP interrupt. The
STOP bit indicates that data transfer between master and slave is over. To clear I2CSR, write
arbitrary value to I2CSR. After this, I2C enters idle state.
The next figure depicts above process for master transmitter operation of I2C.
Master
Receiver
S or Sr
SLA+R
SLA+W
0x86
ACK
0x87
DATA
Rs
Lost?
0x47
N
LOST
LOST&
0x0F
0x1D 0x1F
Slave Receiver (0x1D)
or Transmitter (0x1F)
0x22
STOP
LOST
Cont?
0x0E
P
0x0E
Y
Y
P
LOST
STOP
N
STOP
Y
0x46
ACK
0x22
N
Other master continues
Y
From master to slave /
Master command or Data Write
0x0F
From slave to master
STOP
0x22
P
0xxx
Value of Status Register
ACK
Interrupt, SCL line is held low
P
Interrupt after stop command
LOST&
Arbitration lost as master and
addressed as slave
Figure 4.34 Formats and States in the Master Transmitter Mode
PS029502-0212
PRELIMINARY
117
Z51F0410
Product Specification
4.7.8.2 Master Receiver
To operate I2C in master receiver, follow the recommended steps below.
1. Enable I2C by setting IICEN bit in I2CMR. This provides main clock to the peripheral.
2. Load SLA+R into the I2CDR where SLA is address of slave device and R is transfer direction
from the viewpoint of the master. For master receiver, R is ‘1’. Note that I2CDR is used for
both address and data.
3. Configure baud rate by writing desired value to both I2CSCLLR and I2CSCLHR for the Low
and High period of SCL line.
4. Configure the I2CSDAHR to decide when SDA changes value from falling edge of SCL. If
SDA should change in the middle of SCL LOW period, load half the value of I2CSCLLR to the
I2CSDAHR.
5. Set the START bit in I2CMR. This transmits a START condition. And also configure how to
handle interrupt and ACK signal. When the START bit is set, 8-bit data in I2CDR is
transmitted out according to the baud-rate.
6. This is ACK signal processing stage for address packet transmitted by master. When 7-bit
address and 1-bit transfer direction is transmitted to target slave device, the master can know
whether the slave acknowledged or not in the 9th high period of SCL. If the master gains bus
mastership, I2C generates GCALL interrupt regardless of the reception of ACK from the slave
device. When I2C loses bus mastership during arbitration process, the MLOST bit in I2CSR is
set, and I2C waits in idle state or can be operate as an addressed slave. To operate as a
slave when the MLSOT bit in I2CSR is set, the ACKEN bit in I2CMR must be set and the
received 7-bit address must equal to the SLA bits in I2CSAR. In this case I2C operates as a
slave transmitter or a slave receiver (go to appropriate section). In this stage, I2C holds the
SCL LOW. This is because to decide whether I2C continues serial transfer or stops
communication. The following steps continue assuming that I2C does not lose mastership
during first data transfer.
I2C (Master) can choose one of the following cases according to the reception of ACK signal
from slave.
1) Master receives ACK signal from slave, so continues data transfer because slave can
prepare and transmit more data to master. Configure ACKEN bit in I2CMR to decide whether
I2C ACKnowledges the next data to be received or not.
2) Master stops data transfer because it receives no ACK signal from slave. In this case, set
the STOP bit in I2CMR.
3) Master transmits repeated START condition due to no ACK signal from slave. In this case,
load SLA+R/W into the I2CDR and set START bit in I2CMR.
After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In
case of 1), move to step 7. In case of 2), move to step 9 to handle STOP interrupt. In case of
3), move to step 6 after transmitting the data in I2CDR and if transfer direction bit is ‘0’ go to
master transmitter section.
7. 1-Byte of data is being received.
8. This is ACK signal processing stage for data packet transmitted by slave. I2C holds the SCL
LOW. When 1-Byte of data is received completely, I2C generates TEND interrupt.
I2C can choose one of the following cases according to the RXACK flag in I2CSR.
1) Master continues receiving data from slave. To do this, set ACKEN bit in I2CMR to
ACKnowledge the next data to be received.
2) Master wants to terminate data transfer when it receives next data by not generating ACK
signal. This can be done by clearing ACKEN bit in I2CMR.
3) Because no ACK signal is detected, master terminates data transfer. In this case, set the
STOP bit in I2CMR.
4) No ACK signal is detected, and master transmits repeated START condition. In this case,
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load SLA+R/W into the I2CDR and set the START bit in I2CMR.
After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In
case of 1) and 2), move to step 7. In case of 3), move to step 9 to handle STOP interrupt. In
case of 4), move to step 6 after transmitting the data in I2CDR, and if transfer direction bit is
‘0’ go to master transmitter section.
9. This is the final step for master receiver function of I2C, handling STOP interrupt. The STOP
bit indicates that data transfer between master and slave is over. To clear I2CSR, write
arbitrary value to I2CSR. After this, I2C enters idle state.
The processes described above for master receiver operation of I2C can be depicted as the following
figure.
Master
Transmitter
S or Sr
SLA+W
SLA+R
0x84
ACK
0x85
DATA
0x20
N
STOP
P
0x0C
Y
LOST
Rs
LOST
LOST&
0x0D
0x1D 0x1F
Slave Receiver (0x1D)
or Transmitter (0x1F)
0x44
Sr
0x44
ACK
0x45
Y
N
0x20
STOP
0x0C
LOST
0xxx
P
Other master continues
From master to slave /
Master command or Data Write
ACK
From slave to master
ACK
Value of Status Register
Interrupt, SCL line is held low
P
Interrupt after stop command
LOST&
Arbitration lost as master and
addressed as slave
Figure 4.35 Formats and States in the Master Receiver Mode
4.7.8.3 Slave Transmitter
To operate I2C in slave transmitter, follow the recommended steps below.
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1. If the main operating clock (SCLK) of the system is slower than that of SCL, load value 0x00
into I2CSDAHR to make SDA change within one system clock period from the falling edge of
SCL. Note that the hold time of SDA is calculated by SDAH x period of SCLK where SDAH is
multiple of number of SCLK coming from I2CSDAHR. When the hold time of SDA is longer
than the period of SCLK, I2C (slave) cannot transmit serial data properly.
2. Enable I2C by setting IICEN bit and INTEN bit in I2CMR. This provides main clock to the
peripheral.
3. When a START condition is detected, I2C receives one byte of data and compares it with
SLA bits in I2CSAR. If the GCALLEN bit in I2CSAR is enabled, I2C compares the received
data with value 0x00, the general call address.
Note: General call interrupt can occur as though the received data does not match the
general call address. When general call interrupt happens, I2CDR must be checked to match
0x00.
4. If the received address does not equal to SLA bits in I2CSAR, I2C enters idle state ie, waits
for another START condition. Else if the address equals to SLA bits and the ACKEN bit is
enabled, I2C generates SSEL interrupt and the SCL line is held LOW. Note that even if the
address equals to SLA bits, when the ACKEN bit is disabled, I2C enters idle state. When
SSEL interrupt occurs, load transmit data to I2CDR and write arbitrary value to I2CSR to
release SCL line.
5. 1-Byte of data is being transmitted.
6. In this step, I2C generates TEND interrupt and holds the SCL line LOW regardless of the
reception of ACK signal from master. Slave can select one of the following cases.
1) No ACK signal is detected and I2C waits STOP or repeated START condition.
2) ACK signal from master is detected. Load data to transmit into I2CDR.
After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In
case of 1) move to step 7 to terminate communication. In case of 2) move to step 5. In either
case, a repeated START condition can be detected. For that case, move step 4.
7. This is the final step for slave transmitter function of I2C, handling STOP interrupt. The STOP
bit indicates that data transfer between master and slave is over. To clear I2CSR, write
arbitrary value to I2CSR. After this, I2C enters idle state.
The next figure shows flow chart for handling slave transmitter function of I2C.
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IDLE
S or Sr
SLA+R
GCALL
0x97
0x1F
ACK
LOST&
Y
0x17
DATA
0x22
Y
0x47
ACK
Y
N
STOP
P
0x46
IDLE
From master to slave /
Master command or Data Write
From slave to master
0xxx
Value of Status Register
ACK
Interrupt, SCL line is held low
P
Interrupt after stop command
LOST&
Arbitration lost as master and
addressed as slave
GCALL
General Call Address
Figure 4.36 Formats and States in the Slave Transmitter Mode
4.7.8.4 Slave Receiver
To operate I2C in slave receiver, follow the recommended steps below.
1. If the main operating clock (SCLK) of the system is slower than that of SCL, load value 0x00
into I2CSDAHR to make SDA change within one system clock period from the falling edge of
SCL. Note that the hold time of SDA is calculated by SDAH x period of SCLK where SDAH is
multiple of number of SCLK coming from I2CSDAHR. When the hold time of SDA is longer
than the period of SCLK, I2C (slave) cannot transmit serial data properly.
2. Enable I2C by setting IICEN bit and INTEN bit in I2CMR. This provides main clock to the
peripheral.
3. When a START condition is detected, I2C receives one byte of data and compares it with
SLA bits in I2CSAR. If the GCALLEN bit in I2CSAR is enabled, I2C compares the received
data with value 0x00, the general call address.
4. If the received address does not equal to SLA bits in I2CSAR, I2C enters idle state ie, waits
for another START condition. Else if the address equals to SLA bits and the ACKEN bit is
enabled, I2C generates SSEL interrupt and the SCL line is held LOW. Note that even if the
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address equals to SLA bits, when the ACKEN bit is disabled, I2C enters idle state. When
SSEL interrupt occurs and I2C is ready to receive data, write arbitrary value to I2CSR to
release SCL line.
5. 1-Byte of data is being received.
6. In this step, I2C generates TEND interrupt and holds the SCL line LOW regardless of the
reception of ACK signal from master. Slave can select one of the following cases.
1) No ACK signal is detected (ACKEN=0) and I2C waits STOP or repeated START condition.
2) ACK signal is detected (ACKEN=1) and I2C can continue to receive data from master.
After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In
case of 1) move to step 7 to terminate communication. In case of 2) move to step 5. In either
case, a repeated START condition can be detected. For that case, move step 4.
7. This is the final step for slave receiver function of I2C, handling STOP interrupt. The STOP bit
indicates that data transfer between master and slave is over. To clear I2CSR, write arbitrary
value to I2CSR. After this, I2C enters idle state.
The process can be depicted as following figure when I2C operates in slave receiver mode.
IDLE
S or Sr
SLA+W
GCALL
0x95
0x1D
ACK
LOST&
N
Y
0x15
DATA
0x20
Y
0x45
ACK
Y
N
STOP
P
0x44
IDLE
From master to slave /
Master command or Data Write
From slave to master
0xxx
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Value of Status Register
PRELIMINARY
ACK
Interrupt, SCL line is held low
P
Interrupt after stop command
LOST&
Arbitration lost as master and
addressed as slave
GCALL
General Call Address
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Figure 4.37 Formats and States in the Slave Receiver Mode
4.7.9 Register Map
Table 4.15 I2C Register Map
Name
Address
Dir
Default
Description
I2CMR
DAH
R/W
00H
I2C Mode Control Register
I2CSR
DBH
R
00H
I2C Status Register
I2CSCLLR
DCH
R/W
3FH
SCL Low Period Register
I2CSCLHR
DDH
R/W
3FH
SCL High Period Register
I2CSDAHR
DEH
R/W
01H
SDA Hold Time Register
I2CDR
DFH
R/W
FFH
I2C Data Register
I2CSAR
D7H
R/W
00H
I2C Slave Address Register
4.7.10 I2C Register description
I2C Registers are composed of I2C Mode Control Register (I2CMR), I2C Status Register (I2CSR),
SCL Low Period Register (I2CSCLLR), SCL High Period Register (I2CSCLHR), SDA Hold Time
Register (I2CSDAHR), I2C Data Register (I2CDR), and I2C Slave Address Register (I2CSAR).
4.7.11 Register description for I2C
I2CMR (I2C Mode Control Register) : DAH
7
6
5
4
3
2
1
0
IIF
IICEN
RESET
INTEN
ACKEN
IMASTERl
STOP
START
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IIF
IICEN
RESET
INTEN
ACKEN
MASTER
PS029502-0212
R/W
Initial value : 00H
This is interrupt flag bit.
0
No interrupt is generated or interrupt is cleared
1
An interrupt is generated
Enable I2C Function Block (by providing clock)
0
I2C is inactive
1
I2C is active
Initialize internal registers of I2C.
0
No operation
1
Initialize I2C, auto cleared
Enable interrupt generation of I2C.
0
Disable interrupt, operates in polling mode
1
Enable interrupt
Controls ACK signal generation at ninth SCL period.
Note) ACK signal is output (SDA=0) for the following 3 cases.
When received address packet equals to SLA bits in I2CSAR
When received address packet equals to value 0x00 with GCALL
enabled
When I2C operates as a receiver (master or slave)
0
No ACK signal is generated (SDA=1)
1
ACK signal is generated (SDA=0)
This bit shows whether I2C is in master or slave mode.
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STOP
START
0
I2C is in slave mode.
1
I2C is in master mode.
When I2C is master, generates STOP condition.
0
No operation
1
STOP condition is to be generated
When I2C is master, generates START condition.
0
No operation
1
START or repeated START condition is to be generated
I2CSR (I2C Status Register) : DBH
7
6
5
4
3
2
1
0
GCALL
TEND
STOP
SSEL
MLOST
BUSY
TMODE
RXACK
R
R
R
R
R
R
R
GCALL
TEND
STOP
SSEL
MLOST
BUSY
TMODE
RXACK
R
Initial value : 00H
This bit has different meaning depending on whether I2C is master or
slave. Note 1)
When I2C is a master, this bit represents whether it received AACK
(Address ACK) from slave.
When I2C is a slave, this bit is used to indicate general call.
0
No AACK is received (Master mode)
1
AACK is received (Master mode)
0
Received address is not general call address (Slave mode)
1
General call address is detected (Slave mode)
This bit is set when 1-Byte of data is transferred completely. Note 1)
0
1 byte of data is not completely transferred
1
1 byte of data is completely transferred
This bit is set when STOP condition is detected. Note 1)
0
No STOP condition is detected
1
STOP condition is detected
This bit is set when I2C is addressed by other master. Note 1)
0
I2C is not selected as slave
1
I2C is addressed by other master and acts as a slave
This bit represents the result of bus arbitration in master mode. Note 1)
0
I2C maintains bus mastership
1
I2C has lost bus mastership during arbitration process
This bit reflects bus status.
0
I2C bus is idle, so any master can issue a START condition
1
I2C bus is busy
This bit is used to indicate whether I2C is transmitter or receiver.
0
I2C is a receiver
1
I2C is a transmitter
This bit shows the state of ACK signal.
0
No ACK is received
1
ACK is generated at ninth SCL period
Note 1) These bits can be source of interrupt.
When an I2C interrupt occurs except for STOP interrupt, the SCL line is hold LOW. To release SCL,
write arbitrary value to I2CSR. When I2CSR is written, the TEND, STOP, SSEL, LOST, RXACK bits
are cleared.
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I2CSCLLR (SCL Low Period Register) : DCH
7
6
5
4
3
2
1
0
SCLL7
SCLL6
SCLL5
SCLL4
SCLL3
SCLL2
SCLL1
SCLL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCLL[7:0]
R/W
Initial value : 3FH
This register defines the LOW period of SCL when I2C operates in
master mode. The base clock is SCLK, the system clock, and the
period is calculated by the formula : tSCLK (SCLL + 1) where tSCLK
is the period of SCLK.
I2CSCLHR (SCL High Period Register) : DDH
7
6
5
4
3
2
1
0
SCLH7
SCLH6
SCLH5
SCLH4
SCLH3
SCLH2
SCLH1
SCLH0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 3FH
SCLH[7:0]
This register defines the HIGH period of SCL when I2C operates in
master mode. The base clock is SCLK, the system clock, and the
period is calculated by the formula : tSCLK (SCLH + 3) where tSCLK
is the period of SCLK.
So, the operating frequency of I2C in master mode (fI2C) is calculated by the following equation.
1
fI2C tSCLK
SCLL SCLH 4
I2CSDAHR (SDA Hold Time Register) : DEH
7
6
5
4
3
2
1
0
SDAH7
SDAH6
SDAH5
SDAH4
SDAH3
SDAH2
SDAH1
SDAH0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SDAH[7:0]
R/W
Initial value : 01H
This register is used to control SDA output timing from the falling
edge of SCL. Note that SDA is changed after tSCLK SDAH. In
master mode, load half the value of SCLL to this register to make
SDA change in the middle of SCL. In slave mode, configure this
register regarding the frequency of SCL from master. The SDA is
changed after tSCLK (SDAH + 1). So, to insure normal operation in
slave mode, the value tSCLK (SDAH + 1) must be smaller than the
period of SCL.
I2CDR (I2C Data Register) : DFH
7
6
5
4
3
2
1
0
ICD7
ICD6
ICD5
ICD4
ICD3
ICD2
ICD1
ICD0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : FFH
ICD[7:0]
When I2C is configured as a transmitter, load this register with data
to be transmitted. When I2C is a receiver, the received data is
stored into this register.
I2CSAR (I2C Slave Address Register) : D7H
7
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5
4
3
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0
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SLA7
SLA6
SLA5
SLA4
SLA3
SLA2
SLA1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
GCALLEN
R/W
Initial value : 00H
SLA[7:1]
These bits configure the slave address of this I2C module when I2C
operates in slave mode.
GCALLEN
This bit decides whether I2C allows general call address or not
when I2C operates in slave mode.
0
Ignore general call address
1
Allow general call address
4.8 12-Bit A/D Converter
4.8.1 Overview
The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding
12-bit digital value. The A/D module has tenth analog inputs. The output of the multiplex is the input
into the converter, which generates the result via successive approximation. The A/D module has four
registers which are the control register ADCM (A/D Converter Mode Register), ADCM2 (A/D
Converter Mode Register 2) and A/D result register ADCHR (A/D Converter Result High Register) and
ADCLR (A/D Converter Result Low Register). It is selected for the corresponding channel to be
converted by setting ADSEL[3:0]. To executing A/D conversion, ADST bit sets to ‘1’. The register
ADCHR and ADCLR contains the results of the A/D conversion. When the conversion is completed,
the result is loaded into the ADCHR and ADCLR, the A/D conversion status bit AFLAG is set to ‘1’,
and the A/D interrupt is set. For processing A/D conversion, AFLAG bit is read as ‘0’. If using STBY
(power down) bit, the ADC is disabled. Also internal timer, external generating event, comparator, the
trigger of timer1pwm and etc. can start ADC regardless of interrupt occurrence.
ADC Conversion Time = ADCLK * 60 cycles
After STBY bit is reset (ADC power enable) and it is restarted, during some cycle, ADC conversion
value may have an inaccurate value.
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4.8.2 Block Diagram
÷2
fx
Pre
scaler
÷4
MUX
÷8
÷32
12bit A/D Converter Data Register
2
CKSEL[1:0]
ADCRH[7:0]
(8bit)
ADCLK
ADCRL[7:4]
(4bit)
ADST
Ext VDD
[9BH]
Vss
Clear
[9CH]
B/G Vref
AFLAG
12
VDC
AN7
Successive
Approximation
Circuit
MUX
AN6
ADIF
ADC
Interrupt
Comparator
AN1
AN0
4
ADS[3:0]
ADST
Resistor Ladder
Circuit
AN0
Figure 4.38 ADC Block Diagram
Analog
Input
AN0
AN7
~
Analog
Power
Input
0~1000pF
22uF
Figure 4.39 A/D Analog Input Pin
Connecting Capacitor
PS029502-0212
AVDD
Figure 4.40 A/D Power(AVDD) Pin
Connecting Capacitor
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4.8.3 ADC Operation
Align bit set “0”
ADCO11
ADCO10
ADCO9
ADCO8
ADCO7
ADCO6
ADCO5
ADCO4
ADCRH7 ADCRH6 ADCRH5 ADCRH4 ADCRH3 ADCRH2 ADCRH1 ADCRH0
ADCO3
ADCO2
ADCO1
ADCO0
ADCRL7
ADCRL6
ADCRL5
ADCRL4
ADCRL[7:4]
ADCRH[7:0]
ADCRL[3:0] bits are “0”
Align bit set “1”
ADCO11
ADCO10
ADCO9
ADCO8
ADCRH3 ADCRH2 ADCRH1 ADCRH0
ADCRH[4:0]
ADCRH[7:4] bits are “0”
ADCO7
ADCO6
ADCO5
ADCO4
ADCO3
ADCO2
ADCO1
ADCO0
ADCRL7
ADCRL6
ADCRL5
ADCRL4
ADCRL3
ADCRL2
ADCRL1
ADCRL0
ADCRL[7:0]
Figure 4.41 ADC Operation for Align bit
SET ADCM2
Select ADC Clock & Data Align Bit.
SET ADCM
ADC enable & Select AN Input Channel.
Converting START
N
Start ADC Conversion.
If Conversion is completed, AFLG is set “1” and ADC
interrupt is occurred.
AFLAG = 1?
Y
READ ADCRH/L
After Conversion is completed, read ADCRH and ADCRL.
ADC END
Figure 4.42 A/D Converter Operation Flow
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4.8.4 Register Map
Table 4.16 ADC Register Map
Name
Address
Dir
Default
Description
ADCM
9AH
R/W
8FH
A/D Converter Mode Register
ADCRH
9BH
R
-
A/D Converter Result High Register
ADCRL
9CH
R
-
A/D Converter Result Low Register
ADCM2
9BH
R/W
8FH
A/D Converter Mode 2 Register
4.8.5 ADC Register description
The ADC Register consists of A/D Converter Mode Register (ADCM), A/D Converter Result High
Register (ADCRH), A/D Converter Result Low Register (ADCRL), A/D Converter Mode 2 Register
(ADCM2).
Note) when STBY bit is set to ‘1’, ADCM2 can be read. If ADC enables, it is possible only to write
ADCM2.When reading, ADCRH is read.
4.8.6 Register description for ADC
ADCM (A/D Converter Mode Register) : 9AH
7
6
5
4
3
2
1
0
STBY
ADST
REFSEL
AFLAG
ADSEL3
ADSEL2
ADSEL1
ADSEL0
R/W
R/W
R/W
R/
R/W
R/W
R/W
STBY
ADST
REFSEL
AFLAG
ADSEL[3:0]
PS029502-0212
R/W
Initial value : 8FH
Control operation of A/D standby (power down)
0
ADC module enable
1
ADC module disable (power down)
Control A/D Conversion stop/start.
0
ADC Conversion Stop
1
ADC Conversion Start
A/D Converter reference selection
0
Internal Reference (VDD)
1
External Reference(AVREF, AN0 disable)
A/D Converter operation state
0
During A/D Conversion
1
A/D Conversion finished
A/D Converter input selection
ADSEL3
ADSEL2 ADSEL1 ADSEL0 Description
0
0
0
0
Channel0(AN0)
0
0
0
1
Channel1(AN1)
0
0
1
0
Channel2(AN2)
0
0
1
1
Channel3(AN3)
0
1
0
0
Channel4(AN4)
0
1
0
1
Channel5(AN5)
0
1
1
0
Channel6(AN6)
0
1
1
1
Channel7(AN7)
1
0
0
0
Channel8(N/A)
1
0
0
1
Channel9(N/A)
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1
0
1
0
Channel10(VDC:1.8V)
1
0
1
1
Channel11(Bandgap
Vref:1.17V)
1
1
0
0
Channel12(VSS)
1
1
0
1
Channel13(Ext. VDD)
1
1
1
0
Channel14(N/A)
1
1
1
1
Channel15(N/A)
ADCRH (A/D Converter Result High Register) : 9BH
7
6
5
4
3
2
1
0
ADDM11
ADDM10
ADDM9
ADDM8
ADDM7
ADDL11
ADDM6
ADDL10
ADDM5
ADDL9
ADDM4
ADDL8
R
R
R
R
R
R
R
ADDM[11:4]
MSB align, A/D Converter High result (8-bit)
ADDL[11:8]
LSB align, A/D Converter High result (4-bit)
R
Initial value : xxH
ADCRL (A/D Converter Result Low Register) : 9CH
7
6
5
4
3
2
1
0
ADDM3
ADDL7
ADDM2
ADDL6
ADDM1
ADDL5
ADDM0
ADDL4
ADDL3
ADDL2
ADDL1
ADDL0
R
R
R
R
R-
R
R
ADDM[3:0]
MSB align, A/D Converter Low result (4-bit)
ADDL[7:0]
LSB align, A/D Converter Low result (8-bit)
R
Initial value : xxH
ADCM2 (A/D Converter Mode Register) : 9BH
7
6
5
4
3
2
1
0
EXTRG
TSEL2
TSEL1
TSEL0
AMUXEN
ALIGN
CKSEL1
CKSEL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EXTRG
TSEL[2:0]
AMUXEN
PS029502-0212
R/W
Initial value : 8FH
A/D external Trigger
0
External Trigger disable
1
External Trigger enable
A/D Trigger Source selection
TSEL2
TSEL1
TSEL0
0
0
0
Description
Ext. Interrupt 0
0
0
1
Analog Comparator Low to High
0
1
0
Analog Comparator High to Low
0
1
1
Timer0 interrupt
1
0
0
Timer1 interrupt
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Timer4 Interrupt
Control A/D Converter MUX output
0
A/D Converter MUX output disable
1
When STBY=1, A/D Converter MUX output enable
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Product Specification
ALIGN
CKSEL[1:0]
A/D Converter data align selection.
0
MSB align (ADCRH[7:0], ADCRL[7:4])
1
LSB align (ADCRH[3:0], ADCRL[7:0])
A/D Converter Clock selection
CKSEL1
CKSEL0
ADC Clock
ADC VDD
0
0
fx/2
Test Only
0
1
fx/4
3V~5V
1
0
fx/8
2.7V~3V
1
1
fx/32
2.4V~2.7V
Note) 1. fx : system clock
2. ADC clock have to be used
3MHz
under.
PSR0 (ADC Pin Selection Register) : 9FH
7
6
5
4
3
2
1
0
AIN07_EN
AIN06_EN
AIN05_EN
AIN04_EN
AIN03_EN
AIN02_EN
AIN01_EN
AIN00_EN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PSR0[7:0]
PS029502-0212
R/W
Initial value : 00H
ADC Input Pin Channel Selection (Disable logic input gate)
0
disable
1
enable
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Product Specification
4.9 Analog Comparator
4.9.1 Overview
The Analog Comparator compares the input values on the positive pin AN5 and the negative pin
AN4. When the voltage on the positive pin AN5 is higher than the voltage on the negative pin AN4,
the Analog Comparator output, ACOUT, is set.
4.9.2 Block Diagram
ACBG
ACIE
ACE
B/G
V f
AN4
MUX
Analog
Comparator
Interrupt
Interrupt
Select
Comparator
ACISM[1:0]
AN5
ADC MUX
Output
ACIF
MUX
ACO
AMUXENB
(ADCM2.3)
Figure 4.43 Analog Comparator Block Diagram
4.9.3 IN/OUT signal description
ACE : This enables Analog Comparator. When ACE is ‘0’, the output of Comparator goes LOW.
BGR : Band Gap Reference Voltage
ACBG : This selects (-) input source between BGR and AN4. When ACBG is ‘1’, the (-) input to AC is
BGR.
AN4 : This can be (-) input to the AC, and comes directly from external analog pad.
AN5 : This can be (+) input to the AC, and comes directly from external analog pad.
AMUXENB : This selects (+) input source between multiplexed output of ADC and AN5. AMUXENB is
the inverted signal of AMUXEN bit in ADCM2 register. When AMUXENB is ‘0’, the (+) input to AC
comes from ADC module which is selected by ADSEL[3:0], the channel selection bits in ADCM
register.
ACOUT : This is the output of Comparator.
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4.9.4 Register Map
Table 4.17 Analog Comparator Register Map
Name
ACCSR
Address
Dir
E9H
Default
R/W
Description
00H
Analog Comparator Control & Status Register
4.9.5 Analog Comparator Register description
Analog Comparator Register has one control register, Analog Comparator Control & Status Register
(ACCSR). Note that AMUXENB is the inverted signal of AMUXEN bit which comes from ADC’s
ADCM2 register
4.9.6 Register description for Analog Comparator
ACCSR (Analog Comparator Control & Status Register) : E9H
7
6
5
4
3
2
1
0
ACE
ACBG
ACO
ACIF
ACIE
-
ACISM1
ACISM0
R/W
R/W
R
R
R/W
-
R/W
ACE
R/W
Initial value : 00H
Enable Analog Comparator (AC).
ACBG
0
Disable AC (power down)
1
Enable AC
Select (-) input source of AC, Band Gap Reference Voltage or AN4.
0
(-) input is from AN4
1
(-) input is from Band Gap Reference Voltage
This bit represents the value of ACOUT (Output of Analog Comparator).
ACO bit is sampled by SCLK, system clock, twice. When ACE is ‘0’, this
bit is also cleared.
ACO
ACIF
ACIE
ACISM[1:0]
0
Comparator output is LOW
1
Comparator output is HIGH
This bit is set when an Analog Comparator Interrupt is generated
according to the ACISM[1:0] bits. This bit is cleared when Analog
Comparator Interrupt is executed or ‘0’ is written to this bit field.
0
No interrupt generated or cleared
1
Interrupt generated
Enable Analog Comparator Interrupt.
0
Disable Interrupt, Polling mode operation
1
Enable Interrupt
Select Interrupt Mode of Analog Comparator.
ACISM1
ACISM0
Description
0
0
Reserved
0
1
Interrupt on falling edge of ACOUT
1
0
Interrupt on rising edge of ACOUT
1
1
Interrupt on both edge of ACOUT
PSR1 (Comparator Pin Selection Register) : A0H
7
6
5
4
3
2
1
0
ACO_EN
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Product Specification
R/W
Initial value : 00H
PSR1[0]
Analog Comparator Output Enable (Disable logic input gate)
0
disable
1
enable
4.10 Buzzer Driver
4.10.1 Overview
The Buzzer consists of 8 Bit Counter and BUZDR (Buzzer Data Register), BUZCR (Buzzer Control
Register). The Square Wave (61.035Hz~125 KHz, @8MHz) gets out of P12/BUZ pin. BUZDR (Buzzer
Data Register) controls the Buzzer frequency (look at the following expression). In the BUZCR
(Buzzer Control Register), BUCK[1:0] selects source clock divided from prescaler.
f BUZ (Hz) 
Oscillator Frequency
2  Prescaler Ratio  (BUZDR  1)
Buzzer Frequency (kHz)
BUZDR[7:0]
BUZCR[2:1]=00
BUZCR[2:1]=01
BUZCR[2:1]=10
BUZCR[2:1]=11
0000_0000
125kHz
62.5kHz
31.25kHz
15.625kHz
0000_0001
62.5kHz
31.25kHz
15.625kHz
7.812kHz
…
…
…
…
…
1111_1101
492.126Hz
246.063Hz
123.031Hz
61.515Hz
1111_1110
490.196Hz
245.098Hz
122.549Hz
61.274Hz
1111_1111
488.281Hz
244.141Hz
122.07Hz
61.035Hz
Table 11-12 Buzzer Frequency at 8 Mhz
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4.10.2 Block Diagram
8-bit Up-counter
÷32
Pre
scaler
fx
÷64
Overflow
Counter
MUX
÷128
BUZCR[0]
÷256
F/F
BUZCR[2:1]
Selection Input
Clock
BUZO PIN
2
Counter
Writing to BUZDR
RESET
Buzzer Control Register
[96H]
BUZCR
Buzzer Data Register
[8FH]
BUZDR
Figure 4-38 Buzzer Driver Block Diagram
4.10.3 Register Map
Name
Address
Dir
Default
Description
BUZDR
8FH
R/W
FFH
Buzzer Data Register
BUZCR
96H
R/W
00H
Buzzer Control Register
Table 11-13 Register Map
4.10.4 Buzzer Driver Register description
Buzzer Driver consists of Buzzer Data Register (BUZDR), Buzzer Control Register (BUZCR).
4.10.5 Register description for Buzzer Driver
BUZDR (Buzzer Data Register) : 8FH
7
6
5
4
3
2
1
0
BUZDR7
BUZDR6
BUZDR5
BUZDR4
BUZDR3
BUZDR2
BUZDR1
BUZDR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : FFH
BUZDR[7:0]
This bits control the Buzzer frequency
Its resolution is 00H ~ FFH
BUZCR (Buzzer Control Register) : 96H
7
6
5
4
3
2
1
0
-
-
-
-
-
BUCK1
BUCK0
BUZEN
-
-
-
-
-
R/W
R/W
BUCK[1:0]
PS029502-0212
R/W
Initial value : 00H
Buzzer Driver Source Clock Selection
PRELIMINARY
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Z51F0410
Product Specification
BUZEN
BUCK1
BUCK0
Source Clock
0
0
fx/32
0
1
fx/64
1
0
fx/128
1
1
fx/256
Buzzer Driver Operation Control
0
Buzzer Driver disable
1
Buzzer Driver enable
Note) fx: Main system clock oscillation frequency
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Product Specification
5. Power Down Operation
5.1 Overview
The Z51F0410 MCU features three power-down modes to minimize the power consumption of the
device. In power down mode, power consumption is reduced considerably. The device provides three
kinds of power saving functions, IDLE, STOP1 and STOP2 mode. In three modes, program is
stopped.
5.2 Peripheral Operation In IDLE/STOP Mode
Table 5.1 Peripheral Operation during Power Down Mode.
Peripheral
IDLE Mode
CPU
ALL CPU Operation
are Disable
ALL CPU Operation are Disable
ALL CPU Operation are Disable
RAM
STOP1 Mode
STOP2 Mode
Retain
Retain
Retain
Basic Interval
Timer
Operates
Continuously
Operates Continuously
Stop
Watch Dog
Timer
Operates
Continuously
Operates Continuously
Stop
Watch Timer
Operates
Continuously
Stop (Only operate in sub clock mode)
Stop (Only operate in sub clock mode)
TimerP0~1
Operates
Continuously
Halted (Only when the Event Counter
Mode is Enable, Timer operates
Normally)
Halted (Only when the Event Counter
Mode is Enable, Timer operates
Normally)
ADC
Operates
Continuously
Stop
Stop
BUZ
Operates
Continuously
Stop
Stop
SPI/SCI
Operates
Continuously
Only operate with external clock
Only operate with external clock
I2C
Operates
Continuously
Stop
Stop
Internal OSC
(8MHz)
Oscillation
Stop
Stop
Main OSC
(1~8MHz)
Oscillation
Stop
Stop
Sub OSC
(32.768kHz)
Oscillation
Oscillation
Oscillation
Internal
RCOSC
(128kHz)
Oscillation
Oscillation
Stop
I/O Port
Retain
Retain
Retain
Control
Register
Retain
Retain
Retain
Address Data
Bus
Retain
Retain
Retain
By RESET, Timer Interrupt (EC0), SIO
(External clock), External Interrupt,
UART by ACK PCI, I2C (slave mode),
WT (sub clock),WDT, BIT
By RESET, Timer Interrupt (EC0), SIO
(External clock), External Interrupt,
UART by ACK PCI, I2C (slave mode),
WT (sub clock)
Release
Method
By
RESET,
Interrupts
all
5.3 IDLE mode
The power control register is set to ‘01h’ to enter the IDLE Mode. In this mode, the internal oscillation
circuits remain active. Oscillation continues and peripherals are operated normally but CPU stops. It is
released by reset or interrupt. To be released by interrupt, interrupt should be enabled before IDLE
mode. If using reset, because the device becomes initialized state, the registers have reset value.
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Product Specification
VDD
16ms, 32ms,
64
CPU Clock
External
Interrupt
Release
Normal Operation
Stand-by Mode
Normal Operation
Figure 5.1 IDLE Mode Release Timing by External Interrupt
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5.4 STOP mode
The power control register is set to ‘03h’ to enter the STOP Mode. In the stop mode, the main
oscillator, system clock and peripheral clock is stopped, but watch timer continue to operate. With the
clock frozen, all functions are stopped, but the on-chip RAM and control registers are held.
The source for exit from STOP mode is hardware reset and interrupts. The reset re-defines all the
control registers.
When exit from STOP mode, enough oscillation stabilization time is required to normal operation.
Figure 5.2 shows the timing diagram. When released from STOP mode, the Basic interval timer is
activated on wake-up. Therefore, before STOP instruction, user must be set its relevant prescale
divide ratio to have long enough time. this guarantees that oscillator has started and stabilized.
OSC
CPU Clock
External
Interrupt
STOP Instruction
Execute
BIT Counter
n
n+1
N+2
Release
n+3
0
1
FE
FF
0
1
Clear & Start
By Software setting
Normal Operation
STOP Operation
Normal Operation
Before executed STOP instruction, BIT must be set properly by
software to get stabilization.
Figure 5.2 STOP Mode Release Timing by External Interrupt
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5.5 Release Operation of STOP1, 2 Mode
After STOP1, 2 mode is released, the operation begins according to content of related interrupt
register just before STOP1, 2 mode start (Figure 5.3). Interrupt Enable Flag of All (EA) of IE should be
set to `1`. Released by only interrupt which each interrupt enable flag = `1`, and jump to the relevant
interrupt service routine.
SET SCCR.7
SET PCON[1:0]
SET IEx.b
STOP1, 2 Mode
Interrupt Request
N
Corresponding Interrupt
Enable Bit(IE, IE1, IE2, IE3)
IEX.b==1 ?
Y
STOP1, 2 Mode
Release
Interrupt Service
Routine
Nest Instruction
Figure 5.3 STOP1, 2 Mode Release Flow
5.5.1 Register Map
Table 5.2 PCON Register Map
Name
PS029502-0212
Address
Dir
Default
PRELIMINARY
Description
140
Z51F0410
Product Specification
PCON
87H
R/W
00H
Power Control Register
5.5.2 Power Down Operation Register description
The Power Down Operation Register consists of the Power Control Register (PCON).
5.5.3 Register description for Power Down Operation
PCON (Power Control Register) : 87H
7
6
5
4
3
2
1
0
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
IDLE Mode
01H
IDLE mode enable
STOP1, 2 Mode
03H
STOP1, 2 mode enable
Note)
1. To enter IDLE mode, PCON must be set to ‘01H’.
2. To STOP1,2 mode, PCON must be set to ‘03H’.
(In STOP1,2 mode, PCON register is cleared automatically by interrupt or reset)
3.
When PCON is set to ‘03H’, if SCCR[7] is set to ‘1’, it enters the STOP1 mode. if SCCR[7] is
cleared to ‘0’, it enters the STOP2 mode
4. The different thing in STOP 1,2 is only clock operation of internal 128kHz-OSC during STOP
mode operating.
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6. RESET
6.1 Overview
The Z51F0410 MCU features reset by external RESETB pin. The following is the hardware setting
value.
Table 6.1 Reset state
On Chip Hardware
Initial Value
Program Counter (PC)
0000h
Accumulator
00h
Stack Pointer (SP)
07h
Peripheral Clock
On
Control Register
Peripheral Registers refer
Brown-Out Detector
Enable
6.2 Reset source
The Z51F0410 MCU features five types of reset generation procedures. The following is the reset
sources.
- External RESETB
- Power ON RESET (POR)
- WDT Overflow Reset (In the case of WDTEN = `1`)
- BOD Reset (In the case of BODEN = `1 `)
- OCD Reset
6.3 Block Diagram
Ext RESET
Disable by FUSE
RESET Noise
Canceller
BOD_OUT
BOD Enable
RESET Noise
Canceller
WDT RST
S
WDT RST
WDT RSTEN
R
WDT RST
IFBIT
(BIT Overflow)
Q
Internal
Reset
Figure 6.1 RESET Block Diagram
6.4 RESET Noise Canceller
The Figure 6.2 is the noise canceller diagram for noise cancel of RESET. It has the noise cancel
value of about 7us (@VDD=5V) to the low input of System Reset.
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Product Specification
t < TRNC
t < TRNC
A
t > TRNC
t > TRNC
t > TRNC
A’
Figure 6.2 Reset noise canceller time diagram
6.5 Power ON RESET
When rising device power, the POR (Power ON Reset) have a function to reset the device. If using
POR, it executes the device RESET function instead of the RESET IC or the RESET circuits. And
External RESET PIN is able to be used as Normal I/O pin.
Fast VDD Rise Time
VDD
nPOR
(Internal Signal)
BIT Overflows
BIT Starts
Internal RESETb
Oscillation
Figure 6.3 Fast VDD rising time
Slow VDD Rise Time, max 0.02v/ms
VPOR=1.4V (Typ)
VDD
nPOR
(Internal Signal)
BIT Overflows
BIT Starts
Internal RESETb
Oscillation
Figure 6.4 Internal RESET Release Timing On Power-Up
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Product Specification
Counting for config read start after POR is released
VDD
16ms, 32ms,
64
Internal nPOR
PAD RESETB (R20)
“H”
BOD_RESETB
Ext_reset have not an effect on counter value for config read
BIT (for Config)
BIT (for Reset)
Config Read
00 01 02 03 04 05 06 .. ..
00 01 02 03
00
.. 2F 30
31
01 02 .. ..
.. 3F 40 00 01 02 03
250us (4Khz) X 30h = about 12ms
Config 26 Bytes
.. XX XX. ..X
XX XX
Config Data
X
250us X 40h = about 16ms
RESET_SYSB
16ms, 32ms, 64ms Selectable
INT-OSC (128KHz)
INT-OSC 128KHz/32
INT-OSC 128KHz / 32 = 4KHz (250us)
Figure 6.5 Configuration timing when Power-on
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:VDD Input
:Internal OSC
⑥
④
Reset Release
Config Read
②
POR
①
③
⑤
⑦
Figure 6.6 Boot Process Wave Form
Table 6.2 Boot Process Description
Process
Description
①
-No Operation
②
-1st POR level Detection
-Internal OSC (128KHz) ON
Remarks
-about 1.4V ~ 1.5V
- (INT-OSC128KHz/32) 30h Delay section (=12ms)
③
-VDD input voltage must rise over than flash
operating voltage for Config read
-Slew Rate
0.025V/ms
-about 1.5V ~ 1.6V
④
- Config read point
⑤
- Rising section to Reset Release Level
-Config Value is determined by
Writing Option
-16ms point after
Ext_reset release
POR
or
- Reset Release section (BIT overflow)
⑥
i) after16ms, after External Reset Release (External
reset)
- BIT is used for Peripheral
stability
ii) 16ms point after POR (POR only)
⑦
-Normal operation
6.6 External RESETB Input
The External RESETB is the input to a Schmitt trigger. A reset in accomplished by holding the reset
pin low for at least 7us over, within the operating voltage range and oscillation stable, it is applied, and
the internal state is initialized. After reset state becomes ‘1’, it needs the stabilization time with 16ms
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and after the stable state, the internal RESET becomes ‘1’. The Reset process step needs 5 oscillator
clocks. And the program execution starts at the vector address stored at address 0000H.
1
2
3
4
5
OSC
RESETB
Release
Internal
RESETB
Release
ADDRESS
BUS
?
?
CORE
BUS
?
Stabilization Time
TST = 16ms
00
?
?
02
RESET
Step
01
02
?
?
?
?
Process
Main Program
Figure 6.7 Timing Diagram after RESET
PRESCALER COUNT START
VDD
OSC START TIMING
Figure
6.8generating
Oscillatortime
generating
waveform
example
Note) as shown Figure 13-8, the
stable
is not included
in the
start-up time.
6.7 Brown Out Detector Processor
The Z51F0410 MCU features an On-chip Brown-out detection circuit for monitoring the VDD level
during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected
by BODLS[1:0] bit to be 1.6V, 2.5V, 3.6V or 4.3V. In the STOP mode, this will contribute significantly
to the total current consumption. So to minimize the current consumption, the BODEN bit is set to off
by software.
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STOP_MODE
External VDD
BODLS[1:0]
Brown Out
Detector
(BOD)
1
RESET_BODB
MUX
D
BODEN
DEBOUNCE
CLK
Q
0
CP
r
CPU
Write
SCLK
(System CLK)
D
Q
BODRF
(BOD Reset Flag)
CP
r
nPOR
Figure 6.9 Block Diagram of BOD
VDD
VBODMAX
VBODMIN
16ms
Internal
RESETB
VDD
VBODMAX
VBODMIN
t < 16ms
16ms
Internal
RESETB
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Figure 6.10 Internal Reset at the power fail situation
“H”
VDD
“H”
Internal nPOR
“H”
PAD RESETB (R20)
BOD_RESETB
BIT (for Config)
00 01 02 .. ..
F1
BIT (for Reset)
01 02 ..
00
.. 2F 30
F1
..
.. 3F 40 00 01 02 03
250us X 30h = about 12ms
Config Read
250us X 40h = about 16ms
RESET_SYSB
Main OSC Off
INT-OSC (128KHz)
INT-OSC 128KHz/32
INT-OSC 128KHz / 32 = 4KHz (250us)
Figure 6.11 Configuration timing when BOD RESET
6.7.1 Register Map
Table 6.3 BOD Register Map
Name
BODR
Address
Dir
0x86
Default
R/W
Description
81H
BOD Control Register
6.7.2 Reset Operation Register description
Reset control Register consists of the BOD Control Register (BODR).
6.7.3 Register description for Reset Operation
BODR (BOD Control Register) : 81H
7
6
5
4
3
2
1
0
PORF
EXTRF
WDTRF
OCDRF
BODRF
BODLS[1]
BODLS[0]
BODEN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PORF
Power-On Reset flag bit. The bit is reset by writing ‘0’ to this bit.
0
PS029502-0212
R/W
Initial value : 81H
No detection
PRELIMINARY
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Product Specification
1
EXTRF
WDTRF
OCDRF
BODRF
BODLS[1:0]
BODEN
PS029502-0212
Detection
External Reset flag bit. The bit is reset by writing ‘0’ to this bit or by Power
ON reset.
0
No detection
1
Detection
Watch Dog Reset flag bit. The bit is reset by writing ‘0’ to this bit or by
Power ON reset.
0
No detection
1
Detection
On-Chip Debug Reset flag bit. The bit is reset by writing ‘0’ to this bit or by
Power ON reset.
0
No detection
1
Detection
Brown-Out Reset flag bit. The bit is reset by writing ‘0’ to this bit or by
Power ON reset.
0
No detection
1
Detection
BOD level Voltage
BODLS1
BODLS0
Description
0
0
1.6V
0
1
2.5V
1
0
3.6V
1
1
4.3V
BOD operation
0
BOD disable
1
BOD enable
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7. On-chip Debug System
7.1 Overview
7.1.1 Description
On-chip debug System (OCD) of the Z51F0410 MCU can be used for programming the non-volatile
memories and on-chip debugging. Detailed descriptions for programming via the OCD interface can
be found in the following chapter.
Figure 7.1 shows a block diagram of the OCD interface and the On-chip Debug system.
7.1.2 Feature
• Two-wire external interface: 1-wire serial clock input, 1-wire bi-directional serial data bus
• Debugger Access to:
− All Internal Peripheral Units
− Internal data RAM
− Program Counter
− Flash and Data EEPROM Memories
• Extensive On-chip Debug Support for Break Conditions, Including
− Break Instruction
− Single Step Break
− Program Memory Break Points on Single Address
− Programming of Flash, EEPROM, Fuses, and Lock Bits through the two-wire Interface
− On-chip Debugging Supported by Dr.Choice®
• Operating frequency
Supports the maximum frequency of the target MCU
Target MCU internal circuit
Format
converter
DSCL
USB
DSDA
BDC
CPU
DBG
Control
DBG Register
Address bus
Internal data bus
User I/O
Code memory
-SRAM
-Flash
-EEPROM
Data memory
Peripheral
Figure 7.1 Block Diagram of On-chip Debug System
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7.2 Two-pin external interface
7.2.1 Basic transmission packet
 10-bit packet transmission using two-pin interface.
 1-packet consists of 8-bit data, 1-bit parity and 1-bit acknowledge.
 Parity is even of ‘1’ for 8-bit data in transmitter.
 Receiver generates acknowledge bit as ‘0’ when transmission for 8-bit data and its parity has no
error.
 When transmitter has no acknowledge (Acknowledge bit is ‘1’ at tenth clock), error process is
executed in transmitter.
 When acknowledge error is generated, host PC makes stop condition and transmits command
which has error again.
 Background debugger command is composed of a bundle of packet.
 Star condition and stop condition notify the start and the stop of background debugger command
respectively.
Figure 7.2 10-bit transmission packet
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7.2.2 Packet transmission timing
7.2.2.1 Data transfer
DSDA
LSB
acknowledgement
signal from receiver
LSB
acknowledgement
signal from receiver
DSCL
1
St
1
10
ACK
10
Sp
ACK
START
STOP
Figure 7.3 Data transfer on the twin bus
7.2.2.2 Bit transfer
DSDA
DSCL
data line
stable:
data valid
except Start and Stop
change
of data
allowed
Figure 7.4 Bit transfer on the serial bus
7.2.2.3 Start and stop condition
DSDA
DSDA
DSCL
DSCL
St
Sp
START condition
STOP condition
Figure 7.5 Start and stop condition
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7.2.2.4 Acknowledge bit
Data output
by transmitter
no acknowledge
Data output
By receiver
acknowledge
DSCL from
master
1
2
9
10
clock pulse for acknowledgement
Figure 7.6 Acknowledge on the serial bus
Acknowledge bit
transmission
Minimum 500ns
Acknowledge bit
transmission
wait HIGH
start HIGH
Host PC
DSCL OUT
Start wait
Target Device
DSCL OUT
Maximum 5 T SCLK
minimum 1 T SCLK
for next byte
transmission
DSCL
Internal Operation
Figure 7.7 Clock synchronization during wait procedure
7.2.3 Connection of transmission
Two-pin interface connection uses open-drain (wire-AND bidirectional I/O).
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VDD
pull -up
resistors
Rp
Rp
DSDA(Debugger Serial Data Line)
DSCL(Debugger Serial Clock Line)
VDD
DSCL
OUT
DSCL
IN
DSDA
OUT
DSDA
IN
VDD
DSCL
OUT
DSDA
OUT
DSDA
IN
DSCL
IN
Target Device(Slave)
Host Machine(Master)
Current source for DSCL to fast 0 to 1 transition in high speed mode
Figure 7.8 Connection of transmission
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8. Memory Programming
8.1 Overview
8.1.1 Description
The Z51F0410 MCU incorporates flash and data EEPROM memory to which a program can be
written, erased, and overwritten while mounted on the board. Also, data EEPROM can be
programmed or erased in user program.
Serial ISP modes and byte-parallel ROM writer mode are supported.
8.1.2 Features
•
Flash Size : 4Kbytes
•
Single power supply program and erase
•
Command interface for fast program and erase operation
•
Up to 10,000 program/erase cycles at typical voltage and temperature for flash memory
•
Up to 100,000 program/erase cycles at typical voltage and temperature for data EEPROM
memory
•
Security feature
8.2 Flash and EEPROM Control and status register
Registers to control Flash and Data EEPROM are Mode Register (FEMR), Control Register (FECR),
Status Register (FESR), Time Control Register (FETCR), Address Low Register (FEARL), Address
Middle Register (FEARM), address High Register (FEARH) and Data Register (FEDR). They are
mapped to SFR area and can be accessed only in programming mode.
8.2.1 Register Map
Table 8-1 Flash and EEPROM Register Map
Name
Address
Dir
Default
Description
FEMR
EAH
R/W
00H
Flash and EEPROM Mode Register
FECR
EBH
R/W
03H
Flash and EEPROM Control Register
FESR
ECH
R/W
80H
Flash and EEPROM Status Register
FETCR
EDH
R/W
00H
Flash and EEPROM Time Control Register
FEARL
F2H
R/W
00H
Flash and EEPROM Address Low Register
FEARM
F3H
R/W
00H
Flash and EEPROM Address Middle Register
FEARH
F4H
R/W
00H
Flash and EEPROM Address High Register
FEDR
F5H
R/W
00H
Flash and EEPROM Data Register
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8.2.2 Register description for Flash and EEPROM
FEMR (Flash and EEPROM Mode Register) : EAH
7
6
5
4
3
2
1
0
FSEL
ESEL
PGM
ERASE
PBUFF
OTPE
VFY
FEEN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FSEL
ESEL
PGM
ERASE
PBUFF
OTPE
VFY
R/W
Initial value : 00H
Select flash memory.
0
Deselect flash memory
1
Select flash memory
Select data EEPROM
0
Deselect data EEPROM
1
Select data EEPROM
Enable program or program verify mode with VFY
0
Disable program or program verify mode
1
Enable program or program verify mode
Enable erase or erase verify mode with VFY
0
Disable erase or erase verify mode
1
Enable erase or erase verify mode
Select page buffer
0
Deselect page buffer
1
Select page buffer
Select OTP area instead of program memory
0
Deselect OTP area
1
Select OTP area
Set program or erase verify mode with PGM or ERASE
Program Verify: PGM=1, VFY=1
Erase Verify: ERASE=1, VFY=1
FEEN
Enable program and erase of Flash and data EEPROM. When inactive, it
is possible to read as normal mode
0
Disable program and erase
1
Enable program and erase
FECR (Flash and EEPROM Control Register) : EBH
7
6
5
4
3
2
1
0
AEF
AEE
EXIT1
EXIT0
WRITE
READ
nFERST
nPBRST
R/W
R/W
R/W
R/W
R/W
R/W
R/W
AEF
AEE
EXIT[1:0]
PS029502-0212
R/W
Initial value : 03H
Enable flash bulk erase mode
0
Disable bulk erase mode of Flash memory
1
Enable bulk erase mode of Flash memory
Enable data EEPROM bulk erase mode
0
Disable bulk erase mode of data EEPROM
1
Enable bulk erase mode of data EEPROM
Exit from program mode. It is cleared automatically after 1 clock
EXIT1
EXIT0
Description
0
0
Don’t exit from program mode
0
1
Don’t exit from program mode
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WRITE
READ
1
0
Don’t exit from program mode
1
1
Exit from program mode
Start to program or erase of Flash and data EEPROM. It is cleared
automatically after 1 clock
0
No operation
1
Start to program or erase of Flash and data EEPROM
Start auto-verify of Flash or data EEPROM. It is cleared automatically after
1 clock
0
No operation
1
Start auto-verify of Flash or data EEPROM
nFERST
Reset Flash or data EEPROM control logic. It is cleared automatically
after 1 clock
0
No operation
1
Reset Flash or data EEPROM control logic.
nPBRST
Reset page buffer with PBUFF. It is cleared automatically after 1 clock
PBUFF
nPBRST
Description
0
0
Page buffer reset
1
0
Write checksum reset
WRITE and READ bits can be used in program, erase and verify mode with FEAR registers. Read or writes for
memory cell or page buffer uses read and write enable signals from memory controller. Indirect address mode
with FEAR is only allowed to program, erase and verify
FESR (Flash and EEPROM Status Register) : ECH
7
6
5
4
3
2
1
0
PEVBSY
VFYGOOD
PCRCRD
ENCRYPT
ROMINT
WMODE
EMODE
VMODE
R
R/W
R/W
R/W
R/W
R
R
PEVBSY
VFYGOOD
PCRCRD
ENCRYPT
ROMINT
R
Initial value : 80H
Operation status flag. It is cleared automatically when operation starts.
Operations are program, erase or verification
0
Busy (Operation processing)
1
Complete Operation
Auto-verification result flag.
0
Auto-verification fails
1
Auto-verification successes
CRC Calculation Data Read Control
0
FEARH, FEARM, FEARL represents 24bit Checksum
1
FEARM, FEARL represent 16bit CRC result
Encryption Mode Control for PGM
0
Normal Data PGM Mode
1
Encryption PGM Mode
Flash and Data EEPROM interrupt request flag. Auto-cleared when
program/erase/verify starts. Active in program/erase/verify completion
0
No interrupt request.
1
Interrupt request.
WMODE
Write mode flag
EMODE
Erase mode flag
VMODE
Verify mode flag
FEARL (Flash and EEPROM address low Register) : F2H
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7
6
5
4
3
2
1
0
ARL7
ARL6
ARL5
ARL4
ARL3
ARL2
ARL1
ARL0
R/W
R.W
R.W
R.W
R.W
R.W
R.W
ARL[7:0]
R.W
Initial value : 00H
Flash and EEPROM address low
CHKSUM[7:0] Checksum Result from auto verify mode (PCRCRD==0)
CRC[7:0]
CRC Result from auto verify mode (PCRCRD==1)
FEARM (Flash and EEPROM address middle Register) : F3H
7
6
5
4
3
2
1
0
ARM7
ARM6
ARM5
ARM4
ARM3
ARM2
ARM1
ARM0
R/W
R.W
R.W
R.W
R.W
R.W
R.W
ARM[7:0]
R.W
Initial value : 00H
Flash and EEPROM address middle
CHKSUM[15:8] Checksum Result from auto verify mode
CRC[15:8]
CRC Result from auto verify mode (PCRCRD==1)
FEARH (Flash and EEPROM address high Register) : F4H
7
6
5
4
3
2
1
0
ARH7
ARH6
ARH5
ARH4
ARH3
ARH2
ARH1
ARH0
R/W
R.W
R.W
R.W
R.W
R.W
R.W
ARH[7:0]
R.W
Initial value : 00H
Flash and EEPROM address high
CHKSUM[23:16] Checksum Result from auto verify mode
FEAR registers are used for program, erase and auto-verify. In program and erase mode, it is page
address and ignored the same least significant bits as the number of bits of page address. In autoverify mode, address increases automatically by one.
FEARs are write-only register. Reading these registers returns 24-bit checksum result
FEDR (Flash and EEPROM data control Register) : F5H
7
6
5
4
3
2
1
0
FEDR7
FEDR6
FEDR5
FEDR4
FEDR3
FEDR2
FEDR1
FEDR0
W
W
W
W
W
W
W
FEDR[7:0]
W
Initial value : 00H
Flash and EEPROM data
Data register. In no program/erase/verify mode, READ/WRITE of FECR read or write data from
EEPROM or Flash to this register or from this register to Flash or EEPROM.
The sequence of writing data to this register is used for EEPROM program entry. The mode entrance
sequence is to write 0xA5 and 0x5A to it in order.
FETCR (Flash and EEPROM Time control Register) : EDH
7
6
5
4
3
2
1
0
TCR7
TCR6
TCR5
TCR4
TCR3
TCR2
TCR1
TCR0
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Product Specification
R/W
R/W
R/W
TCR[7:0]
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
Flash and EEPROM Time control
Program and erase time is controlled by setting FETCR register. Program and erase timer uses 10bit counter. It increases by one at the edge of 128KHz clock (fFETCR). It is cleared when program or
erase starts. Timer stops when 10-bit counter is same to FETCR. PEVBSY is cleared when program,
erase or verify start and set when program, erase or verify stop.
Maximum program/erase time: 1/fFETCR * 1024 = 8ms (1/fFETCR = 7.8us @128KHz clock)
In the case of 50% of error rate of counter source clock, program or erase time are 4~12ms
* Program/erase time calculation
for page write or erase, Tpe = (TCON+1) * 2 * 1/fFETCR
for bulk erase, Tbe = (TCON+1) * 4 * 1/fFETCR
※ Recommended program/erase time (FETCR = FFh)
Min
Typ
Max
Unit
program/erase time
2
4
6
ms
bulk erase time
4
8
12
ms
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Z51F0410
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8.3 Memory map
8.3.1 Flash Memory Map
Program memory uses 4-Kbyte of Flash memory. It is read by byte and written by byte or page. One
page is 32-byte
FFFFh
P
R
O
G
R
A
M
F
E
A
R
pgm/ers/vfy
Flash
MUX
C
O
U
N
T
E
R
0FFFh
4KBytes
0000h
Figure 8.1 Flash Memory Map
15
14
13
12
11
10
9
8
7
6
5
PAGE ADDRESS
4
3
2
1
0
WORD ADDRESS
Program Memory
0xFFFF
Page 2048
0x1F
Page 2047
0x00
Page 1
0x0000
Page 0
* Page buffer size: 32Bytes
Figure 8.2 Address configuration of Flash memory
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8.3.2 Data EEPROM Memory Map
Data EEPROM memory uses 256-byte of EEPROM. It is read by byte and written by byte or page.
One page is 16-byte. It is mapped to external data memory of 8051
FFFFh
pgm/ers/vfy
D
P
T
R
F
E
A
R
L
MUX
XDATA Memory
00FFh
Data EEPROM
(256Bytes)
0000h
Figure 8.3 Data EEPROM memory map
15
14
13
12
11
10
9
8
7
6
5
4
3
PAGE ADDRESS
2
1
0
WORD ADDRESS
Data Memory
0xFFFF
0xF
Page 4096
Page 4095
0x0
Page 1
0x0000
*Page buffer size: 16Bytes
Page 0
Figure 8.4 Address configuration of data EEPROM
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Z51F0410
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8.4 Serial In-System Program Mode
Serial in-system program uses the interface of debugger which uses two wires. Refer to chapter 14
in details about debugger
8.4.1 Flash operation
Configuration(This Configuration is just used for follow description)
7
6
5
4
3
2
1
0
-
FEMR[4] & [1]
FEMR[5] & [1]
-
-
FEMR[2]
FECR[6]
FECR[7]
-
ERASE&VFY
PGM&VFY
-
-
OTPE
AEE
AEF
Master Reset
Page Buffer Reset
Page Buffer Load(0X00H)
Page Buffer Reset
Page Buffer Load
In the case of OTP
OTPE flag Set
In the case of OTP
OTPE flag Set
Erase
Erase Latency(500us)
Program
Page Buffer Reset
Pgm Latency(500us)
Configuration Reg. setting
Page Buffer Reset
Cell Read
Configuration Reg. setting
No
Pass/Fail?
Cell Read
Yes
Configuration Reg. Clear
Pass/Fail?
Figure 8.5 The sequence of page program and erase of Flash memory
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Master Reset
Page Buffer Reset
Page Buffer Load
Configuration Reg.<0> Set
Erase
Erase Latency(500us)
Page Buffer Reset
Configuration Reg.<0> clear
Reg.<6:5> setting
Cell Read
Pass/Fail?
Figure 8.6 The sequence of bulk erase of Flash memory
8.4.1.1 Flash Read
Step 1. Enter OCD(=ISP) mode.
Step 2. Set ENBDM bit of BCR.
Step 3. Enable debug and Request debug mode.
Step 4. Read data from Flash.
8.4.1.2 Enable program mode
Step 1. Enter OCD(=ISP) mode.1
Step 2. Set ENBDM bit of BCR.
Step 3. Enable debug and Request debug mode.
Step 4. Enter program/erase mode sequence.
2
(1) Write 0xAA to 0xF555.
(2) Write 0x55 to 0xFAAA.
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(3) Write 0xA5 to 0xF555.
1
Refer to how to enter ISP mode..
2
Command sequence to activate Flash write/erase mode. It is composed of sequentially writing data
of Flash memory.
8.4.1.3 Flash write mode
Step 1. Enable program mode.
Step 2. Reset page buffer. FEMR: 1000_0001 FECR:0000_0010
Step 3. Select page buffer. FEMR:1000_1001
Step 4. Write data to page buffer.(Address automatically increases by twin.)
Step 5. Set write mode. FEMR:1010_0001
Step 6. Set page address. FEARH:FEARM:FEARL=20’hx_xxxx
Step 7. Set FETCR.
Step 8. Start program. FECR:0000_1011
Step 9. Insert one NOP operation
Step 10. Read FESR until PEVBSY is 1.
Step 11. Repeat step2 to step 8 until all pages are written.
8.4.1.4 Flash page erase mode
Step 1. Enable program mode.
Step 2. Reset page buffer. FEMR: 1000_0001 FECR:0000_0010
Step 3. Select page buffer. FEMR:1000_1001
Step 4. Write ‘h00 to page buffer. (Data value is not important.)
Step 5. Set erase mode. FEMR:1001_0001
Step 6. Set page address. FEARH:FEARM:FEARL=20’hx_xxxx
Step 7. Set FETCR.
Step 8. Start erase. FECR:0000_1011
Step 9. Insert one NOP operation
Step 10. Read FESR until PEVBSY is 1.
Step 11. Repeat step2 to step 8 until all pages are erased.
8.4.1.5 Flash bulk erase mode
Step 1. Enable program mode.
Step 2. Reset page buffer. FEMR: 1000_0001 FECR:0000_0010
Step 3. Select page buffer. FEMR:1000_1001
Step 4. Write ‘h00 to page buffer. (Data value is not important.)
Step 5. Set erase mode. FEMR:1001_0001.
(Only main cell area is erased. For bulk erase including OTP area, select OTP area.(set FEMR
to 1000_1101.)
Step 6. Set FETCR
Step 7. Start bulk erase. FECR:1000_1011
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Step 9. Insert one NOP operation
Step 9. Read FESR until PEVBSY is 1.
8.4.1.6 Flash OTP area read mode
Step 1. Enter OCD(=ISP) mode.
Step 2. Set ENBDM bit of BCR.
Step 3. Enable debug and Request debug mode.
Step 4. Select OTP area. FEMR:1000_0101
Step 5. Read data from Flash.
8.4.1.7 Flash OTP area write mode
Step 1. Enable program mode.
Step 2. Reset page buffer. FEMR: 1000_0001 FECR:0000_0010
Step 3. Select page buffer. FEMR:1000_1001
Step 4. Write data to page buffer.(Address automatically increases by twin.)
Step 5. Set write mode and select OTP area. FEMR:1010_0101
Step 6. Set page address. FEARH:FEARM:FEARL=20’hx_xxxx
Step 7. Set FETCR.
Step 8. Start program. FECR:0000_1011
Step 9. Insert one NOP operation
Step 10. Read FESR until PEVBSY is 1.
8.4.1.8 Flash OTP area erase mode
Step 1. Enable program mode.
Step 2. Reset page buffer. FEMR: 1000_0001 FECR:0000_0010
Step 3. Select page buffer. FEMR:1000_1001
Step 4. Write ‘h00 to page buffer. (Data value is not important.)
Step 5. Set erase mode and select OTP area. FEMR:1001_0101
Step 6. Set page address. FEARH:FEARM:FEARL=20’hx_xxxx
Step 7. Set FETCR.
Step 8. Start erase. FECR:0000_1011
Step 9. Insert one NOP operation
Step 10. Read FESR until PEVBSY is 1.
8.4.1.9 Flash program verify mode
Step 1. Enable program mode.
Step 2. Set program verify mode. FEMR:1010_0011
Step 3. Read data from Flash.
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8.4.1.10 OTP program verify mode
Step 1. Enable program mode.
Step 2. Set program verify mode. FEMR:1010_0111
Step 3. Read data from Flash.
8.4.1.11 Flash erase verify mode
Step 1. Enable program mode.
Step 2. Set erase verify mode. FEMR:1001_0011
Step 3. Read data from Flash.
8.4.1.12 Flash page buffer read
Step 1. Enable program mode.
Step 2. Select page buffer. FEMR:1000_1001
Step 3. Read data from Flash.
8.4.2 Data EEPROM operation
Program and erase operation of Data EEPROM are executed by direct and indirect address mode.
Direct address mode uses external data area of 8051. Indirect address mode uses address register of
SFR area..
8.4.2.1 Data EEPROM Read
Step 1. Enter OCD(=ISP) mode.
Step 2. Set ENBDM bit of BCR.
Step 3. Enable debug and Request debug mode.
Step 4. Read data from Data EEPROM.
8.4.2.2 Enable program mode
1
Step 1. Enter OCD(=ISP) mode.
Step 2. Set ENBDM bit of BCR.
Step 3. Enable debug and Request debug mode.
Step 4. Enter program/erase mode sequence.2
(1) Write 0xA5 to FEDR.
(2) Write 0x5A to FEDR.
1
Refer to how to enter ISP mode..
2
Command sequence to activate data EEPROM write/erase mode. It is composed of sequentially
writing to data register(FEDR)
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8.4.2.3 EEPROM write mode
Step 1. Enable program mode.
Step 2. Reset page buffer. FEMR: 0100_0001 FECR:0000_0010
Step 3. Select page buffer. FEMR:0100_1001
Step 4. Write data to page buffer.(Address automatically increases by twin.)
Step 5. Set write mode. FEMR:0110_0001
Step 6. Set page address. FEARH:FEARM:FEARL=20’hx_xxxx
Step 7. Set FETCR.
Step 8. Start program. FECR:0000_1011
Step 9. Insert one NOP operation
Step 10. Read FESR until PEVBSY is 1.
Step 11. Repeat step2 to step 8 until all pages are written.
8.4.2.4 EEPROM page erase mode
Step 1. Enable program mode.
Step 2. Reset page buffer. FEMR: 0100_0001 FECR:0000_0010
Step 3. Select page buffer. FEMR:0100_1001
Step 4. Write ‘h00 to page buffer. (Data value is not important.)
Step 5. Set erase mode. FEMR:0101_0001
Step 6. Set page address. FEARH:FEARM:FEARL=20’hx_xxxx
Step 7. Set FETCR.
Step 8. Start erase. FECR:0000_1011
Step 9. Insert one NOP operation
Step 10. Read FESR until PEVBSY is 1.
Step 11. Repeat step2 to step 8 until all pages are erased.
8.4.2.5 EEPROM bulk erase mode
Step 1. Enable program mode.
Step 2. Reset page buffer. FEMR: 0100_0001 FECR:0000_0010
Step 3. Select page buffer. FEMR:0100_1001
Step 4. Write ‘h00 to page buffer. (Data value is not important.)
Step 5. Set erase mode. FEMR:0101_0001.
Step 6. Set FETCR
Step 7. Start bulk erase. FECR:0100_1011
Step 8. Insert one NOP operation
Step 9. Read FESR until PEVBSY is 1.
8.4.2.6 Data EEPROM program verify mode
Step 1. Enable program mode.
Step 2. Set program verify mode. FEMR:0110_0011
PS029502-0212
PRELIMINARY
167
Z51F0410
Product Specification
Step 3. Read data from Flash.
8.4.2.7 Data EEPROM erase verify mode
Step 1. Enable program mode.
Step 2. Set erase verify mode. FEMR:0101_0011
Step 3. Read data from Flash.
8.4.2.8 Data EEPROM page buffer read
Step 1. Enable program mode.
Step 2. Select page buffer. FEMR:0100_1001
Step 3. Read data from Flash.
8.4.3 Summary of Flash and Data EEPROM Program/Erase Mode
Table 8-2 Flash and Data EEPROM Operation Mode
Operation mode
Flash read
Description
Read cell by byte.
F
Flash write
Write cell by bytes or page.
L
Flash page erase
Erase cell by page.
A
Flash bulk erase
Erase the whole cells.
S
Flash program verify
Read cell in verify mode after programming.
H
Flash erase verify
Read cell in verify mode after erase.
Flash page buffer load
Load data to page buffer.
Data EEPROM read
Read cell by byte.
Data EEPROM write
Write cell by bytes or page.
Data EEPROM page erase
Erase cell by page.
Data EEPROM bulk erase
Erase the whole cells.
Data EEPROM program verify
Read cell in verify mode after programming.
Data EEPROM erase verify
Read cell in verify mode after erase.
Data EEPROM page buffer load
Load data to page buffer.
E
E
P
R
O
M
PS029502-0212
PRELIMINARY
168
Z51F0410
Product Specification
8.5 Parallel Mode
8.5.1 Overview
Parallel program mode transfers address and data by byte. 3-byte address can be entered by one
from the lease significant byte of address. If only LSB is changed, only one byte can be transferred.
And if the second byte is changed, the first and second byte can be transferred. Upper 4-bit of the
most significant byte selects memory to be accessed. Table 8-1 shows memory type. Address autoincrement is supported when read or write data without address
RESETB
PDATA[7:0]
nRD
nWR
nALE
Figure 8.7 Pin diagram for parallel programming
Table 8-3 The selection of memory type by ADDRH[7:4]
ADDRH[7:4]
Memory Type
0
0
0
0
Program Memory
0
0
0
1
External Memory
0
0
1
0
SFR
PS029502-0212
PRELIMINARY
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Z51F0410
Product Specification
8.5.2 Parallel Mode instruction format
Table 8-4 Parallel mode instruction format
Instruction
n-byte data read
with
3-byte
address
n-byte data write
with
3-byte
address
n-byte data read
with
2-byte
address
n-byte data write
with
2-byte
address
n-byte data read
with
1-byte
address
n-byte data write
with
1-byte
address
PS029502-0212
Signal
Instruction Sequence
nALE
L
nWR
L
H
L
H
L
H
H
H
H
H
H
H
H
H
nRD
H
H
H
H
H
H
L
H
L
H
L
H
L
H
PDATA
ADDRL
ADDRM
ADDRH
DATA0
DATA1
---
DATAn
nALE
L
L
L
H
H
H
H
nWR
L
H
L
H
L
H
L
H
L
H
L
H
L
H
nRD
H
H
H
H
H
H
H
H
H
H
H
H
H
H
PDATA
ADDRL
ADDRM
ADDRH
DATA0
DATA1
---
DATAn
nALE
L
L
H
H
H
H
H
nWR
L
H
L
H
H
H
H
H
H
H
H
H
H
H
nRD
H
H
H
H
L
H
L
H
L
H
L
H
L
H
PDATA
ADDRL
ADDRM
DATA0
DATA1
DATA2
---
DATAn
nALE
L
L
H
H
H
H
H
nWR
L
H
L
H
L
H
L
H
L
H
L
H
L
H
nRD
H
H
H
H
H
H
H
H
H
H
H
H
H
H
PDATA
ADDRL
ADDRM
DATA0
DATA1
DATA2
---
DATAn
nALE
L
H
H
H
H
H
H
nWR
L
H
H
H
L
H
L
H
L
H
L
H
L
H
nRD
H
H
L
H
H
H
H
H
H
H
H
H
H
H
PDATA
ADDRL
DATA0
DATA1
DATA2
DATA3
---
DATAn
nALE
L
H
H
H
H
H
H
nWR
L
H
L
H
L
H
L
H
L
H
L
H
L
H
nRD
H
H
H
H
H
H
H
H
H
H
H
H
H
H
PDATA
ADDRL
L
L
DATA0
H
DATA1
PRELIMINARY
H
DATA2
H
DATA3
---
H
DATAn
170
Z51F0410
Product Specification
8.5.3 Parallel Mode timing diagram
1 - byte read with 3 -byte address
Write
AL
Write
AM
1- byte read with 2 -byte address
Write
AH
Read
Data Out
TARS
Write
AL
Write
AM
2- byte read with 1-byte address
Read
Data Out
T ARH
Write
AL
Read
Data Out
Read
Data Out
DO
DO
TAWH
TAWS
nALE
nWR
address auto- increment
nRD
PDATA
AL(00H)
AM(F0H)
AH(00H)
DO
AL(00H)
AM(A0H)
Read @0F000H
DO
AL(01H)
Read @0A000H
Read @0A001H
Read @0A002H
Figure 8.8 Parallel Byte Read Timing of Program Memory
1 - byte write with 3 - byte address
Write
AL
Write
AM
Write
AH
1- byte write with 2 - byte address
Write
Data
T AWS
Write
AL
Write
AM
2- byte write with 1 - byte address
Write
Data
Write
AL
Read
Data Out
Write
Data
T AWH
nALE
address auto- increment
nWR
nRD
PDATA
AL(00H)
AM(F0H)
AH(00H)
DI(00H)
Write 0x00 @0x0F000
AL(00H)
AM(A0H)
DI(01H)
AL(01H)
Write 0x01 @0x0A000H
DI(02H)
Write 0x02 @0x0A001
DI(03H)
Write 0x03 @0x0A002
Figure 8.9 Parallel Byte Write Timing of Program Memory
Table 8-5 Control Pin Description
Pin
P01
P02
P03
P04
P05
Function
PDATA[0]
PDATA[1]
nALE
nWR
nRD
R05
R03
8.6 Mode entrance method of ISP and byte-parallel mode
8.6.1 Mode entrance method for ISP
TARGET MODE
PS029502-0212
R03
PRELIMINARY
171
Z51F0410
Product Specification
OCD(ISP)
‘hC
‘hC
‘hC
Release from worst 1.7V
Power on reset
Low period required during more 10us if external reset is used
PAD_RESETB (R02)
R05
R03
RESET_SYSB
Figure 8.10 ISP mode
8.6.2 Mode entrance of Byte-parallel
TARGET MODE
R0[7:6],R0[3],R0[1]
R0[7:6],R0[3],R0[1]
R0[7:6],R0[3],R0[1]
Byte-Parallel Mode
4‘h5
4‘hA
4‘h5
Release from worst 1.7V
Power on reset
Low period required during more 10us if external reset is used
PAD_RESETB (R02)
R05
Sample R0[7:6],R0[3],R0[1]at the falling edge of R05
R0[7],[6],[3],[1]
‘h5
‘hA
‘h5
RESET_SYSB
Figure 8.11 Byte-parallel mode (10pin package only)
PS029502-0212
PRELIMINARY
172
Z51F0410
Product Specification
8.7 Security
The Z51F0410 MCU provides one Lock bit which can be left unprogrammed (“0”) or can be
programmed (“1”) to obtain the additional features listed in Table 8-6. The Lock bit can only be erased
to “0” with the bulk erase command
Table 8-6 Security policy using lock-bits
USER MODE
LOCK
MODE
ISP/PMODE/BTMODE
DATA
EEPROM
Flash
OTP
LOC
KE
LOC
KF
R
W
P
E
B
E
R
W
P
E
B
E
R
0
0
X
X
X
X
O
O
O
O
0
1
X
X
X
X
O
O
O
O
1
0
X
X
X
X
O
O
O
1
1
X
X
X
X
O
O
O
DATA
EEPROM
Flash
OTP
W
P
E
B
E
R
W
P
E
B
E
R
W
P
E
B
E
R
W
P
E
B
E
X
X
X
X
O
O
O
O
O
O
O
O
O
O
O
O
X
X
X
X
X
X
X
O
O
O
O
O
O
X
X
O
O
X
X
X
X
O
◇
◇
◇
X
X
X
O
O
◇
◇
◇
O
X
X
X
X
X
X
X
◇
X
X
X
O
O
X
X
◇
•
LOCKF: Lock bit of Flash memory
•
LOCKE: Lock bit of data EEPROM
•
R: Read
•
W: Write
•
PE: Page erase
•
BE: Bulk Erase
•
O: Operation is possible.
•
X: Operation is impossible.
•
◇: When LOCKE is programmed, each operation can be done after data EEPROM is erased
with the bulk erase command.
PS029502-0212
PRELIMINARY
173
Z51F0410
Product Specification
9. Configure option
9.1 Configure option Control Register
FUSE_CONF (Pseudo-Configure Data) : 0x00:FDH
7
6
BITP[1:0]
R
R
5
4
3
2
1
0
SXINEN
XINENA
RSTDIS
ENCRYPT
LOCKE
LOCKF
R
R
R
R
R
BITP[1;0]
SXINEN
XINENA
RSTDIS
ENCRYPT
LOCKE
LOCKF
R
Initial value : 00H
BIT Period Control (Reset Release Time Control)
00
16ms
01
32ms
10
64ms
External Sub Oscillator Enable Bit
0
Sub OSC disable (default)
1
Sub OSC enable
External Main Oscillator Enable Bit
0
Main OSC disable (default)
1
Main OSC Enable
External RESETB disable Bit
0
External RESET enable
1
External RESET disable
Super Lock Enable Bit (Encryption Mode)
0
Super Lock Disable
1
Super Lock Enable (ROM Data Encrypted)
DATA memory LOCK bit
0
LOCK Disable
1
LOCK Enable
CODE memory LOCK bit
0
LOCK Disable
1
LOCK Enable
USEED0 (User Lock Private Key) : 0x06:D4H
7
6
5
4
-
-
-
-
3
2
1
-
-
-
0
USEED0[7:0]
USEED0[7:0]
Initial value : 00H
User Seed Key for Code Encryption
USEED0 is only available when ENCRYPT is 1
USEED1 (User Lock Private Key) : 0x07:D3H
7
6
5
4
3
2
1
-
-
-
0
USEED1[7:0]
-
-
USEED1[7:0]
PS029502-0212
-
Initial value : 00H
User Seed Key for Code Encryption
PRELIMINARY
174
Z51F0410
Product Specification
USEED1 is only available when ENCRYPT is 1
9.2 Serial ID
The Z51F0410 MCU supports 16 bytes of user serial ID for device identification. These ID are
mapped to SFR area. User can write SID to 0x0A~0x19 of OTP area and read SID of SFR by indirect
adressing mode.
SID is mappet to D6H and SIDA to D5H.
SIDX (Serial ID X) : D5H
7
6
5
4
-
-
-
-
3
2
1
-
-
-
0
SIDX[7:0]
SIDX[7:0]
Initial value : 00H
User Serial ID X X is from 0 to 15.
Table 9-1 Summary of SID
OTP address
Initial value
SID0
0x0A
00H
SID1
0x0B
00H
SID2
0x0C
00H
SID3
0x0D
00H
SID4
0x0E
00H
SID5
0x0F
00H
SID6
0x10
00H
SID7
0x11
00H
SID8
0x12
00H
SID9
0x13
00H
SID10
0x14
00H
SID11
0x15
00H
SID12
0x16
00H
SID13
0x17
00H
SID14
0x18
00H
SID15
0x19
00H
PS029502-0212
PRELIMINARY
175
Z51F0410
Product Specification
10. APPENDIX
10.1 Instruction Table
Instructions are either 1, 2 or 3 bytes long as listed in the ‘Bytes’ column below.
Each instruction takes either 1, 2 or 4 machine cycles to execute as listed in the following table. 1
machine cycle comprises 2 system clock cycles.
Mnemonic
ADD A,Rn
ADD A,dir
ADD A,@Ri
ADD A,#data
ADDC A,Rn
ADDC A,dir
ADDC A,@Ri
ADDC A,#data
SUBB A,Rn
SUBB A,dir
SUBB A,@Ri
SUBB A,#data
INC A
INC Rn
INC dir
INC @Ri
DEC A
DEC Rn
DEC dir
DEC @Ri
INC DPTR
MUL AB
DIV AB
DA A
Mnemonic
ANL A,Rn
ANL A,dir
ANL A,@Ri
ANL A,#data
ANL dir,A
ANL dir,#data
ORL A,Rn
ORL A,dir
ORL A,@Ri
ORL A,#data
ORL dir,A
ORL dir,#data
XRL A,Rn
XRL A,dir
XRL A, @Ri
XRL A,#data
XRL dir,A
XRL dir,#data
CLR A
CPL A
SWAP A
RL A
RLC A
RR A
PS029502-0212
ARITHMETIC
Description
Add register to A
Add direct byte to A
Add indirect memory to A
Add immediate to A
Add register to A with carry
Add direct byte to A with carry
Add indirect memory to A with carry
Add immediate to A with carry
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect memory from A with borrow
Subtract immediate from A with borrow
Increment A
Increment register
Increment direct byte
Increment indirect memory
Decrement A
Decrement register
Decrement direct byte
Decrement indirect memory
Increment data pointer
Multiply A by B
Divide A by B
Decimal Adjust A
LOGICAL
Description
AND register to A
AND direct byte to A
AND indirect memory to A
AND immediate to A
AND A to direct byte
AND immediate to direct byte
OR register to A
OR direct byte to A
OR indirect memory to A
OR immediate to A
OR A to direct byte
OR immediate to direct byte
Exclusive-OR register to A
Exclusive-OR direct byte to A
Exclusive-OR indirect memory to A
Exclusive-OR immediate to A
Exclusive-OR A to direct byte
Exclusive-OR immediate to direct byte
Clear A
Complement A
Swap Nibbles of A
Rotate A left
Rotate A left through carry
Rotate A right
PRELIMINARY
Bytes
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
4
4
1
Hex code
28-2F
25
26-27
24
38-3F
35
36-37
34
98-9F
95
96-97
94
04
08-0F
05
06-07
14
18-1F
15
16-17
A3
A4
84
D4
Bytes
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
Cycles
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
Hex code
58-5F
55
56-57
54
52
53
48-4F
45
46-47
44
42
43
68-6F
65
66-67
64
62
63
E4
F4
C4
23
33
03
176
Z51F0410
Product Specification
RRC A
Mnemonic
MOV A,Rn
MOV A,dir
MOV A,@Ri
MOV A,#data
MOV Rn,A
MOV Rn,dir
MOV Rn,#data
MOV dir,A
MOV dir,Rn
MOV dir,dir
MOV dir,@Ri
MOV dir,#data
MOV @Ri,A
MOV @Ri,dir
MOV @Ri,#data
MOV DPTR,#data
MOVC A,@A+DPTR
MOVC A,@A+PC
MOVX A,@Ri
MOVX A,@DPTR
MOVX @Ri,A
MOVX @DPTR,A
PUSH dir
POP dir
XCH A,Rn
XCH A,dir
XCH A,@Ri
XCHD A,@Ri
Rotate A right through carry
DATA TRANSFER
Description
Move register to A
Move direct byte to A
Move indirect memory to A
Move immediate to A
Move A to register
Move direct byte to register
Move immediate to register
Move A to direct byte
Move register to direct byte
Move direct byte to direct byte
Move indirect memory to direct byte
Move immediate to direct byte
Move A to indirect memory
Move direct byte to indirect memory
Move immediate to indirect memory
Move immediate to data pointer
Move code byte relative DPTR to A
Move code byte relative PC to A
Move external data(A8) to A
Move external data(A16) to A
Move A to external data(A8)
Move A to external data(A16)
Push direct byte onto stack
Pop direct byte from stack
Exchange A and register
Exchange A and direct byte
Exchange A and indirect memory
Exchange A and indirect memory nibble
BOOLEAN
Description
1
1
13
Bytes
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
Cycles
1
1
1
1
1
2
1
1
2
2
2
2
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
Hex code
E8-EF
E5
E6-E7
F8-FF
A8-AF
78-7F
F5
88-8F
85
86-87
75
F6-F7
A6-A7
76-77
90
93
83
E2-E3
F2-F3
F0
C0
23
C0
D0
C8-CF
C5
C6-C7
D6-D7
Mnemonic
CLR C
CLR bit
SETB C
SETB bit
CPL C
CPL bit
ANL C,bit
ANL C,/bit
ORL C,bit
ORL C,/bit
MOV C,bit
MOV bit,C
Clear carry
Clear direct bit
Set carry
Set direct bit
Complement carry
Complement direct bit
AND direct bit to carry
AND direct bit inverse to carry
OR direct bit to carry
OR direct bit inverse to carry
Move direct bit to carry
Move carry to direct bit
Bytes
1
2
1
2
1
2
2
2
2
2
2
2
Cycles
1
1
1
1
1
1
2
2
2
2
1
2
Hex code
C3
C2
D3
D2
B3
B2
82
B0
72
A0
A2
92
Mnemonic
ACALL addr 11
LCALL addr 16
RET
RETI
AJMP addr 11
LJMP addr 16
SJMP rel
JC rel
JNC rel
JB bit,rel
JNB bit,rel
JBC bit,rel
JMP @A+DPTR
JZ rel
BRANCHING
Description
Absolute jump to subroutine
Long jump to subroutine
Return from subroutine
Return from interrupt
Absolute jump unconditional
Long jump unconditional
Short jump (relative address)
Jump on carry = 1
Jump on carry = 0
Jump on direct bit = 1
Jump on direct bit = 0
Jump on direct bit = 1 and clear
Jump indirect relative DPTR
Jump on accumulator = 0
Bytes
2
3
1
1
2
3
2
2
2
3
3
3
1
2
Cycles
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Hex code
11→F1
12
22
32
01→E1
02
80
40
50
20
30
10
73
60
PS029502-0212
PRELIMINARY
177
Z51F0410
Product Specification
JNZ rel
CJNE A,dir,rel
CJNE A,#d,rel
CJNE Rn,#d,rel
CJNE @Ri,#d,rel
DJNZ Rn,rel
DJNZ dir,rel
Mnemonic
NOP
Jump on accumulator ≠ 0
Compare A,direct jne relative
Compare A,immediate jne relative
Compare register, immediate jne relative
Compare indirect, immediate jne relative
Decrement register, jnz relative
Decrement direct byte, jnz relative
MISCELLANEOUS
Description
No operation
Mnemonic
MOVC @(DPTR++),A
TRAP
2
3
3
3
3
3
3
2
2
2
2
2
2
2
70
B5
B4
B8-BF
B6-B7
D8-DF
D5
Bytes
1
Cycles
1
Hex code
00
ADDITIONAL INSTRUCTIONS (selected through EO[7:4])
Description
Bytes
M8051W/M8051EW-specific instruction supporting
1
software download into program memory
Software break command
1
Cycles
Hex code
2
A5
1
A5
In the above table, an entry such as E8-EF indicates a continuous block of hex opcodes used for 8
different registers, the register numbers of which are defined by the lowest three bits of the
corresponding code. Non-continuous blocks of codes, shown as 11→F1 (for example), are used for
absolute jumps and calls, with the top 3 bits of the code being used to store the top three bits of the
destination address.
The CJNE instructions use the abbreviation #d for immediate data; other instructions use #data.
PS029502-0212
PRELIMINARY
178
Z51F0410
Product Specification
10.2 Instructions on how to use the input port.

Error occur status

Using compare jump instructions with input port, it could cause error due to the timing conflict
inside the MCU.
Compare jump Instructions which cause potential error used with input port condition:

JB
bit, rel ; jump on direct bit=1
JNB
bit, rel ; jump on direct bit=0
JBC
bit, rel ; jump on direct bit=1 and clear
CJNE A, dir, rel
; compare A, direct jne relative
DJNZ dir, rel ; decrement direct byte, jnz relative

It is only related with Input port. Internal parameters, SFRs and output bit ports don’t cause an
y error by using compare jump instructions.
If input signal is fixed, there is no error in using compare jump instructions.


Error status example
while(1){
if (P00==1){ P10=1; }
zzz: JNB
080.0, xxx ; it can cause an error
else { P10=0; }
SETB
088.0
P11^=1;
SJMP
yyy
}
unsigned char ret_bit_err(void)
{
return !P00;
xxx: CLR
088.0
yyy: MOV
C,088.1
CPL
C
MOV
088.1,C
SJMP
zzz
MOV
R7, #000
JB
MOV
}
080.0, xxx ; it can cause an error
R7, #001
xxx: RET

Preventative measures (2 cases)
PS029502-0212
PRELIMINARY
179
Z51F0410
Product Specification

Do not use input bit port for bit operation but for byte operation. Using byte operation instead
of bit operation will not cause any error in using compare jump instructions for input port.
while(1){
zzz:
if ((P0&0x01)==0x01){ P10=1; }
else { P10=0; }
P11^=1;
}
MOV
A, 080
; read as byte
JNB
0E0.0, xxx
SETB
088.0
SJMP
yyy
xxx:
CLR
088.0
yyy:
MOV
C,088.1
CPL
C
MOV
088.1,C
SJMP
zzz
; compare
If you use input bit port for compare jump instruction, you have to copy the input port as internal
register or carry bit and then use compare jump instruction.
bit tt;
zzz: MOV
while(1){
C,080.0
; input port to C
MOV
020.0, C
if (tt==0){ P10=1;}
JB
020.0, xxx ; compare with internal register
else { P10=0;}
SETB
088.0
SJMP
yyy
tt=P00;
P11^=1;
}
PS029502-0212
xxx:
CLR
088.0
yyy:
MOV
C,088.1
CPL
C
MOV
088.1,C
SJMP
zzz
PRELIMINARY
; C to internal register
180
Z51F0410
Product Specification
181
Customer Support
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experiencing with our products, please visit Zilog’s Technical Support page at 
http://support.zilog.com.
To learn more about this product, find additional documentation, or to discover other facets about Zilog product offerings, please visit the Zilog Knowledge Base or consider participating in the Zilog Forum.
This publication is subject to replacement by a later edition. To determine whether a later
edition exists, please visit the Zilog website at http://www.zilog.com.
PS029502-0212
PRELIMINARY
Customer Support