H CAT24AC128 EE GEN FR ALO 128kbit I2C Serial CMOS EEPROM With Three Chip Address Input Pins LE A D F R E ETM FEATURES ■ 400kHz (2.5V) and 100kHz (1.8V) I2C bus ■ Commercial, industrial and extended compatibility automotive temperature ranges ■ 1.8 to 5.5 volt operation ■ Write protect feature – Entire array protected when WP at VIH ■ Low power CMOS technology ■ 1,000,000 program/erase cycles ■ Schmitt trigger filtered inputs for noise ■ 100 year data retention suppression ■ 64-Byte page write buffer ■ 8-Pin DIP, 8-Pin SOIC (JEDEC/EIAJ) or ■ Self-timed write cycle with auto-clear 14-pin TSSOP DESCRIPTION via the I2C bus serial interface and is available in 8-pin DIP, 8-pin SOIC or 14-pin TSSOP packages. Three device address inputs allows up to 8 devices to share a common 2-wire I2C bus. The CAT24AC128 is a 128kbit Serial CMOS EEPROM internally organized as 16,384 words of 8 bits each. Catalyst’s advanced CMOS technology substantially reduces device power requirements. The CAT24AC128 features a 64-byte page write buffer. The device operates BLOCK DIAGRAM PIN CONFIGURATION SOIC Package (J, K, W, X) DIP Package (P, L) EXTERNAL LOAD 1 2 3 4 A0 A1 A2 VSS 8 7 6 5 VCC WP SCL SDA A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA VCC WORD ADDRESS BUFFERS VSS TSSOP Package (U14, Y14) A0 A1 NC NC NC A2 VSS 1 14 2 3 13 12 4 11 5 10 6 9 7 8 SENSE AMPS SHIFT REGISTERS DOUT ACK COLUMN DECODERS 512 V CC WP NC NC NC SCL SDA SDA START/STOP LOGIC XDEC 256 E2PROM 256X512 CONTROL LOGIC WP PIN FUNCTIONS Pin Name DATA IN STORAGE Function SDA Serial Data/Address SCL Serial Clock WP Write Protect VCC +1.8V to +5.5V Power Supply VSS Ground A0 - A2 Device Address Inputs HIGH VOLTAGE/ TIMING CONTROL SCL A0 A1 A2 STATE COUNTERS SLAVE ADDRESS COMPARATORS * Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1028, Rev. I CAT24AC128 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(1) ........... –2.0V to +VCC + 2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Package Power Dissipation Capability (TA = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100mA RELIABILITY CHARACTERISTICS Symbol NEND Parameter (3) Typ. Max. Units 1,000,000 Cycles/Byte Data Retention 100 Years VZAP(3) ESD Susceptibility 2000 Volts ILTH(3)(4) Latch-up 100 mA TDR(3) Endurance Min. D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +5.5V, unless otherwise specified. Symbol Parameter Test Conditions ICC1 Power Supply Current - Read ICC2 Max Units fSCL = 100 KHz VCC = 5V 1 mA Power Supply Current - Write fSCL = 100 KHz VCC = 5V 3 mA ISB(5) Standby Current VIN = GND or VCC VCC = 5V 1 µA ILI Input Leakage Current VIN = GND to VCC 3 µA ILO Output Leakage Current VOUT = GND to VCC 3 µA VIL Input Low Voltage –1 VCC x 0.3 V VIH Input High Voltage VCC x 0.7 VCC + 0.5 V VOL1 Output Low Voltage (VCC = +3.0V) IOL = 3.0 mA 0.4 V VOL2 Output Low Voltage (VCC = +1.8V) IOL = 1.5 mA 0.5 V CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol Test Conditions Min Min Typ Typ Max Units CI/O(3) Input/Output Capacitance (SDA) VI/O = 0V 8 pF CIN(3) Input Capacitance (SCL, WP, A0, A1, A2) VIN = 0V 6 pF Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. (5) Maximum standby current (ISB) = 10µA for the Extended Automotive temperature range. Doc. No. 1028, Rev. I 2 CAT24AC128 A.C. CHARACTERISTICS VCC = +1.8V to +5.5V, unless otherwise specified Output Load is 1 TTL Gate and 100pF Read & Write Cycle Limits Symbol Parameter VCC = 1.8 V - 5.5 V Min VCC = 2.5 V - 5.5 V Max Min Units 400 kHz 0.9 µs FSCL Clock Frequency tAA SCL Low to SDA Data Out and ACK Out 0.1 tBUF(1) Time the Bus Must be Free Before a New Transmission Can Start 4.7 1.2 µs tHD:STA Start Condition Hold Time 4.0 0.6 µs tLOW Clock Low Period 4.7 1.2 µs tHIGH Clock High Period 4.0 0.6 µs tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 4.0 0.6 µs tHD:DAT Data In Hold Time 0 0 ns tSU:DAT Data In Setup Time 100 100 ns tR(1) SDA and SCL Rise Time 1.0 0.3 µs SDA and SCL Fall Time 300 300 ns tF (1) 100 Max 3.5 0.05 tSU:STO Stop Condition Setup Time 4.7 0.6 µs tDH Data Out Hold Time 100 50 ns tWR Write Cycle Time tSP Input Suppression (SDA, SCL) 5 5 ms 100 100 ns Power-Up Timing (1)(2) Symbol Parameter tPUR tPUW Min Typ Max Units Power-Up to Read Operation 1 ms Power-Up to Write Operation 1 ms Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. FUNCTIONAL DESCRIPTION The CAT24AC128 supports the I 2 C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24AC128 operates as a Slave device. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. 3 Doc. No. 1028, Rev. I CAT24AC128 PIN DESCRIPTIONS I2C BUS PROTOCOL SCL: Serial Clock The features of the I2C bus protocol are defined as follows: The serial clock input clocks all data transferred into or out of the device. (1) Data transfer may be initiated only when the bus is not busy. SDA: Serial Data/Address (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. START Condition WP: Write Protect This input, when tied to GND, allows write operations to the entire memory. When this pin is tied to Vcc, the entire memory is write protected. When left floating, memory is unprotected. The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24AC128 monitors the SDA and SCL lines and will not respond until this condition is met. A0, A1, A2: Device Address Inputs These inputs set the device address when cascading multiple devices. When these pins are left floating the default values are zeroes. A maximum of eight devices can be cascaded. Figure 1. Bus Timing STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. tHIGH tF tLOW tR tLOW SCL tSU:STA tHD:DAT tHD:STA tSU:DAT tSU:STO SDA IN tAA tBUF tDH SDA OUT Figure 2. Write Cycle Timing SCL SDA 8TH BIT BYTE n ACK tWR STOP CONDITION START CONDITION Figure 3. Start/Stop Timing SDA SCL START BIT Doc. No. 1028, Rev. I STOP BIT 4 ADDRESS CAT24AC128 DEVICE ADDRESSING When the CAT24AC128 begins a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT24AC128 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. The bus Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1010 (Fig. 5). The next three significant bits (A2, A1, A0) are the device address bits and define which device the master is accessing. Up to eight CAT24AC128 devices may be individually addressed by the system. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. WRITE OPERATIONS Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends two 8-bit address words that are to be written into the address pointers of the CAT24AC128. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The CAT24AC128 acknowledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to nonvolatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. After the Master sends a START condition and the slave address byte, the CAT24AC128 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT24AC128 then performs a Read or Write operation depending on the state of the R/W bit. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. Page Write The CAT24AC128 writes up to 64 bytes of data, in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed The CAT24AC128 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8bit byte. Figure 4. Acknowledge Timing SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ACKNOWLEDGE START Figure 5. Slave Address Bits 1 0 1 0 A2 A1 A0 R/W *A0, A1 and A2 must compare to its corresonding hard wired inputs (pins 1, 2 and 3). 5 Doc. No. 1028, Rev. I CAT24AC128 If the WP pin is tied to VCC, the entire memory array is protected and becomes read only. The CAT24AC128 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device’s failure to send an acknowledge after the first byte of data is received. to send up to 63 additional bytes. After each byte has been transmitted, CAT24AC128 will respond with an acknowledge, and internally increment the six low order address bits by one. The high order bits remain unchanged. If the Master transmits more than 64 bytes before sending the STOP condition, the address counter ‘wraps around’, and previously transmitted data will be overwritten. READ OPERATIONS The READ operation for the CAT24AC128 is initiated in the same manner as the write operation with one exception, that R/W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ. When all 64 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT24AC128 in a single write cycle. Acknowledge Polling Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, CAT24AC128 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If CAT24AC128 is still busy with the write operation, no ACK will be returned. If CAT24AC128 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation. Immediate/Current Address Read The CAT24AC128’s address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N+1. If N=E (where E=16383), then the counter will ‘wrap around’ to address 0 and continue to clock out data. After the CAT24AC128 receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8 bit byte requested. The master device does not send an acknowledge, but will generate a STOP condition. WRITE PROTECTION Selective/Random Address Read The Write Protection feature allows the user to protect against inadvertent programming of the memory array. Selective/Random READ operations allow the Master Figure 6. Byte Write Timing S T A R T BUS ACTIVITY: MASTER SDA LINE SLAVE ADDRESS BYTE ADDRESS A15–A8 A7–A0 S S T O P DATA P ** A C K *=Don't Care Bit A C K A C K A C K Figure 7. Page Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS A15–A8 A7–A0 S DATA DATA n+63 P ** A C K A C K A C K *=Don't Care Bit Doc. No. 1028, Rev. I DATA n S T O P 6 A C K A C K A C K A C K CAT24AC128 device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte addresses of the location it wishes to read. After CAT24AC128 acknowledges, the Master device sends the START condition and the slave address again, this time with the R/W bit set to one. The CAT24AC128 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. data. The CAT24AC128 will continue to output an 8-bit byte for each acknowledge sent by the Master. The operation will terminate when the Master fails to respond with an acknowledge, thus sending the STOP condition. The data being transmitted from CAT24AC128 is outputted sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT24AC128 address bits so that the entire memory array can be read during one operation. If more than E (where E=16383) bytes are read out, the counter will ‘wrap around’ and continue to clock out data bytes. Sequential Read The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT24AC128 sends the initial 8-bit byte requested, the Master will respond with an acknowledge which tells the device it requires more Figure 8. Current Address Read Timing S T A R T BUS ACTIVITY: MASTER SDA LINE SLAVE ADDRESS S T O P DATA P S N O A C K A C K 8 SCL SDA 9 8TH BIT DATA OUT NO ACK STOP 24AC128 F08 Figure 9. Random Address Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS S T A R T BYTE ADDRESS A15–A8 A7–A0 ** S A C K SLAVE ADDRESS S T O P DATA S A C K A C K P A C K N O A C K *=Don't Care Bit 7 Doc. No. 1028, Rev. I CAT24AC128 Figure 10. Sequential Current Address Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS DATA n DATA n+1 DATA n+2 S T O P DATA n+x S P A C K A C K A C K N O A C K A C K Figure 11. Sequential Random Address Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS S T A R T BYTE ADDRESS A15–A8 A7–A0 ** S A C K SLAVE ADDRESS DATA n DATA n+1 DATA n+2 S T O P DATA n+x S A C K P A C K A C K A C K A C K A C K N O A C K ORDERING INFORMATION Rev A(2) 24AC128 Die Revision Blank: 2.5V - 5.5V 1.8: 1.8V - 5.5V L: PDIP (Lead-free, Halogen-free) X: SOIC, EIAJ (Lead-free, Halogen-free) W: SOIC, JEDEC (Lead-free, Halogen-free) Y: TSSOP (Lead-free, Halogen-free) GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating) GX: SOIC, EIAJ (Lead-free, Halogen-free, NiPdAu lead plating) GW: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating) GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating) Notes: (1) The device used in the above example is a CAT24AC128KI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage, Tape & Reel) (2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWA). For additional information, please contact your Catalyst sales office. Doc. No. 1028, Rev. I 8 CAT24AC128 8-LEAD 300 MIL WIDE PLASTIC DIP (P, L) 0.245 (6.17) 0.295 (7.49) 0.300 (7.62) 0.325 (8.26) 0.355 (9.02) 0.400 (10.16) 0.120 (3.05) 0.150 (3.81) 0.180 (4.57) MAX 0.015 (0.38) 0.110 (2.79) 0.150 (3.81) 0.100 (2.54) BSC 0.310 (7.87) 0.380 (9.65) 0.045 (1.14) 0.060 (1.52) 0.014 (0.36) 0.022 (0.56) Notes: 1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters. 8-LEAD 150 MIL WIDE SOIC (J, W) 0.1497 (3.80) 0.1574 (4.00) 0.1890 (4.80) 0.1968 (5.00) 0.2284 (5.80) 0.2440 (6.20) 0.0099 (0.25) X 45 0.0196 (0.50) 0.0075 (0.19) 0.0098 (0.25) 0.0532 (1.35) 0.0688 (1.75) 0 —8 0.050 (1.27) BSC 0.013 (0.33) 0.020 (0.51) 0.0040 (0.10) 0.0098 (0.25) 0.016 (0.40) 0.050 (1.27) Notes: 1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters. 9 Doc. No. 1028, Rev. I CAT24AC128 8-LEAD 210 MIL WIDE SOIC (K, X) 0.205 (5.20) 0.213 (5.40) 0.303 (7.70) 0.318 (8.10) 0.0267 (0.68) 0.0303 (0.77) 0.205 (5.15) 0.210 (5.35) 0.008 (0.20) 0.080 (2.03) MAX 4 REF 0.046 (1.17) 0.054 (1.37) 0.025 (0.65) 0.0137 (0.35) 0.0177 (0.45) Note: 1. All linear dimensions are in inches and parenthetically in millimeters. 14-LEAD TSSOP (U14, Y14) -D8 14 7.72 TYP 4.16 TYP 6.4 4.4 + 0.1 -B(1.78 TYP) 3.2 0.42 TYP 0.65 TYP 0.2 C B A 7 1 LAND PATTERN RECOMMENDATION ALL LEAD TIPS PIN #1 IDENT. SEE DETAIL A 1.1 MAX TYP 0.1 C ALL LEAD TIPS 0.09 - 0.20 TYP (0.9) -C0.10 + 0.05 TYP 0.65 TYP GAGE PLANE 0.19 - 0.30 TYP 0.3 M A B S C S 0.25 0 o- 8 o Dimension D Doc. No. 1028, Rev. I 0.6+0.1 Pkg Min Max 14 4.9 5.1 SEATING PLANE DETAIL A 10 REVISION HISTORY Date 07/7/2004 Rev. G 07/27/2004 06/23/2005 H I Reason Added Die Revision to Ordering Information Started revision history Updated DC Operating Characteristics table and notes Update Features Update Pin Functions Update Reliability Characteristics Update D.C. Operating Characteristics Update A.C. Characteristics Update Read Operations Update Figures 8, 9, 10 Add Figure 11 Update Ordering Information Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. 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Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: 1028 I 06/23/05