Dialog DA7211-01UA6 Ultra-low power stereo codec Datasheet

DA7211
Ultra-low power stereo codec
Company confidential
General description
DA7211 features a high fidelity and powerful 72 mW per channel headphone amplifier. The device
may be operated from a single 1.8 V supply. Total device consumption is only 2.5 mW which helps
extend music playback time for battery operated equipment.
The fully integrated fractional PLL has been designed to use minimal power while supporting a wide
range of input and output frequencies. Internal suppression circuits help maintain audio
synchronisation in the presence of system noise on the external clock.
Six analogue input pins allow multiple audio sources to be internally mixed, eliminating the need for
external switches. Both single-ended and fully-differential line and microphone inputs are supported
with built-in variable gain amplifiers to optimise the dynamic range prior to digitisation. This provides
hardware support for ambient noise cancellation.
The DA7211 provides two volume-controlled differential/single-ended stereo line-out drivers and
ground-centred stereo amplifiers to directly drive standard 3-wire 16 Ω headphones. For example the
dc coupled, dedicated pop-free drivers may be connected simultaneously to stereo headphones,
stereo speakers and a mono line out without external switches.
All filtering functions are performed digitally including 5-band EQ and a digital input AGC with
programmable attack and decay parameters. A configurable signal processing engine allows various
audio enhancements and effects such as acoustic filtering, transducer equalisation, wind noise
suppression and 3D sound
The multi-slot I2S/PCM interface supports all common sample rates between 8 and 96 kHz in master
or slave mode operation.
Key features
■ Stereo multi-bit Delta Sigma DAC with SNR
■ Audio serial data bus supports I2S,
100 dB ('A' weighted @ 48 kHz)
left/right justified, DSP and TDM modes
■ Stereo multi-bit Delta Sigma ADC with SNR
■ Stereo or mono differential microphone
96 dB ('A' weighted @ 48 kHz)
interface
■ Ultra low-power stereo headphone driver with ■ Programmable ultra-low noise bias supply for
electret microphones
□ Stereo DAC to HP playback power:
2.5 mW
■ Volume controlled stereo auxiliary inputs and
outputs supporting FM Radio and fixed gain
□ 2x58 mW output power (16 Ω)
speaker amplifiers
□ ‘Capless’ output via GND centred signals
■ Multi-mode audio routing and mixers
□ Four level charge pump with continuous
■ Pop & click suppression circuitry
tracking of audio signal (Class G)
■ ASSP DSP filter engine for digital audio
□ Short circuit protection
enhancements (acoustic filtering, wind noise
suppression, 5-band equaliser, 3D sound,
automatic gain control)
■ Support of 8, 11.025, 12, 16, 22.05, 24, 32,
44.1, 48 and 96 kHz sample rates
■ On-chip PLL with signal shaper and audio
Sample Rate Matching
■ 2-wire software control interface
■ Supports supply from single voltage
(1.8/2.5 V)
■ Extensive modular power control
■ Package: 36 bump WL-CSP 3x3 – 0.5 mm
pitch
Applications
■ Personal media players
■ Portable consumer devices
Datasheet
CFR0011-120-00 Rev 5
■ Music handsets
■ Personal navigation devices
Revision 3e
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© 2015 Dialog Semiconductor
DA7211
Ultra-low power stereo codec
Company confidential
Contents
General description ............................................................................................................................. 1
Key features ......................................................................................................................................... 1
Applications ......................................................................................................................................... 1
Contents ............................................................................................................................................... 2
Figures .................................................................................................................................................. 3
Tables ................................................................................................................................................... 4
1
Terms and definitions ................................................................................................................... 8
2
Block diagram ................................................................................................................................ 9
3
Pinout ........................................................................................................................................... 10
3.1 The 36-ball DA7211 device ................................................................................................. 12
4
Absolute maximum ratings ........................................................................................................ 13
5
Recommended operating conditions ........................................................................................ 13
6
Electrical characteristics ............................................................................................................ 14
7
Timing characteristics ................................................................................................................ 23
7.1 Digital audio interface timing - I2S/DSP (in master/slave mode) ........................................ 23
7.2 Digital audio control timing - 2-wire control timing .............................................................. 24
8
Functional description ................................................................................................................ 26
8.1 Stereo codec ....................................................................................................................... 26
8.1.1
Input signal chain ................................................................................................. 26
8.1.2
Microphone inputs ............................................................................................... 27
8.1.3
Auxiliary inputs ..................................................................................................... 27
8.1.4
Stereo audio ADC ................................................................................................ 28
8.1.5
Automatic level control (ALC) .............................................................................. 30
8.1.6
Noise gate ............................................................................................................ 32
8.2 Output signal chain ............................................................................................................. 32
8.2.1
Stereo audio DAC ................................................................................................ 32
8.2.2
Soft mute ............................................................................................................. 33
8.2.3
Output mixer and line-out amplifier ...................................................................... 34
8.2.4
Headphone amplifier ............................................................................................ 35
8.2.5
Ambient noise suppression ................................................................................. 37
8.2.6
Digital signal processing engine .......................................................................... 37
8.3 Programming the general purpose filter .............................................................................. 39
8.4 Hi-Fi recording ..................................................................................................................... 40
8.4.1
5-band equaliser for recording path ..................................................................... 40
8.4.2
Digital audio processing for the record path ........................................................ 42
8.5 Hi-Fi playback ..................................................................................................................... 43
8.5.1
5-band equaliser for playback path ..................................................................... 43
8.5.2
Digital audio processing for playback path .......................................................... 44
8.6 Telephone/Bluetooth voice recording/playback at low sample rates .................................. 45
8.6.1
Voice filtering for recording at low sample rates .................................................. 45
8.6.2
Voice filtering for playback at low sample rates .................................................. 46
8.6.3
Digital audio processing for phone applications .................................................. 48
9
INTERFACES................................................................................................................................ 49
Datasheet
CFR0011-120-00 Rev 5
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DA7211
Ultra-low power stereo codec
9.1
9.2
Company confidential
Digital audio interface (DAI) ................................................................................................ 49
9.1.1
Operation modes DAI interface ........................................................................... 49
9.1.2
Right justified mode ............................................................................................. 49
9.1.3
Left justified mode................................................................................................ 50
9.1.4
I2S mode ............................................................................................................. 50
9.1.5
DSP mode ........................................................................................................... 50
9.1.6
TDM mode ........................................................................................................... 50
9.1.7
Clocking schemes................................................................................................ 51
9.1.8
Master mode ........................................................................................................ 53
9.1.9
Programming master and 32 kHz mode – PLL enabled ..................................... 55
Slave mode ......................................................................................................................... 57
9.2.1
Conditions: ........................................................................................................... 57
9.2.2
Programming slave mode – PLL not enabled ..................................................... 57
9.2.3
Programming slave mode – PLL enabled ........................................................... 59
9.2.4
32 kHz master or slave mode .............................................................................. 61
9.2.5
Phase locked loop (PLL)...................................................................................... 61
9.2.6
Control interface .................................................................................................. 62
9.2.7
2-wire communication .......................................................................................... 62
9.2.8
Details of the 2-wire control bus protocol ............................................................ 63
10 Register definitions ..................................................................................................................... 65
10.1 Register map ....................................................................................................................... 65
10.2 Control and status registers ................................................................................................ 68
10.3 Codec registers .................................................................................................................. 70
10.4 GP filter engine ................................................................................................................... 89
10.5 ALC level controls ............................................................................................................... 99
11 Package information ................................................................................................................. 102
11.1 Package outlines ............................................................................................................... 102
11.2 Soldering information ........................................................................................................ 102
12 Ordering information ................................................................................................................ 102
13 Applications information .......................................................................................................... 103
13.1 Supporting information ...................................................................................................... 103
13.2 Minimum component recommendations ........................................................................... 103
13.3 General component suggestions ...................................................................................... 104
Figures
Figure 1: DA7211 block diagram ........................................................................................................... 9
Figure 2: DA7211 pad arrangement (bottom view ball side up) .......................................................... 10
Figure 3: DA7211 power supply topology ........................................................................................... 12
Figure 4: I2S/DSP timing diagram ....................................................................................................... 23
Figure 5: 2-wire control timing diagram ............................................................................................... 24
Figure 6: Typical microphone applications .......................................................................................... 27
Figure 7: ADC and DAC DC blocking (cut-off frequency setting ‘00’ to ‘11’, 16 kHz) ......................... 29
Figure 8: ADC pass band attenuation (audio mode, 48 kHz).............................................................. 29
Figure 9: ADC pass band suppression (audio mode, 48 kHz) ............................................................ 30
Figure 10: Operation of ALC................................................................................................................ 30
Figure 11: DAC DC blocking (cut-off frequency setting ‘00’ to ‘11’, 48 kHz) ....................................... 33
Figure 12: DAC pass band attenuation (audio mode, 48 kHz)............................................................ 34
Datasheet
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DA7211
Ultra-low power stereo codec
Company confidential
Figure 13: DAC pass band suppression (audio mode, 48 kHz) .......................................................... 34
Figure 14: DA7211 audio signal paths ................................................................................................ 35
Figure 15: Digital signal processing engine (simplified block diagram) .............................................. 38
Figure 16: Direct form I implementation of a second order IIR filter ................................................... 38
Figure 17: Band 5 (LP 50 Hz) frequency response at FS = 48 kHz .................................................... 41
Figure 18: Band 5 (BP 150 Hz) frequency response at FS = 48 kHz ................................................. 41
Figure 19: Band 5 (BP 500 Hz) frequency response at FS = 48 kHz ................................................. 41
Figure 20: Band 5 (BP 2500 Hz) frequency response at FS = 48 kHz ............................................... 42
Figure 21: Band 5 (HP 5000 Hz) frequency response at FS = 48 kHz ............................................... 42
Figure 22: Record only ........................................................................................................................ 43
Figure 23: Record with sound monitor ................................................................................................ 43
Figure 24: Stereo playback (for example, freefield headphone equalisation) ..................................... 44
Figure 25: Sound spatialiser for stereo speaker ................................................................................. 44
Figure 26: Voice mode recording high pass filter (cut-off frequency setting ‘000’ to ‘111’, 8 kHz) .... 45
Figure 27: Voice mode recording frequency response (setting ‘001’, 8 kHz) ..................................... 46
Figure 28: Voice mode recording stop band suppression (8 kHz) ...................................................... 46
Figure 29: Voice mode playback high-pass filter (cut-off frequency setting ‘000’ to ‘111’, 16 kHz) ... 47
Figure 30: Voice mode playback frequency response (setting ‘001’, 8 kHz) ...................................... 47
Figure 31: Voice mode playback stop band suppression (8 kHz) ....................................................... 48
Figure 32: Transmit (red), receive (green) and sidetone (blue) sound filtering for phone applications
............................................................................................................................................................. 48
Figure 33: Right justified format .......................................................................................................... 49
Figure 34: Left justified format ............................................................................................................. 50
Figure 35: I2S format ........................................................................................................................... 50
Figure 36: DSP format ......................................................................................................................... 50
Figure 37: TDM left justified format ..................................................................................................... 51
Figure 38: TDM DSP format ................................................................................................................ 51
Figure 39: PLL master mode start up sequence ................................................................................. 56
Figure 40: Non-PLL mode start-up sequence ..................................................................................... 59
Figure 41: PLL Slave mode start-up sequence ................................................................................... 61
Figure 42: PLL block diagram.............................................................................................................. 62
Figure 43: Schematic of a 2-wire control bus ...................................................................................... 62
Figure 44: 2-wire byte write (SI/DATA line) ......................................................................................... 63
Figure 45: Examples of 2-wire byte read (SI/DATA line) .................................................................... 63
Figure 46: Examples of 2-wire page read (SI/DATA line) ................................................................... 64
Figure 47: 2-wire page write (SI/DATA line) ........................................................................................ 64
Figure 48: 2-wire repeated write (SI/DATA line) ................................................................................. 64
Figure 49: 36 bump WL-CSP 0.5mm pitch package outline drawing ............................................... 102
Tables
Table 1: Pin description ....................................................................................................................... 10
Table 2: Absolute maximum ratings .................................................................................................... 13
Table 3: Recommended operating conditions ..................................................................................... 13
Table 4: Power dissipation table ......................................................................................................... 14
Table 5: Power consumption figures 1: ............................................................................................... 15
Table 6: Power consumption figures 2: ............................................................................................... 15
Table 7: Electrical characteristics: Microphone bias ........................................................................... 16
Table 8: Electrical characteristics: Input mixing units .......................................................................... 16
Table 9: Electrical characteristics: Analogue to digital converter (ADC) ............................................. 17
Table 10: Electrical characteristics: Digital to analogue converter (DAC) ........................................... 18
Table 11: Electrical characteristics: Line out and receiver amplifier ................................................... 19
Table 12: Electrical characteristics: Dynamic charge pump ................................................................ 20
Table 13: Electrical characteristics: Headphone amplifier .................................................................. 21
Table 14: Electrical characteristics: Phase locked loop (MCLK) ......................................................... 22
Table 15: Electrical characteristics: Digital I/O .................................................................................... 22
Table 16: I2S/DSP timing characteristics ............................................................................................ 23
Table 17: 2-wire control timing characteristics .................................................................................... 24
Datasheet
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DA7211
Ultra-low power stereo codec
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Table 18: Start-up times after setting SC_MST_EN = 1 ..................................................................... 25
Table 19: ADC digital high pass filter specifications ........................................................................... 28
Table 20: Permitted register values for ALC_NOIS (0x85 [5:0]) ......................................................... 31
Table 21: DAC digital high pass filter specifications ........................................................................... 33
Table 22: Headphone/OUT1 amplifier gain settings ........................................................................... 36
Table 23: GP filter section enable bits ................................................................................................. 39
Table 24: Band-equaliser corner frequencies ..................................................................................... 40
Table 25: 5-band-equaliser turn-over/centre frequencies ................................................................... 40
Table 26: Voice mode recording high pass filter specifications .......................................................... 45
Table 27: Voice mode playback high-pass filter specifications ........................................................... 47
Table 28: Internal system clock frequency .......................................................................................... 52
Table 29: Block enable and system standby bits ................................................................................ 52
Table 30: ADC and DAC clock frequencies ........................................................................................ 53
Table 31: Master mode PLL-DIV look up table ................................................................................... 54
Table 32: SRM mode PLL-DIV look up table ...................................................................................... 54
Table 33: PLL master mode register setting recommendations.......................................................... 55
Table 34: MCLK frequencies in non-PLL slave mode ......................................................................... 57
Table 35: Non-PLL slave mode and PLL master mode sample rate settings ..................................... 58
Table 36: SRM mode PLL division ratio settings ................................................................................ 60
Table 37: Slave mode PLL-enabled register setting recommendations ............................................. 60
Table 38: Register map ....................................................................................................................... 65
Table 39: CONTROL 0x01 .................................................................................................................. 68
Table 40: STATUS 0x02...................................................................................................................... 68
Table 41: STARTUP 1 0x03 ................................................................................................................ 69
Table 42: STARTUP 2 0x04 ................................................................................................................ 69
Table 43: STARTUP 3 0x05 ................................................................................................................ 70
Table 44: MIC_L 0x07 ......................................................................................................................... 70
Table 45: MIC_R 0x08......................................................................................................................... 71
Table 46: AUX1_L 0x09 ...................................................................................................................... 71
Table 47: AUX1_R 0x0A ..................................................................................................................... 71
Table 48: IN_GAIN 0x0C ..................................................................................................................... 72
Table 49: INMIX_L 0x0D ..................................................................................................................... 73
Table 50: INMIX_R 0x0E ..................................................................................................................... 73
Table 51: ADC_HPF 0x0F ................................................................................................................... 74
Table 52: ADC 0x10 ............................................................................................................................ 74
Table 53: ADC_EQ1_2 0x11 ............................................................................................................... 75
Table 54: ADC_EQ3_4 0x12 ............................................................................................................... 76
Table 55: ADC_EQ5 0x13 ................................................................................................................... 77
Table 56: DAC_HPF 0x14 ................................................................................................................... 78
Table 57: DAC_L 0x15 ........................................................................................................................ 78
Table 58: DAC_R 0x16........................................................................................................................ 79
Table 59: DAC_SEL 0x17 ................................................................................................................... 79
Table 60: SOFTMUTE 0x18 ................................................................................................................ 80
Table 61: DAC_EQ1_2 0x19 ............................................................................................................... 81
Table 62: DAC_EQ3_4 0x1A .............................................................................................................. 82
Table 63: DAC_EQ5 0x1B................................................................................................................... 83
Table 64: OUTMIX_L 0x1C ................................................................................................................. 83
Table 65: OUTMIX_R 0x1D................................................................................................................. 84
Table 66: OUT1_L 0x1E ...................................................................................................................... 84
Table 67: OUT1_R 0x1F ..................................................................................................................... 85
Table 68: HP_L_VOL 0x21.................................................................................................................. 85
Table 69: HP_R_VOL 0x22 ................................................................................................................. 86
Table 70: HP_CFG 0x23 ..................................................................................................................... 86
Table 71: ZEROX 0x24 ....................................................................................................................... 86
Table 72: DAI_SRC_SEL 0x25 ........................................................................................................... 87
Table 73: DAI_CFG1 0x26 .................................................................................................................. 87
Table 74: DAI_CFG2 0x27 .................................................................................................................. 87
Table 75: DAI_CFG3 0x28 .................................................................................................................. 88
Table 76: PLL_DIV1 0x29 ................................................................................................................... 88
Datasheet
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Ultra-low power stereo codec
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Table 77: PLL_DIV2 0x2A ................................................................................................................... 88
Table 78: PLL_DIV3 0x2B ................................................................................................................... 88
Table 79: PLL 0x2C ............................................................................................................................. 89
Table 80: GP1A A0L 0x2D .................................................................................................................. 89
Table 81: GP1A A0H 0x2E .................................................................................................................. 89
Table 82: GP1B A0L 0x2F................................................................................................................... 90
Table 83: GP1B A0H 0x30 .................................................................................................................. 90
Table 84: GP2A A0L 0x31 ................................................................................................................... 90
Table 85: GP2A A0H 0x32 .................................................................................................................. 90
Table 86: GP2B_A0L 0x33 .................................................................................................................. 90
Table 87: GP2B_A0H 0x34 ................................................................................................................. 90
Table 88: GP1C_A0L 0x35.................................................................................................................. 90
Table 89: GP1C_A0H 0x36 ................................................................................................................. 90
Table 90: GP1D_A0L 0x37.................................................................................................................. 90
Table 91: GP1D_A0H 0x38 ................................................................................................................. 90
Table 92: GP2C_A0L 0x39.................................................................................................................. 90
Table 93: GP2C_A0H 0x3A................................................................................................................. 91
Table 94: GP2D_A0L 0x3B ................................................................................................................. 91
Table 95: GP2D_A0H 0x3C ................................................................................................................ 91
Table 96: GP1A_A1L 0x3D ................................................................................................................. 91
Table 97: GP1A_A1L 0x3E ................................................................................................................. 91
Table 98: GP1B_A1L 0x3F.................................................................................................................. 91
Table 99: GP1B_A1H 0x40 ................................................................................................................. 91
Table 100: GP2A_A1L 0x41 ................................................................................................................ 91
Table 101: GP2A_A1H 0x42 ............................................................................................................... 91
Table 102: GP2B_A1L 0x43 ................................................................................................................ 91
Table 103: GP2B_A1H 0x44 ............................................................................................................... 91
Table 104: GP1C_A1L 0x45................................................................................................................ 92
Table 105: GP1C_A1H 0x46 ............................................................................................................... 92
Table 106: GP1D_A1L 0x47................................................................................................................ 92
Table 107: GP1D_A1H 0x48 ............................................................................................................... 92
Table 108: GP2C_A1L 0x49................................................................................................................ 92
Table 109: GP2C_A1H 0x4A .............................................................................................................. 92
Table 110: GP2D_A1L 0x4B ............................................................................................................... 92
Table 111: GP2D_A1H 0x4C .............................................................................................................. 92
Table 112: GP1A_A2L 0x4D ............................................................................................................... 92
Table 113: GP1A_A2H 0x4E ............................................................................................................... 92
Table 114: GP1B_A2L 0x4F................................................................................................................ 92
Table 115: GP1B_A2H 0x50 ............................................................................................................... 93
Table 116: GP2A_A2L 0x51 ................................................................................................................ 93
Table 117: GP2A_A2H 0x52 ............................................................................................................... 93
Table 118: GP2B_A2L 0x53 ................................................................................................................ 93
Table 119: GP2B_A2H 0x54 ............................................................................................................... 93
Table 120: GP1C_A2L 0x55................................................................................................................ 93
Table 121: GP1C_A2H 0x56 ............................................................................................................... 93
Table 122: GP1D_A2L 0x57................................................................................................................ 93
Table 123: GP1D_A2H 0x58 ............................................................................................................... 93
Table 124: GP2C_A2L 0x59................................................................................................................ 93
Table 125: GP2C_A2H 0x5A .............................................................................................................. 93
Table 126: GP2D_A2L 0x5B ............................................................................................................... 94
Table 127: GP2D_A2H 0x5C .............................................................................................................. 94
Table 128: GP1A_B1L 0x5D ............................................................................................................... 94
Table 129: GP1A_B1H 0x5E ............................................................................................................... 94
Table 130: GP1B_B1L 0x5F................................................................................................................ 94
Table 131: GP1B_B1H 0x60 ............................................................................................................... 94
Table 132: GP2A_B1L 0x61 ................................................................................................................ 94
Table 133: GP2A_B1H 0x62 ............................................................................................................... 94
Table 134: GP2B_B1L 0x63 ................................................................................................................ 94
Table 135: GP2B_B1H 0x64 ............................................................................................................... 94
Datasheet
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Ultra-low power stereo codec
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Table 136: GP1C_B1L 0x65................................................................................................................ 94
Table 137: GP1C_B1H 0x66 ............................................................................................................... 95
Table 138: GP1D_B1L 0x67................................................................................................................ 95
Table 139: GP1D_B1H 0x68 ............................................................................................................... 95
Table 140: GP2C_B1L 0x69................................................................................................................ 95
Table 141: GP2C_B1H 0x6A .............................................................................................................. 95
Table 142: GP2D_B1L 0x6B ............................................................................................................... 95
Table 143: GP2D_B1H 0x6C .............................................................................................................. 95
Table 144: GP1A_B2L 0x6D ............................................................................................................... 95
Table 145: GP1A_B2H 0x6E ............................................................................................................... 95
Table 146: GP1B_B2L 0x6F................................................................................................................ 95
Table 147: GP1B_B2H 0x70 ............................................................................................................... 95
Table 148: GP2A_B2L 0x71 ................................................................................................................ 96
Table 149: GP2A_B2H 0x72 ............................................................................................................... 96
Table 150: GP2B_B2L 0x73 ................................................................................................................ 96
Table 151: GP2B_B2H 0x74 ............................................................................................................... 96
Table 152: GP1C_B2L 0x75................................................................................................................ 96
Table 153: GP1C_B2H 0x76 ............................................................................................................... 96
Table 154: GP1D_B2L 0x77................................................................................................................ 96
Table 155: GP1D_B2H 0x78 ............................................................................................................... 96
Table 156: GP2C_B2L 0x79................................................................................................................ 96
Table 157: GP2C_B2H 0x7A .............................................................................................................. 96
Table 158: GP2D_B2L 0x7B ............................................................................................................... 96
Table 159: GP2D_B2H 0x7C .............................................................................................................. 97
Table 160: GPF_SRC1 0x7D .............................................................................................................. 97
Table 161: GPF_SRC2 0x7E .............................................................................................................. 98
Table 162: DSP_CFG 0x7F................................................................................................................. 98
Table 163: CHIP_ID 0x81.................................................................................................................... 99
Table 164: INTERFACE 0x82 ............................................................................................................. 99
Table 165: ALC_MAX 0x83 ................................................................................................................. 99
Table 166: ALC_MIN 0x84 .................................................................................................................. 99
Table 167: ALC_NOIS 0x85 ................................................................................................................ 99
Table 168: ALC_ATT 0x86 .................................................................................................................. 99
Table 169: ALC_REL 0x87 ................................................................................................................ 100
Table 170: ALC_DEL 0x88 ................................................................................................................ 100
Table 171: A_HID_UNLOCK 0x8A .................................................................................................... 100
Table 172: A_TST_UNLOCK 0x8B ................................................................................................... 100
Table 173: A_PLL0 0x8F ................................................................................................................... 100
Table 174: A_PLL1 0x90 ................................................................................................................... 100
Table 175: A_ADC0 0x95 .................................................................................................................. 101
Table 176: A_DAC0 0x96 .................................................................................................................. 101
Table 177: A_CPHP6 0xA2 ............................................................................................................... 101
Table 178: A_CP_MODE 0xA7 ......................................................................................................... 101
Table 179: Ordering information ........................................................................................................ 102
Datasheet
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Terms and definitions
ADC
ALC
ASSP
DAC
DAI
DMIC
DSP
FIR
I2C
I2S
IIR
GP
LDO
MCLK
PCM
PGA
PLL
PSRR
RDL
RC
SC
SDM
SNR
SRM
TDM
THD+N
VCO
WL-CSP
Datasheet
CFR0011-120-00 Rev 5
Analogue to Digital Converter
Automatic Level Control
Application Specific Standard Product
Digital to Analogue Converter
Digital Audio Interface
Digital microphone
Digital Signal Processor or Digital Signal Processing
Finite Impulse Response (Filter)
Inter-Integrated Circuit interface
Inter-IC Sound
Infinite Impulse Response (Filter)
General Purpose (Filter)
Low Dropout regulator
Master Clock
Pulse Code Modulation
Programmable Gain Amplifier
Phase Locked Loop
Power Supply Rejection Ratio
Redistribution Layer
Resistance-Capacitance
System Controller
Sigma Delta Modulator
Signal to Noise Ratio
Sample Rate Matching
Time Division Multiplexing
Total Harmonic Distortion plus Noise
Voltage-Controlled Oscillator
Wafer Level-Chip Scale Packaging
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Block diagram
OUT1P_L
+
Sidetone-Filter
OUT1 L
OUT1N_L
AUX1_L
A1 PGA L
+
IN PGA L
ADC L
DAC L
Receiver
HP_L
MICP_L
HP L
ADC
DIGITAL
FILTERS
Acoustic
Filtering,
Wind/Zoom
Noise
Suppression,
5 Band
Equaliser,
Automatic
Gain Control
+
M PGA L
MIC
-
DATOUT
MICN_L
FM
Radio
MICBIAS
DA7211
MICP_R
+
M PGA R
MIC
Headphones
DAC
DIGITAL
FILTERS
Digital Mixer,
Acoustic
Filtering,
5 Band
Equaliser,
3D Sound
-
HP R
HP_R
GROUND CENTRED
CLASS G
HEADPHONE
AMPLIFIERS
HPCSP
1uF
HPCF1P
1uF
HPCF1N
Charge
Pump
GNDCP
HPCF2P
1uF
MICN_R
1uF
HPCF2N
HPCSN
AUX1_R
A1 PGA R
+
IN PGA R
ADC R
Speaker
DAC R
OUT1P_R
100nF
+
OUT1 R
DA7202
100nF
OUT1N_R
PLL
MCLK
I2S/PCM
INTERFACE
GND
1uF
VMID
DACREF
VBG
ADCREF
VDDD
AVDD
VDDCP
WCLK
DATIN
DATOUT
CLK
SI
SK
1uF 100nF 1uF
AGND
CODEC CONTROL
INTERFACE
Figure 1: DA7211 block diagram
Datasheet
CFR0011-120-00 Rev 5
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DA7211
Ultra-low power stereo codec
3
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Pinout
A
VBG
AGND
OUT1N_R
DACREF
OUT1P_R
HPR
B
MICP_L
VMID
ADCREF
OUT1N_L
OUT1P_L
HPL
C
MICP_R
MICBIAS
AUX1_L
AVDD
HPCSP
HPCSN
D
AUX1_R
MICN_R
MICN_L
VDD
HPCF2N
HPCF2P
E
DATIN
DATOUT
GND
CLK
GNDCP
HPCF1N
F
MCLK
SK
SI
WCLK
VDDCP
HPCF1P
6
5
4
3
2
1
Figure 2: DA7211 pad arrangement (bottom view ball side up)
Table 1: Pin description
Pin no.
Pin name
Description
5A
AGND
Analogue ground
3C
AVDD
Analogue supply
3D
VDD
Digital and input supply
4C
AUX1_L
Left channel single-ended auxiliary input
6B
MICP_L
Left channel differential microphone +ve input
4D
MICN_L
Left channel differential microphone –ve input
5C
MICBIAS
Current supply for microphone
6C
MICP_R
Right channel differential microphone +ve input
5D
MICN_R
Right channel differential microphone -ve input
6D
AUX1_R
Right channel single-ended auxiliary input
6F
MCLK
Master clock input (reference to PLL)
6E
DATIN
I2S digital data input
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Ultra-low power stereo codec
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Pin no.
Pin name
Description
5E
DATOUT
I2S digital data output
5F
SK
Digital clock for 2-wire
4F
SI
2-wire input and open drain output
3E
CLK
Digital bit clock for I2S
3F
WCLK
Digital word clock for I2S
2F
VDDCP
Headphone charge pump supply
1F
HPCF1P
Head phone amp charge pump floating cap1 +ve
1E
HPCF1N
Head phone amp charge pump floating cap1 –ve
2E
GNDCP
Headphone and digital ground
1D
HPCF2P
Head phone amp charge pump floating cap2 +ve
2D
HPCF2N
Head phone amp charge pump floating cap2 –ve
1C
HPCSN
Head phone amp charge pump storage cap –ve
2C
HPCSP
Head phone amp charge pump storage cap +ve
1B
HPL
Left head phone amp output
1A
HPR
Right head phone amp output
4E
GND
Ground bump
3A
DACREF
Decoupling capacitor for DAC
2A
OUT1P_R
Differential or single ended +ve line out right
4A
OUT1N_R
Differential –ve line out right
2B
OUT1P_L
Differential or single ended +ve line out left
3B
OUT1N_L
Differential –ve line out left
4B
ADCREF
Decoupling capacitor for ADC
5B
VMID
Decoupling capacitor for VMID
6A
VBG
Decoupling capacitor for VBG
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Ultra-low power stereo codec
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The 36-ball DA7211 device
The VDDIO and the digital core supplies are joined in the RDL layer, so the internal LDO is unusable
and should remain disabled. Separating the digital supply voltages from the AVDD allows a digital
supply as low as 1.2 V to be used.
VDD
AVDD
Pin
Pin
3D
3C
VDDCP
VDDADC
VDDDAC
Pin
2F
XVDD
LDO
(off)
VDDIO
VDDIO
(1.2 to 2.5 V)
VDD
Digital Core
(1.2 to 2.5 V)
AVDD
(1.8 to 2.5 V)
VDDADC
(1.8 to 2.5 V)
VDDDAC
(1.8 to 2.5 V)
VDDCP
(1.5 to 2.5 V)
Figure 3: DA7211 power supply topology
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Absolute maximum ratings
Table 2: Absolute maximum ratings
Parameter
Description
Min
Max
Unit
Storage temperature
-40
+95
°C
Ta
Operating temperature
-40
+85
°C
AVDD
VDDCP
Power Supply Input
-0.3
2.75
V
Supply voltage all input pins
except power
-0.3
AVDD+
0.3
V
Maximum power dissipation
200
mW
Package thermal resistance
40
k/W
2
kV
ESD susceptibility
Human body model
Stresses beyond those listed under ‘Absolute maximum ratings’ may cause permanent damage to the
device. These are stress ratings only, so functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specification are not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note 1
5
Conditions (Note 1)
Recommended operating conditions
Table 3: Recommended operating conditions
Parameter
Description
Conditions
Operating temperature
Min
Typ
Max
Unit
-40
+85
°C
VDD
Supply voltage digital and
I/O
Min and max values can
accept +/-5% tolerances
1.2
2.5
V
AVDD
Supply voltage analogue
Min and max values can
accept +/-5% tolerances
1.8
2.5
V
VDDCP
Supply voltage headphone
Max value can accept +/5% tolerances
1.8
2.5
V
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Electrical characteristics
Table 4: Power dissipation table
Parameter
Note 2
Description
Conditions (Note 2)
All registers at default
values
Powerdown
Digital playback to lineout
Min
Typ
Max
Unit
6
µA
DACL/R to OUT1L/R
3.15
mW
Digital playback to HP no
load
DACL/R to HPL/R
quiescent
2.54
mW
Digital playback to HP with
load
DACL/R to HPL/R 16 Ω
load 0.1 mW
4.66
mW
Analogue bypass to
lineout
AUX1L/R to OUT1L/R
2.87
mW
Analogue bypass to HP no
load
AUX1L/R to HPL/R
quiescent
2.43
mW
Analogue bypass to HP
with load
AUX1L/R to HPL/R 16 Ω
load 0.1 mW
4.57
mW
Microphone stereo record
MICL/R to ADCL/R
2.38
mW
Mic one channel record
and digital playback to
lineout
MICR to ADCR
3.10
mW
Mic stereo record and
digital playback to HP no
load
MICL/R to ADCL/R and
DACL/R to HPL/R
quiescent
4.35
mW
Mic stereo record and
digital playback to HP with
load
MICL/R to ADCL/R and
DACL/R to HPL/R 16 Ω
load 0.1 mW
6.49
mW
SC_CLK_DIS, 0x03[7] = 1 for all measurements
VMID_BUFF_EN, 0x96[2:0] = 000 for all modes not using DAC
AVDD and VDDCP = 1.8 V. Internal regulator configured for 1.2 V, 0xB7 [5:4] = 11
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Table 5: Power consumption figures 1:
AVDD and VDDCP = 1.8 V (Note 3)
Current (mA)
DA7211
Power (mW)
AVDD
1.8 V
VDDCP
1.8 V
VDD
1.2 V
AVDD
VDDCP
VDD
Total
Powerdown
0.005
0
0.006
0.009
0
0.007
0.016
DACL/R to HPL/R quiescent no load
Class G On
0.303
0.191
0.686
0.545
0.344
0.823
1.712
DACL/R to HPL/R 16 Ω load 0.1 mW
Class G On
0.336
1.357
0.726
0.605
2.443
0.871
3.918
DACL/R to HPL/R "Love Comes
Around" 16 Ω
0.298
0.279
0.731
0.536
0.503
0.877
1.915
DACL/R to HPL/R "Love Comes
Around" 16 Ω & MIC2ADC
0.331
0.365
0.84
0.595
0.657
1.008
2.26
DACL/R to HPL/R "Love Comes
Around" 16 Ω & MIC2ADC & PLL
0.762
0.365
1.13
1.372
0.657
1.356
3.385
DACL/R to HPL/R "Love Comes
Around" 16 Ω & MIC2ADC &
MICBIAS (2 k load,1.5 V) & PLL
0.776
0.365
1.13
1.397
0.657
1.356
3.41
Table 6: Power consumption figures 2:
AVDD and VDDCP = 2.5 V (Note 3)
Current (mA)
DA7211
Power (mW)
AVDD
2.5 V
VDDCP
2.5 V
VDD
1.2 V
AVDD
VDDCP
VDD
Total
Powerdown
0.303
0.204
0.685
0.758
0.509
0.822
2.089
DACL/R to HPL/R quiescent no load
Class G On
0.336
1.416
0.724
0.839
3.54
0.869
5.248
DACL/R to HPL/R 16 Ω load 0.1 mW
Class G On
0.306
0.306
0.728
0.765
0.764
0.874
2.403
DACL/R to HPL/R "Love Comes
Around" 16 Ω
0.311
0.3
0.833
0.777
0.75
1
2.527
DACL/R to HPL/R "Love Comes
Around" 16 Ω & MIC2ADC
0.824
0.298
1.01
2.06
0.745
1.212
4.017
DACL/R to HPL/R "Love Comes
Around" 16 Ω & MIC2ADC & PLL
0.832
0.298
1.003
2.08
0.745
1.204
4.029
DACL/R to HPL/R "Love Comes
Around" 16 Ω & MIC2ADC &
MICBIAS (2 k load,1.5 V) & PLL
0.303
0.204
0.685
0.758
0.509
0.822
2.089
Note 3
Corinne Bailey Rae, ‘Love Comes Around’ 44.1 kHz, volume referenced to a 0.1 mW sine wave. The
gain from a pure sine wave input is adjusted to give 0.1 mW output. Power consumption
measurements are then made while playing the music track played at the same volume.
Datasheet
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Revision 3e
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Ultra-low power stereo codec
Company confidential
Test conditions: VDD=2.5 V, Ta=25°C, fs=48 kHz, 24-bit audio data unless specified otherwise
Table 7: Electrical characteristics: Microphone bias
Parameter
Description
Conditions
Min
Typ
Max
Unit
VBIAS
Bias Voltage
No load, AVDD = 2.5 V
No load, AVDD = 1.8 V
2.2
1.5
Programmable
2.3
1.6
V
IBIAS
Maximum Current
Voltage drop < 50 mV
PSRR with
respect to
AVDD
Power Supply Rejection
Ratio
20 Hz - 2 kHz
2 kHz - 20 kHz
VN
Output Noise Voltage
Capacitive Load
2
mA
70
50
IBIAS < 100 µA,
100 µA < IBIAS < 2 mA
dB
5
µVRMS
100
200
pF
Table 8: Electrical characteristics: Input mixing units
(MICP_L, MICN_L, AUX_L, MICP_R, MICN_R, AUX1_R)
Parameter
Description
Conditions
VMAX
Full-scale Input Signal
single-ended
differential
MIC-PGA=0 dB
IN-PGA=0 dB
RIN
Input resistance
0.8*AVDD
1.6*AVDD
Unit
VPP
12
15
18
6
variable
40
Frequency Response
+/- 0.5 dB
20
20k
Hz
Amplitude Ripple
20 Hz – 20 kHz
-0.5
0.5
dB
MIC-PGA
AUX1-PGA
-6
-48
24
21
dB
IN-PGA
-4.5
18
6
k
Programmable Gain Step
Size
MIC-PGA
Absolute Gain Accuracy
0 dB @ 1 kHz
-1.0
1.0
dB
Input Gain L/R-Mismatch
20 Hz – 20 kHz
-0.1
0.1
dB
Input Gain Step Error
20 Hz – 20 kHz
-0.1
0.1
dB
AUX1-PGA, IN-PGA
Inputs connected to GND
A-weighting input referred,
measured @ ADC output
5
6.5
AUX1 (Gain = 21 dB)
Power Supply Rejection
Ratio
dB
1.5
Mic (Gain = 42 dB)
Note 4
Max
AUX1
Input Noise Level
PSRR with
respect to
AVDD
Typ
Mic, single-ended
Programmable Gain
Note 4
VNOISE
Min
20 Hz - 2 kHz
2 kHz - 20 kHz,
single-ended input
80
70
µVRMS
dB
The gain describes the ratio of input and output signal level at the related amplifier stage (independent
of whether the connection is single ended or differential).
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Ultra-low power stereo codec
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Table 9: Electrical characteristics: Analogue to digital converter (ADC)
Parameter
Description
Conditions
Full-scale Input Signal
Corresponding digital level
0 dBFS
SNR
Signal to Noise Ratio
THD+N
THD+N
VMAX
Min
Unit
VPP
A-weighting, no input
selected
96
dB
Total Harmonic Distortion
Plus Noise
-1 dBFS
-89
dB
Total Harmonic Distortion
Plus Noise
-1 dBFS, 32 kHz PLL mode
-80
dB
90
dB
BPASS
Pass band
BSTOP
Stop band
fs  48 kHz
fs = 88.2/96 kHz
Pass band Ripple
Voice Mode
Music Mode
Stop band Attenuation
Voice Mode
Music Mode
Group delay
Voice Mode
Music Mode (Note 5)
fs= 88.2/96 kHz
Group delay mismatch
Between left and right
channel
Power Supply Rejection
Ratio
20 Hz - 2 kHz
2 kHz - 20 kHz
Note 5
Max
1.6*
AVDD
Channel separation
PSRR with
respect to
AVDD
Typ
0.56*fs
0.45*fs
kHz
7*fs
3.5*fs
kHz
+/-0.3
+/-0.1
dB
70
55
dB
4.3/fs
18/fs
9/fs
600
2
80
70
µs
µs
dB
5-band-equaliser disabled.
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Table 10: Electrical characteristics: Digital to analogue converter (DAC)
Parameter
Description
Conditions
Full-scale Output Signal
Corresponding digital level
0 dBFS
SNR
Signal to Noise Ratio
THD+N
THD+N
VMAX
Min
BSTOP
PSRR with
respect to
AVDD
Max
Unit
1.6*AV
DD
VPP
A weighting
102
dB
Total Harmonic Distortion
Plus Noise
-1 dBFS
-85
dB
Total Harmonic Distortion
Plus Noise
-1 dBFS, 32 kHz PLL mode
-80
dB
90
dB
Channel separation
BPASS
Typ
Pass band
Stop band
fs  48 kHz
fs = 88.2/96 kHz
Pass band Ripple
Voice Mode
Music Mode
Stop band Attenuation
Voice Mode
Music Mode
Group delay
Voice Mode
Music Mode
fs = 88.2/96 kHz
Group delay variation
0.56*fs
0.45*fs
kHz
7*fs
3.5*fs
kHz
±0.15
±0.1
dB
70
55
dB
650
µs
20 Hz to 20 kHz
1
µs
Group delay mismatch
Between left and right
channel
2
µs
Power Supply Rejection
Ratio
20 Hz - 2 kHz
2 kHz - 20 kHz
Datasheet
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4.8/fs
18.5/fs
9/fs
70
60
dB
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Ultra-low power stereo codec
Company confidential
Table 11: Electrical characteristics: Line out and receiver amplifier
(OUT1P_L, OUT1N_L, OUT1P_R, OUT1N_R)
Parameter
Description
Conditions
VMAX
Full-scale Input Signal
No load, single-ended
No load, differential
single-ended output mode
Load Impedance
differential output mode
Frequency Response
+/- 0.5 dB
Amplitude Ripple
20 Hz – 20 kHz
Programmable Gain
Typ
Max
0.8*AVDD
1.6 *AVDD
Unit
VPP
1

µH
200
pF
1

H
200
pF
20
20k
Hz
-0.5
0.5
dB
-54
15
dB
500
25
2k
32
Mute Attenuation
100
Programmable Gain Step
Size
1.5
dB
dB
Absolute Gain Accuracy
0 dB @ 1 kHz
-0.8
0.8
dB
Input Gain L/R-Mismatch
20 Hz – 20 kHz
-0.1
0.1
dB
Input Gain Step Error
20 Hz – 20 kHz
-0.1
0.1
dB
Signal to Noise Ratio
A weighting
VNOISE
Output Noise Level
THD+N
Total Harmonic Distortion
Plus Noise
PSRR with
respect to
AVDD
Min
Power Supply Rejection
Ratio
102
20 - 20 kHz, unweighted
gain < -15 dB
single-ended
differential
<5.5
<4.5
-1 dBFS, 44.1 kHz slave
mode non A-weighting
-90
dB
µV
20 Hz - 2 kHz
70
2 kHz - 20 kHz
single-ended output
47
dB
20 Hz - 2 kHz
2 kHz - 20 kHz
90
70
dB
differential output
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Table 12: Electrical characteristics: Dynamic charge pump
(HPCSP, HPCSN)
Parameter
Description
Conditions
VDDCSP
Positive dynamic supply
voltage
Positive dynamic supply
voltage
Min
Typ
Max
Unit
VDDCP
VDDCP/2
(VDDCP/3,
VDDCP/4)
VDDCSN
Negative dynamic supply
voltage
Negative dynamic supply
voltage
-VDDCP
-VDDCP/2
(-VDDCP/3,
-VDDCP/4)
Floating capacitors
1.0
µF
Storage capacitors
1.0
µF
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Table 13: Electrical characteristics: Headphone amplifier
(HPL, HPR)
Parameter
Description
Conditions
VMAX
Full-scale Output Signal
No load
Min
DC output offset
PMAX
Output Power per channel
Dynamic internal supply
voltages
IQ
Typ
VPP
100
µV
25
30
VDDCP = 2.5 V, THD <
0.1%, RL=16 Ω 1 kHz
50
58
Quiescent current per
channel
from VDDCP
Load Impedance
13 < RL < 
mW RMS
mW RMS
±VDD
±VDD/2
(±VDD/3
(±VDD/4)
100
13
uA
16
400
500
Frequency Response
+/- 0.5 dB
Amplitude Ripple
20 Hz – 20 kHz
Programmable Gain
SNR
VNOISE
THD+N
PSRR with
respect to
AVDD
Unit
1.6*VDD
CP
VDDCP = 1.8 V, THD <
0.1%, RL=16 Ω 1 kHz
VDD/3 or VDD/4 can
optionally be selected if two
flying caps are available
Max

µH
pF
20
20k
-0.5
0.5
dB
-54
15
dB
Mute Attenuation
100
dB
Programmable Gain Step
Size
1.5
dB
Absolute Gain Accuracy
0 dB @ 1 kHz
-0.8
0.8
dB
Input Gain L/R-Mismatch
20 Hz – 20 kHz
-0.1
0.1
dB
Input Gain Step Error
20 Hz – 20 kHz
-0.1
0.1
dB
Signal to Noise Ratio
A weighting, gain = 0 dB
100
Output Noise Level
20 to 20 kHz, unweighted,
gain < -15 dB
<4.5
Total Harmonic Distortion
Plus Noise
VDDCP = 1.8 V, -5 dBFS,
RL=16 Ω
-70
Power Supply Rejection
Ratio
20 Hz - 2 kHz
2 kHz - 20 kHz
Output power per channel
VDDCP=2.5 V, THD<1%,
RL=16 Ω, 1 kHz
Datasheet
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70
50
dB
µVrms
dB
dB
72
mW
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Ultra-low power stereo codec
Company confidential
Table 14: Electrical characteristics: Phase locked loop (MCLK)
Parameter
Description
Conditions
Input Jitter
Input Impedance
Max
Unit
cycle to cycle
35
ps
rms
100
ps
DC impedance > 10 MΩ
Min
300
0.5
Typ

1
2
pF
12.288
MHz
80
MHz
Interface mode (MCLK is 256 Fs, PLL off)
Fin
Input frequency
256 Fs
128 Fs (96 kHz)
11.289
Oscillator mode (MCLK from standard oscillator, PLL on)
10
Fin
Input frequency
32 kHz mode
VIN AC
32.768
kHz
I2S tracking range (SRM)
Maximum mismatch of
I2S word-clock
4
%
I2S clock drift
Maximum frequency drift
of I2S word clock
50
ppm/s
MCLK Shaper range
For AC coupling with
internal clock shaping
1000
mVPP
Max
Unit
300
500
Table 15: Electrical characteristics: Digital I/O
(Ta = -40 to +85ºC)
Parameter
Description
VIH
CLK, WCLK, DATIN, SK,
SI, PD, MCLK
Input High Voltage
0.7*VDD
CLK, WCLK, DATIN, SK,
SI, PD, MCLK,
-0.3
VIL
Conditions
Min
Typ
VDD
V
0.3*VDD
V
Input Low Voltage
VOH @
1 mA
CLK, WCLK, DATOUT
VOL @
1 mA
CLK, WCLK, DATOUT
Output Low Voltage
0.8*VDD
VDD
0
0.3
0.7*VDD
VDD
-0.3
0.3*VDD
Output High Voltage
MCLK
Input High Voltage
DC-coupled TTL signal
MCLK
Input Low Voltage
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V
V
V
V
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Ultra-low power stereo codec
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Timing characteristics
7.1
Digital audio interface timing - I2S/DSP (in master/slave mode)
T
WCLK
tdCW
tsW
tf
thW
thC
tr
tlC
CLK
tdWD
tdCD
DATOUT
tsD
thD
DATIN
Figure 4: I2S/DSP timing diagram
Table 16: I2S/DSP timing characteristics
(Ta = -40 to +85ºC)
Parameter
Description
Conditions
Min
Input impedance
DC impedance > 10 MΩ
300
1.0
Typ
Max
Unit
2.5
Ω
pF
T
CLK period
tr
CLK rise time
8
ns
tf
CLK fall time
8
ns
thC
CLK high period
40%
60%
T
tlC
CLK low period
40%
60%
T
tdCW
CLK to WCLK delay
-30%
+30%
T
tdCD
CLK to DATOUT delay
-30%
+30%
T
WCLK high time
thW
WCLK low time
tlW
75
ns
DSP mode
100%
T
Non-DSP mode
Word
length
T
DSP mode
100%
T
Non-DSP mode
Word
length
T
tsW
WCLK setup time
Slave mode
7
ns
thW
WCLK hold time
Slave mode
2
ns
tsD
DATIN setup time
7
ns
thD
DATIN hold time
2
ns
tdWD
DATOUT to WCLK delay
DATOUT is synchronised to CLK
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Digital audio control timing - 2-wire control timing
Figure 5: 2-wire control timing diagram
Table 17: 2-wire control timing characteristics
(Ta = -40 to +85ºC)
Parameter
Description
Conditions
Bus free time STOP to
START
Min
Typ
Max
1.3
Bus Line Capacitive load
Unit
µs
100
pF
400
kHz
Standard/Fast Mode
SK clock frequency
1
Bus free time STOP to
START
1.3
µs
Start condition set-up time
0.6
µs
STH
Start condition hold time
0.6
µs
CLKL
SK low time
1.3
µs
CLKH
SK high time
0.6
µs
2-wire SK and SI rise/fall
time
DST
SI set-up time
DHT
SI hold-time
TSS
Stop condition set-up time
300
ns
100
ns
0
ns
0.6
µs
High Speed Mode
SK clock frequency
1
1700
kHz
Start condition set-up time
160
ns
STH
Start condition hold time
160
ns
CLKL
SK low time
160
ns
CLKH
SK high time
60
ns
DST
TSS
HS-2-wire SK rise/fall time
40
ns
HS-2-wire SI rise/fall time
80
ns
SI set-up time
10
ns
SI hold-time
0
ns
Stop condition set-up time
16
ns
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Table 18: Start-up times after setting SC_MST_EN = 1
Source
Output
Comment
VBG
VBG voltage >90% with 1 µF
VBG capacitor
All analogue inputs and
DACL/R
HPL/R
Slave mode; 200 ms added
delay required
All analogue inputs and
DACL/R
HPL/R
All analogue inputs and
DACL/R
Min
Typ
Max
Unit
25
ms
200
ms
32 kHz PLL master mode;
200 ms added delay required
500
ms
OUT1L/R
Slave mode
250
ms
All analogue inputs
ADCL/R
Slave mode
200
ms
All analogue inputs
ADCL/R
32 kHz PLL master mode
600
ms
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Functional description
DA7211 is an ultra-low power audio codec with a true ground headphone, mixing capability and a
programmable ASSP filter engine. It offers Hi-Fi audio quality with class-leading power consumption
for portable media applications.
Featuring a high-efficiency headphone amplifier and a minimum supply voltage of 1.8 V, the ultra-low
2.5 mW power consumption extends music playback time for battery operated equipment.
The integrated PLL uses a FRACT-N PLL architecture that supports a large range of input and output
frequencies. This can accept standard mobile phone/USB system clock frequencies, thus enabling
audio data synchronisation when no master clock is readily available.
Eight analogue input pins allow multiple audio sources to be internally mixed, eliminating the need for
external switches. Both single-ended and fully-differential line and microphone inputs are supported
with built-in variable gain amplifiers to optimise dynamic range prior to digitisation. This allows a
diverse variety of analogue audio sources such as baseband voice, mobile TV, Wi-Fi and FM radio to
be managed.
Input and output mixers with stereo-to-mono conversion also support mono configurations such as
headset/baseband line outputs.
Three output drivers are available in the output stage of the DA7211. One output driver will directly
drive standard 3-wire 16 Ω headphones whilst the other two provide two adjustable, fully differential
stereo lineout channels. For example the dc-coupled, dedicated pop-free drivers may be connected
simultaneously to stereo headphones, stereo speakers and a mono line out without external
switches.
All filtering and sidetone functions are performed digitally including 5-band EQ and a digital input
AGC with programmable attack and decay parameters.
The multi-slot I2S/PCM interface supports all common sample rates between 8 and 96 kHz in master
or slave modes.
8.1
8.1.1
Stereo codec
Input signal chain
The DA7211 has three flexible stereo analogue inputs that can be set up as line inputs, microphone
inputs, or both. They can be configured as differential or single ended. Line inputs (AUX1_L/R) and
microphone outputs can be routed to the ADC or directly to the output mixers via a bypass path.
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Microphone inputs
The DA7211 includes two analogue microphone inputs, which can be used as a stereo or two mono
microphones. These can either be connected in (i) fully differential mode for improved common mode
noise rejection and (ii) single ended or in pseudo-differential (by connecting MICN to GND). The
larger signal should be always connected to MICPL or MICPR and the smaller should be connected
to MICNL or MICNR.
The microphone PGAs are enabled by the MIC_L_EN/MIC_R_EN controls (address 0x07/0x08,
(Table 44 and Table 45). For maximum flexibility each microphone channel includes an individual
gain setting MIC_L_VOL (address 0x7, Table 44), which have a range of -6 dB to +24 dB in 6 dB
steps. A maximum gain from microphone to ADC input of +42 dB can be selected with a resolution of
1.5 dB.
Figure 6: Typical microphone applications
Standard electret microphones can be supplied from an on chip microphone bias. This generates an
ultra-low noise voltage to feed several electret microphones with up to 2 mA. Depending on the
provided AVDD level, the bias voltage can be configured via MICBIAS_SEL (address 0x07, Table
44). If it is not needed then the microphone bias can be powered down using MICBIAS_EN (address
0x07, Table 44).
8.1.3
Auxiliary inputs
Standard analogue sources are supported via the stereo line inputs AUX1_L and AUX1_R. Mono
sound sources are intended to be connected to the right channel of AUX1. Each channel includes
individual gain settings of 48 to 21 dB in 1.5 dB steps using AUX1_L_VOL and AUX1_R_VOL
(address 0x09/0x0A, Table 46 and Table 47). A maximum gain from auxiliary to ADC input of +36 dB
with a resolution of 1.5 dB can be selected. The gain describes the overall input signal to output
signal ratio (independent whether the path is single ended or differential).
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Stereo audio ADC
DA7211 includes a low power 24 bit high quality stereo audio ADC, which uses a continuous time
delta-sigma modulator providing improved robustness against uncorrelated environmental noise. The
ADC supports sampling rates from 8 kHz to 96 kHz. A master clock has to be provided at MCLK
whenever the ADC or DAC are in operation.
Dependent on the intended recording path, the stereo ADC can power down one channel at a time
via controls ADC_L_EN and ADC_R_EN (address 0x10, Table 52) to provide optimal power
dissipation. To enable saturation free maximum signal-to-noise, the input levels of the ADC are
adjusted with input PGAs.
The inputs to left and right input mixers are controlled by the bits in the INMIX_L and INMIX_R
registers (addresses 0x0D and 0x0E, Table 49 and Table 50). Gain settings for the left and right
PGAs are controlled by INPGA_L_VOL and INPGA_R_VOL (address 0x0C, Table 48), with a range
of 4.5 dB to 18 dB with 1.5 dB resolution.
For smooth volume changes the gain update can be synchronised to signal zero crossings enabled
using INZX_L_EN and INZX_R_EN (address 0x24, Table 71). Disabling the left ADC saves power
for mono recordings of stereo input signals by using the analogue stereo to mono conversion from
the input mixer. This configuration requires setting the INPGA_L_VOL to 0 dB (‘0011’) and the
assertion of IN_R_IN_L (address 0x0E, Table 50).
The IIR filters are enabled using ADC_HPF_EN (address 0xF, Table 51, and see blocks ‘ADC HP’ in
Figure 15). The filters (typ. <2 Hz roll-off) are configurable by control ADC_HPF_F0 (address 0x0F,
Table 51) and, if enabled, will remove any DC offset from the input path. After Reset, the filters for
both channels are enabled by default. Enabling the high pass filter is especially important if the ADC
output is fed back into the DAC.
By default the ADC bias current is minimised, but it is possible to improve the THD+N performance of
the ADC by approximately 4 dB by increasing this current. The bias current is increased by setting
the ADC_T2 bit (address 0x95[3], Table 175).
Also by default the VMID buffer current is enabled for DAC operation, but this buffer is not required
for analogue only paths and for ADC only operation. The VMID bias current can be disabled by
setting the VMID_BUFF_EN bits (address 0x96[2:0], Table 176) and a significant power saving can
be made.
Table 19: ADC digital high pass filter specifications
Sampling
frequency
(kHz)
48
(KHZ)
00
01
10
11
2
4
8
16
44.1
1.8
3.7
7.3
14.7
32
1.3
2.7
5.3
10.7
24
1
2
4
8
22.05
0.9
1.8
3.7
7.3
16
0.7
1.3
2.7
5.3
12
0.5
1
2
4
11.025
0.4
0.9
1.8
3.7
8
0.3
0.7
1.3
2.7
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Figure 7: ADC and DAC DC blocking (cut-off frequency setting ‘00’ to ‘11’, 16 kHz)
Figure 8: ADC pass band attenuation (audio mode, 48 kHz)
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Figure 9: ADC pass band suppression (audio mode, 48 kHz)
8.1.5
Automatic level control (ALC)
For improved sound recordings of signals with a widely changing loudness the DA7211 offers an
automatic recording level control (ALC).
It is enabled via ALC_EN (address 0x10, Table 52) and monitors the analogue signal before it enters
the ADC and adapts the input gain to keep a constant recording volume irrespective of the analogue
input signal level.
Figure 10 (below) illustrates the operation of the ALC. It shows an input signal with high level. The
output level is reduced when its level is above the upper threshold, and increased when it falls below
the minimum threshold.
ALC Input
ALC MAX
level
ALC Gain
ALC
MIN
level
Release time
ALC Output
Attack time
Figure 10: Operation of ALC
If this absolute value of an analogue signal is greater than ALC_MAX (address 0x83, Table 165),
then the gain is ramped down at a rate determined by the ALC_ATT (address 0x86, Table 168).
If this absolute value is lower than a level set in ALC_MIN (address 0x84, Table 166), the gain is
ramped up at a rate determined by ALC_REL (address 0x87, Table 169).
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ALC_MAX needs to be greater than ALC_MIN (minimum delta 1.5 dB). The target level is best
achieved by setting these values close to each other. A wider delta allows for a larger input range,
and that will reduce the ALC activity. The value of ALC_REL is configured in increments of 4 sample
periods. The gain-ramping is performed inside the input PGA in steps of 1.5 dB. To prevent audible
clicks each analogue gain step is interpolated by 8 digital volume steps of 0.25 dB inside the ADC
(the rate refers to the intermediate steps inside the ADC). However, the level must be lower than
ALC_MIN for a time greater than the hold time in order for this gain increase to take place.
The hold time is determined by ALC_DEL (address 0x88, Table 170) in increments of ALC_REL
periods, which allows long hold periods to be programmed for a reduction of potential ‘gain pumping’
during dynamic signal content.
For ALC noise value, refer to Table 20.
Table 20: Permitted register values for ALC_NOIS (0x85 [5:0])
Dec
Bin
Hex
Level (dB)
Dec
Bin
Hex
Level (dB)
60
111100
3C
-0.5
29
011101
1D
-47
59
111011
3B
-2
28
011100
1C
-48.5
58
111010
3A
-3.5
27
011011
1B
-50
57
111001
39
-5
26
011010
1A
-51.5
56
111000
38
-6.5
25
011001
19
-53
55
110111
37
-8
24
011000
18
-54.5
54
110110
36
-9.5
23
010111
17
-56
53
110101
35
-11
22
010110
16
-57.5
52
110100
34
-12.5
21
010101
15
-59
51
110011
33
-14
20
010100
14
-60.5
50
110010
32
-15.5
19
010011
13
-62
49
110001
31
-17
18
010010
12
-63.5
48
110000
30
-18.5
17
010001
11
-65
47
101111
2F
-20
16
010000
10
-66.5
46
101110
2E
-21.5
15
001111
0F
-68
45
101101
2D
-23
14
001110
0E
-69.5
44
101100
2C
-24.5
13
001101
0D
-71
43
101011
2B
-26
12
001100
0C
-72.5
42
101010
2A
-27.5
11
001011
0B
-74
41
101001
29
-29
10
001010
0A
-75.5
40
101000
28
-30.5
9
001001
09
-77
39
100111
27
-32
8
001000
08
-78.5
38
100110
26
-33.5
7
000111
07
-80
37
100101
25
-35
6
000110
06
-81.5
36
100100
24
-36.5
5
000101
05
-83
35
100011
23
-38
4
000100
04
-84.5
34
100010
22
-39.5
3
000011
03
-86
33
100001
21
-41
2
000010
02
-86
32
100000
20
-42.5
1
000001
01
-86
31
011111
1F
-44
0
000000
00
-86
30
011110
1E
-45.5
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Examples for ALC_ATT (address 0x86, Table 168).
(fs=44.1 kHz; sample period = 22.67 µs)
Setting
ms per 1 dB step
11111111 (FF)
23.2
10111111 (BF)
17.4
01111111 (7F)
11.6
00111111 (3F)
5.8
00011111 (1F)
2.9
00001111 (0F)
1.5
00000100 (04)
0.5
Examples for ALC_REL (address 0x87,Table 169).
(fs=44.1 kHz; sample period = 22.67 µs)
Setting
ms per 1 dB step
11111111 (FF)
92.9
10111111 (BF)
69.7
01111111 (7F)
46.4
00111111 (3F)
23.2
00011111 (1F)
11.6
00001111 (0F)
5.8
00000100 (04)
0.5
8.1.6
Noise gate
A noise gate feature is provided to avoid ‘noise pumping’ where the gain of the channel is increased
to the maximum when there is no signal is present (i.e. only noise). If the level of the input signal
drops below the threshold configured inside control ALC_NOIS (address 0x85, Table 167) the
channel gain is held.
8.2
8.2.1
Output signal chain
Stereo audio DAC
The integrated stereo DAC is suitable for high quality audio playback of MP3 files and portable
multimedia files of all kinds. The DAC has individually enabled channels via controls DAC_L_EN and
DAC_R_EN (address 0x17, Table 59).
The DA7211 supports the option of individually phase inverted output signals using controls
DAC_L_INV (address 0x15, Table 57).and DAC_R_INV (address 0x16, Table 58).
A digital high pass filter for each DAC channel is implemented (configurable by control DAC_HPF_F0
(address 0x14, Table 56) that can be enabled via control DAC_HPF_EN (address 0x14, Table 56,
see blocks ‘DAC HP’ in Figure 15). After Reset, the high pass filters for both channels are enabled by
default.
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Table 21: DAC digital high pass filter specifications
Sampling
frequency
(kHz)
48
Cut-off frequency (Hz) at DAC_HPF_F0 setting
00
01
10
11
2
4
8
16
44.1
1.8
3.7
7.3
14.7
32
1.3
2.7
5.3
10.7
24
1
2
4
8
22.05
0.9
1.8
3.7
7.3
16
0.7
1.3
2.7
5.3
12
0.5
1
2
4
11.025
0.4
0.9
1.8
3.7
8
0.3
0.7
1.3
2.7
(KHZ)
Figure 11: DAC DC blocking (cut-off frequency setting ‘00’ to ‘11’, 48 kHz)
8.2.2
Soft mute
To improve the user’s perception of audio reconfigurations, the DAC channel signals may be soft
muted by asserting control SOFT_MUTE (address 0x18, Table 60). The soft mute function
attenuates the digital input to the DAC, ramping the gain down in steps of 0.1875 dB from the
nominal level to -77.25 dB, before completely muting the channel.
When SOFT_MUTE is released, the attenuation is set to -77.25 dB, and then ramped up to the initial
gain. Both left and right channels are muted simultaneously. The ramping speed is dependent on the
audio sample rate and can be configured by control MUTE_RATE (address 0x18, Table 60). Status
bits SOFTMUTED and MUTING may be read from the system status register (address 0x02,
Table 40).
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Figure 12: DAC pass band attenuation (audio mode, 48 kHz)
Figure 13: DAC pass band suppression (audio mode, 48 kHz)
8.2.3
Output mixer and line-out amplifier
For playback the output mixer has to be enabled via OUT1_L_EN and OUT1_R_EN (addresses
0x1C, Table 64 and 0x1D, Table 65). The audio signal can be mixed from all sources and listened to
via headphones/speakers and recorded simultaneously if required.
OUTMIX_L and OUTMIX_R (addresses 0x1C, Table 64 and 0x1D, Table 65) are independent of the
input path, thus allowing recording of a different audio signal when listening to stereo sources like FM
Radio or MP3 playback. The playback sound can be mixed with background or inverted background
microphone signals (side tone) to enable a basic headphone environmental noise reduction or to
compensate unwanted damping of environmental sound happening with sealed headphones.
Playback signals can be inverted individually for left and right channel via OUT_L_INV (address
0x1C, Table 64), OUT_R_INV (address 0x1D, Table 65) or for playback of signals from the DAC via
DAC_L_INV/DAC_R_INV (address 0x15, Table 57).
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A stereo to mono conversion can either be realised by the input or the output mixer. This allows
direct feeding of phone earpiece receivers, high power speaker amplifiers and other mono devices
with the complete audio content. Unused channels of the stereo line out can be switched off to
reduce power consumption using OUT1_L_EN (address 0x1E, Table 66) and OUT1_R_EN (address
0x1F, Table 67). The mixer allows listening to mono signals like baseband or Bluetooth voice also at
both channels of stereo headphones.
Each differential channel of OUT1 can alternatively be individually configured to be single ended via
OUT1_L_SE (address 0x1E, Table 66) and OUT1_R_SE (address 0x1F, Table 67). Typical earpiece
receivers with an impedance > 32 Ω can be driven directly in differential mode at all outputs. This
amplifier offers individual programmable volume control from +15 dB to –54 dB in 1.5 dB steps, then
mute for steps below -54 dB using controls OUT1_L_VOL (address 0x1E, Table 66) and
OUT1_R_VOL (address 0x1F, Table 67). For smooth volume changes, the gain update can be
synchronised to zero-crossing of the signal using OUTZX_L_EN and OUTZX_R_EN (address 0x24,
Table 71). If no zero-crossing is detected within 2048 sample periods, the gain change is applied
unconditionally. The left and right channels are synchronised independently.
AUX1_L
A1 PGA L
OUT1 L
0x09
0x1E
+
MICP_L
+
M PGA L
MICN_L
MICBIAS
-
INPUT
MIXER L
0x0D
+
DAC L
0x14 to 0x1B
OUTPUT
MIXER L
0x1C
HP L
HP_L
0x21
MICBIAS
+
IN PGA R
ADC R
0x0F to 0x13
DAC R
0x14 to 0x1B
+
0x0C
M PGA R
MICN_R
ADC L
0x0F to 0x13
0x0C
0x07
+
MICP_R
IN PGA L
OUT1P_L
OUT1N_L
0x08
INPUT
MIXER R
0x0E
OUTPUT
MIXER R
0x1D
HP R
HP_R
0x22
DIGITAL FILTERING
0x2D to 0x7F
AUX1_R
OUT1 R
A1 PGA R
PHASE LOCKED LOOP
0x29 to 0x2C
0x0A
I2S/PCM DIGTIAL AUDIO
INTERFACE
0x25 to 0x28
OUT1P_R
OUT1N_R
0x1F
DATIN
CLK
WCLK
DATOUT
MCLK
DA7211
Figure 14: DA7211 audio signal paths
8.2.4
Headphone amplifier
The headphone Class G amplifiers are enabled by controls HP_L_EN and HP_R_EN (address 0x23,
Table 70) and their output can be set to high impedance mode using HP_HIGHZ_L and
HP_HIGHZ_R (address 0x23, Table 70).
They offer 'true ground' technology, which allows cost and space optimisation by removing the need
for large capacitors in the headphone paths. This also enhances the bass performance, which is
typically reduced by conventional AC-coupling. In comparison to alternative approaches like
‘phantom ground’, the ‘true ground’ technology generates real ground-centred output signals, and
provides common GND as required for Mini-USB connectors and CEA-936-A compliant interfaces.
Integrated short-circuit protection enables a ‘resistors free’ connection to a standard audio jack to
achieve a maximum output power of up to 58 mW per channel (referenced to VDDCP). The output
mixing units enable the support of single-ended mono and stereo, as well as differential headphones
selected by OUT_R_INV (address 0x1D, Table 65).
Headphone load impedance is typically 16 Ω, but the paths can also be used as volume controlled
lineout signals for external speaker amplifiers and audio devices. The headphone Class G amplifiers
are supplied from the positive VDDCP rail via a capacitive charge pump that generates the negative
rail required for ‘true ground’ mode. For improved power efficiency it provides dynamically adjusted
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supply voltage levels VDD, VDD/2, VDD/3 and VDD/4, which are automatically adjusted by DA7211
from the average left and right level of the headphone audio signals see control HP_CFG (address
0x23, Table 70).
To minimise the number of external components the charge pump provides a restricted mode
enabled via HP_2CAP_MODE (address 0x23, Table 70), which removes the need for the second
flying cap (at pins HPCF2P and HPCF2N), but disables the VDD/3 and VDD/4 supply voltage levels.
Unlike conventional solutions DA7211 does not require any coupling capacitors at the ‘true ground’
headphone amplifier input. An embedded offset compensation circuit suppresses click and pop noise
during both start-up and dynamic supply-voltage adjustments.
Table 22: Headphone/OUT1 amplifier gain settings
GAIN
CODE
GAIN
CODE
MUTE
0x10
-19.5 dB
0x28
-54.0dB
0x11
-18.0 dB
0x29
-52.5dB
0x12
-16.5 dB
0x2A
-51.0dB
0x13
-15.0 dB
0x2B
-49.5dB
0x14
-13.5 dB
0x2C
-48.0dB
0x15
-12.0 dB
0x2D
-46.5dB
0x16
-10.5 dB
0x2E
-45.0dB
0x17
-9.0 dB
0x2F
-43.5dB
0x18
-7.5 dB
0x30
-42.0dB
0x19
-6.0 dB
0x31
-40.5dB
0x1A
-4.5 dB
0x32
-39.0dB
0x1B
-3.0 dB
0x33
-37.5dB
0x1C
-1.5 dB
0x34
-36.0dB
0x1D
0 dB
0x35
-34.5dB
0x1E
1.5 dB
0x36
-33.0dB
0x1F
3.0 dB
0x37
-31.5dB
0x20
4.5 dB
0x38
-30.0dB
0x21
6.0 dB
0x39
-28.5dB
0x22
7.5 dB
0x3A
-27.0dB
0x23
9.0 dB
0x3B
-25.5dB
0x24
10.5 dB
0x3C
-24.0dB
0x25
12.0 dB
0x3D
-22.5dB
0x26
13.5 dB
0x3E
-21.0dB
0x27
15.0 dB
0x3F
Table 22 relates to the registers shown below
●
●
●
●
HP_L_VOL: 0x21[5:0]
HP_R_VOL: 0x22[5:0]
OUT1_L_VOL: 0x1e[5:0]
OUT1_R_VOL: 0x1f[5:0]
To enable volume balance settings the gain of the headphone buffers can be programmed
independently for both channels by controls HP_L_VOL (addresses 0x21, Table 68) and HP_R_VOL
(addresses 0x22, Table 69) according to Table 22. The gain steps are 1.5 dB from +15 dB down to –
54 dB, and mute for the steps below -54 dB. Alternatively the channels’ gain settings can be
combined with bit STEREO_TRACK (address 0x23, Table 70) and controlled for both channels with
volume register HP_R_VOL (address 0x22, Table 69).
For smooth volume changes the gain update can be synchronised to audio signal zero-crossings by
enabling HPZX_L_EN and HPZX_R_EN (address 0x24, Table 71). If no zero-crossing is detected
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within 2048 sample periods, the gain change is applied unconditionally. The left and right channels
are synchronised independently.
The headphone outputs are supported by DC offset compensation circuitry to minimise any possible
pop and click artefacts during power up/down. To ensure sufficient time for the DC compensation
circuitry to operate, a delay of 200 ms must be added after SC_MST_EN (address 0x03, Table 41)
bit is enabled.
8.2.5
Ambient noise suppression
DA7211 supports stereo noise suppression by subtracting inverted noise signals from the AUX1
inputs at the headphone outputs. The noise signal must pass through the input PGA, be inverted and
then mixed with the outputs from the DAC. The signal at the AUX1 inputs for example, can be from
microphones picking up ambient noise at the user’s ears.
This mode is enabled via control NOISE_SUP (address 0x01 CONTROL, Table 39) and then offers a
modified headphones volume control via a combination of three gain stages:
a)
Headphones gain settings > 0 dB
All headphone gains settings > 0 dB will be applied to the headphone PGA, but the equivalent gain
will be synchronously subtracted from the input PGA to equalise the overall net gain in the ambient
noise signal path.
For sufficient range of operation, the starting values of INPGA_L_VOL and INPGA_R_VOL (address
0x0C, Table 48) must be configured >= 10.5 dB (settings ‘1010’ to ‘1111’) before enabling the noise
suppression mode.
b)
Headphones gain settings <= 0 dB
When DAC is selected to the headphone output any update of the gain less than or equal to 0 dB,
using controls HP_L_VOL/HP_R_VOL (address 0x21, Table 68 and address 0x22, Table 69), will be
implemented instead using the controls DAC_L_GAIN and DAC_R_GAIN (address 0x15, Table 57
and address 0x16, Table 58). If this were not the case then a large signal on AUX1 could cause
clipping at the headphone output.
For the ambient noise signals from the AUX1 path all headphones gain changes <= 0 dB will be
implemented using the settings of AUX1_L_VOL and AUX1_R_VOL (address 0x09, Table 46). To
allow the full minimum headphone volume of -54 dB, these AUX1_L_VOL and AUX1_R_VOL
controls need to be set to >= 6 dB (setting > 110101’b) before enabling the noise suppression mode.
NOTE – The ALC has to be disabled during noise suppression mode and it is recommended to
enable zero-crossing for gain updates at the headphone amplifier and the AUX1 PGA (see the
register ZEROX (address 0x24, Table 71)). Headphone volume changes should enable digital gain
ramping for DAC playback. The controls INPGA_L_VOL, INPGA_R_VOL, AUX1_L_VOL,
AUX1_R_VOL, DAC_L_GAIN, and DAC_R_GAIN should not be written to when noise suppression is
enabled.
8.2.6
Digital signal processing engine
The digital signal processing engine includes a configurable audio processor that offers flexible
routing and extensive audio enhancement and effects. Linear phase FIR filters perform the
interpolation and decimation for the required sigma-delta sample rates. Configurable high-pass
filtering (optionally enabled) removes any signal DC offset (see blocks ‘ADC HP’ and ‘DAC HP’ in
Figure 15) and offers 5-band equalisation during recording and sound playback.
Alternatively it can provide dedicated voice band filtering at samples rates  16 kHz (see blocks ‘ADC
IIR’ and ‘DAC IIR’ in Figure 15).
An additional general purpose (GP) filter engine offers up to eight second-order biquad filter stages
with configurable 16-bit coefficients, and supports flexible digital audio routing and mixing
arrangements. Figure 15 shows some possible routings (a subset of the available settings) for filter
blocks GP1A to GP2D with the related control registers. Typical use cases with example
configurations are explained in the section 8.3.
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DAI Left Input
I2S/PCM Left
ADC L
GP1A
ADC
HP L
ADC
IIR L
ADC
HP R
ADC
IIR R
Company confidential
DAI Left Output
GP1B
GP1C
GP1D
+
+
+
+
ADC R
GP2A
DAI Right Input
GP2B
+
I2S/PCM Right
+
+
GP2C
GP2D
+
DAC L
DAC
IIR L
DAC
HP L
DAC
IIR R
DAC
HP R
+
DAC R
DAI Right Output
Figure 15: Digital signal processing engine (simplified block diagram)
The GP filter sections are implemented using a Direct Form 1 architecture, as shown in Figure 16.
This structure implements the transfer function:
H(z) = a0 + a1 z + a2 z2
1-b1 z - b2 z2
X(n)
Y(n)
e.g.
GP1A_A0L
GP1A_A0H
0x2D/0x2E
a0
+
+
z-1
e.g.
GP1A_A1L
GP1A_A1H
0x3D/0x3E
z-1
a1
+
+
z-1
e.g.
GP1A_A2L
GP1A_A2H
0x4D/0x4E
e.g.
GP1A_B1L
GP1A_B1H
0x5D/0x5E
b1
z-1
a2
e.g.
GP1A_B2L
GP1A_B2H
0x6D/0x6E
b2
Figure 16: Direct form I implementation of a second order IIR filter
Each of the five coefficients may be configured by the user, for each filter section. The coefficients
are specified as 16-bit two’s-complement numbers, ranging from -2 to +2. Denominator coefficients
must be negated, that is, if b1 is positive then a negative value (-b1) must be programmed, and
conversely, if b1 is negative then a positive value (+b1) must be programmed. Coefficients must be
selected carefully to specify a stable filter.
The filter sections are arranged in four groups, where the input to each filter group can be
programmed to be one of up to seven possible sources:
● The two digital audio interface (DAI) output ports (left or right)
● The output from the two ADC channels (left or right)
● The output from a previously processed filter group (one of the up to three remaining groups)
If the processing function of a filter is not required the group can be disabled. In this case, the output
path of the filter group is connected directly to the input source. Disabling a filter group reduces the
power consumption of the filter group to a minimum.
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Programming the general purpose filter
The general purpose filter is configured using two groups of registers. These are coefficient
programming and path selection. The coefficients should be programmed using the registers
GP1A_A0L (address 0x2D, Table 80) to GP2D_B2H (address 0x7C, Table 159). Coefficients are
programmed as two 8-bit registers of signed values representing the range +2 to -2.
Example
GP1A_B1L and GP1A_B1H contain the two’s complement low and high bytes of the -b1 coefficient
of the filter illustrated in Figure 16. If a coefficient value of 1.45 is required, -b1 is programmed as the
coefficient number multiplied by a scaling factor.
The scaling factor 214 is used to convert the floating point number into an integer value for
programming. The low byte will always be an 8-bit unsigned hexadecimal value, while the high byte
contains the sign bit of the two’s complement word.
Scale the unsigned decimal coefficient value:
b1 = 1.45 x 214 = 23756.8 ≈ 23757
The unsigned scaled value in binary:
b1 = 0101110011001100b
Convert to two’s complement; invert the binary value and add the MSB sign bit:
b1 = 10100011001100112 = A333h
GP1A_B1L = 33h = 00110011
GP1A_B1H = A3h = 10100011, where MSB is the two’s complement sign-bit
Note that the denominator coefficient is explicitly negated. The value of the -b1 term is positive, so a
negative value must be programmed. There are eight fully programmable, second-order IIR biquad
filter sections grouped in the following pairs:
●
●
●
●
1AB
1CD
2AB
2CD
The output of the first section in each group is cascaded with the second section. The filter sections
are processed in a fixed order: 1A, 1B, 1C, 1D, 2A, 2B, 2C, 2D.
Each filter group can be programmed to take its input from one of seven possible sources, that is,
from either an ADC or an I2S channel, or from any filter section that has been previously processed
using GP_1AB_SRC and GP_2AB_SRC (address 0x7D, Table 160) and GP_1CD_SRC and
GP_2CD_SRC (address 0x7E, Table 161) It is possible to cascade all eight GP filters together using
these registers. Each filter block can be enabled or disabled in register DSP_CFG (address 0x7F,
Table 162).
Table 23: GP filter section enable bits
Control
Definition
GP1AB_EN
Enable GP section 1AB
GP1CD_EN
Enable GP section 1CD
GP2AB_EN
Enable GP section 2AB
GP2CD_EN
Enable GP section 2CD
The outputs of some groups can be summed together, as controlled by register DSP_CFG (address
0x7F, Table 162).
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Table 24: Band-equaliser corner frequencies
Control
Definition
DSP_MIX_1
Output of group 1AB is summed with 1CD
DSP_MIX_2
Output of group 1CD is summed with 2AB
DSP_MIX_3
Output of group 2AB is summed with 2CD
When using the summing facility, the user must ensure that the source signal filter sections are
activated and their output levels are such that clipping does not occur.
At 88.2 kHz and 96 kHz sample rates, the number of useable filter sections is halved. Only sections
1B, 1D, 2B and 2D are available.
8.4
8.4.1
Hi-Fi recording
5-band equaliser for recording path
To allow user-specific sound control, the recording path includes a programmable 5-band equaliser
(combined in the ADC IIR blocks in Figure 15). This is enabled using control ADC_EQ_EN (address
0x13, Table 55).
A low-pass filter, three band-pass filters and a high-pass filter with turn over frequencies at
approximately 50 Hz, 300 Hz, 1.2 kHz and 5 kHz (bandpass centre frequencies at 150, 500 and
2500 Hz) are controlled using the registers ADC_EQ1_VOL to ADC_EQ5_VOL (addresses: 0x11,
Table 53; 0x12, Table 54; 0x13, Table 55). These registers boost or damp each frequency band
from -10.5 dB to +12 dB in 1.5 dB steps. Saturation of the signal from boosted frequencies can be
prevented by an overall damping control ADC_EQ_GAIN (address 0x13, Table 55), which provides
attenuation from -18 dB to 0 dB in 6 dB steps.
Table 25: 5-band-equaliser turn-over/centre frequencies
Sampling
frequency kHz
Low pass
Band pass
Band pass
Band pass
High pass
50 Hz
150 Hz
500 Hz
2500 Hz
5000 Hz
96.0
n.a.
n.a.
n.a.
n.a.
n.a.
88.2
n.a.
n.a.
n.a.
n.a.
n.a.
48.0
67
143
627
2565
5100
44.1
62
131
576
2357
4686
32.0
45
95
418
1710
3400
24.0
67
144
659
2953
6230
22.05
62
132
605
2713
5724
16.0
45
96
439
1969
4153
12.0
67
147
726
2230
3050
11.025
62
135
667
2049
2802
8.0
45
98
484
1486
2033
The 5-band equaliser cannot be used at 88.2 kHz and 96 kHz sampling rates, and is automatically
disabled if the ADC is configured to Voice Mode using control ADC_HPF_F0 (address 0x0F,
Table 51). The frequency responses of the 5-band equaliser are illustrated in Figure 17 to Figure 21.
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Figure 17: Band 5 (LP 50 Hz) frequency response at FS = 48 kHz
Figure 18: Band 5 (BP 150 Hz) frequency response at FS = 48 kHz
Figure 19: Band 5 (BP 500 Hz) frequency response at FS = 48 kHz
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Figure 20: Band 5 (BP 2500 Hz) frequency response at FS = 48 kHz
Figure 21: Band 5 (HP 5000 Hz) frequency response at FS = 48 kHz
8.4.2
Digital audio processing for the record path
When Record only is selected, the DAC and playback filter units can be powered down. The general
purpose filter engine can offer 8th order stereo filters to correct the acoustic frequency response of
the connected microphone (Figure 22).
If less filtering is required, filter stages can be bypassed using the filter enable controls described in
Table 23.
For mono playback, this can also be achieved by switching off a complete channel (blocks not
required are highlighted in the following figures in light grey).
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I2S/PCM L
GP
1A
ADC L
ADC
HP L
ADC
IIR L
ADC
HP R
ADC
IIR R
GP
1B
GP
1D
+
+
+
+
GP
2A
ADC R
GP
1C
GP
2B
+
+
+
GP
2C
GP
2D
DAC L
DAC
IIR L
DAC
HP L
DAC
IIR R
DAC
HP R
+
+
DAC R
I2S/PCM R
Figure 22: Record only
If it is intended to listen to the recording as it is being made, or to listen to another sound at the same
time as the recording, the general purpose filter engine offers a split mode for parallel record and
playback equalisation. This mode supports applications that perform active noise cancellation.
I2S/PCM L
GP
1A
ADC L
ADC
HP L
ADC
IIR L
ADC
HP R
ADC
IIR R
GP
1C
GP
1D
+
+
+
+
GP
2A
ADC R
GP
1B
GP
2B
+
+
+
GP
2C
GP
2D
+
+
DAC L
DAC
IIR L
DAC
HP L
DAC
IIR R
DAC
HP R
DAC R
I2S/PCM R
Figure 23: Record with sound monitor
8.5
8.5.1
Hi-Fi playback
5-band equaliser for playback path
To allow user-specific sound settings, the digital playback path includes a programmable 5-band
equaliser, which is enabled using control DAC_EQ_EN (address 0x1B, Table 63).
A low-pass filter, three band pass filters and a high-pass filter, with corner frequencies at
approximately 100 Hz, 300 Hz, 1 kHz, 3 kHz and 3 kHz (for FS = 44.1 kHz) are controlled by the
registers DAC_EQ1_VOL to DAC_EQ5_VOL (addresses: 0x19, Table 61; 0x1A, Table 62; 0x1B,
Table 63). These registers boost or damp each frequency band from -10.5 dB to +12 dB in 1.5 dB
steps. Saturation of the signal from boosted frequencies can be prevented by an overall damping
control ADC_EQ_GAIN (address 0x1B, Table 63).
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The 5-band equaliser cannot be used at a 96 kHz sampling rate and is automatically disabled if the
ADC is configured to Voice Mode using control DAC_VOICE_EN (address 0x14, Table 56). Details
of corner frequencies are shown in Table 25. Frequency responses are illustrated in Figure 17 to
Figure 21.
8.5.2
Digital audio processing for playback path
In addition to the user selectable sound settings offered by the 5-band equaliser, the playback path
offers up to 8th order configurable audio filtering, for example, to correct the frequency response of
connected receivers, speakers or headphones.
I2S/PCM L
GP
1A
ADC L
ADC
HP L
ADC
IIR L
ADC
HP R
ADC
IIR R
GP
1C
GP
1D
+
+
+
+
GP
2A
ADC R
GP
1B
GP
2B
+
+
+
GP
2C
GP
2D
+
DAC L
DAC
IIR L
DAC
HP L
DAC
IIR R
DAC
HP R
+
DAC R
I2S/PCM R
Figure 24: Stereo playback (for example, freefield headphone equalisation)
For applications with stereo speakers the digital signal processing offers stereo widening with 3D
audio effects.
I2S/PCM L
GP
1A
ADC L
ADC
HP L
ADC
IIR L
ADC
HP R
ADC
IIR R
ADC R
GP
1B
GP
1C
GP
1D
+
+
+
+
GP
2A
GP
2B
+
+
+
GP
2C
GP
2D
+
+
DAC L
DAC
IIR L
DAC
HP L
DAC
IIR R
DAC
HP R
DAC R
I2S/PCM R
Figure 25: Sound spatialiser for stereo speaker
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Telephone/Bluetooth voice recording/playback at low sample rates
DA7211 offers a dedicated Voice Mode with configurable voice in-band and enhanced out-of-band
suppression for sample rates up to 16 kHz.
8.6.1
Voice filtering for recording at low sample rates
When the sampling frequency is 8, 11.025, 12 or 16 kHz, a Voice Mode can be enabled via
ADC_VOICE_EN (address 0xF, Table 51) where the low frequency roll off is configured using
control ADC_VOICE_F0 (address 0xF, Table 51).
Note 6
Voice filter setting takes precedence over the 5-band equaliser. If the voice filter is enabled for the
ADC path, the 5 band equaliser for recording is disabled.
Table 26: Voice mode recording high pass filter specifications
Cut-off frequency [Hz] at setting
Fs [kHz]
000
001
010
011
100
101
110
111
8.0
2.5
25
50
100
150
200
300
400
11.025
3.4
34.5
69
138
207
276
413
551
12.0
3.75
37.5
75
150
225
300
450
600
16.0
5
50
100
200
300
400
600
800
Figure 26: Voice mode recording high pass filter
(cut-off frequency setting ‘000’ to ‘111’, 8 kHz)
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Figure 27: Voice mode recording frequency response (setting ‘001’, 8 kHz)
Figure 28: Voice mode recording stop band suppression (8 kHz)
8.6.2
Voice filtering for playback at low sample rates
For playback the voice mode is enabled via DAC_VOICE_EN (Address 0x14, Table 56) where the
low frequency roll off is configured via control DAC_VOICE_F0 (Address 0x14, Table 56).
Note 7
Voice filter setting takes precedence over the 5 band-equaliser. If the voice filter is enabled for the
DAC signal the 5-band-equalizer for playback is automatically disabled.
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Table 27: Voice mode playback high-pass filter specifications
Cut-off frequency [Hz] at DAC_VOICE_F0 setting
Fs [kHz]
000
001
010
011
100
101
110
111
8.0
2.5
25
50
100
150
200
300
400
11.025
3.4
34.5
69
138
207
276
413
551
12.0
3.75
37.5
75
150
225
300
450
600
16.0
5
50
100
200
300
400
600
800
Figure 29: Voice mode playback high-pass filter
(cut-off frequency setting ‘000’ to ‘111’, 16 kHz)
Figure 30: Voice mode playback frequency response (setting ‘001’, 8 kHz)
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Figure 31: Voice mode playback stop band suppression (8 kHz)
8.6.3
Digital audio processing for phone applications
The general purpose filter engine offers a parallel 4th order acoustic equalisation of microphone and
receiver/speaker, and filtering of the sidetone signal to suppress oscillations from any acoustic
feedback loop. This allows corrections to the frequency response of acoustic transducers and their
mechanical environment that is required for GSM/3GPP type approval of mobile phone applications.
I2S/PCM L
GP
1A
ADC L
ADC
HP L
ADC
IIR L
ADC
HP R
ADC
IIR R
GP
1C
GP
1D
+
+
+
+
GP
2A
ADC R
GP
1B
GP
2B
+
+
+
GP
2C
GP
2D
+
DAC L
DAC
IIR L
DAC
HP L
DAC
IIR R
DAC
HP R
+
DAC R
I2S/PCM R
Figure 32: Transmit (red), receive (green) and sidetone (blue) sound filtering
for phone applications
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Company confidential
INTERFACES
9.1
Digital audio interface (DAI)
Audio data is transferred to and from DA7211 via a serial 2-wire digital audio interface, which is
enabled with bit DAI_EN. It is compatible with the Phillips I2S bus specification in normal, left
justified, and right justified modes, and operates in both master and slave modes. In addition to I2S,
the codec supports the DSP/PCM format of Bluetooth and mobile phone voice links, and offers a
multi device TDM mode. The four bus lines are the clock (CLK), the serial data-in line (DATAIN), the
serial data-out line (DATAOUT), and the word select line (WCLK).
For voice stream monitoring within dual processor architectures, DA7211 includes loop back modes
that allow merging of the mono (left) RX and TX data into the PCM/I2S TX data stream configured
via control DAI_OUT_R_SRC (address 0x25, Table 72).
Serial data and control signals are clocked onto the bus at the falling edge of the CLK clock signal.
This guarantees that they are stable at the rising edge of CLK. The serial data is sampled into
DA7211 on the rising edge of the CLK clock signal.
The interface is enabled via DAI_EN (address 0x28, Table 75) and can operate as either the bus
master or as a slave (see control DAI_MODE (address 0x26, Table 73). In master mode, DA7211
generates the WCLK and CLK signals, whereas in the default slave mode these are inputs to the
device. If the output from the ADC is not required, the serial data output from this pin can be disabled
using control DAI_OE (address 0x28, Table 75).
The device may also be used in a system where several devices are connected to the master, using
Time Division Multiplexing (TDM). The serial input and output data for each device is valid at a
certain offset from the start of the frame. The serial data output from the device is tri-stated until the
data from the device is valid, thus allowing several devices to have their serial data out pins
connected together.
9.1.1
Operation modes DAI interface
Serial data is transferred as two’s complement with the MSB first. The protocol format is selected via
control DAI_FORMAT (address 0x28, Table 75). DA7211 is configured to operate with data word
lengths of 16, 20, 24, or 32 bits using control DAI_WORD (address 0x26, Table 73).
In master mode the device can be configured via DAI_FRAME (address 0x26, Table 73) to generate
either twice the selected word-length bit clocks per frame, or 256, 128, or 64 bit clocks per frame. In
slave modes, the device may be clocked by any number of bit clocks per frame provided that there
are sufficient clocks to transfer all the data bits, which are defined by the word length configuration
register.
In loop mode, the RX right data overrides available TX left data using control DAI_SRC_SEL
(address 0x25, Table 72).
9.1.2
Right justified mode
In right-justified mode the LSB of the left channel is valid on the rising edge of the bit clock preceding
the falling edge of word clock. The LSB of the right channel is valid on the rising edge of the bit clock
preceding the rising edge of the word clock.
WCLK = 1; left channel data
WCLK = 0: right channel data
WCLK
CLK
< left channel data>
DATA
N-1
N-2
1
< right channel data>
0
N-1
N-2
1
0
Figure 33: Right justified format
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Left justified mode
In left-justified mode the MSB of the right channel is valid on the rising edge of the bit clock following
the falling edge of the word clock.
The MSB of the left channel is valid on the rising edge of the bit clock following the rising edge of the
word clock.
WCLK = 1; left channel data
WCLK = 0: right channel data
WCLK
CLK
< left channel data>
DATA
N-2
N-1
< right channel data>
1
0
N-1
N-2
1
0
Figure 34: Left justified format
9.1.4
I2S mode
In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the
falling edge of the word clock.
Similarly the MSB of the right channel is valid on the second rising edge of the bit clock after the
rising edge of the word clock.
WCLK = 1; right channel data
WCLK = 0: left channel data
WCLK
CLK
< right channel data>
DATA
N-1
N-2
< left channel data>
1
0
N-1
N-2
1
0
Figure 35: I2S format
9.1.5
DSP mode
In DSP mode, the rising edge of the word clock starts the data transfer, first with the left channel
data, and followed immediately by the right channel data. Each data bit is valid on the falling edge of
the bit clock.
WCLK
CLK
< left channel data >
DATA
N-1
N-2
1
< right channel data >
0
N-1
N-2
1
0
Figure 36: DSP format
9.1.6
TDM mode
TDM modes are implemented by defining the data to be valid a certain number of bit clock periods
after the start of the frame. This is configured using the offset value DAI_TDM_OFFS (address 0x27,
Table 74). It is recommended that TDM is used in either the Left Justified or DSP mode.
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In the Left Justified TDM mode, the left channel data is valid DAI_TDM_OFFS clock cycles after the
rising edge of the word clock, and the right channel data is valid after the same DAI_TDM_OFFS
number of clock cycles after the falling edge of the word clock.
In the DSP TDM mode, the left channel data is valid DAI_TDM_OFFS clock cycles after the rising
edge of the word clock pulse, and the right channel data is valid immediately after the left channel
data. The number of bits of the data is determined by the word length setting in the configuration
registers. The serial data output pin will be tri-stated when the output is not valid.
WCLK
CLK
offset
DATA
offset
< left channel data>
N-2
N-1
1
0
< right channel data>
N-1
N-2
1
0
Figure 37: TDM left justified format
WCLK
CLK
< left channel data>
offset
DATA
N-1
N-2
1
< right channel data>
0
N-1
N-2
1
0
Figure 38: TDM DSP format
TDM mode is enabled via DAI_TDM (address 0x28 Table 75) and may be configured to operate in
mono only using the control DAI_TDM_MONO (address 0x26 Table 73). In this case, only one
channel data is received from the bus and placed on the bus. Other devices may place data on the
bus immediately after the left channel data.
9.1.7
Clocking schemes
The internal system clock of the DA7211 runs at either 12.288 MHz or 11.2896 MHz. Which of these
two system clock speeds is used depends on the audio sample rate as shown in Table 28. However,
the external MCLK input choice has a number of options that depend on the sample rate, the
MCLK_RANGE setting, whether the device is operating in Master or Slave Mode, and whether the
PLL has been enabled.
For all DA7211 operations, the device must be started with an external MCLK input to allow register
settings to be made. The DA7211 will not start up correctly unless this external clock is available.
The initial frequency of the MCLK input during register set up is unimportant as long as it is within the
10 to 80 MHz range, but the frequency must be valid for DAC, ADC and filter operation.
Note: In PLL-enabled modes, register writes are clocked into the register map by the control interface
clock (SK) until the PLL clock is locked and available.
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Table 28: Internal system clock frequency
Sample rate (kHz)
System clock rate FSYS (MHz)
ADC/DAC clock rate
FSDM (MHz)
8
12.288
3.072
16
12.288
3.072
32
12.288
3.072
48
12.288
3.072
96
12.288
3.072
11.025
11.2896
2.8224
25.05
11.2896
2.8224
44.1
11.2896
2.8224
88.2
11.2896
2.8224
Table 29: Block enable and system standby bits
Block enable
register bit
SC_MST_EN = 1 required to
enable I/O block bit?
Start-up register bit for
setting I/O to standby
MIC_L
0x07[7]
Yes
0x05[0]
MIC_R
0x08[7]
Yes
0x05[1]
AUX1_L
0x09[7]
Yes
0x05[3]
AUX1_R
0x0A[7]
Yes
0x05[2]
ADC_L
0x10[3]
Yes
0x05[5]
ADC_R
0x10[7]
Yes
0x05[6]
OUT1_L
0x1E[7]
Yes
0x04[0]
OUT1_R
0x1F[7]
Yes
0x04[1]
HP_L
0x23[7]
Yes
0x04[3]
HP_R
0x23[3]
Yes
0x04[4]
DAC_L
0x17[7]
Yes
0x04[5]
DAC_R
0x17[3]
Yes
0x04[6]
INMIX_L mixer
0x0D[7]
No
n/a
INMIX_R mixer
0x0E[7]
No
n/a
OUT_L mixer
0x1C[7]
No
n/a
OUT_R mixer
0x1D[7]
No
n/a
I/O
Table 29 summarises the registers bits that must be enabled before SC_MST_EN is enabled if that
block operation is required. Each block can be set in and out of standby after SC_MST_EN = 1.
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9.1.8
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Master mode
In Master mode (controlled by DAI_MODE - address 0x26, Table 73) DA7211 can generate all
supported audio sampling rates directly from a provided MCLK signal at either 12.288 MHz or
11.2896 MHz. In this case the PLL is not required and it should be bypassed and disabled with
PLL_EN (address 0x2C, Table 79).
DA7211 can also generate all internal clocks without offset, as well as the sample rate, the CLK
signal, and the WCLK signal from an MCLK signal in the range of 10 MHz to 80 MHz. This is done
using the embedded fractional-N PLL (see controls MCLK_RANGE and PLL_DIV_L to PLL_DIV_H.
Table 30: ADC and DAC clock frequencies
Sample
rate
[kHz]
Voice mode
(Note 8)
8
ADC decimation
DAC SDM oversample
SDM rate Fs
FSDM frequency
[kHz]
96
32
384
3072
8
Y
96
16
384
3072
11.025
Y
64
32
256
2822.4
12
Y
64
32
256
3072
48
16
192
3072
48
8
192
3072
22.05
32
16
128
2822.4
24
32
16
128
3072
32
24
8
96
3072
44.1
16
8
64
2822.4
48
16
8
64
3072
96
Note 9
8
4
32
2822.4
16
16
Y
Note 8
Voice filter has stopband attenuation of >75 dB. The IIR engine implements voice filtering, or 5-band
equalisation. For rates other than 44.1 kHz, the 5-band equalisation turnover frequencies scale with
the sampling rate.
Note 9
No TDM on digital audio interface.
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Table 31: Master mode PLL-DIV look up table
Input MCLK
[MHz]
PLL_DIV_H
PLL_DIV_H
PLL_DIV_H
Audio frequency
[kHz]
[MHz]
12.0
0xE8
0x6C
0x2
44.1 (Note 10)
12.0
0xF3
0x12
0x7
48.0 (Note 11)
13.0
0xDF
0x28
0xC
44.1 (Note 10)
13.0
0xE8
0xFD
0x5
48.0 (Note 11)
13.5
0xDB
0x0A
0xD
44.1 (Note 10)
13.5
0xE4
0x82
0x3
48.0 (Note 11)
14.4
0xD4
0x5A
0x2
44.1 (Note 10)
14.4
0xDD
0x3A
0x0
48.0 (Note 11)
19.2
0xBB
0x43
0x9
44.1 (Note 10)
19.2
0xC1
0xEB
0x8
48.0 (Note 11)
19.68
0xB9
0x6D
0xA
44.1 (Note 10)
19.68
0xBF
0xEC
0x0
48.0 (Note 11)
19.8
0xB8
0xFB
0xB
44.1 (Note 10)
19.8
0xBF
0x70
0x0
48.0 (Note 11)
Note 10 Including harmonics such as 11.025, 22.05 and 88.2 kHz sample rates.
Note 11 Including audio frequencies such as 8.0, 12.0, 16.0, 32.0, 24.0, 36.0, 48.0, 96.0 kHz sample rates.
Table 32: SRM mode PLL-DIV look up table
Datasheet
CFR0011-120-00 Rev 5
Input MCLK
[MHz]
PLL_DIV_H
PLL_DIV_M
PLL_DIV_L
0.032768
0xD4
0x99
0x0
12.0
0xED
0xBF
0x5
13.0
0xE4
0x13
0x0
13.5
0xDF
0xC6
0x8
14.4
0xD8
0xCA
0x1
19.2
0xBE
0x97
0x9
19.68
0xBC
0xAC
0xD
19.8
0xBC
0x35
0xE
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Programming master and 32 kHz mode – PLL enabled
If DA7211 is to be used in Master Mode with the PLL, a clock signal must first be applied to the
MCLK pin. The frequency of this clock must either be 32.768 kHz (32 kHz Mode), or within the range
10 to 80 MHz.
MCLK_RANGE (address 0x2B[5:4]) must be set to the appropriate frequency range at the MCLK pin.
The Sample Rate Matching (SRM) only needs to be enabled if 32 kHz Mode is being used. SRM is
enabled by asserting MCLK_SRM_EN (address 0x26[7]).
For the PLL to assume initial lock, it is necessary to set the PLL division ratio bits in registers 0x29,
0x2A, 0x2B. The settings for PLL Master Mode differ from those of PLL 32 kHz Mode. For 32 kHz
mode, MCLK_RANGE (address 0x2C[5:4]) = 00. For all other PLL Master Mode operations,
MCLK_RANGE (address 0x2C[5:4]) = 01, 10 or 11. These settings will allow the PLL lock cycle to
start in the correct frequency range. It is not necessary to assert MCLK_DET_ENA in PLL Master
Mode as the CLK and WCLK outputs are produced by the DA7211 itself.
It is also necessary to assert vco_rst, 0x90[0] to ensure successful PLL lock. To access this bit is
necessary to first enter the following register settings 0x8A = 8Bh and 0x8B =B4h.
As with non-PLL slave mode, to set the required sample rate, the correct clock division ratio must be
set within register 0x2C[3:0], (see Table 35).
Table 33: PLL master mode register setting recommendations
0x2C
PLL
4
MCLK_SHAPE_EN
0
Enable MCLK shaper for low level non TTL signals - optional
5
MCLK_DET_EN
0
Enable automatic detection of sample rate
6
MCLK_SRM_EN
0
Enable DAI sample rate tracking, sample rate defined by FS
7
PLL_EN
1
0: Disable and bypass PLL
1: Enable PLL
Dialog Semiconductor recommend that good quality external clocks are used to supply the DAI, but if
the only available MCLK source is of poor quality, it can be improved by using the optional bit
MCLK_SHAPE_EN.
Figure 39 shows a basic start-up up configuration sequence for PLL master mode.
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Apply clock to
MCLK pin in the
range 10 to
80MHz, or
32.768kHz
Set MCLK division
ratio or 32.768kHz
mode
0x2B[5:4]
Enable DAI
master mode
0x26[7] = 1
Is 32.768kHz
Mode Selected?
Yes
Enable SRM
function
0x2C[6] = 1
No
Set PLL division
ratios for MCLK
provided
externally
0x29[7:0]
0x2A[7:0]
0x2B[3:0]
Set PLL division
ratios for
32.768kHz MCLK
provided
externally
0x29[7:0] = D4h
0x2A[7:0] = 99h
0x2B[3:0] = 0h
Enable vco_rst bit
0x8A = 8Bh
0x8B = B4h
0x90 = 1
Write to all
registers that
require setting up
for chosen path
functions
Set gain of active
analogue outputs
to mute
Select I/Os and
blocks that require
power down
0x04[6:0]
0x05[6:0]
Enable PLL
0x2C[7] = 1
Activate system
controller
0x03[0] = 1
Device power up
Figure 39: PLL master mode start up sequence
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9.2
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Slave mode
Slave mode is selected by setting DAI_MODE (address 0x26, Table 73) = 0. The CLK and WCLK
signals are supplied by the application.
9.2.1
Conditions:
(i) Sample Rate Matching (SRM) Disabled
SRM is not needed if the audio sample rate is known and the CLK and WCLK signals are derived
from the same master clock as the MCLK input. In this case CLK and WCLK are synchronised with
MCLK, so the SRM function should be disabled and the PLL_DIV registers programmed as shown in
Table 32. Alternatively, lowest power dissipation can be achieved if the MCLK frequency can be set
to 256×Fs (12.288 MHz or 11.2896 MHz) and the PLL switched off.
(ii) Sample Rate Matching (SRM) Enabled
SRM is needed if the sample rate on the audio interface is unknown, or the CLK and WCLK signals
are derived from a different clock domain to the MCLK input.
SRM (MCLK_SRM_EN = 1 address 0x2C, Table 79) keeps the internal clocks synchronised with
WCLK.
If the sample rate is known, the value of FS should be set accordingly. If the sample rate is not
known, it can be derived from WCLK and automatically programmed by asserting MCLK_DET_EN
(address 0x2C, Table 79).
The Sample Rate Matching (SRM) functions by pulling the PLL frequency away from the nominal
value specified by the PLL control registers (addresses 0x29 to 0x2B, Table 78). In this mode the
register settings shown in Table 33 should be used. Enabling the SRM offers maximum flexibility for
clocking schemes as it removes the need to have common clock domains for the application
processor and audio codec processor.
Programming slave mode – PLL not enabled
9.2.2
In either Slave or Master mode, and when the PLL is not enabled, an exact multiple of (256 * Fs)
must be input to the MCLK pin (see Table 34).
In order to set the correct clock division ratio within the DA7211 for a particular sample rate, it is
necessary to set the correct sample rate setting in the FS register (address 0x2C [3:0], Table 79).
The possible sample rates and MCLK frequencies are shown in Table 34.
Table 34: MCLK frequencies in non-PLL slave mode
MCLK (MHz)
Sample rate
(kHz)
MCLK_RANGE =
00
MCLK_RANGE =
01
MCLK_RANGE =
10
MCLK_RANGE =
11
8
n/a
12.288
24.576
49.152
16
n/a
12.288
24.576
49.152
32
n/a
12.288
24.576
49.152
48
n/a
12.288
24.576
49.152
96
n/a
12.288
24.576
49.152
11.025
n/a
11.2896
22.5792
45.1584
25.05
n/a
11.2896
22.5792
45.1584
44.1
n/a
11.2896
22.5792
45.1584
88.2
n/a
11.2896
22.5792
45.1584
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Table 35: Non-PLL slave mode and PLL master mode sample rate settings
0x2C[3:0]
Sample rate
0000
Not used
0001
8 kHz
0010
11.025 kHz
0011
12 kHz
0100
Not used
0101
16 kHz
0110
22.05 kHz
0111
24 kHz
1000
Not used
1001
32 kHz
1010
44.1 kHz
1011
48 kHz
1100
Not used
1101
Not used
1110
88.1 kHz
1111
96 kHz
If only analogue paths are required then it is possible to use MCLK = 32.768 kHz for the register
setup. For all other 32.768 kHz modes, the PLL must be enabled for any operation that requires
ADC, DAC or digital filtering.
Figure 40: Non-PLL mode start-up sequence shows a basic start-up up configuration sequence for
non-PLL slave mode.
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Is the signal path
analogue only?
Yes then
32.768kHz
clock
maybe used
Company confidential
Set 32.768kHz
mode
0x2B[5:4] = 00
Is master mode
required?
No
Apply 12.288 or
11.2896MHz clock
or multiples to
MCLK pin
Yes
Select master
mode
0x26[7] = 1
No
Select I/Os and
blocks that require
power down
0x04[6:0]
0x05[6:0]
Set MCLK division
ratio mode
0x2B[5:4]
Activate system
controller
SC_MST_EN bit
0x02[0] = 1
Provide internal
MCLK for register
writes
0x2B[6] = 1
Write to all
registers which
require setup for
chosen path
functions
Set gain of active
analogue output
paths to mute
Device power up
Figure 40: Non-PLL mode start-up sequence
9.2.3
Programming slave mode – PLL enabled
If PLL mode is enabled and the MCLK_DET_EN (0x2C[5]) bit is set, the value read from this register
will be the automatically detected sample rate from the PLL track circuitry. Register 0x2C[3:0] can be
set to 0000 in this case. Sample rate changes will be updated on the positive edge of DAI clock.
It is also recommended that the Sample Rate Matching (SRM) tracking function is enabled (register
0x2C[6]) when the PLL is used in slave mode. This means that any changes in the sample rate can
be tracked automatically without any input from the controlling processor. Failure to enable SRM can
result in intermittent audible clicking on the DAC outputs.
In order to allow the PLL to assume initial lock, it is necessary to set the PLL division ratio bits and
the MCLK_RANGE in registers 0x29, 0x2A, 0x2B and 0x2C. These functions cause the PLL lock
cycle to start in the correct frequency range. The division ratio settings for SRM mode differ from
those of master mode (see section 9.1.8).
It is also necessary to set the vco_rst bit, 0x90[0] = 1 to ensure a successful PLL lock. To access this
bit, it is necessary to first enter the following register settings: 0x8A = 8Bh and 0x8B = B4h.
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Table 36: SRM mode PLL division ratio settings
MCLK
(MHz)
PLL_DIV_H
0x29[7:0]
PLL_DIV_M PLL_DIV_L
0x2A[7:0]
0x2B[3:0]
0.032768
0xD4
0x99
0x0
12.0
0xED
0xBF
0x5
13.0
0xE4
0x13
0x0
13.5
0xDF
0xC6
0x8
14.4
0xD8
0xCA
0x1
19.2
0xBE
0x79
0x7
19.68
0xBC
0xAC
0xD
19.8
0xBC
0x35
0xE
Table 35 contains the division ratios for a selection of common oscillator frequencies that can be
used for generating the internal 256 * Fs master clock from the PLL. If an uncommon frequency is
used, the division ratio values can be calculated.
The feedback divide ratio PLL_DIV is a 20-bit two’s complement value in the range -0.5 to +0.5,
which can be calculated using
 8 * FSYS 

9
FMCLK 

PLL _ DIV 
16
For example, if FMCLK = 13.7 MHz and FSYS = 12.288 MHz then PLL_DIV = -0.114033, which
equals 0xE2CEC as a 20-bit two’s-complement number. This value is written to the three PLL_DIV
registers:
● PLL_DIV_H (0x29) = E2h
● PLL_DIV_M (0x2A) = CEh
● PLL_DIV_L (0x2B[3:0]) = Ch
Note
A PLL division ratio calculation tool is available on request.
Dialog Semiconductor recommend that good quality external clocks are used to supply the DAI, but if
the only available MCLK source is of poor quality. It can be improved by using the optional bit
MCLK_SHAPE_EN.
Table 37: Slave mode PLL-enabled register setting recommendations
0x2C
PLL
4
MCLK_SHAPE_EN
0
Enable MCLK shaper for low level non TTL signals - optional
5
MCLK_DET_EN
1
Enable automatic detection of sample rate
6
MCLK_SRM_EN
1
Enable DAI sample rate tracking, sample rate defined by FS
7
PLL_EN
1
0: Disable and bypass PLL
1: Enable PLL
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Apply clock to
MCLK pin in the
range 10-80MHz
Write to all
registers which
require setup for
chosen path
functions
Set MCLK division
ratio mode
0x2B[5:4]
Set gain of active
analogue outputs
to mute
Select I/Os and
blocks that require
power down
0x04[6:0]
0x05[6:0]
Set PLL division
ratios for MCLK
provided
externally
0x29[7:0]
0x2A[7:0]
0x2B[3:0]
Activate system
controller
0x02[0] = 1
Enable PLL, SRM
and and MCLK
detection functions
0x2C[7:5] = 111
Device power up
Enable vco_rst bit
0x8A = 8Bh
0x8B = B4h
0x90[0] = 1
Figure 41: PLL Slave mode start-up sequence
9.2.4
32 kHz master or slave mode
With the 32 kHz mode enabled, the DA7211 is able to accept a standard watch-crystal frequency
(32.768 kHz) input on MCLK. It does this by enabling an on-chip reference oscillator and using the
SRM system to track the MCLK input. The 32 kHz mode is enabled by setting MCLK_RANGE
(address 0x2B, Table 78), and since the SRM is required, the PLL_DIV settings in Table 31 should
be used.
The 32 kHz mode works with the DA7211 in Master (Note 12) or Slave modes, but it is not possible
to use the automatic detection of audio sample rate.
Note 12 In 32 kHz Master Mode the sample rates 11.025, 22.05, 44.1 and 88.2 kHz will have a maximum offset
of 0.14%.
9.2.5
Phase locked loop (PLL)
A PLL is integrated into the codec. This uses standard oscillator master clock signals to generate the
target audio sample rates and all internal clock signals. If no 256 * Fs master clock signal is provided,
the PLL can be enabled with control PLL_EN (address 0x2C, Table 79). The PLL supports a wide
range of common oscillator frequencies between 10 and 20 MHz (see Table 31)
The PLL can also be fed from the 2nd or 4th harmonics of these frequencies via an input clock
divider (configured using control MCLK_RANGE (address 0x2B Table 78). The master clock input
can be either a standard TTL signal. It can also be any kind of saw tooth, square or sine wave if the
embedded signal shaper is enabled via control MCLK_SHAPE_EN (address 0x2C, Table 79). If the
host provides the 256 * FS master clock, the PLL can be disabled to reduce dissipation power.
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32 kHz mode
15 MHz
OSC
PLL Bypass
10 – 20 MHz
MCLK
Digital Clock
12.288 / 11.290 MHz
98.3 or 90.3 MHz
20 – 40 MHz
MCLK
¸2
40 – 80 MHz
MCLK
¸4
PFD / CP
Loop Filter
¸2
VCO
¸2
¸2
¸4
DAC & ADC Clock
3.072 / 2.822 MHz
¸(9 + Y[n])
Y[n]
Sigma-Delta
Modulator
Lock
Detect
X
PLL_DIV
SRM
WCLK
Lock
32.768 kHz
MCLK
32 kHz Master Mode
Figure 42: PLL block diagram
9.2.6
Control interface
The DA7211 has a 2-wire control interface.
AVDD
Host
processor
AVDD
SK
DA7211
SI Peripheral
device
SCL
SDA
2-wire interface
SCL
SDA Peripheral
device
Figure 43: Schematic of a 2-wire control bus
9.2.7
2-wire communication
The 2-wire interface supports 7-bit address protocol. DA7211 responds to the device address
001 1010.
SK provides the 2-wire clock and SI carries all the control bidirectional 2-wire data. The 2-wire
interface is open-drain, supporting multiple devices on a single line. The attached devices only drive
the bus lines low by connecting them to ground.
The bus lines are pulled high by pull-up resistors (2 KΩ to 20 KΩ range). As a result, two devices
cannot conflict if they drive the bus simultaneously. In standard/fast mode the highest frequency of
the bus is 400 kHz.
The exact frequency can be determined by the application and does not have any relation to the
DA7211 internal clock signals. DA7211 will follow the host clock speed within the described
limitations, and does not initiate any clock arbitration or slow down.
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In high speed mode, the maximum frequency of the bus is 1.7 MHz. This mode is supported if the SK
line is driven with a push-pull stage from the host and if the host enables an external 3 mA pull-up at
the SI pin to decrease the rise time of the data. In this mode the SI line on DA7211 is able to sink up
to 12 mA. In all other respects the high speed mode behaves as the standard/fast mode.
Communication on the 2-wire bus always takes place between two devices, one acting as the master
and the other as the slave, but DA7211 will only operate as a slave. The 2-wire interface has direct
(linear) access to the whole DA7211 register space (except 0x00 and 0x80). This is achieved by
using the MSB of the 2-wire 8 bit register address as a selector of the register page.
9.2.8
Details of the 2-wire control bus protocol
Data is transmitted access the 2-wire bus in groups of eight bits. To send a bit, the SI line is driven
towards the intended state while the SK is LOW (a low on SI indicates a zero bit). Once the SI has
settled, the SK line is brought HIGH and then LOW. This pulse on SK clocks the SI bit into the
receiver’s shift register.
A two byte serial protocol is used containing one byte for address and one byte data. Data and
address transfer is MSB transmitted first for both read and write operations. All transmission begins
with the START condition from the master during the bus is in IDLE state (the bus is free). It is
initiated by a high to low transition on the SI line while the SK is in the high state (a STOP condition is
indicated by a low to high transition on the SI line while the SK is in the high state).
S
SLAVEadr
7-bits
W
A
REGadr
1-bit
A
DATA
8-bits
Master to Slave
P
A
8-bits
Slave to Master
S = START condition
P = STOP condition
A = Acknowledge (low)
W = Write (low)
Figure 44: 2-wire byte write (SI/DATA line)
When the host reads data from a register it first has to write access DA7211 with the target register
address. It then read accesses DA7211 with a Repeated START or alternatively a second START
condition. After receiving the data the host sends no acknowledge and terminates the transmission
with a STOP condition.
S
SLAVEadr W A
7-bits
S
1-bit
SLAVEadr W A
7-bits
1-bit
Master to Slave
REGadr
A Sr SLAVEadr
8-bits
7-bits
REGadr
A
P
S
8-bits
R
A
1-bit
8-bits
SLAVEadr
7-bits
A* P
DATA
R
1-bit
A
DATA
A* P
8-bits
Slave to Master
S = START condition
Sr = Repeated START condition
P = STOP condition
A = Acknowledge (low)
A* = Not acknowledge
W = Write (low)
R = Read (high)
Figure 45: Examples of 2-wire byte read (SI/DATA line)
Consecutive (page) read out mode is initiated from the master by sending an Acknowledge instead of
Not acknowledge after receipt of the data word. The 2-wire control block then increments the address
pointer to the next 2-wire address and sends the data to the master. This enables an unlimited read
of data bytes until the master sends a NACK (‘Not Acknowledge’) directly after the receipt of data,
followed by a subsequent STOP condition.
If a non-existent 2-wire address is read out then the DA7211 will return code zero.
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S SLAVEadr W A
7-bits
REGadr
1 bit
7-bits
A Sr SLAVEadr R A
8-bits
S SLAVEadr W A
REGadr
Company confidential
7-bits
Master to Slave
A
DATA
8-bits
1-bit
A
8-bits
SLAVEadr R A
7-bits
8-bits
1-bit
1-bit
S
A P
DATA
DATA
DATA
A* P
8-bits
A
A* P
DATA
8-bits
8-bits
Slave to Master
S = START condition
Sr = Repeat START condition
P = STOP condition
A = Acknowledge (low)
A* = Not Acknowledge
W = Write (low)
R = Read (high)
Figure 46: Examples of 2-wire page read (SI/DATA line)
Note - The slave address after the Repeated START condition must be the same as the previous
slave address.
Consecutive (page) write mode is supported if the Master sends several data bytes following a slave
register address. The 2-wire control block then increments the address pointer to the next 2-wire
address, stores the received data and sends an Acknowledge until the master sends the STOP
condition.
S SLAVEadr W A
7-bits
1 bit
REGadr
A
8-bits
Master to Slave
DATA
8-bits
A
DATA
1-bit
8-bits
A
DATA
A
8-bits
……….
A
P
Repeated writes
Slave to Master
S = START condition
Sr = Repeat START condition
P = STOP condition
A = Acknowledge (low)
A* = Not Acknowledge
W = Write (low)
R = Read (high)
Figure 47: 2-wire page write (SI/DATA line)
Using the control WRITE_MODE (address 0x01, Table 39) the device can be configured to accept an
alternate write mode where the host transmits alternate addresses and
write data. This allows the host to perform several write operations to non consecutive registers. Data
will be stored at the previously received register address:
S SLAVEadr W A
7-bits
1 bit
REGadr
8-bits
Master to Slave
A
DATA
8-bits
A
REGadr
1-bit
8-bits
A
DATA
8-bits
A
……….
A
P
Repeated writes
Slave to Master
S = START condition
Sr = Repeat START condition
P = STOP condition
A = Acknowledge (low)
*
A = Not Acknowledge
W = Write (low)
R = Read (high)
Figure 48: 2-wire repeated write (SI/DATA line)
If a new START or STOP condition occurs within a message, the bus will return to IDLE-mode.
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10 Register definitions
WARNING: Any writes to RESERVED registers or bits can result in unexpected operation. This
section gives an overview of all user accessible registers in the Register map table.
Detailed descriptions are given in Register description tables, which are grouped per functional block.
10.1 Register map
Table 38: Register map
A d d r ess
F unct i o n
7
1
CONTROL
WRITE_M ODE
6
5
4
3
2
1
NOISE_SUP
BIAS_EN
V_IO
M UTING
SOFTM UTED
I2S_LOCK
2
STATUS
3
STARTUP1
4
STARTUP2
STARTUP2[ 6:0]
5
STARTUP3
STARTUP3[ 6:0]
7
M IC_L
M IC_L_EN
8
M IC_R
M IC_R_EN
9
AUX1_L
AUX1_L_EN
AUX1_L_VOL[ 5:0]
0a
AUX1_R
AUX1_R_EN
AUX1_R_VOL[ 5:0]
0c
IN_GAIN
SC_CLK_DIS
SC_OVERRIDE
M ICBIAS_EN
M ICBIAS_SEL[ 1:0]
0
PLL_LOCK
0b00000000
SC_M ST_EN
0b00000000
0b00000000
0b00000000
M IC_L_M UTE
M IC_L_VOL[ 2:0]
0b00000000
M IC_R_M UTE
M IC_R_VOL[ 2:0]
0b00000000
INPGA_R_VOL[ 3:0]
0b00010000
0b00010000
INPGA_L_VOL[ 3:0]
0d
INM IX_L
IN_L_EN
0e
INM IX_R
IN_R_EN
IN_R_IN_L
0f
ADC_HPF
ADC_VOICE_EN
ADC_VOICE_F0[ 2:0]
10
ADC
ADC_R_EN
D ef aul t
0b00010000
0b00000000
IN_L_OUTM IX_L
IN_L_A1_L
IN_L_M IC_R
IN_L_M IC_L
0b00000000
IN_R_OUTM IX_R
IN_R_A1_R
IN_L_M IC_L
IN_L_M IC_R
0b00000000
ADC_HPF_EN
ADC_R_M UTE
ADC_L_EN
ADC_HPF_F0[ 1:0]
ADC_L_M UTE
ALC_EN
0b00001000
0b00000000
11
ADC_EQ1_2
ADC_EQ2_VOL[ 7:4]
ADC_EQ1_VOL[ 3:0]
0b00000000
12
ADC_EQ3_4
ADC_EQ4_VOL[ 7:4]
ADC_EQ3_VOL[ 3:0]
0b00000000
13
ADC_EQ5
ADC_EQ_EN
ADC_EQ5_VOL[ 3:0]
0b00000000
14
DAC_HPF
DAC_VOICE_EN
15
DAC_L
DAC_L_INV
DAC_L_GAIN[ 6:0]
16
DAC_R
DAC_R_INV
DAC_R_GAIN[ 6:0]
17
DAC_SEL
DAC_R_EN
18
SOFT_M UTE
SOFT_M UTE
ADC_EQ_GAIN[ 1:0]
DAC_VOICE_F0[ 2:0]
DAC_HPF_EN
DAC_R_SRC[ 2:0]
DAC_M UTE
DAC_HPF_F0[ 1:0]
0b00001000
0b00010000
0b00010000
DAC_L_EN
RAM P_EN
DAC_L_SRC[ 2:0]
0b01010100
M UTE_RATE[ 2:0]
0b01000000
19
DAC_EQ1_2
DAC_EQ2_VOL[ 7:4]
DAC_EQ1_VOL[ 3:0]
0b00000000
1a
DAC_EQ3_4
DAC_EQ4_VOL[ 7:4]
DAC_EQ3_VOL[ 3:0]
0b00000000
1b
DAC_EQ5
DAC_EQ_EN
1c
OUTM IX_L
OUT_L_EN
OUT_L_INV
OUT_L_DAC_L
OUT_L_IN_R
OUT_L_IN_L
OUT_L_A1_L
0b00000000
1d
OUTM IX_R
OUT_R_EN
OUT_R_INV
OUT_R_DAC_R
OUT_R_IN_R
OUT_R_IN_L
OUT_R_A1_R
0b00000000
1e
OUT1_L
OUT1_L_EN
OUT1_L_SE
OUT1_L_VOL[ 5:0]
1f
OUT1_R
OUT1_R_EN
OUT1_R_SE
OUT1_R_VOL[ 5:0]
0b00110101
21
HP_L_VOL
HP_L_VOL[ 5:0]
0b00010000
22
HP_R_VOL
23
HP_CFG
HP_R_EN
HP_M ODE
24
ZEROX
HPZX_R_EN
HPZX_L_EN
25
DAC_EQ_GAIN
DAC_EQ5_VOL[ 3:0]
0b00000000
0b00110101
HP_R_VOL[ 5:0]
DAI_SRC_SEL DAI_IN_R_M IX
STEREO_TRACK HP_HIGHZ_R
OUTZX_R_EN
OUTZX_L_EN
DAI_OUT_R_SRC[ 2:0]
INZX_R_EN
HP_2CAP_M ODE HP_HIGHZ_L
INZX_L_EN
DAI_IN_L_M IX
A1ZX_L_EN
DAI_OUT_L_SRC[ 2:0]
DAI_FRAM E[ 1:0]
0b00000010
0b00000000
0b01110110
DAI_CFG1
27
DAI_CFG2
28
DAI_CFG3
29
PLL_DIV1
2a
PLL_DIV2
2b
PLL_DIV3
2c
PLL
2d
GP1A_A0L
GP1A_A0L[ 7:0]
2e
GP1A_A0H
GP1A_A0H[ 7:0]
0b01000000
2f
GP1B_A0L
GP1B_A0L[ 7:0]
0b00000000
30
GP1B_A0H
GP1B_A0H[ 7:0]
0b01000000
31
GP2A_A0L
GP2A_A0L[ 7:0]
0b00000000
CFR0011-120-00 Rev 5
DAI_TDM _M ONO
A1ZX_R_EN
26
Datasheet
DAI_M ODE
0b00010000
HP_L_EN
DAI_WORD[ 1:0]
0b00000000
DAI_TDM _OFFS[ 7:0]
DAI_EN
DAI_OE
0b00000000
DAI_TDM
DAI_FORM AT[ 1:0]
PLL_DIV_H[ 7:0]
PLL_DIV_M [ 7:0]
PLL_BYP
PLL_EN
M CLK_RANGE[ 1:0]
M CLK_SRM _EN M CLK_DET_ENM CLK_SHAPE_EN
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0b00001000
0b00000000
0b00000000
PLL_DIV_L[ 3:0]
FS[ 3:0]
0b00010000
0b00001010
0b00000000
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Ultra-low power stereo codec
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32
GP2A_A0H
GP2A_A0H[ 7:0]
0b01000000
33
GP2B_A0L
GP2B_A0L[ 7:0]
0b00000000
34
GP2B_A0H
GP2B_A0H[ 7:0]
0b01000000
35
GP1C_A0L
GP1C_A0L[ 7:0]
0b00000000
36
GP1C_A0H
GP1C_A0H[ 7:0]
0b01000000
37
GP1D_A0L
GP1D_A0L[ 7:0]
0b00000000
38
GP1D_A0H
GP1D_A0H[ 7:0]
0b01000000
39
GP2C_A0L
GP2C_A0L[ 7:0]
0b00000000
3a
GP2C_A0H
GP2C_A0H[ 7:0]
0b01000000
3b
GP2D_A0L
GP2D_A0L[ 7:0]
0b00000000
3c
GP2D_A0H
GP2D_A0H[ 7:0]
0b01000000
3d
GP1A_A1L
GP1A_A1L[ 7:0]
0b00000000
3e
GP1A_A1H
GP1A_A1H[ 7:0]
0b00000000
3f
GP1B_A1L
GP1B_A1L[ 7:0]
0b00000000
40
GP1B_A1H
GP1B_A1H[ 7:0]
0b00000000
41
GP2A_A1L
GP2A_A1L[ 7:0]
0b00000000
42
GP2A_A1H
GP2A_A1H[ 7:0]
0b00000000
43
GP2B_A1L
GP2B_A1L[ 7:0]
0b00000000
44
GP2B_A1H
GP2B_A1H[ 7:0]
0b00000000
45
GP1C_A1L
GP1C_A1L[ 7:0]
0b00000000
46
GP1C_A1H
GP1C_A1H[ 7:0]
0b00000000
47
GP1D_A1L
GP1D_A1L[ 7:0]
0b00000000
48
GP1D_A1H
GP1D_A1H[ 7:0]
0b00000000
49
GP2C_A1L
GP2C_A1L[ 7:0]
0b00000000
4a
GP2C_A1H
GP2C_A1H[ 7:0]
0b00000000
4b
GP2D_A1L
GP2D_A1L[ 7:0]
0b00000000
4c
GP2D_A1H
GP2D_A1H[ 7:0]
0b00000000
4d
GP1A_A2L
GP1A_A2L[ 7:0]
0b00000000
4e
GP1A_A2H
GP1A_A2H[ 7:0]
0b00000000
4f
GP1B_A2L
GP1B_A2L[ 7:0]
0b00000000
50
GP1B_A2H
GP1B_A2H[ 7:0]
0b00000000
51
GP2A_A2L
GP2A_A2L[ 7:0]
0b00000000
52
GP2A_A2H
GP2A_A2H[ 7:0]
0b00000000
53
GP2B_A2L
GP2B_A2L[ 7:0]
0b00000000
54
GP2B_A2H
GP2B_A2H[ 7:0]
0b00000000
55
GP1C_A2L
GP1C_A2L[ 7:0]
0b00000000
56
GP1C_A2H
GP1C_A2H[ 7:0]
0b00000000
57
GP1D_A2L
GP1D_A2L[ 7:0]
0b00000000
58
GP1D_A2H
GP1D_A2H[ 7:0]
0b00000000
59
GP2C_A2L
GP2C_A2L[ 7:0]
0b00000000
5a
GP2C_A2H
GP2C_A2H[ 7:0]
0b00000000
5b
GP2D_A2L
GP2D_A2L[ 7:0]
0b00000000
5c
GP2D_A2H
GP2D_A2H[ 7:0]
0b00000000
5d
GP1A_B1L
GP1A_B1L[ 7:0]
0b00000000
5e
GP1A_B1H
GP1A_B1H[ 7:0]
0b00000000
5f
GP1B_B1L
GP1B_B1L[ 7:0]
0b00000000
60
GP1B_B1H
GP1B_B1H[ 7:0]
0b00000000
61
GP2A_B1L
GP2A_B1L[ 7:0]
0b00000000
62
GP2A_B1H
GP2A_B1H[ 7:0]
0b00000000
63
GP2B_B1L
GP2B_B1L[ 7:0]
0b00000000
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64
GP2B_B1H
GP2B_B1H[ 7:0]
0b00000000
65
GP1C_B1L
GP1C_B1L[ 7:0]
0b00000000
66
GP1C_B1H
GP1C_B1H[ 7:0]
0b00000000
67
GP1D_B1L
GP1D_B1L[ 7:0]
0b00000000
68
GP1D_B1H
GP1D_B1H[ 7:0]
0b00000000
69
GP2C_B1L
GP2C_B1L[ 7:0]
0b00000000
6a
GP2C_B1H
GP2C_B1H[ 7:0]
0b00000000
6b
GP2D_B1L
GP2D_B1L[ 7:0]
0b00000000
6c
GP2D_B1H
GP2D_B1H[ 7:0]
0b00000000
6d
GP1A_B2L
GP1A_B2L[ 7:0]
0b00000000
6e
GP1A_B2H
GP1A_B2H[ 7:0]
0b00000000
6f
GP1B_B2L
GP1B_B2L[ 7:0]
0b00000000
70
GP1B_B2H
GP1B_B2H[ 7:0]
0b00000000
71
GP2A_B2L
GP2A_B2L[ 7:0]
0b00000000
72
GP2A_B2H
GP2A_B2H[ 7:0]
0b00000000
73
GP2B_B2L
GP2B_B2L[ 7:0]
0b00000000
74
GP2B_B2H
GP2B_B2H[ 7:0]
0b00000000
75
GP1C_B2L
GP1C_B2L[ 7:0]
0b00000000
76
GP1C_B2H
GP1C_B2H[ 7:0]
0b00000000
77
GP1D_B2L
GP1D_B2L[ 7:0]
0b00000000
78
GP1D_B2H
GP1D_B2H[ 7:0]
0b00000000
79
GP2C_B2L
GP2C_B2L[ 7:0]
0b00000000
7a
GP2C_B2H
GP2C_B2H[ 7:0]
0b00000000
7b
GP2D_B2L
GP2D_B2L[ 7:0]
0b00000000
7c
GP2D_B2H
GP2D_B2H[ 7:0]
7d
GPF_SRC1
GP_2AB_SRC[ 2:0]
GP_1AB_SRC[ 2:0]
7e
GPF_SRC2
GP_2CD_SRC[ 2:0]
GP_1CD_SRC[ 2:0]
7f
DSP_CFG
DSP_M IX[ 2:0]
81
CHIP_ID
82
INTERFACE
IF_BASE_ADDR[ 2:0]
83
ALC_M AX
ALC_M ERGE
0b00000000
GP_2CD_EN
GP_1CD_EN
M RC[ 3:0]
GP_2AB_EN
0b01100100
0b01110101
GP_1AB_EN
M M RC[ 3:0]
0b00000000
0b00010001
0b00101100
ALC_M AX[ 5:0]
0b01000000
84
ALC_M IN
ALC_M IN[ 5:0]
0b00000000
85
ALC_NOIS
ALC_NOIS[ 5:0]
0b00000000
86
ALC_ATT
ALC_ATT[ 7:0]
0b00000000
87
ALC_REL
ALC_REL[ 7:0]
0b00000000
88
ALC_DEL
ALC_DEL[ 7:0]
0b00000000
8A
A_HID_UNLOCK
A_HID_UNLOCK[ 7:0]
0b00000000
8B
A_TEST_UNLOCK
A_TEST_UNLOCK[ 7:0]
8F
A_PLL0
90
A_PLL1
95
A_ADC0
96
A_DAC0
A_CPHP6
A2
A7
A_CP_M ODE
Datasheet
CFR0011-120-00 Rev 5
0b00000000
SIGDEL DISABLE 0b00000000
VCORST_EN
ADC_T2
0b00000000
0b00000000
VM ID_BUFF_EN
0b00000000
CP _RISE_TIM E
0b10000000
A_CP_M ODE[ 7:0]
0b01111110
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10.2 Control and status registers
Table 39: CONTROL 0x01
Bit
Mode
Symbol
Description
Reset
7
R/W
WRITE_MODE
2-wire multiple write mode
0
0 = page Write Mode
1 = repeated Write Mode
6:4
R
Reserved
Reserved
001
3
R/W
NOISE_SUP
Enable noise suppression mode (see section 8.2.5)
0
2
R/W
BIAS_EN
Bias current to the entire chip
0
0 = bias off (device power down)
1 = supply bias current (device in operation)
1
R
VDDIO_RANGE
VDDIO voltage
0 = VDDIO > 2.65 V
0
1 = VDDIO <= 2.65 V
Must be set to 1
0
R
REG_EN
Digital Regulator enable
0
0 = disable
1 = enable
Table 40: STATUS 0x02
Bit
Mode
Symbol
Description
Reset
7:4
R
Reserved
Reserved
0000
3
R
MUTING
0 = unmute
0
1 = mute
2
R
SOFTMUTED
0 = normal mute
1 = softmute (ref. SOFTMUTE section)
0
1
R
I2S_LOCK
Digital audio interface (DAI) lock status
0 = not locked
0
1 = locked to frame rate lock
0
R
PLL_LOCK
PLL status
0
0 = PLL not locked
1 = PLL locked
Datasheet
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Table 41: STARTUP 1 0x03
Bit
Mode
Symbol
Description
Reset
7
W
SC_CLK_DIS
System Controller Clock Disable
0
0 = clock enabled
1 = clock disabled (provides power saving)
6:5
R
Reserved
Reserved
00
4
R/W
SC_OVERRIDE
Test enable that forces everything to be enabled
instantly on the next clock cycle
0
3:1
R
Reserved
Reserved
00
0
R/W
SC_MST_EN
System Controller Master Enable. All subsystems
should be enabled first before enabling this bit.
0 = everything off
1 = device active
0
Table 42: STARTUP 2 0x04
Bit
Mode
Symbol
Description
Reset
7
R
Reserved
Reserved
0
6:0
R/W
STARTUP2
Output standby control.
0000000
0 = normal
1 = standby
[6] – DAC R standby
[5] – DAC L standby
[4] – HP R standby
[3] – HP L standby
[2] – Reserved
[1] – OUT1R standby
[0] – OUT1L standby
Datasheet
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Table 43: STARTUP 3 0x05
Bit
Mode
Symbol
Description
Reset
7
R
Reserved
Reserved
0
6:0
R/W
STARTUP3
Input standby control.
0 = normal
1 = standby
0000000
[6] – ADC R standby
[5] – ADC L standby
[4] – Reserved
[3] – AUX1_R input standby
[2] – AUX1_L input standby
[1] – MIC_R input standby
[0] – MIC_L input standby
Note: Standby is to reduce the power consumption
and not necessarily to mute the block.
10.3 Codec registers
Table 44: MIC_L 0x07
Bit
Mode
Symbol
Description
Reset
7
R/W
MIC_L_EN
Enable left MIC amplifier
0
0 = disable
1 = enable (must be set beforeRes SC_MST_EN)
6
R/W
MICBIAS_EN
Enable MICBIAS supply
0 = disable
0
1 = enable
5:4
R/W
MICBIAS_SEL
MIC bias voltage selection
00 = 1.5 V
01 = 1.6 V
3
R/W
MIC_L_MUTE
00
10 = 2.2 V
11 = 2.3 V
Mute left MIC amplifier
0
0 = unmute
1 = mute
2:0
R/W
MIC_L_VOL
Gain of left MIC amplifier
000 = -6 dB
000
001 = 0 dB
010 = +6 dB
011 = +12 dB
100 = +18 dB
101/110/111 = +24 dB
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Table 45: MIC_R 0x08
Bit
Mode
Symbol
Description
Reset
7
R/W
MIC_R_EN
Enable right MIC amplifier
0
0 = disable
1 = enable (must be set before SC_MST_EN)
6:4
R
Reserved
Reserved
000
3
R/W
MIC_R_MUTE
Mute right MIC amplifier
0 = unmute
0
1 = mute
2:0
R/W
MIC_R_VOL
Gain of right MIC amplifier
000
Setting option is the same as L-channel (0x7[2:0])
Table 46: AUX1_L 0x09
Bit
Mode
Symbol
Description
Reset
7
R/W
AUX1_L_EN
Enable left AUX1 amplifier
0
0 = disable
1 = enable (must be set before SC_MST_EN)
6
R
Reserved
Reserved
0
5:0
R/W
AUX1_L_VOL
Gain of left AUX1 amplifier
000000 to 010000 (default) = mute
010000
010001 = -54 dB
010010 = -52.5 dB
010011 = -51 dB
…
continuing in 1.5 dB steps through
110101 = 0 dB, to
…
111111 = +15 dB
Table 47: AUX1_R 0x0A
Bit
Mode
Symbol
Description
Reset
7
R/W
AUX1_R_EN
Enable right AUX1 amplifier
0 = disable
0
1 = enable (must be set before SC_MST_EN)
6
R
Reserved
Reserved
0
5:0
R/W
AUX1_R_VOL
Gain of right AUX1 amplifier
010000
000000 to 010000 (default) = mute
010001 = -54 dB
010010 = -52.5 dB
010011 = -51 dB
…
continuing in 1.5 dB steps through
110101 = 0 dB, to
…
111111 = +15 dB
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Table 48: IN_GAIN 0x0C
Bit
Mode
Symbol
Description
Reset
7:4
R/W
INPGA_R_VOL
Gain of right input PGA
0000
0000 = -4.5 dB
0001 = -3 dB
0010 = -1.5 dB
0011 = 0 dB
0100 = +1.5 dB
0101 = + 3 dB
0110 = +4.5 dB
0111 = + 6 dB
1000 = + 7.5 dB
1001 = + 9 dB
1010 = +10.5 dB
1011 = +12 dB
1100 = +13.5 dB
1101 = +15 dB
1110 = +16.5 dB
1111 = +18 dB
While ALC is active, the gain is controlled by ALC
and this register setting is not effective.
3:0
R/W
INPGA_L_VOL
Gain of left input PGA
0000
0000 = -4.5 dB
0001 = -3 dB
0010 = -1.5 dB
0011 = 0 dB
0100 = +1.5 dB
0101 = + 3 dB
0110 = +4.5 dB
0111 = + 6 dB
1000 = + 7.5 dB
1001 = + 9 dB
1010 = +10.5 dB
1011 = +12 dB
1100 = +13.5 dB
1101 = +15 dB
1110 = +16.5 dB
1111 = +18 dB
While ALC is active, the gain is controlled by ALC
and this register setting is not effective.
Datasheet
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Table 49: INMIX_L 0x0D
Bit
Mode
Symbol
Description
Reset
7
R/W
IN_L_EN
Enable left input PGA
0
0 = disable
1 = enable (must be set before SC_MST_EN)
6:5
R
Reserved
Reserved
00
4
R/W
IN_L_OUTMIX_L
1 = Add OUTMIX_L into input mixer L
0
3
R/W
Reserved
Reserved
0
2
R/W
IN_L_A1_L
1 = Add AUX1_L into input mixer L
0
1
R/W
IN_L_MIC_R
1 = Add MIC_R into input mixer L
0
0
R/W
IN_L_MIC_L
1 = Add MIC_L into input mixer L
0
Table 50: INMIX_R 0x0E
Bit
Mode
Symbol
Description
Reset
7
R/W
IN_R_EN
Enable right input PGA
0 = disable
0
1 = enable (must be set before SC_MST_EN)
6
R
Reserved
Reserved
0
5
R/W
IN_R_IN_L
1 = Add INPGA_L (stereo to mono)
0
4
R/W
IN_R_OUTMIX_R
1 = Add OUTMIX_R into input mixer R
0
3
R
Reserved
Reserved
0
2
R/W
IN_R_A1_R
1 = Add AUX1_R into input mixer R
0
1
R/W
IN_R_MIC_L
1 = Add MIC_L into input mixer R
0
0
R/W
IN_R_MIC_R
1 = Add MIC_R into input mixer R
0
Datasheet
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Table 51: ADC_HPF 0x0F
Bit
Mode
Symbol
Description
Reset
ADC Voice Filter
7
R/W
ADC_VOICE_EN
0 = disable
1 = enable
0
ADC Voice (8 kHz) High pass 3 dB cut-off at:
000 = 2.5 Hz
001 = 25 Hz
010 = 50 Hz
6:4
R/W
ADC_VOICE_F0
011 = 100 Hz
100 = 150 Hz
000
101 = 200 Hz
110 = 300 Hz
111 = 400 Hz
3
R/W
ADC_HPF_EN
ADC High Pass Filter
0 = disable
1
1 = enable
2
R
Reserved
Reserved
0
ADC High Pass Filter f0 is at
00 = Fs/8192 x π
1:0
R/W
ADC_HPF_F0
01 = Fs/4096 x π
10 = Fs/2048 x π
00
11 = Fs/1024 x π
Table 52: ADC 0x10
Bit
7
Mode
R/W
Symbol
Description
Reset
ADC_R_EN
Enable right ADC channel
0 = disable
0
1 = enable (must be set before SC_MST_EN)
Mute right ADC channel
6
R/W
ADC_R_MUTE
0 = unmute
1 = mute
0
5:4
R
Reserved
Reserved
00
3
R/W
ADC_L_EN
Enable left ADC channel
0 = disable
0
1 = enable (must be set before SC_MST_EN)
Mute left ADC channel
2
R/W
ADC_L_MUTE
0 = unmute
1 = mute
0
1
R
Reserved
Reserved
0
0
RW
ALC_EN
ALC enable
0 = disable
0
1 = enable
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Table 53: ADC_EQ1_2 0x11
Bit
Mode
Symbol
Description
7:4
R/W
ADC_EQ2_VOL
Gain of ADC 5-Band EQ band 2:
Reset
0000 = +12 dB
0001 =+10.5 dB
0010 =+9 dB
0011 =+7.5 dB
0100 =+6 dB
0101 =+4.5 dB
0110 =+3 dB
0111 =+1.5 dB
0000
1000= 0 dB
1001= - 1.5 dB
1010= - 3 dB
1011= - 4.5 dB
1100= - 6 dB
1101= - 7.5 dB
1110= - 9 dB
1111= -10.5 dB
3:0
R/W
ADC_EQ1_VOL
Gain of ADC 5-Band EQ band 1:
0000 = +12 dB
0001 =+10.5 dB
0010 =+9 dB
0011 =+7.5 dB
0100 =+6 dB
0101 =+4.5 dB
0110 =+3 dB
0111 =+1.5 dB
1000= 0 dB
0000
1001= - 1.5 dB
1010= - 3 dB
1011= - 4.5 dB
1100= - 6 dB
1101= - 7.5 dB
1110= - 9 dB
1111= -10.5 dB
Datasheet
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Table 54: ADC_EQ3_4 0x12
Bit
Mode
Symbol
Description
7:4
R/W
ADC_EQ4_VOL
Gain of ADC 5-Band EQ band 4:
Reset
0000 = +12 dB
0001 =+10.5 dB
0010 =+9 dB
0011 =+7.5 dB
0100 =+6 dB
0101 =+4.5 dB
0110 =+3 dB
0111 =+1.5 dB
0000
1000= 0 dB
1001= - 1.5 dB
1010= - 3 dB
1011= - 4.5 dB
1100= - 6 dB
1101= - 7.5 dB
1110= - 9 dB
1111= -10.5 dB
3:0
R/W
ADC_EQ3_VOL
Gain of ADC 5-Band EQ band 3:
0000 = +12 dB
0001 =+10.5 dB
0010 =+9 dB
0011 =+7.5 dB
0100 =+6 dB
0101 =+4.5 dB
0110 =+3 dB
0111 =+1.5 dB
1000= 0 dB
0000
1001= - 1.5 dB
1010= - 3 dB
1011= - 4.5 dB
1100= - 6 dB
1101= - 7.5 dB
1110= - 9 dB
1111= -10.5 dB
Datasheet
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Table 55: ADC_EQ5 0x13
Bit
Mode
Symbol
Description
Reset
7
R/W
ADC_EQ_EN
0 = disable
1 = enable
7
6
R
Reserved
Reserved
6
Enable ADC 5-Band EQ
Gain of ADC 5-BandEQ:
00 = 0 dB
5:4
R/W
ADC_EQ_GAIN
01 = -6 dB
10 = -12 dB
5:4
11 = -18 dB
Gain of ADC 5-Band EQ band 5:
0000 = +12 dB
0001 =+10.5 dB
0010 =+9 dB
0011 =+7.5 dB
0100 =+6 dB
0101 =+4.5 dB
3:0
R/W
ADC_EQ5_VOL
0110 =+3 dB
0111 =+1.5 dB
3:0
1000= 0 dB
1001= - 1.5 dB
1010= - 3 dB
1011= - 4.5 dB
1100= - 6 dB
1101= - 7.5 dB
1110= - 9 dB
1111= -10.5 dB
Datasheet
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Table 56: DAC_HPF 0x14
Bit
Mode
Symbol
7
R/W
DAC_VOICE_EN
Description
Reset
DAC Voice Filter
0 = disable
1 = enable
0
DAC Voice (8 kHz) High pass 3 dB cut-off at:
000 = 2.5 Hz
001 = 25 Hz
010 = 50 Hz
6:4
R/W
DAC_VOICE_F0
011 = 100 Hz
100 = 150 Hz
000
101 = 200 Hz
110 = 300 Hz
111 = 400 Hz
For 11.025/12.0 and 16 kHz see Table 26
DAC High Pass Filter
3
R/W
DAC_HPF_EN
0 = disable
1 = enable
1
2
R/W
DAC_MUTE
Mute DAC (both channels)
0
DAC High Pass Filter f0 is at
1:0
R/W
DAC_HPF_F0
00 = Fs/8192 x π
01 = Fs/4096 x π
00
10 = Fs/2048 x π
11 = Fs/1024 x π
Table 57: DAC_L 0x15
Bit
Mode
Symbol
Description
Reset
7
R/W
DAC_L_INV
left DAC channel inversion
0 = normal
0
1 = Inverted
DAC left channel digital volume control
0000000 = 12 db
0000001 = 11.25 dB
…
6:0
R/W
DAC_L_GAIN
continuing in 0.75 dB steps through
0010000 = 0 dB
0010000
0010001 = -0.75 dB
…to
1110111 = -77.25 dB
1111xxx = mute
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Table 58: DAC_R 0x16
Bit
Mode
Symbol
7
R/W
DAC_R_INV
Description
Reset
0 = normal
0
1 = Invert right DAC channel
DAC right channel digital volume control
0000000 = 12 db
0000001 = 11.25 dB
6:0
R/W
DAC_R_GAIN
…
continuing in 0.75 dB steps through
0010000
0010000 = 0 dB
0010001 = -0.75 dB
…to
1110111 = -77.25 dB
1111xxx = mute
Table 59: DAC_SEL 0x17
Bit
7
Mode
R/W
Symbol
Description
Reset
DAC_R_EN
Enable right DAC channel
0 = disable
0
1 = enable (must be set before SC_MST_EN)
DAC_R input source selection:
000 = 1AB
001 = 2AB
6:4
R/W
DAC_R_SRC
010 = 1CD
011 = 2CD
101
100 = DAI_L
101 = DAI_R
110 = ADC_L
111 = ADC_R
3
R/W
DAC_L_EN
Enable left DAC channel
0 = disable
0
1 = enable (must be set before SC_MST_EN)
DAC_L input source selection:
000 = 1AB
001 = 2AB
010 = 1CD
2:0
R/W
DAC_L_SRC
011 = 2CD
100 = DAI_L
100
101 = DAI_R
110 = ADC_L
111 = ADC_R
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Table 60: SOFTMUTE 0x18
Bit
Mode
Symbol
R/W
SOFT_MUTE
R/W
RAMP_EN
7
6
Description
Reset
Softmute trigger
0 = disabled
1 = start SOFTMUTE
Digital gain ramping
0 = disabled (immediate)
0
1
1 = enabled (ramping)
5:3
R
Reserved
Reserved
000
000 = 1 sample/0.1875 dB
001 = 2 samples/0.1875 dB
010 = 4 samples/0.1875 dB
2:0
R/W
MUTE_RATE
011 = 8 samples/0.1875 dB
100 = 16 samples/0.1875 dB
000
101 = 32 samples/0.1875 dB
110 = 64 samples/0.1875 dB
111 = not used
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Table 61: DAC_EQ1_2 0x19
Bit
Mode
Symbol
Description
7:4
R/W
DAC_EQ2_VOL
Gain of DAC 5-Band EQ band 2:
Reset
0000 = +12 dB
0001 =+10.5 dB
0010 =+9 dB
0011 =+7.5 dB
0100 =+6 dB
0101 =+4.5 dB
0110 =+3 dB
0111 =+1.5 dB
0000
1000= 0 dB
1001= - 1.5 dB
1010= - 3 dB
1011= - 4.5 dB
1100= - 6 dB
1101= - 7.5 dB
1110= - 9 dB
1111= -10.5 dB
3:0
R/W
DAC_EQ1_VOL
Gain of DAC 5-Band EQ band 1:
0000 = +12 dB
0001 =+10.5 dB
0010 =+9 dB
0011 =+7.5 dB
0100 =+6 dB
0101 =+4.5 dB
0110 =+3 dB
0111 =+1.5 dB
1000= 0 dB
0000
1001= - 1.5 dB
1010= - 3 dB
1011= - 4.5 dB
1100= - 6 dB
1101= - 7.5 dB
1110= - 9 dB
1111= -10.5 dB
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Table 62: DAC_EQ3_4 0x1A
Bit
Mode
Symbol
Description
7:4
R/W
DAC_EQ4_VOL
Gain of DAC 5-Band EQ band 4:
Reset
0000 = +12 dB
0001 =+10.5 dB
0010 =+9 dB
0011 =+7.5 dB
0100 =+6 dB
0101 =+4.5 dB
0110 =+3 dB
0111 =+1.5 dB
0000
1000= 0 dB
1001= - 1.5 dB
1010= - 3 dB
1011= - 4.5 dB
1100= - 6 dB
1101= - 7.5 dB
1110= - 9 dB
1111= -10.5 dB
3:0
R/W
DAC_EQ3_VOL
Gain of DAC 5-Band EQ band 3:
0000 = +12 dB
0001 =+10.5 dB
0010 =+9 dB
0011 =+7.5 dB
0100 =+6 dB
0101 =+4.5 dB
0110 =+3 dB
0111 =+1.5 dB
1000= 0 dB
0000
1001= - 1.5 dB
1010= - 3 dB
1011= - 4.5 dB
1100= - 6 dB
1101= - 7.5 dB
1110= - 9 dB
1111= -10.5 dB
Datasheet
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Table 63: DAC_EQ5 0x1B
Bit
Mode
Symbol
Description
Reset
7
R/W
DAC_EQ_EN
0 = disable
1 = enable
0
6:4
R
Reserved
Reserved
000
Enable DAC 5-Band EQ
Gain of DAC 5-Band EQ band 5:
0000 = +12 dB
0001 =+10.5 dB
0010 =+9 dB
0011 =+7.5 dB
0100 =+6 dB
0101 =+4.5 dB
0110 =+3 dB
3:0
R/W
DAC_EQ5_VOL
0111 =+1.5 dB
1000= 0 dB
0000
1001= - 1.5 dB
1010= - 3 dB
1011= - 4.5 dB
1100= - 6 dB
1101= - 7.5 dB
1110= - 9 dB
1111= -10.5 dB
Table 64: OUTMIX_L 0x1C
Bit
Mode
Symbol
Description
Reset
Enable left output PGA
7
6
R/W
R/W
OUT_L_EN
OUT_L_INV
0 = disable
1 = enable (must be set before SC_MST_EN)
0
OUTMIX left channel inversion
0 = normal
0
1 = Invert (not active for signal routed from DAC_L)
5
R
Reserved
Reserved
0
4
R/W
OUT_L_DAC_L
1 = Add DAC_L
0
3
R/W
OUT_L_IN_R
1 = Add IN_R
0
2
R/W
OUT_L_IN_L
1 = Add IN_L
0
1
R
Reserved
Reserved
0
0
R/W
OUT_L_A1_L
1 = Add AUX1_L
0
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Table 65: OUTMIX_R 0x1D
Bit
Mode
Symbol
7
R/W
OUT_R_EN
6
R/W
OUT_R_INV
Description
Reset
Enable right output PGA
0 = disable
1 = enable (must be set before SC_MST_EN)
0
OUTMIX right channel inversion
0 = normal
0
1 = Invert (not active for signal routed from DAC_L)
5
R
Reserved
Reserved
0
4
R/W
OUT_R_DAC_R
1 = Add DAC_R
0
3
R/W
OUT_R_IN_R
1 = Add IN_R
0
2
R/W
OUT_R_IN_L
1 = Add IN_L
0
1
R
Reserved
Reserved
0
0
R/W
OUT_R_A1_R
1 = Add AUX1_R
0
Table 66: OUT1_L 0x1E
Bit
Mode
Symbol
Description
Reset
7
R/W
OUT1_L_EN
Enable left OUT1 amplifier
0 = disable
0
1 = enable (must be set before SC_MST_EN)
OUT1 L single-ended mode selection
6
R/W
OUT1_L_SE
0 = differential mode
1 = single-ended mode
0
OUT1 left channel volume control
000000 – 001111 = Reserved
010000 = mute
010001 = -54 dB
5:0
R/W
OUT1_L_VOL
010010 = -52.5 dB
… continuing in 1.5 dB steps through
110101
110101 = 0 dB (default)
to…
111111 = 15 dB
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Table 67: OUT1_R 0x1F
Bit
Mode
Symbol
7
R/W
OUT1_R_EN
6
R/W
OUT1_R_SE
Description
Reset
Enable right OUT1 amplifier
0 = disable
1 = enable (must be set before SC_MST_EN)
0
OUT1 R single-ended mode selection
0 = differential mode
0
1 = single-ended mode
OUT1 right channel volume control
000000 – 001111 = Reserved
010000 = mute
010001 = -54 dB
010010 = -52.5 dB
5:0
R/W
OUT1_R_VOL
110101
… continuing in 1.5 dB steps through
110101 = 0 dB (default)
to…
111111 = 15 dB
Table 68: HP_L_VOL 0x21
Bit
Mode
Symbol
Description
Reset
7:6
R
Reserved
Reserved
00
Head phone left channel volume control
000000 – 001111 = Reserved
010000 = mute (default)
010001 = -54 dB
010010 = -52.5 dB
5:0
R/W
HP_L_VOL
… continuing in 1.5 dB steps through
110101 = 0 dB
010000
to…
111111 = 15 dB
If you wish the right channel volume to be the same
as left channel, please refer to 0x23 HP_CFG[5]
STEREO_TRACK
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Table 69: HP_R_VOL 0x22
Bit
Mode
Symbol
Description
Reset
7:6
R
Reserved
Reserved
00
Head phone right channel volume control
000000 – 001111 = Reserved
010000 = mute (default)
010001 = -54 dB
010010 = -52.5 dB
5:0
R/W
HP_R_VOL
… continuing in 1.5 dB steps through
110101 = 0 dB
010000
to…
111111 = 15 dB
If you wish the right channel volume to be the same
as left channel, please refer to 0x23 HP_CFG[5]
STEREO_TRACK
Table 70: HP_CFG 0x23
Bit
7
Mode
R/W
Symbol
Description
Reset
0
HP_R_EN
Enable right headphone amplifier
0 = disable
1 = enable (must be set before SC_MST_EN)
6
R/W
Reserved
Reserved
0
5
R/W
STEREO_TRACK
1 = HP_R volume also controls HP_L
0
4
R/W
HP_HIGHZ_R
Set right head phone out to high impedance
0
3
R/W
HP_L_EN
0 = disable
1 = enable (must be set before SC_MST_EN)
0
2
R/W
Reserved
Reserved
0
1
R/W
HP_2CAP_MODE
Set charge pump to 2 capacitor mode
1
0
R/W
HP_HIGHZ_L
Set left head phone out to high impedance
0
Enable left headphone amplifier
Table 71: ZEROX 0x24
Bit
Mode
Symbol
Description
Reset
7
R/W
HPZX_R_EN
Enable zero crossing for right HP gain update
0
6
R/W
HPZX_L_EN
Enable zero crossing for left HP gain update
0
5
R/W
OUTZX_R_EN
Enable zero crossing for right OUT1 gain update
0
4
R/W
OUTZX_L_EN
Enable zero crossing for left OUT1 gain update
0
3
R/W
INZX_R_EN
Enable zero crossing for right input PGA gain
update
0
2
R/W
INZX_L_EN
Enable zero crossing for left input PGA gain update
0
1
R/W
AUX1ZX_R_EN
Enable zero crossing for right AUX1 amp gain
update
0
0
R/W
AUX1ZX_L_EN
Enable zero crossing for left AUX1 amp gain update
0
Datasheet
CFR0011-120-00 Rev 5
Revision 3e
86 of 105
15-Oct-2015
© 2015 Dialog Semiconductor
DA7211
Ultra-low power stereo codec
Company confidential
Table 72: DAI_SRC_SEL 0x25
Bit
Mode
Symbol
Description
Reset
7
R/W
DAI_IN_R_MIX
1 = DAI receive right channel is mixed from L+R
data
0
DAI_R transmit source selection:
000: = 1AB
001 = 2AB
6:4
R/W
DAI_OUT_R_SRC
010 = 1CD
011 = 2CD
111
100 = DAI_L (cross loop back)
101 = DAI_R (loop back)
110 = ADC_L
111 = ADC_R
3
R/W
DAI_IN_L_MIX
1 = DAI receive left channel is mixed from L+R data
0
DAI_L transmit source selection:
000: = 1AB
001 = 2AB
010 = 1CD
2:0
R/W
DAI_OUT_L_SRC
011 = 2CD
100 = DAI_L (cross loop back)
110
101 = DAI_R (loop back)
110 = ADC_L
111 = ADC_R
Table 73: DAI_CFG1 0x26
Bit
Mode
Symbol
7
R/W
DAI_MODE
6:5
R
Reserved
4
R/W
DAI_TDM_MONO
Description
Reset
0 = DA7211 is clock slave
0
1 = DA7211 is clock master
Reserved
00
0 = TDM mode is stereo
1 = TDM transmits/receives left channel left DAI
channel only
0
Data transmission frame length:
00 = 2xDAI_WORD
3:2
R/W
DAI_FRAME
01 = 64 bitclocks
10 = 128 bitclocks
00
11 = 256 bitclocks
Data word length:
00 = 16 bits
1:0
R/W
DAI_WORD
01 = 20 bits
10 = 24 bits
00
11 = 32 bits
Table 74: DAI_CFG2 0x27
Bit
Mode
Symbol
Description
Reset
7:0
R/W
DAI_TDM_OFFS
TDM data for device is valid at this offset from
beginning of frame. The offset is measured in the
number clock cycles.
00000000
Datasheet
CFR0011-120-00 Rev 5
Revision 3e
87 of 105
15-Oct-2015
© 2015 Dialog Semiconductor
DA7211
Ultra-low power stereo codec
Company confidential
Table 75: DAI_CFG3 0x28
Bit
Mode
Symbol
Description
Reset
7
R/W
DAI_EN
0 = disable
1 = enable
7
6:4
R
Reserved
Reserved
6:4
3
R/W
DAI_OE
DATOUT enable:
0 = disable (tristate when ADC is disabled)
3
Enable digital audio interface
1 = enabled
Tristate DATOUT mode enable
2
R/W
DAI_TDM
0 = disable (normal)
1 = enable (TDM mode)
2
Digital Audio Interface format selection
00 = I2S mode
1:0
R/W
DAI_FORMAT
01 = Left Justified mode
10 = right justified mode
1:0
11 = DSP mode
Table 76: PLL_DIV1 0x29
Bit
Mode
Symbol
Description
Reset
7:0
R/W
PLL_DIV_H
Feedback divider ratio bit [19:12].
Refer to Table 31 and Table 32 for suggested
settings.
00000000
Table 77: PLL_DIV2 0x2A
Bit
Mode
Symbol
Description
Reset
7:0
R/W
PLL_DIV_M
Feedback divider ratio bit [11:4].
Refer to Table 31 and Table 32 for suggested
settings.
00000000
Table 78: PLL_DIV3 0x2B
Bit
Mode
Symbol
Description
Reset
7
R
Reserved
Reserved
0
PLL_BYP
Bypass PLL
0 = disable (do not disable unless PLL is
operational)
1 = enable (PLL bypassed)
0
6
R/W
MCLK frequency range:
00 = 32.768 kHz
5:4
R/W
MCLK_RANGE
01 = 10-20 MHz
10 = 20-40 MHz
01
11 = 40-80 MHz
3:0
R/W
Datasheet
CFR0011-120-00 Rev 5
PLL_DIV_L
Feedback divider ratio bit [3:0].
Refer to Table 31 and Table 32 for suggested
settings.
Revision 3e
88 of 105
0000
15-Oct-2015
© 2015 Dialog Semiconductor
DA7211
Ultra-low power stereo codec
Company confidential
Table 79: PLL 0x2C
Bit
Mode
Symbol
7
R/W
PLL_EN
6
R/W
MCLK_SRM_EN
Description
Reset
PLL enable
0 = disable and bypass PLL
1 = enable PLL
0
Sample rate tracking
0 = disabled
0
1 = enabled
5
R/W
MCLK_DET_EN
automatic detection of sample rate
0 = disabled
0
1 = enabled
Enable MCLK shaper for low level non TTL signals
4
R/W
MCLK_SHAPE_EN
0 = disabled
1 = enabled
0
In MCLK_DET mode, the value read from this
register will be the automatically detected sample
rate from the PLL track circuitry. This will be
updated on the positive edge of the DAI clock.
0000 = reserved
0001 = 8 kHz
0010 = 11.025 kHz
0011 = 12 kHz
0100 = reserved
3:0
R/W
FS
0101 = 16 kHz
0110 = 22.05 kHz
1010
0111 = 24 kHz
1000= reserved
1001 = 32 kHz
1010 = 44.1 kHz
1011 = 48 kHz
1100 = reserved
1101 = reserved
1110 = 88.2 kHz
1111 = 96 kHz
10.4 GP filter engine
Table 80: GP1A A0L 0x2D
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1A A0L
A0L bit 7:0 of A0 coefficient
00000000
Table 81: GP1A A0H 0x2E
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1A A0H
A0H bit 15:8 of A0 coefficient
01000000
Datasheet
CFR0011-120-00 Rev 5
Revision 3e
89 of 105
15-Oct-2015
© 2015 Dialog Semiconductor
DA7211
Ultra-low power stereo codec
Company confidential
Table 82: GP1B A0L 0x2F
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1B A0L
A0L bit 7:0 of A0 coefficient
00000000
Table 83: GP1B A0H 0x30
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1B A0H
A0H bit 15:8 of A0 coefficient
01000000
Table 84: GP2A A0L 0x31
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2A A0L
A0L bit 7:0 of A0 coefficient
00000000
Table 85: GP2A A0H 0x32
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2A A0H
A0H bit 15:8 of A0 coefficient
01000000
Table 86: GP2B_A0L 0x33
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2B_A0L
A0L bit 7:0 of A0 coefficient
00000000
Table 87: GP2B_A0H 0x34
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2B_A0H
A0H bit 15:8 of A0 coefficient
01000000
Table 88: GP1C_A0L 0x35
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1C_A0L
A0L bit 7:0 of A0 coefficient
00000000
Table 89: GP1C_A0H 0x36
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1C_A0H
A0H bit 15:8 of A0 coefficient
01000000
Table 90: GP1D_A0L 0x37
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1D_A0L
A0L bit 7:0 of A0 coefficient
00000000
Table 91: GP1D_A0H 0x38
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1D_A0H
A0H bit 15:8 of A0 coefficient
01000000
Table 92: GP2C_A0L 0x39
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2C_A0L
A0L bit 7:0 of A0 coefficient
00000000
Datasheet
CFR0011-120-00 Rev 5
Revision 3e
90 of 105
15-Oct-2015
© 2015 Dialog Semiconductor
DA7211
Ultra-low power stereo codec
Company confidential
Table 93: GP2C_A0H 0x3A
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2C_A0H
A0H bit 15:8 of A0 coefficient
01000000
Table 94: GP2D_A0L 0x3B
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2D_A0L
A0L bit 7:0 of A0 coefficient
00000000
Table 95: GP2D_A0H 0x3C
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2D_A0H
A0H bit 15:8 of A0 coefficient
01000000
Table 96: GP1A_A1L 0x3D
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1A_A1L
A1L bit 7:0 of A1 coefficient
00000000
Table 97: GP1A_A1L 0x3E
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1A_A1L
A1H bit 15:8 of A1 coefficient
00000000
Table 98: GP1B_A1L 0x3F
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1B_A1L
A1L bit 7:0 of A1 coefficient
00000000
Table 99: GP1B_A1H 0x40
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1B_A1H
A1H bit 15:8 of A1 coefficient
00000000
Table 100: GP2A_A1L 0x41
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2A_A1L
A1L bit 7:0 of A1 coefficient
00000000
Table 101: GP2A_A1H 0x42
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2A_A1H
A1H bit 15:8 of A1 coefficient
00000000
Table 102: GP2B_A1L 0x43
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2B_A1L
A1L bit 7:0 of A1 coefficient
00000000
Table 103: GP2B_A1H 0x44
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2B_A1H
A1H bit 15:8 of A1 coefficient
00000000
Datasheet
CFR0011-120-00 Rev 5
Revision 3e
91 of 105
15-Oct-2015
© 2015 Dialog Semiconductor
DA7211
Ultra-low power stereo codec
Company confidential
Table 104: GP1C_A1L 0x45
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1C_A1L
A1L bit 7:0 of A1 coefficient
00000000
Table 105: GP1C_A1H 0x46
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1C_A1H
A1H bit 15:8 of A1 coefficient
00000000
Table 106: GP1D_A1L 0x47
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1D_A1L
A1L bit 7:0 of A1 coefficient
00000000
Table 107: GP1D_A1H 0x48
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1D_A1H
A1H bit 15:8 of A1 coefficient
00000000
Table 108: GP2C_A1L 0x49
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2C_A1L
A1L bit 7:0 of A1 coefficient
00000000
Table 109: GP2C_A1H 0x4A
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2C_A1H
A1H bit 15:8 of A1 coefficient
00000000
Table 110: GP2D_A1L 0x4B
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2D_A1L
A1L bit 7:0 of A1 coefficient
00000000
Table 111: GP2D_A1H 0x4C
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2D_A1H
A1H bit 15:8 of A1 coefficient
00000000
Table 112: GP1A_A2L 0x4D
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1A_A2L
A2L bit 7:0 of A2 coefficient
00000000
Table 113: GP1A_A2H 0x4E
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1A_A2H
A2H bit 15:8 of A2 coefficient
00000000
Table 114: GP1B_A2L 0x4F
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1B_A2L
A2L bit 7:0 of A2 coefficient
00000000
Datasheet
CFR0011-120-00 Rev 5
Revision 3e
92 of 105
15-Oct-2015
© 2015 Dialog Semiconductor
DA7211
Ultra-low power stereo codec
Company confidential
Table 115: GP1B_A2H 0x50
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1B_A2H
A2H bit 15:8 of A2 coefficient
00000000
Table 116: GP2A_A2L 0x51
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2A_A2L
A2L bit 7:0 of A2 coefficient
00000000
Table 117: GP2A_A2H 0x52
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2A_A2H
A2H bit 15:8 of A2 coefficient
00000000
Table 118: GP2B_A2L 0x53
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2B_A2L
A2L bit 7:0 of A2 coefficient
00000000
Table 119: GP2B_A2H 0x54
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2B_A2H
A2H bit 15:8 of A2 coefficient
00000000
Table 120: GP1C_A2L 0x55
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1C_A2L
A2L bit 7:0 of A2 coefficient
00000000
Table 121: GP1C_A2H 0x56
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1C_A2H
A2H bit 15:8 of A2 coefficient
00000000
Table 122: GP1D_A2L 0x57
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1D_A2L
A2L bit 7:0 of A2 coefficient
00000000
Table 123: GP1D_A2H 0x58
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1D_A2H
A2H bit 15:8 of A2 coefficient
00000000
Table 124: GP2C_A2L 0x59
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2C_A2L
A2L bit 7:0 of A2 coefficient
00000000
Table 125: GP2C_A2H 0x5A
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2C_A2H
A2H bit 15:8 of A2 coefficient
00000000
Datasheet
CFR0011-120-00 Rev 5
Revision 3e
93 of 105
15-Oct-2015
© 2015 Dialog Semiconductor
DA7211
Ultra-low power stereo codec
Company confidential
Table 126: GP2D_A2L 0x5B
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2D_A2L
A2L bit 7:0 of A2 coefficient
00000000
Table 127: GP2D_A2H 0x5C
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2D_A2H
A2H bit 15:8 of A2 coefficient
00000000
Table 128: GP1A_B1L 0x5D
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1A_B1L
B1L bit 7:0 of B1 coefficient
00000000
Table 129: GP1A_B1H 0x5E
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1A_B1H
B1H bit 15:8 of B1 coefficient
00000000
Table 130: GP1B_B1L 0x5F
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1B_B1L
B1L bit 7:0 of B1 coefficient
00000000
Table 131: GP1B_B1H 0x60
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1B_B1H
B1H bit 15:8 of B1 coefficient
00000000
Table 132: GP2A_B1L 0x61
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2A_B1L
B1L bit 7:0 of B1 coefficient
00000000
Table 133: GP2A_B1H 0x62
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2A_B1H
B1H bit 15:8 of B1 coefficient
00000000
Table 134: GP2B_B1L 0x63
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2B_B1L
B1L bit 7:0 of B1 coefficient
00000000
Table 135: GP2B_B1H 0x64
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2B_B1H
B1H bit 15:8 of B1 coefficient
00000000
Table 136: GP1C_B1L 0x65
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1C_B1L
B1L bit 7:0 of B1 coefficient
00000000
Datasheet
CFR0011-120-00 Rev 5
Revision 3e
94 of 105
15-Oct-2015
© 2015 Dialog Semiconductor
DA7211
Ultra-low power stereo codec
Company confidential
Table 137: GP1C_B1H 0x66
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1C_B1H
B1H bit 15:8 of B1 coefficient
00000000
Table 138: GP1D_B1L 0x67
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1D_B1L
B1L bit 7:0 of B1 coefficient
00000000
Table 139: GP1D_B1H 0x68
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1D_B1H
B1H bit 15:8 of B1 coefficient
00000000
Table 140: GP2C_B1L 0x69
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2C_B1L
B1L bit 7:0 of B1 coefficient
00000000
Table 141: GP2C_B1H 0x6A
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2C_B1H
B1H bit 15:8 of B1 coefficient
00000000
Table 142: GP2D_B1L 0x6B
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2D_B1L
B1L bit 7:0 of B1 coefficient
00000000
Table 143: GP2D_B1H 0x6C
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2D_B1H
B1H bit 15:8 of B1 coefficient
00000000
Table 144: GP1A_B2L 0x6D
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1A_B2L
B2L bit 7:0 of B2 coefficient
00000000
Table 145: GP1A_B2H 0x6E
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1A_B2H
B2H bit 15:8 of B2 coefficient
00000000
Table 146: GP1B_B2L 0x6F
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1B_B2L
B2L bit 7:0 of B2 coefficient
00000000
Table 147: GP1B_B2H 0x70
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1B_B2H
B2H bit 15:8 of B2 coefficient
00000000
Datasheet
CFR0011-120-00 Rev 5
Revision 3e
95 of 105
15-Oct-2015
© 2015 Dialog Semiconductor
DA7211
Ultra-low power stereo codec
Company confidential
Table 148: GP2A_B2L 0x71
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2A_B2L
B2L bit 7:0 of B2 coefficient
00000000
Table 149: GP2A_B2H 0x72
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2A_B2H
B2H bit 15:8 of B2 coefficient
00000000
Table 150: GP2B_B2L 0x73
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2B_B2L
B2L bit 7:0 of B2 coefficient
00000000
Table 151: GP2B_B2H 0x74
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2B_B2H
B2H bit 15:8 of B2 coefficient
00000000
Table 152: GP1C_B2L 0x75
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1C_B2L
B2L bit 7:0 of B2 coefficient
00000000
Table 153: GP1C_B2H 0x76
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1C_B2H
B2H bit 15:8 of B2 coefficient
00000000
Table 154: GP1D_B2L 0x77
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1D_B2L
B2L bit 7:0 of B2 coefficient
00000000
Table 155: GP1D_B2H 0x78
Bit
Mode
Symbol
Description
Reset
7:0
W
GP1D_B2H
B2H bit 15:8 of B2 coefficient
00000000
Table 156: GP2C_B2L 0x79
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2C_B2L
B2L bit 7:0 of B2 coefficient
00000000
Table 157: GP2C_B2H 0x7A
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2C_B2H
B2H bit 15:8 of B2 coefficient
00000000
Table 158: GP2D_B2L 0x7B
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2D_B2L
B2L bit 7:0 of B2 coefficient
00000000
Datasheet
CFR0011-120-00 Rev 5
Revision 3e
96 of 105
15-Oct-2015
© 2015 Dialog Semiconductor
DA7211
Ultra-low power stereo codec
Company confidential
Table 159: GP2D_B2H 0x7C
Bit
Mode
Symbol
Description
Reset
7:0
W
GP2D_B2H
B2H bit 15:8 of B2 coefficient
00000000
Table 160: GPF_SRC1 0x7D
Bit
Mode
Symbol
Description
Reset
7
R
Reserved
Reserved
0
GP Filter 2AB source selection:
000 = 1AB
001 = reserved
6:4
R/W
GP_2AB_SRC
010 = 1CD
011 = reserved
110
100 = DAI_L
101 = DAI_R
110 = ADC_L
111 = ADC_R
3
R
Reserved
Reserved
0
GP Filter 1AB source selection:
000 = reserved
2:0
R/W
GP_1AB_SRC
001 = reserved
010 = reserved
011 = reserved
100 = DAI_L
100
101 = DAI_R
110 = ADC_L
111 = ADC_R
Datasheet
CFR0011-120-00 Rev 5
Revision 3e
97 of 105
15-Oct-2015
© 2015 Dialog Semiconductor
DA7211
Ultra-low power stereo codec
Company confidential
Table 161: GPF_SRC2 0x7E
Bit
Mode
Symbol
Description
Reset
7
R
Reserved
Reserved
0
GP Filter 2CD source selection:
000 = 1AB
001 = 2AB
6:4
R/W
GP_2CD_SRC
010 = 1CD
011 = reserved
111
100 = DAI_L
101 = DAI_R
110 = ADC_L
111 = ADC_R
3
R
Reserved
Reserved
0
GP Filter 1CD source selection:
000 = 1AB
001 = reserved
010 = reserved
2:0
R/W
GP_1CD_SRC
011 = reserved
100 = DAI_L
101
101 = DAI_R
110 = ADC_L
111 = ADC_R
Table 162: DSP_CFG 0x7F
Bit
Mode
Symbol
Description
Reset
7
R
Reserved
Reserved
0
6
R/W
DSP_MIX_3
1 = Output of section 2AB is mixed with 2CD
0
5
R/W
DSP_MIX_2
1 = Output of section 1CD is mixed with 2AB
0
4
R/W
DSP_MIX_1
1 = Output of section 1AB is mixed with 1CD
0
Enable GP section 2CD
3
2
R/W
R/W
GP2CD_EN
GP1CD_EN
0 = disable
1 = enable
Enable GP section 1CD
0 = disable
0
0
1 = enable
Enable GP section 2AB
1
R/W
GP2AB_EN
0 = disable
1 = enable
0
Enable GP section 1AB
0
R/W
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GP1AB_EN
0 = disable
1 = enable
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Table 163: CHIP_ID 0x81
Bit
Mode
Symbol
7:4
R
MRC
3:0
R
MMRC
Description
Reset
Read back of mask revision code (MRC)
0001
– code 0 for AA release
Read back of metal mask release code (MMRC)
– starts with a code 0
0001
Description
Reset
Table 164: INTERFACE 0x82
Bit
Mode
Symbol
7:5
R
IF_BASE_ADDR
4:0
R
Reserved
3 MSB of 2-wire control interface base address
XXX1010 + R/W
001
00110100 = 0x34 (write address)
00110101 = 0x35 (read address)
Reserved
00000
10.5 ALC level controls
Table 165: ALC_MAX 0x83
Bit
Mode
Symbol
Description
Reset
7
R
Reserved
Reserved
0
6
R/W
ALC_MERGE
5:0
R/W
ALC_MAX
ALC joined stereo mode
0 = disabled (channels updates independently)
1 = enabled (channels update synchronously)
1
ALC max control level (refer to Table 20)
maximum value of ALC_MAX = 3Ch = -0.5 dB
000000
Table 166: ALC_MIN 0x84
Bit
Mode
Symbol
Description
Reset
7:6
R
Reserved
Reserved
00
5:0
R/W
ALC_MIN
ALC min control level: (refer to Table 20)
maximum value of ALC_MIN = 3Bh = -2 dB
000000
Table 167: ALC_NOIS 0x85
Bit
Mode
Symbol
Description
Reset
7:6
R
Reserved
Reserved
00
5:0
R/W
ALC_NOIS
ALC noise gate level: (refer to Table 20)
Note that the minimum value of ALC_NOIS is 86 dB
000000
Table 168: ALC_ATT 0x86
Bit
7:0
Mode
R/W
Symbol
Description
Reset
ALC_ATT
ALC attack rate:
Number of sample periods between two gain
steps of 0.25 dB
00000000
00000000 = 0.25 dB/sample period
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Table 169: ALC_REL 0x87
Bit
Mode
Symbol
Description
Reset
ALC release rate:
7:0
R/W
ALC_REL
Number of periods between two gain steps of
0.25 dB in increments of 4 sample periods
00000000
00000000 = 0.0625 dB/sample period
Table 170: ALC_DEL 0x88
Bit
Mode
Symbol
Description
Reset
7:0
R/W
ALC_DEL
ALC release delay:
Time delay before ALC release starts in
increments of ALC_REL periods
00000000
Description
Reset
Table 171: A_HID_UNLOCK 0x8A
Bit
Mode
Symbol
7:0
W
A_HID_UNLOCK
Register unlock:
Set to 0x8B (10001011) to use the registers
below
00000000
Table 172: A_TST_UNLOCK 0x8B
Bit
Mode
Symbol
Description
Reset
7:0
W
A_TST_UNLOCK
Register unlock:
Set to 0xB4 (10110100) to use the registers
below
00000000
Table 173: A_PLL0 0x8F
Unlocking registers 0x8A and 0x8B is required to access this register
Bit
Mode
Symbol
Description
Reset
Disable sigma delta modulator in the analogue PLL.
0
W
SIGDEL_DISABLE
7:6
W
Reserved
If = 1, reduces current when using internal
oscillator. Must be enabled when using PLL
Reserved
0
0000000
Table 174: A_PLL1 0x90
Unlocking registers 0x8A and 0x8B is required to access this register
Bit
Mode
Symbol
Description
Reset
7:1
W
Reserved
Reserved
0000000
0
W
VCORST_EN
Separate power-down signal for the VCO reset
controller
0 = disabled
1
1 = enabled for all PLL operations
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Table 175: A_ADC0 0x95
Unlocking registers 0x8A and 0x8B is required to access this register
Bit
Mode
Symbol
Description
Reset
7:4
W
Reserved
Reserved
0000
3
W
ADC_T2
0 = default current
1 = increased current; improved THD performance
0
2:0
W
Reserved
Reserved
000
ADC bias current increase:
Table 176: A_DAC0 0x96
Unlocking registers 0x8A and 0x8B is required to access this register
Bit
Mode
Symbol
Description
Reset
7:3
W
Reserved
Reserved
00000
2:0
W
VMID_BUFF_EN
VMID buffer disable during ADC and analogue only
modes to save power
000 = VMID buffer disabled
111 = VMID buffer enabled
111
Table 177: A_CPHP6 0xA2
Unlocking registers 0x8A and 0x8B is required to access this register
Bit
Mode
Symbol
Description
Reset
7:0
W
CP_RISE_TIME
Set 0x80 (10000000) for maximum output power.
Set 0x84 (10000100) for reduced inrush current
10000000
Table 178: A_CP_MODE 0xA7
Unlocking registers 0x8A and 0x8B is required to access this register
Bit
Mode
Symbol
7:0
W
A_CP_MODE
Datasheet
CFR0011-120-00 Rev 5
Description
Headphone charge pump enable:
Set 0x7C (01111110)
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11 Package information
11.1 Package outlines
Figure 49: 36 bump WL-CSP 0.5mm pitch package outline drawing
11.2 Soldering information
Refer to the JEDEC standard J-STD-020 for relevant soldering information. This document can be
downloaded from http://www.jedec.org.
12 Ordering information
The ordering number consists of the part number followed by a suffix indicating the packing method.
For details and availability, please contact Dialog Semiconductor’s local sales representative.
Table 179: Ordering information
Part number
Package
DA7211-01UA2
DA7211-01UA6
Datasheet
CFR0011-120-00 Rev 5
Size (mm)
Shipment form
Pack quantity
36-bump CSP
Pb-free/green
Tape and Reel
2,000 pcs.
36-bump CSP
Pb-free/green
Waffle Pack
(engineering samples only
- not for mass production)
900 pcs.
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13 Applications information
13.1 Supporting information
The bass response of the analogue inputs and outputs is determined by the output coupling
capacitor and associated resistive load. If smaller footprint, low value capacitors are preferred, then
the low frequency cut-off will be increased.
To maintain maximum audio bandwidth, larger capacitors are recommended, taking into account the
relationship
Low frequency cut-off =
1
2RC
The analogue outputs can support between 32 Ω (16 Ω for headphone outputs) and line level loads
(e.g. >=10 kΩ), so the range of capacitor values is wider, and care is required when making the
selection.
13.2 Minimum component recommendations
To ensure datasheet performance is maintained it is recommended that the following minimum
component criteria are met. Figure 49 shows recommended components and input/output
configurations.
Figure 49: DA7211 36-pin CSP component recommendations
● It is recommended that ceramic capacitors are used where possible for low ESR.
● It is recommended that C0G or X7R dielectric is used where possible to minimise distortion.
● The voltage rating of any capacitor used should be much greater than the maximum peak signal
amplitude expected. It has been shown that capacitors with a large voltage rating introduce less
distortion into the signal paths.
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● For example the voltage rating of the 1 µF capacitors in the output paths should be chosen as
16 V
● All capacitors >=10 µF should use minimum dielectric specification X5R where possible.
● All 100 nF power supply decoupling capacitors should be placed as close as possible to
associated pins. Reference: C1, C18 and C28.
● All 1 µF voltage reference capacitors should be placed as close as possible to associated pins.
Reference: C7, C15-17.
● The headphone output amplifier is driven by a PWM based charge pump. To maintain efficiency
the 1 µF charge pump capacitors should be placed as close as possible to associated pins.
Reference: C2-C5.
● The control interface data I/O pin, SI, is open drain and therefore requires an external pull-up. If
the control interface data output of the system processor does not support an internal pull-up,
then an external resistor R2 is required.
13.3 General component suggestions
The following components and input/output configurations are suggested below.
● Headphone output and microphone input connectors shown in Figure 49 are of the 3.5 mm
RCA/phono type, but any other suitable connector is acceptable.
● J1 is configured as a mono microphone input. The ground reference connection MICN_R, pin 5D,
is internally referenced to a voltage 0.45*AVDD and therefore must be connected to AGND (or
ground plane if connected to AGND) through C23. Similarly MICP_R, pin 6C, should be
connected to the signal input via C22.
● MICBIAS, pin 5C, can supply up to 2 mA of current for biasing electret microphones. The
MICBIAS pin must be separated from the mic input by ≈200 Ω resistor.
● A capacitive load of 100 nF is also required for output stability and doubles as a decoupling
capacitor.
● If two microphones are supplied by this pin, then separate RC circuits are implemented for each
microphone to provide isolation between inputs, as shown in Figure 49.
● J2 is configured as a differential microphone input. The positive signal input is connected to
MICP_L, pin 6B, the inputs pins are internally referenced to voltage 0.45*AVDD and therefore
must be connected through C20. Similarly, the negative signal input is connected to MICN_L, pin
4D, through C21. To maintain balance the value of R4 should match that of R3.
● When the line outputs are used to drive a differential load of 32 Ω, coupling caps are not required
● If the analogue outputs, excluding the headphone outputs, are used with line level loads (e.g.
≈10 kΩ) and minimum bass response of the outputs is not deemed important, it could be
acceptable to reduce the coupling capacitors for OUT1L/R analogue output pins to less than
1 µF. An absolute minimum value of 100 nF is recommended. Reference: C10-13.
● It is unlikely that the bass response of the microphone used will be much lower than 100 Hz. The
microphone inputs have an impedance ≈15 kΩ, it could therefore be acceptable to use coupling
capacitors less than 1 µF without significantly affecting the input signal bandwidth. An absolute
minimum value of 100 nF is recommended.
● The input impedance of the analogue inputs is ≈30 kΩ. If minimum bass response of the
analogue inputs is not deemed important, the input coupling capacitors for MICL/R and AUX1L/R
can be reduced to less than 1 µF. An absolute minimum value of 100 nF is recommended.
Reference: C21-27.
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Status definitions
Revision
Datasheet status
Product status
Definition
1.<n>
Target
Development
This datasheet contains the design specifications for product
development. Specifications may be changed in any manner without
notice.
2.<n>
Preliminary
Qualification
This datasheet contains the specifications and preliminary
characterisation data for products in pre-production. Specifications
may be changed at any time without notice in order to improve the
design.
3.<n>
Final
Production
This datasheet contains the final specifications for products in
volume production. The specifications may be changed at any time
in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via Customer Product Notifications.
4.<n>
Obsolete
Archived
This datasheet contains the specifications for discontinued products.
The information is provided for reference only.
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