PD - 94528C AFL5003R3S 50V Input, 3.3V Output HYBRID-HIGH RELIABILITY DC/DC CONVERTER Description The AFL Series of DC/DC converters feature high power density with no derating over the full military temperature range. This device is offered as part of a complete family of converters providing single and dual output voltages originally created to operate over a broad input voltage range of 28V to 270V with output power ranging from 66W to 120W. For applications requiring higher output power, multiple converters can be operated in parallel. The internal current sharing circuits assure equal current distribution among the paralleled converters. This series incorporates International Rectifier’s proprietary magnetic pulse feedback technology providing optimum dynamic line and load regulation response. This feedback system samples the output voltage at the pulse width modulator fixed clock frequency, nominally 550 KHz. Multiple converters can be synchronized to a system clock in the 500KHz to 700KHz range or to the synchronization output of one converter. Under voltage lockout, primary and secondary referenced inhibit, soft start and load fault protection are provided on all models. These converters are hermetically packaged in two enclosure variations, utilizing copper core pins to minimize resistive DC losses. Three lead styles are available, each fabricated using International Rectifier’s rugged ceramic lead-to-package seal assuring long term hermeticity in the most harsh environments. AFL Features n n n n n n n n n n n n n n n 30V To 80V Input Range 3.3V Output High Power Density - 50W/in3 66W Output Power Parallel Operation with Stress and Current Sharing Low Profile (0.380") Seam Welded Package Ceramic Feed thru Copper Core Pins High Efficiency - to 74% Full Military Temperature Range Continuous Short Circuit and Overload Protection Remote Sensing Terminals Primary and Secondary Referenced Inhibit Functions Line Rejection > 40dB - DC to 50KHz External Synchronization Port Fault Tolerant Design Manufactured in a facility fully qualified to MIL-PRF38534, these converters are fabricated utilizing DSCC qualified processes. For available screening options, refer to device screening table in the data sheet. Variations in electrical, mechanical and screening can be accommodated. Contact IR Santa Clara for special requirements. www.irf.com 1 12/12/06 AFL5003R3S Specifications Absolute Maximum Ratings Input voltage Soldering temperature Operating case temperature Storage case temperature -0.5V to +50VDC 300°C for 10 seconds -55°C to +125°C -65°C to +135°C Electrical Performance Characteristics -55°C < TCASE < +125°C, 30V< VIN < 80V unless otherwise specified. Parameter Group A Subgroups Test Conditions INPUT VOLTAGE Note 6 OUTPUT VOLTAGE V IN = 50 Volts, 100% Load 1 2, 3 Nom Max Unit 30 50 80 V 3.27 3.30 3.33 V 3.23 3.37 VIN = 30, 50, 80 Volts,, Note 6 OUTPUT CURRENT 20 Note 6 OUTPUT POWER MAXIMUM CAPACITIVE LOAD 4 OUTPUT VOLTAGE TEMPERATURE COEFFICIENT OUTPUT VOLTAGE REGULATION Line Load 1, 2, 3 Inhibit 1 Inhibit 2 -0.015 +0.015 %/°C -20 +20 mV -35 +35 VIN = 30, 50, 80 Volts,, 100% Load, BW = 10MHz INPUT RIPPLE CURRENT 1, 2, 3 30 VIN = 50 Volts, I OUT = 0 80 100 5.00 50 Pin 4 Shorted to Pin 2 Pin 12 Shorted to Pin 8 VIN = 50 Volts, 100% Load B.W. = 10MHz V OUT = 90% V NOM CURRENT LIMIT POINT Expressed as a Percentage of Full Rated Load VIN = 50 Volts, 100% Load Note 1, 6 1, 2, 3 1 2, 3 1, 2, 3 1, 2, 3 W µF 10,000 No Load, 50% Load, 100% Load VIN = 30, 50, 80 Volts, INPUT CURRENT No Load 66 A Note 1 1, 2, 3 OUTPUT RIPPLE VOLTAGE mV pp mA 60 mA pp 125 115 140 % 33 W Note 5 1 2 3 115 105 125 VIN = 50 Volts, LOAD FAULT POWER DISSIPATION Overload or Short Circuit 1, 2, 3 EFFICIENCY 1, 2, 3 SWITCHING FREQUENCY 1, 2, 3 ISOLATION Min 1 MTBF VIN = 50 Volts, 100% Load 72 74 500 550 % 600 KHz Input to Output or Any Pin to Case (except Pin 3). Test @ 500VDC 100 MΩ MIL-HDBK-217F, AIF @ TC = 40°C 300 KHrs For Notes to Specifications, refer to page 3 2 www.irf.com AFL5003R3S Elecrical Performance Characteristics (Continued) Parameter ENABLE INPUTS (Inhibit Function) Converter Off Sink Current Converter On Sink Current SYNCHRONIZATION INPUT Frequency Range Pulse Amplitude, Hi Pulse Amplitude, Lo Pulse Rise Time Pulse Duty Cycle Group A Subgroups 1, 2, 3 1, 2, 3 Test Conditions Min Logical Low, Pin 4 or Pin 12 Note 1 Logical High, Pin 4 and Pin 12 - Note 9 Note 1 -0.5 1, 2, 3 1, 2, 3 1, 2, 3 Nom 2.0 500 2.0 -0.5 Note 1 Note 1 20 Max Unit 0.8 100 50 100 V µA V µA 700 10 0.8 100 80 KHz V V ns % Note 2, 8 LOAD TRANSIENT RESPONSE Amplitude Recovery 4, 5, 6 4, 5, 6 Load Step 50% ⇔ 100% -450 450 200 mV µs Amplitude Recovery 4, 5, 6 4, 5, 6 Load Step 10% ⇔ 50% -450 450 400 mV µs -500 500 500 mV µs 250 120 mV ms Note 1, 2, 3 LINE TRANSIENT RESPONSE VIN Step = 30 ⇔ 80 Volts Amplitude Recovery TURN-ON CHARACTERISTICS Overshoot Delay VIN = 30, 50, 80 Volts,. Note 4 4, 5, 6 4, 5, 6 Enable 1, 2 on. (Pins 4, 12 high or open) LOAD FAULT RECOVERY Same as Turn On Characteristics. LINE REJECTION MIL-STD-461, CS101, 30Hz to 50KHz Note 1 40 50 dB Notes to Specifications: 1. 2. 3. 4. 5. 6. 7. 8. Parameters not 100% tested but are guaranteed to the limits specified in the table. Recovery time is measured from the initiation of the transient to where VOUT has returned to within ±1.0% of VOUT at 50% load. Line transient transition time ≥ 100µs. Turn-on delay is measured with an input voltage rise time of between 100V and 500V per millisecond. Current limit point is that condition of excess load causing output voltage to drop to 90% of nominal. Parameter verified as part of another test. All electrical tests are performed with the remote sense leads connected to the output leads at the load. Load transient transition time ≥ 10µs. 9. Enable inputs internally pulled high. Nominal open circuit voltage www.irf.com ≈ 4.0VDC. 3 AFL5003R3S Block Diagram Figure I. AFL Single Output + Input 1 Input Filter Enable 1 4 Output Filter Primary Bias Supply 7 +Output 10 +Sense Current Sense Sync Output 5 Sync Input 6 Case Control FB 3 Error Amp & Ref Share Amplifier 11 Share 12 Enable 2 Sense Amplifier Input Return 2 Circuit Operation and Application Information The AFL series of converters employ a forward switched mode converter topology. (refer to Figure I.) Operation of the device is initiated when a DC voltage whose magnitude is within the specified input limits is applied between pins 1 and 2. If pin 4 is enabled (at a logical 1 or open) the primary bias supply will begin generating a regulated housekeeping voltage bringing the circuitry on the primary side of the converter to life. Two power MOSFETs used to chop the DC input voltage into a high frequency square wave, apply this chopped voltage to the power transformer. As this switching is initiated, a voltage is impressed on a second winding of the power transformer which is then rectified and applied to the primary bias supply. When this occurs, the input voltage is shut out and the primary bias voltage becomes exclusively internally generated. The switched voltage impressed on the secondary output transformer winding is rectified and filtered to provide the converter output voltage. An error amplifier on the secondary side compares the output voltage to a precision reference and generates an error signal proportional to the difference. This error signal is magnetically coupled through the feedback transformer into the controller section of the converter varying the pulse width of the square wave signal driving the MOSFETs, narrowing the width if the output voltage is too high and widening it if it is too low. 4 Return Sense Output Return not used, the sense leads should be connected to their respective output terminals at the converter. Figure III. illustrates a typical application. Inhibiting Converter Output (Enable) As an alternative to application and removal of the DC voltage to the input, the user can control the converter output by providing TTL compatible, positive logic signals to either of two enable pins (pin 4 or 12). The distinction between these two signal ports is that enable 1 (pin 4) is referenced to the input return (pin 2) while enable 2 (pin 12) is referenced to the output return (pin 8). Thus, the user has access to an inhibit function on either side of the isolation barrier. Each port is internally pulled “high” so that when not used, an open connection on both enable pins permits normal converter operation. When their use is desired, a logical “low” on either port will shut the converter down. Figure II. Enable Input Equivalent Circuit +5.6 V Pin 4 or Pin 12 1N4148 100K 290K Disable 2N3904 Remote Sensing Connection of the + and - sense leads at a remotely located load permits compensation for resistive voltage drop between the converter output and the load when they are physically separated by a significant distance. This connection allows regulation to the placard voltage at the point of application. When the remote sensing features is 9 8 180K Pin 2 or Pin 8 www.irf.com AFL5003R3S high level of +2.0V. The sync output of another converter which has been designated as the master oscillator provides a convenient frequency source for this mode of operation. When external synchronization is not required, the sync in pin should be left unconnected there by permitting the converter to operate at its’ own internally set frequency. Internally, these ports differ slightly in their function. In use, a low on Enable 1 completely shuts down all circuits in the converter while a low on Enable 2 shuts down the secondary side while altering the controller duty cycle to near zero. Enabling by the use of either port is transparent to the user save for minor differences in idle current. (See specification table). The sync output signal is a continuous pulse train set at 550 ± 50KHz, with a duty cycle of 15 ± 5.0%. This signal is referenced to the input return and has been tailored to be compatible with the AFL sync input port. Transition times are less than 100ns and the low level output impedance is less than 50Ω. This signal is active when the DC input voltage is within the specified operating range and the converter is not inhibited. This output has adequate drive reserve to synchronize at least five additional converters. A typical synchronization connection option is illustrated in Figure III. Synchronization of Multiple Converters When operating multiple converters, system requirements often dictate operation of the converters at a common frequency. To accommodate this requirement, the AFL series converters provide both a synchronization input and output. The sync input port permits synchronization of an AFL converter to any compatible external frequency source operating between 500KHz and 700KHz. This input signal should be referenced to the input return and have a 10% to 90% duty cycle. Compatibility requires transition times less than 100ns, maximum low level of +0.8V and a minimum Figure III. Preferred Connection for Parallel Operation Power Input 12 1 Vin Enable 2 Rtn Share Case Enable 1 Optional Synchronization Connection AFL + Sense - Sense Sync Out Return Sync In + Vout 7 6 Share Bus 12 1 Enable 2 Vin Share Rtn Case Enable 1 AFL + Sense - Sense Sync Out Return Sync In + Vout 6 1 to Load 7 12 Vin Enable 2 Rtn Share Case Enable 1 AFL + Sense - Sense Sync Out Return Sync In + Vout 6 7 (Other Converters) Parallel Operation-Current and Stress Sharing Figure III. illustrates the preferred connection scheme for operation of a set of AFL converters with outputs operating in parallel. Use of this connection permits equal sharing of a load current exceeding the capacity of an individual AFL among the members of the set. An important feature of the www.irf.com AFL series operating in the parallel mode is that in addition to sharing the current, the stress induced by temperature will also be shared. Thus if one member of a paralleled set is operating at a higher case temperature, the current it provides to the load will be reduced as compensation for the temperature induced stress on that device. 5 AFL5003R3S When operating in the shared mode, it is important that symmetry of connection be maintained as an assurance of optimum load sharing performance. Thus, converter outputs should be connected to the load with equal lengths of wire of the same gauge and sense leads from each converter should be connected to a common physical point, preferably at the load along with the converter output and return leads. All converters in a paralleled set must have their share pins connected together. This arrangement is diagrammatically illustrated in Figure III. showing the outputs and sense pins connected at a star point which is located close as possible to the load. As a consequence of the topology utilized in the current sharing circuit, the share pin may be used for other functions. In applications requiring a single converter, the voltage appearing on the share pin may be used as a “current monitor”. The share pin open circuit voltage is nominally +1.00V at no load and increases linearly with increasing output current to +2.20V at full load. The share pin voltage is referenced to the output return pin. Thermal Considerations Because of the incorporation of many innovative technological concepts, the AFL series of converters is capable of providing very high output power from a package of very small volume. These magnitudes of power density can only be obtained by combining high circuit efficiency with effective methods of heat removal from the die junctions. This requirement has been effectively addressed inside the device; but when operating at maximum loads, a significant amount of heat will be generated and this heat must be conducted away from the case. To maintain the case temperature at or below the specified maximum of 125°C, this heat must be transferred by conduction to an appropriate heat dissipator held in intimate contact with the converter base-plate. Because effectiveness of this heat transfer is dependent on the intimacy of the baseplate/heatsink interface, it is strongly recommended that a high thermal conductivity heat transferance medium is inserted between the baseplate and heatsink. The material most frequently utilized at the factory during all testing and burn-in processes is sold under the trade name of Sil-Pad® 4001. This particular product is an insulator but electrically conductive versions are also available. Use of these materials assures maximum surface contact with the heat dissipator thereby compensating for minor variations of either surface. While other available types of heat conductive materials and compounds may provide similar performance, these alternatives are often less convenient and are frequently messy to use. A conservative aid to estimating the total heat sink surface area (A HEAT SINK ) required to set the maximum case temperature rise (∆T) above ambient temperature is given by the following expression: . ⎧ ∆T ⎫ −143 ⎬ A HEAT SINK ≈ ⎨ − 3.0 ⎩ 80P 0.85 ⎭ where ∆T = Case temperature rise above ambient ⎧ 1 ⎫ − 1⎬ P = Device dissipation in Watts = POUT ⎨ ⎩ Eff ⎭ As an example, it is desired to maintain the case temperature of an AFL27015S at ≤ +85°C in an area where the ambient temperature is held at a constant +25°C; then ∆T = 85 - 25 = 60°C From the Specification Table, the worst case full load efficiency for this device is 83%; therefore the power dissipation at full load is given by ⎧ 1 ⎫ P = 120 • ⎨ − 1⎬ = 120 • ( 0.205) = 24.6W ⎩ .83 ⎭ and the required heat sink area is ⎫ −1.43 ⎧ 60 ⎬ − 3.0 = 71 in2 A HEAT SINK = ⎨ ⎩ 80 • 24.6 0.85 ⎭ Thus, a total heat sink surface area (including fins, if any) of 71 in2 in this example, would limit case rise to 60°C above ambient. A flat aluminum plate, 0.25" thick and of approximate dimension 4" by 9" (36 in2 per side) would suffice for this application in a still air environment. Note that to meet the criteria in this example, both sides of the plate require unrestricted exposure to the ambient air. 1Sil-Pad is a registered Trade Mark of Bergquist, Minneapolis, MN 6 www.irf.com AFL5003R3S Input Filter The AFL5003R3S series converters incorporate a single stage LC input filter whose elements dominate the input load impedance characteristic during the turn-on sequence. The input circuit is as shown in Figure IV. Figure IV. Input Filter Circuit Finding a resistor value for a particular output voltage, is simply a matter of substituting the desired output voltage and the nominal device voltage into the equation and solving for the corresponding resistor value. Figure V. Connection for VOUT Adjustment Enable 2 0.75µH Share Pin 1 AFL5003R3S 2.7µfd + Sense RADJ - Sense Return To Load + Vout Pin 2 Caution: Do not set Radj < 500Ω Undervoltage Lockout A minimum voltage is required at the input of the converter to initiate operation. This voltage is set to 26.5V ±1.5V. To preclude the possibility of noise or other variations at the input falsely initiating and halting converter operation, a hysteresis of approximately 2.0V is incorporated in this circuit. Thus if the input voltage drops to 24.5V ± 1.5V, the converter will shut down and remain inoperative until the input voltage returns to ≈ 25V. Output Voltage Adjust In addition to permitting close voltage regulation of remotely located loads, it is possible to utilize the converter sense pins to incrementally increase the output voltage over a limited range. The adjustments made possible by this method are intended as a means to “trim” the output to a voltage setting for some particular application, but are not intended to create an adjustable output converter. These output voltage setting variations are obtained by connecting an appropriate resistor value between the +sense and -sense pins while connecting the -sense pin to the output return pin as shown in Figure V. below. The range of adjustment and corresponding range of resistance values can be determined by use of the following equation. ⎧ ⎫ VNOM ⎬ Radj = 100 • ⎨ ⎩VOUT - VNOM -.025 ⎭ Where Attempts to adjust the output voltage to a value greater than 120% of nominal should be avoided because of the potential of exceeding internal component stress ratings and subsequent operation to failure. Under no circumstance should the external setting resistor be made less than 500Ω. By remaining within this specified range of values, completely safe operation fully within normal component derating limits is assured. Examination of the equation relating output voltage and resistor value reveals a special benefit of the circuit topology utilized for remote sensing of output voltage in the AFL50XXS series of converters. It is apparent that as the resistance increases, the output voltage approaches the nominal set value of the device. In fact the calculated limiting value of output voltage as the adjusting resistor becomes very large is ≈ 25mV above nominal device voltage. The consequence is that if the +sense connection is unintentionally broken, an AFL50XXS has a fail-safe output voltage of Vout + 25mV, where the 25mV is independent of the nominal output voltage. It can be further demonstrated that in the event of both the + and - sense connections being broken, the output will be limited to Vout + 440mV. This 440mV is also essentially constant independent of the nominal output voltage. While operation in this condition is not damaging to the device, not all performance parameters will be met. VNOM = device nominal output voltage, and VOUT = desired output voltage www.irf.com 7 AFL5003R3S Mechanical Outlines Case X Case W Pin Variation of Case Y 3.000 ø 0.128 2.760 0.050 0.050 1 12 0.250 0.250 0.200 Typ Non-cum 6 7 1.260 1.500 1.000 Ref 1.000 Pin ø 0.040 Pin ø 0.040 0.220 2.500 0.220 2.800 2.975 max 0.525 0.238 max 0.42 0.380 Max 0.380 Max Case Y Case Z Pin Variation of Case Y 1.150 0.300 ø 0.140 0.25 typ 0.050 0.050 1 12 0.250 0.250 1.000 Ref 6 1.750 1.000 Ref 0.200 Typ Non-cum 7 1.500 1.750 2.00 Pin ø 0.040 0.375 Pin ø 0.040 0.220 0.220 0.36 2.500 2.800 2.975 max 0.525 0.238 max 0.380 Max 0.380 Max Tolerances, unless otherwise specified: .XX .XXX = = ±0.010 ±0.005 BERYLLIA WARNING: These converters are hermetically sealed; however they contain BeO substrates and should not be ground or subjected to any other operations including exposure to acids, which may produce Beryllium dust or fumes containing Beryllium 8 www.irf.com AFL5003R3S Device Screening Requirement MIL-STD-883 Method Temperature Range No Suffix ES d -20°C to +85°C -55°C to +125°C Element Evaluation HB e -55°C to +125°C CH -55°C to +125°C MIL-PRF-38534 N/A N/A N/A Class H 2023 N/A N/A N/A N/A Internal Visual 2017 c Yes Yes Yes Temperature Cycle 1010 N/A Cond B Cond C Cond C Constant Acceleration 2001, Y1 Axis N/A 500 Gs 3000 Gs 3000 Gs PIND 2020 N/A N/A N/A N/A 48 hrs@hi temp Non-Destructive Bond Pull Burn-In 1015 N/A Final Electrical MIL-PRF-38534 25°C ( Group A ) & Specification 25°C d 160 hrs@125°C 160 hrs@125°C -55°C, +25°C, -55°C, +25°C, +125°C +125°C PDA MIL-PRF-38534 N/A N/A N/A 10% Seal, Fine and Gross 1014 Cond A Cond A, C Cond A, C Cond A, C Radiographic 2012 N/A N/A N/A N/A External Visual 2009 Yes Yes Yes c Notes: Best commercial practice Sample tests at low and high temperatures -55°C to +105°C for AHE, ATO, ATW Part Numbering Pin Designation Pin # Designation 1 + Input 2 Input Return 3 Case Ground 4 Enable 1 5 Sync Output 6 Sync Input 7 + Output 8 Output Return 9 Return Sense 10 + Sense 11 Share 12 Enable 2 Model AFL 50 03R3 S X /CH Screening Level (Please refer to Screening Table) Input Voltage No suffix, ES, HB, CH 28 = 28V 50 = 50V 120 = 120V 270 = 270V Case Style Output Voltage W, X, Y, Z Output S = Single 03R3 = 3.3V WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331 IR SANTA CLARA: 2270 Martin Av., Santa Clara, California 95050, Tel: (408) 727-0500 Visit us at www.irf.com for sales contact information. Data and specifications subject to change without notice. 12/2006 www.irf.com 9