Single Port VDSL2 Line Driver with Shutdown AD8398A APPLICATIONS ADSL2+/VDSL2 CO/CPE line drivers PLC line drivers Consumer xDSL modems Twisted pair line drivers 14 VCC 13 OUT B 16 OUT A FUNCTIONAL BLOCK DIAGRAM 12 NC NC 1 −IN A 2 – – 11 −IN B +IN A 3 + + 10 +IN B GND 4 VEE 7 NC = NO CONNECT PD0 8 NC 5 NC 6 9 PD1 07760-001 Voltage feedback Wide output swing 18.4 V p-p differential, RLOAD, DIFF = 20 Ω from 12 V supply High output current Linear output current of 450 mA peak Low distortion −65 dBc for Profile 8b @ 20.4 dBm −55 dBc for Profile 17a @ 14.5 dBm High speed 85 MHz bandwidth (AV DIFF = 5) 15 NC FEATURES Figure 1. Thermally Enhanced, 4 mm × 4 mm, 16-Lead LFCSP_WQ TYPICAL APPLICATION DIAGRAM 1/2 TIP AD8398A VMID* 1/2 RING *VMID = VCC + VEE 2 07760-002 AD8398A Figure 2. Typical VDSL2 Application GENERAL DESCRIPTION The AD8398A comprises two high speed, voltage feedback operational amplifiers. When configured as a differential line driver, the AD8398A is an ideal choice for ADSL2+, VDSL2, and power line communications (PLC) applications. It has high output current, high bandwidth, and fast slew rate, combined with exceptional multitone power ratio (MTPR) and commonmode stability. The AD8398A is available in a thermally enhanced 4 mm × 4 mm, 16-lead LFCSP. The AD8398A incorporates power management functionality via two CMOS-compatible control pins, PD0 and PD1. These pins select one of four operating modes: full power, medium power, low power, or complete power-down. In the power-down mode, the quiescent current drops to 0.7 mA. The AD8398A operates in the industrial temperature range of −40°C to +85°C. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008–2010 Analog Devices, Inc. All rights reserved. AD8398A* Product Page Quick Links Last Content Update: 11/01/2016 Comparable Parts Discussions View a parametric search of comparable parts View all AD8398A EngineerZone Discussions Documentation Sample and Buy Data Sheet • AD8398A: Single Port VDSL2 Line Driver with Shutdown Data Sheet Visit the product page to see pricing options Design Resources • • • • Technical Support Submit a technical question or find your regional support number AD8398A Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. This content may be frequently modified. AD8398A TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................6 Applications....................................................................................... 1 Applications Information .................................................................8 Functional Block Diagram .............................................................. 1 Power Control Modes of Operation ...........................................8 Typical Application Diagram .......................................................... 1 Exposed Thermal Pad Connections ...........................................8 General Description ......................................................................... 1 Power Supply Bypassing ...............................................................8 Revision History ............................................................................... 2 Board Layout..................................................................................8 Specifications..................................................................................... 3 Multitone Power Ratio..................................................................9 Absolute Maximum Ratings............................................................ 4 Lightning and AC Power Fault ....................................................9 Thermal Resistance ...................................................................... 4 Outline Dimensions ....................................................................... 10 Maximum Power Dissipation ..................................................... 4 Ordering Guide .......................................................................... 10 ESD Caution.................................................................................. 4 Pin Configuration and Function Descriptions............................. 5 REVISION HISTORY 9/10—Rev. C to Rev. D Change to General Description Section ........................................ 1 3/10—Rev. B to Rev. C Changes to Figure 14........................................................................ 9 12/09—Rev. A to Rev. B Changes to Figure 13, Figure 14, and Figure 15 ........................... 9 10/09—Rev. Sp0 to Rev. A Changed RLOAD to RLOAD, Diff Throughout........................................ 1 Changes to DC Performance, Differential Input Offset Voltage Parameter, Table 1 .............................................................. 3 Changes to Figure 4.......................................................................... 5 Changes to Figure 8 and Figure 9................................................... 6 Changes to Exposed Thermal Pad Connections Section............ 8 11/08—Revision Sp0: Initial Version Rev. D | Page 2 of 12 AD8398A SPECIFICATIONS VS = 12 V, ±6 V at TA = 25°C, AV DIFF = 5, RLOAD, DIFF = 20 Ω, PD1 = 0, PD0 = 0, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Slew Rate NOISE/DISTORTION PERFORMANCE MTPR Off Isolation Input Voltage Noise Input Current Noise Differential Output Voltage Noise DC PERFORMANCE Differential Input Offset Voltage Input Offset Voltage Input Bias Current Open-Loop Gain Common-Mode Rejection INPUT CHARACTERISTICS Input Resistance OUTPUT CHARACTERISTICS Differential Swing Linear Peak Output Current POWER SUPPLY Operating Range Supply Current Power Supply Rejection POWER-DOWN PINS PD1, PD0 VIL PD1, PD0 VIH PD1, PD0 Bias Current Enable Time Disable Time Test Conditions/Comments Min Typ Max Unit AV DIFF = 5, VOUT = 2 V peak, measured differentially PD1 = 0, PD0 = 0 PD1 = 0, PD0 = 1 PD1 = 1, PD0 = 0 VOUT = 4 V peak, measured differentially 85 85 75 600 MHz MHz MHz V/μs Profile 8b at 20.4 dBm in VDSL2 application Profile 17a at 14.5 dBm in VDSL2 application PD1 = 1, PD0 = 1 f = 100 kHz f = 100 kHz f = 100 kHz in VDSL2 application −65 −55 −80 4.8 0.9 120 dBc dBc dBc nV/√Hz pA/√Hz nV/√Hz −2 Measured differentially ±0.1 16 0.5 63 −100 f < 100 kHz 1.9 MΩ VDSL2 at 20.4 dBm, MTPR = −65 dBc 18.4 450 V p-p mA peak Dual supply Single supply PD1 = 0, PD0 = 0 PD1 = 0, PD0 = 1 PD1 = 1, PD0 = 0 PD1 = 1, PD0 = 1 Measured differentially ±6 12 33.2 22.9 13.3 0.7 −94 V V mA mA mA mA dB 17.6 Referenced to GND Referenced to GND PD1, PD0 = 0 V PD1, PD0 = 3 V PD1, PD0 = (1, 1) − (0, 0) PD1, PD0 = (0, 0) − (1, 1) Rev. D | Page 3 of 12 29 20 12 0.8 2 15 6 60 600 +2 55 1 −74 37 25.5 14.5 1.1 −74 30 17 mV mV μA dB dB V V μA μA μs μs AD8398A ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION Rating 13.2 V (TJ MAX − TA)/θJA −65°C to +125°C −40°C to +85°C 300°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The maximum safe power dissipation for the AD8398A is limited by its junction temperature (TJ) on the die. The maximum safe TJ of plastic encapsulated devices, as determined by the glass transition temperature of the plastic, is 150°C. Temporarily exceeding this limit may cause a shift in the parametric performance due to a change in the stresses exerted on the die by the package. Exceeding this limit for an extended period can result in device failure. Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 16-lead LFCSP_WQ on a 4-layer board with six vias connecting the exposed pad to the GND plane layer. 6 TJ = 150°C THERMAL RESISTANCE θJA is specified with the device soldered on a JEDEC circuit board and the thermal pad connected to the GND plane layer using six vias. Table 3. Thermal Resistance Package Type 16-Lead LFCSP_WQ θJA 35.6 Unit °C/W 5 4 3 2 1 0 –40 –30 –20 –10 0 10 20 30 40 50 AMBIENT TEMPERATURE (°C) 60 70 80 07760-003 Parameter Power Supplies (VCC − VEE) Power Dissipation Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature MAXIMUM POWER DISSIPATION (W) Table 2. Figure 3. Maximum Safe Power Dissipation vs. Ambient Temperature, 4-Layer JEDEC Board with Six Thermal Vias ESD CAUTION Rev. D | Page 4 of 12 AD8398A 13 OUT B 15 NC 14 VCC 16 OUT A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NC 1 −IN A 2 +IN A 3 12 NC AD8398A 11 −IN B 10 +IN B 9 PD1 PD0 8 NC 5 NC 6 VEE 7 GND 4 NOTES 1. NC = NO CONNECT 2. EXPOSED PADDLE (EPAD) IS FLOATING, NOT ELECTRICALLY CONNECTED INTERNALLY. 07760-004 TOP VIEW (Not to Scale) Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1, 5, 6, 12, 15 2 3 4 7 8 9 10 11 13 14 16 EPAD Mnemonic NC −IN A +IN A GND VEE PD0 PD1 +IN B −IN B OUT B VCC OUT A Exposed Paddle (EPAD) Description No Connect. Amplifier A Inverting Input. Amplifier A Noninverting Input. Ground. Negative Power Supply Input. Power Mode Control. Power Mode Control. Amplifier B Noninverting Input. Amplifier B Inverting Input. Amplifier B Output. Positive Power Supply Input. Amplifier A Output. The exposed paddle is electrically isolated. Rev. D | Page 5 of 12 AD8398A TYPICAL PERFORMANCE CHARACTERISTICS VCC = 6 V, VEE = −6 V, unless otherwise stated. 21 18 DIFFERENTIAL 12 9 1/2 6 AD8398A 3 0 VMID* COMMON-MODE RLOAD, DIFF = 20Ω –3 PD1 = 0, PD0 = 0 PD1 = 0, PD0 = 1 PD1 = 1, PD0 = 0 –9 –12 0.1 1 1/2 AD8398A 10 100 1000 FREQUENCY (MHz) *VMID = Figure 5. Small Signal Differential and Common-Mode Frequency Response; AV DIFF = 5 (See the Application Circuit in Figure 8) VCC +V 07760-014 –6 07760-017 CLOSED-LOOP GAIN (dB) 15 EE 2 Figure 8. Typical Differential Application Circuit RLOAD, DIFF = 20 Ω 18 15 DIFFERENTIAL 9 6 3 1/2 COMMON-MODE 0 AD8398A –3 VMID* RLOAD, DIFF = 20Ω –6 –9 –12 1/2 PD1 = 0, PD0 = 0 PD1 = 0, PD0 = 1 PD1 = 1, PD0 = 0 –18 –21 0.1 1 AD8398A 10 100 1000 FREQUENCY (MHz) Figure 6. Small Signal Differential and Common-Mode Frequency Response (See the Application Circuit in Figure 9) 30 *VMID = 07760-015 –15 07760-018 CLOSED-LOOP GAIN (dB) 12 VCC + VEE 2 Figure 9. Typical Differential Application Circuit with Positive Feedback RLOAD, DIFF = 20 Ω DIFFERENTIAL 20 0 1/2 PD1 = 0, PD0 = 0 PD1 = 0, PD0 = 1 PD1 = 1, PD0 = 0 –10 –20 TIP AD8398A VMID* –30 –40 –50 COMMON-MODE 1/2 –60 AD8398A 1 10 FREQUENCY (MHz) 100 1000 07760-019 –70 0.1 RING Figure 7. Small Signal Differential and Common-Mode Frequency Response (See the Application Circuit in Figure 10) Rev. D | Page 6 of 12 *VMID = VCC + VEE 2 Figure 10. Typical VDSL2 Application Circuit 07760-016 CLOSED-LOOP GAIN (dB) 10 AD8398A 1000 VOLTAGE NOISE (nV/√Hz) 900 800 700 VDSL2 PROFILE 17a PD1 = 0, PD0 = 0 VDSL2 PROFILE 8b PD1 = 0, PD0 = 1 600 100 10 400 10 12 14 16 18 20 OUTPUT POWER (dBm) Figure 11. Internal Power Dissipation vs. Output Power 1 0.01 0.1 1 10 100 FREQUENCY (MHz) Figure 12. Differential Output Voltage Noise vs. Frequency in a Typical VDSL2 Application Rev. D | Page 7 of 12 07760-007 500 07760-005 INTERNAL POWER DISSIPATION (mW) 1000 AD8398A APPLICATIONS INFORMATION POWER CONTROL MODES OF OPERATION BOARD LAYOUT The AD8398A features four power modes: full power, medium power, low power, and complete power-down. Two CMOScompatible logic pins (PD0 and PD1) select the power mode. The power modes and associated logic states are listed in Table 5. As is the case with all high speed applications, careful attention to printed circuit board (PCB) layout details prevents associated board parasitics from becoming problematic. Proper RF design technique is mandatory. Table 5. Power Modes PD1 0 0 1 1 PD0 0 1 0 1 Power Mode Full power Medium power Low power Power-down Total Supply Current (mA) 33.2 22.9 13.3 0.7 EXPOSED THERMAL PAD CONNECTIONS To ensure adequate heat transfer away from the die, connect the exposed thermal pad to a solid plane layer with low thermal resistance. To maximize the operating life of the AD8398A, the thermal design of the system should be kept below the junction temperature of 125°C. The PCB has a ground plane covering all unused portions of the component side of the board to provide a low impedance return path. Removing the ground plane on all layers from the area near the input and output pins of the AD8398A reduces stray capacitance. Signal lines connecting the feedback and gain resistors should be as short as possible to minimize the inductance and stray capacitance associated with these traces. Place termination resistors and loads as close as possible to their respective inputs and outputs. To minimize coupling (crosstalk) through the board, keep input and output traces as far apart as possible. Wherever there are complementary signals, provide a symmetrical layout to maximize balanced performance. Although it is electrically isolated, the thermal pad typically connects to the ground plane layer. POWER SUPPLY BYPASSING The AD8398A typically operates on ±6 V or +12 V supplies. Power the AD8398A circuit with a well-regulated, properly decoupled power supply. To minimize supply voltage ripple and power dissipation, use high quality capacitors with low equivalent series resistance (ESR), such as multilayer ceramic capacitors (MLCCs). Place a decoupling 0.1 μF MLCC no more than ⅛ inch away from each of the power supply pins. In addition, a 10 μF tantalum capacitor is recommended to provide good decoupling for lower frequency signals and to supply current for fast, large signal changes at the AD8398A outputs. Lay out bypass capacitors to keep return currents away from the inputs of the amplifiers. This layout minimizes any voltage drops that can develop due to ground currents flowing through the ground plane. Rev. D | Page 8 of 12 AD8398A 0 MULTITONE POWER RATIO –10 The discrete multitone (DMT) signal used in xDSL systems carries data in discrete tones or bins that appear in the frequency domain in evenly spaced 4.3125 kHz intervals. In applications using this type of waveform, multitone power ratio (MTPR) is a commonly used measure of linearity. Generally, designers are concerned with two types of MTPR: in band and out of band. In-band MTPR is defined as the measured difference from the peak of one tone that is loaded with data to the peak of an adjacent tone that is intentionally left empty. Out-of-band MTPR is defined as the spurious emissions that occur in the receive bands. Transmit band power and receive band MTPR are shown in Figure 13, Figure 14, and Figure 15 for Profile 17a, Profile 8b, and ADSL2+, respectively. OUTPUT POWER (dB) –20 OUTPUT POWER (dB) –70 –100 0 0.5 1.0 1.5 2.0 2.5 FREQUENCY (MHz) 3.0 07760-012 –90 Figure 15. MTPR of a Typical ADSL2+ DMT Test Signal, VS = ±6 V, Output Power = 20.4 dBm –40 –50 –60 –70 –80 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (MHz) 07760-010 –90 Figure 13. MTPR of a Typical VDSL2 Profile 17a DMT Test Signal, VS = ±6 V, Output Power = 14.5 dBm 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 0 1 2 3 4 5 6 7 8 9 10 FREQUENCY (MHz) 07760-020 OUTPUT POWER (dBm/Hz) –60 DSL line drivers are transformer-coupled to the twisted pair telephone line. In this environment, the AD8398A may be subject to large line transients resulting from events such as lightning strikes or downed power lines. Additional circuitry is required to protect the AD8398A from possible damage due to these events. –30 –120 –50 LIGHTNING AND AC POWER FAULT –20 –100 –40 –80 0 –10 –30 Figure 14. MTPR of a Typical VDSL2 Profile 8b DMT Test Signal, VS = ±6 V, Output Power = 20.4 dBm Rev. D | Page 9 of 12 AD8398A OUTLINE DIMENSIONS 4.10 4.00 SQ 3.90 PIN 1 INDICATOR 0.35 0.30 0.25 0.65 BSC PIN 1 INDICATOR 13 12 16 1 EXPOSED PAD 2.40 2.35 SQ 2.30 9 8 0.80 0.75 0.70 4 0.20 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 5 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD 101408-A TOP VIEW 0.45 0.40 0.35 Figure 16. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-16-20) Dimensions shown in millimeters ORDERING GUIDE Model1 AD8398AACPZ-R2 AD8398AACPZ-R7 AD8398AACPZ-RL 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Z = RoHS Compliant Part. Rev. D | Page 10 of 12 Package Option CP-16-20 CP-16-20 CP-16-20 AD8398A NOTES Rev. D | Page 11 of 12 AD8398A NOTES ©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07760-0-9/10(D) Rev. D | Page 12 of 12