AN3319 Application note STEVAL-ISV006V2: solar battery charger using the SPV1040 Introduction The SPV1040 is a high efficiency, low power and low voltage DC-DC converter that provides a single output voltage up to 5.2 V. Startup is guaranteed at 0.3 V and the device operates down to 0.45 V when coming out from MPPT mode. It is a 100 kHz fixed frequency PWM step-up (or boost) converter able to maximize the energy generated by few solar cells (polycrystalline or amorphous). The duty cycle is controlled by an embedded unit running an MPPT algorithm with the goal of maximizing the power generated from the panel by continuously tracking its output voltage and current. The SPV1040 guarantees the safety of overall application and of converter itself by stopping the PWM switching in the case of an overcurrent or overtemperature condition. The IC integrates a 120 mΩ N-channel MOSFET power switch and a 140 mΩ P-channel MOSFET synchronous rectifier. March 2013 DocID18265 Rev 8 1/25 www.st.com Contents AN3319 Contents 1 Application overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Boost switching application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 SPV1040 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Schematic and bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 External component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 7 Optional Schottky . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Appendix A SPV1040 parallel and series connection . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2/25 DocID18265 Rev 8 AN3319 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Boost application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 PV cell curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Inductor current in continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Inductor current in discontinuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Typical application schematic using the SPV1040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SPV1040 equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 MPPT working principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SPV1040 internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 STEVAL-ISV006V2 top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 STEVAL-ISV006V2 bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 STEVAL-ISV006V2 schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 STEVAL-ISV006V2 IOUT filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 STEVAL-ISV006V2 PCB top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 STEVAL-ISV006V2 PCB bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SPV1040 output parallel connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPV1040 output series connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DocID18265 Rev 8 3/25 Application overview 1 AN3319 Application overview Figure 1 shows the typical architecture of a boost converter based solar battery charger: Figure 1. Boost application schematic $0Y The SPV1040 adapts the characteristics of load to those of panel. In fact, a PV panel is made up of a series of PV cells. Each PV cell provides voltage and current which depend on the PV cell size, on its technology, and on the light irradiation power. The main electrical parameters of a PV panel (typically provided at light irradiation of 1000 W/m2, Tamb=25 °C) are: • VOC (open circuit voltage) • VMP (voltage at maximum power point) • ISC (short-circuit current) • IMP (current at maximum power point) Figure 2 shows the typical characteristics of a PV cell: Figure 2. PV cell curve 3RZ ZHU>:@ &XUUUHQW>$@ ,6& ,03 9ROWDJH J >>9@@ 903 92& $0Y MPP (maximum power point) is the working point of the PV cell at which the product of the extracted voltage and current provides the maximum power. 4/25 DocID18265 Rev 8 AN3319 2 Boost switching application Boost switching application A step-up (or boost) converter is a switching DC-DC converter able to generate an output voltage higher than (or at least equal to) the input voltage. Referring to Figure 1, the switching element (Sw) is typically driven by a fixed frequency square waveform generated by a PWM controller. When Sw is closed (ton) the inductor stores energy and its current increases with a slope depending on the voltage across the inductor and its inductance value. During this time the output voltage is sustained by COUT and the diode does not allow any charge transfer from the output to input stage. When Sw is open (toff), the current in the inductor is forced, flowing toward the output until voltage at the input is higher than the output voltage. During this phase the current in the inductor decreases while the output voltage increases. Figure 3 shows the behavior of inductor current. Figure 3. Inductor current in continuous mode ,/; ,/[SN 9287 9,1 / 9,1 / ,/[PLQ ( (RQRQ ( RII (RII W RQ W RII WLPH $0Y The energy stored in the inductor during ton is ideally equal to the energy released during toff, therefore the relation between ton and toff can be written as follows: t on D = -------------------------( ton + t off ) where “D” is the duty cycle of the square waveform driving the switching element. Boost applications can work in two different modes depending on the minimum inductor current within the switching period, that is if it is not null or null respectively: • Continuous mode (CM) • Discontinuous mode (DCM) DocID18265 Rev 8 5/25 Boost switching application AN3319 Figure 4. Inductor current in discontinuous mode , /[ , /[SN 9287 9,1 9,1 / (RQ W RQ / (RII W RII W LGOH WLPH $0Y Obviously the efficiency is normally higher in CM. Inductance and switching frequency (Fsw) impact the working mode. In fact, in order to have the system working in CM, the rule below should be followed: V OUT2 ( D ⋅ ( 1 – D ) )2 L > -------------- ⋅ ----------------------------------P IN 2 ⋅ F SW According to the above, L is minimum for D = 50 %. 6/25 DocID18265 Rev 8 AN3319 3 SPV1040 description SPV1040 description The following is a quick overview of SPV1040 functions, features, and operating modes. Figure 5. Typical application schematic using the SPV1040 L VPV Lx XSHUT I CTRL_PLUS GND I CTRL_MINUS R3 CIN MPP SET MPP- CINsns VBATT RS VOUT RF1 CF RF2 R1 COUT VCTRL D OUT R2 COUTsns AM06700v1 The SPV1040 acts as an impedance adapter between the input source and output load which is: Figure 6. SPV1040 equivalent circuit 639 , */ 9*/ 39 3DQHO JP9*/ &*/ , 065 &065 5065 9065 ='& $0Y Through the MPPT algorithm, it sets up the DC working point properly by guaranteeing ZIN = Zm (assuming Zm is the impedance of the supply source). In this way, the power extracted from the supply source (PIN = VIN * IIN) is maximum (PM = VM * IM). The voltage-current curve shows all the available working points of the PV panel at a given solar irradiation. The voltage-power curve is derived from the voltage-current curve by plotting the product V*I for each voltage generated. DocID18265 Rev 8 7/25 SPV1040 description AN3319 Figure 7. MPPT working principle 30$; RZHU >:@ 3R &XUUHQWW>$@ ,03 9ROWDJH>9@ 903 92& $0Y Figure 7 shows the logical sequence followed by the device which proceeds for successive approximations in the search for the MPP. This method is called “Perturb and Observe”. The diagram shows that a comparison is made between the digital value of the power Pn generated by the solar cells and sampled at instant n, and the value acquired at the previous sampling period Pn-1. This allows the MPPT algorithm to determine the sign of duty cycle and to increment or decrement it by a predefined amount. In particular, the direction of adjustment (increment or decrement of duty cycle) remains unchanged until condition Pn≥Pn-1 occurs, that is, for as long as it registers an increase of the instantaneous power extracted from the cells string. On the contrary, when it registers a decrease of the power Pn<Pn-1, the sign of duty cycle adjustment is inverted. In the meantime, SPV1040 sets its own duty cycle according to the MPPT algorithm, other controls are simultaneously executed in order to guarantee complete application safety. These controls are mainly implemented by integrated voltage comparators whose thresholds are properly set. Figure 8. SPV1040 internal block diagram V OUT Lx START SIGNAL ANALOG BLOCK ZERO CROSSING DETECTOR + VREF I CTRL_PLUS VMPP-REF OVER TEMPERATURE REVERSE POLARITY MPP BLOCK BURST MODE I CTRL_MINUS PWM CLOCK MPP-SET + DRIVERS CONTROL OVER CURRENT CLOCK Burst Ref XSHUT + DIGITAL CORE - DAC CODE GND Iout Reg Vin Reg Vout Reg V MPP-REF MPP-SET V CTRL + - VREF AM06703v1 8/25 DocID18265 Rev 8 AN3319 SPV1040 description The duty cycle set by the MPPT algorithm can be overwritten if one of the following is triggered: • Overcurrent protection (OVC), peak current on low side switch ≥ 1.8 A • Overtemperature protection (OVT), internal temperature ≥ 155 °C • Output voltage regulation, VCTRL pin triggers 1.25 V • Output current regulation Rs * (ICTRL_PLUS - ICTRL_MINUS) ≥ 50 mV • MPP-SET voltage VMPP-SET ≤ 300 mV at the start-up and VMPP-SET ≤ 450 mV in working mode. Application components must be carefully selected to avoid any undesired trigger of the above thresholds. In order to improve the overall system efficiency, and to reduce the BOM, the SPV1040 also integrates a zero crossing block whose role is to turn-off the synchronous rectifier to prevent reverse current flowing from output to input. DocID18265 Rev 8 9/25 Application example 4 AN3319 Application example Figure 9 and 10 show the demonstration board of a solar battery charger based on SPV1040 and on a status of charge indication circuit. Figure 9. STEVAL-ISV006V2 top view Figure 10. STEVAL-ISV006V2 bottom view STEVAL-ISV006V2 has been designed to recharge any type of battery (except lithium compound) which maximum voltage (VBATT_max) ≤ 5.2 V and supplied by up to 5 W PV panels (constrained by VOC<VBATT_max). By default STEVAL-ISV006V2 is set as follows: • Loaded by a 220 mF super capacitor • Supplyed by a 200 mW PV panel (VOC = 1.65 V, ISC = 150 mA) • Maximum output current 1 A The output trimmer VR2 allow regulating VCTRL across battery. Maximum output current can be regulated by replacing Rs current sensing resistor according to application requirements. Please refer to Section 6: external component selection for details about the whole application set-up. 10/25 DocID18265 Rev 8 AN3319 Application example Further, STEVAL-ISV006V2 provides a simple charge status circuit with 2 LEDs: • Red LED on and green LED off, if the battery voltage is lower than charge threshold • Red LED off and green LED on, if the battery voltage is higher than charge threshold Charge threshold can be regulated by trimmer VR10. Charge status circuit can be bypassed by opening jumper J1. DocID18265 Rev 8 11/25 Schematic and bill of material 5 AN3319 Schematic and bill of material Figure 11. STEVAL-ISV006V2 schematic optional Vbat+ J1 L1 PV+ XSHUT R3 V OUT Lx R5 I CTRL_MINUS GND MPP SET MPP- CIN1 RF1 I CTRL_PLUS XSHUT VLOAD+ VR4 ( DNM) Super Cap V CTRL C4 VR10 R1 RF2 CF COUT1 VR2 PV- Battery Charge Monitor circuit RS1 COUT2 D OUT R9 C2 R11 VLOAD LOAD- VbatAM06706v1 Table 1 shows the list of external components used in the demonstration board. Table 1. BOM Component (alternate label) Name U25/26 Solar battery charger PV panel Poly-crystalline PV panel CIN1 Supplier Serial number STMicroelectronics SPV1040T 200 mW NBSZGD SZGD7050-3P Input capacitor 10 μF EPCOS C2012X5R1A106K C4 Voltage sensing capacitor 100 nF EPCOS C2012X5R1H104K C2 Voltage sensing capacitor 1 nF EPCOS C2012C0G1H102J COUT1 Output capacitor 4.7 μF EPCOS C2012X5R0J475K COUT2 Output capacitor 10 μF EPCOS C2012X5R1A106K R3 Input voltage partitioning resistor 1 kΩ Cyntec RG2012P1001BN VR2, VR10 VR4 (DNM) OUT, MPP-SET and charge indication partitioning resistor 0-1 MkΩ VISHAY 63M-105 R1 Output voltage partitioning resistor 1 MΩ Cyntec RG2012P105BN R11 Output voltage partitioning resistor 330 kΩ Cyntec RG2012P334BN R5 Pull-up resistor 0 Cyntec RL1220TR010FN 12/25 Value DocID18265 Rev 8 AN3319 Schematic and bill of material Table 1. BOM (continued) Component (alternate label) Name Value Supplier Serial number L1 Inductor 10 μH Coilcraft Coilcraft EPCOS XAL6060-103 MSS7341-103 B82442T1103K050 J28 Super capacitor 220 nF Panasonic EECS0HD224H Dout1 Protection diode STMicroelectronics SMM4F5.0 RS1 Output current sense 10 mΩ Cyntec RL1220TR000FN RF1, RF2 Noise filterirng resistors 1 kΩ Cyntec RG2012P1001BN CF1 Noise filtering capacitor 1 μF EPCOS C2012X7R1C105K U27 QUAD comparator STMicroelectronics TS339 D1 Green LED 1.8 V, 2 mA Avago Tech. HLMP-1790 D4 Red LED 1.8 V, 2 mA Avago Tech. HLMP-1700 D5 Reference diode STMicroelectronics STPS160U R6, R7 LED protection resistors 1 kΩ Cyntec RG2012P1001BN R8 Reference resistors 1 MΩ Cyntec RG2012P105BN R9 Charge status threshold resistors 27 kΩ Cyntec RG2012P2701BN DocID18265 Rev 8 13/25 External component selection 6 AN3319 External component selection SPV1040 requires a set of external components and their proper selection guarantees both the best chip functionality and system efficiency. Input voltage capacitor CIN is the input capacitor connected to the input rail in order to reduce the voltage ripple. According to the maximum current (ISC) provided by the PV panel connected at the input, the following formula should be considered to select the proper capacitance value for a specified maximum input voltage ripple (VIN_rp_max): I SC C IN ≥ ------------------------FSW ⋅ VIN _rp_max Maximum voltage of this capacitor is strictly dependent on the input source (typically between 1 V and 3 V). Low-ESR capacitors are a good choice to increase the whole system efficiency. In order to reduce the ESR effect, it is suggested to split the input capacitance into two capacitors placed in parallel. Input voltage partitioning VMPP-SET is the pin used to monitor the voltage generated by the solar cells. The VMPP-SET pin can be directly connected to PV+ rail through a 1 kΩ R3 resistor. With regard to the VMPP-SET pin, two constraints must be taken into account: • • When SPV1040 is off, VMPP-SET voltage must be ≥0.3 to turn-on the device When SPV1040 is in operating mode, it enters BURST MODE if VMPP-SET decreases triggering the 450 mV threshold. Input voltage sensing capacitor C4 is placed as close as possible to the VMPP-SET pin to reject noise on VMPP-SET voltage. However, VMPP-SET must be able to follow the VIN waveform to allow SPV1040 to monitor input voltage variations. It means that the time constant R3*C4 must be chosen according to system properties, which is the MPPT tracking time (TMPP ≅1 ms). The rule below must be followed in order to select C4 capacitance: 1 –3 1 C 4 ≤ T MPP ⋅ ------- = 10 ⋅ --------3R3 10 Assuming R3= 1 kΩ then: C 4 ≤ 10μF 14/25 DocID18265 Rev 8 AN3319 External component selection Inductor selection Inductor selection is a crucial point for this application. The following application constraints must be taken into account: • Maximum input current (i.e. IMP and ISC of PV panel) • Maximum input voltage (i.e. VMP and Voc of PV panel) • Overcurrent threshold of SPV1040 (1.8 A) • Maximum duty cycle of SPV1040 (90 %). The input current from the PV panel flows into the inductor, so: I Lxrms ≅ I MP < I SC According to Figure 3, during the charge phase (switch on), peak current on the inductor depends on the applied voltage (VIN) on the inductance (Lx), and on the duty cycle (ton). Considering the maximum duty cycle (90 %): –6 9 ⋅ 10 VMP ILXpeak = ILXrms + ------------------------------2L x Taking into account the overcurrent threshold: I LXpeak < 1.8A Finally, inductance should be chosen according to the following formula: –6 –6 1 9 ⋅ 10 V MP 1 9 ⋅ 10 V MP L X > --- ⋅ ------------------------------- = --- ⋅ ------------------------------2 2 – I LXrms 2 2 – I MP A safer choice is to replace VMP with VOC. Usually, inductances ranging between 10 μH to 100 μH satisfy most application requirements. Other critical parameters for the inductor choice are Irms, saturation current, and size. Irms is the self rising temperature of the inductor, affecting the nominal inductance value. In particular, the inductance decreases with Irms and the temperature increases. As a consequence the inductor current peak can reach or surpass 1.8 A. Inductor size also affects the maximum current deliverable to the load. In any case, the saturation current of the choke should be higher than the peak current limit of the input source. Hence, the suggested saturation current must be > 1.8 A. At the same size, small inductance values guarantee both faster response to load transients and higher efficiency. Inductors with low series resistance are suggested in order to guarantee high efficiency. Output voltage capacitor A minimum output capacitance must be added at the output in order to reduce the voltage ripple. Critical parameters for capacitors are: capacitance, maximum voltage, and ESR. DocID18265 Rev 8 15/25 External component selection AN3319 According to the maximum current (ISC) provided by the PV panel connected at the input, the following formula can be used to select the proper capacitance value (COUT) for a specified maximum output voltage ripple (VOUT_rp_max): I SC C OUT ≥ -------------------F SW ⋅ VOUT_rp_max Maximum voltage of this capacitor is strictly dependent on the output voltage range. SPV1040 can support up to 5.2 V, so the suggested maximum voltage for these capacitors is 10 V. Low-ESR capacitors are a good choice to increase the whole system efficiency. Output voltage partitioning R1 and R2 are the two resistors used for partitioning the output voltage. The said VOUT_max the maximum output voltage of the battery, R1 and R2 must be selected according to the following rule: R1 V OUT ------- = --------------_max -1 R2 1.25 Also, in order to optimize the efficiency of the whole system, when selecting R1 and R2, their power dissipation must be taken into account. Assuming a negligible current flowing into the VCTRL pin, maximum power dissipation on the series R1+R2 is: ( V OUTmax ) _ PVCTRL_sns = ------------------------------R1 + R2 2 As an empirical rule, R1 and R2 should be selected to get: P VCTRLsns « 0.01 ⋅ ( V OUTmax ⋅ IOUTmax ) _ _ _ Note: In order to guarantee proper functionality of the VCTRL pin, the current flowing into the series R1+R2 should be in the range between 2 µA and 20 µA. Output voltage sensing capacitor C2 is placed in parallel to R2 and as close as possible to the VCTRL pin. Its role is to reject the noise on the voltage sensed by the VCTRL pin. Capacitance value depends on the time constant resulting from R2 (τOUT= C2*R1//R2) and from the system switching frequency (100 kHz), as follows: τ out ≅ 10 ∗ C 2 ≅ 10 * 16/25 1 Fssw 1 1 * Fssw R1 // R 2 DocID18265 Rev 8 AN3319 External component selection Output current sensing filter Rs is placed in the output rail between the ICTRL_MINUS and ICTRL_PLUS pins. Its role is to sense the output current (IOUT) flowing toward the load. Voltage drop on Rs is sensed by the ICTRL_MINUS and ICTRL_PLUS pins and compared with the 50 mV internal threshold. 50mV R S ≅ ---------------------I OUTmax _ The triangular waveform of the current and noise may cause unexpected triggering of the 50 mV threshold. This can be avoided with a filter such as the one shown below: Figure 12. STEVAL-ISV006V2 IOUT filter RS VOUT RF1 ICTRL_PLUS ICTRL_MINUS VBAT+ CF RF2 AM06707v1 Suggested values are: RF1=RF2 = 1 kΩ CF = 1 μF Output protection diode If the load is not a battery, DOUT is required and placed in parallel to the output load. Its role is to protect the devices in case a PV cell providing IMP > 0.5 A is connected when very low load is connected. In fact, SPV1040 is supplied by the VOUT pin, so in the above condition the device is still off when the PV cell is connected and a voltage spike can occur damaging the converter and the battery. In order to guarantee the best system performance and reliability, DOUT should be selected as follows: VBR > VOUT_max VCL ≤ 5.5 V DOUT must be able to dissipate the following maximum power: Pmax = ISC*VCL XSHUT resistor The XSHUT pin controls SPV1040 turn-on (0.3 V ≤ XSHUT ≤ 5.2 V) or turn-off (XSHUT < 0.3 V). DocID18265 Rev 8 17/25 External component selection AN3319 R5 is a 0 Ω pull-up resistor shorting the XSHUT and MPP-SET pins. Removing R5 enables the external control of the XSHUT pin to turn the SPV1040 on/off. 6.1 Optional Schottky An external Schottky diode between Lx and VOUT pins is mandatory in all the applications with VBATT_max > 4.8 V. In fact, voltage on Lx pin can go above the maximum absolute voltage threshold (5.5 V) due to the voltage drop on the high side integrated switch when this is off (discontinuous mode) and current needs to flow from input to output. This Schottky diode should be chosen according to the following criteria: V F ≤ 5.5V - VBATT_max and I F ≥ I Lmax For setting up the application and simulating the related test results please go to www.st.com/edesignstudio. 18/25 DocID18265 Rev 8 AN3319 7 Layout Layout Figure 13. STEVAL-ISV006V2 PCB top view Figure 14. STEVAL-ISV006V2 PCB bottom view Layout guidelines PCB layout is very important in order to minimize voltage and current ripple, high frequency resonance problems, and electromagnetic interference. It is essential to keep the paths where the high switching current circulates as small as possible in order to reduce radiation and resonance problems. Large traces for high current paths and an extended ground plane reduce noise and increase efficiency. The output and input capacitors should be placed as close as possible to the device. The external resistor dividers, if used, should be as close as possible to the VMPP-SET and VCTRL pins of the device, and as far as possible from the high current circulating paths, in order to avoid picking up noise. DocID18265 Rev 8 19/25 SPV1040 parallel and series connection Appendix A AN3319 SPV1040 parallel and series connection Output pins of many SPV1040s can be connected either in parallel or in series. In both cases the output power (Pout) depends on light irradiation of each panel, on application efficiency, and on the specific constraints of the selected topology. The objective of this section is to explain how the output power is impacted by the selected topology. An example with 3 PV panels (panel1, panel2, panel3) is presented, but the conclusion can be extended to a larger number of PV panels. If the panel is lighted and the SPV1040 is on (it means that light irradiation intensity is such that VMPP-SET ≥ 0.3 V): POUTx = ηPINx [x = 1..3] If the panel is completely shaded: POUTx=0 SPV1040 parallel connection This topology guarantees the desired output voltage even when only one panel is irradiated. The obvious constraint of this topology is that VOUT is limited to the SPV1040 maximum output voltage. Figure 15 shows the parallel connection topology: Figure 15. SPV1040 output parallel connection VOUT+ PV3+ PV3 PV2 PV1 Vo3+ SPV1040 PV3- Vo3- PV2+ Vo2+ SPV1040 PV2 PV2- Vo2- PV1+ Vo1+ SPV1040 PV1- Vo1- VOUT- AM06711v1 The output partitioning (R1/R2) of each SPV1040 must be coherent with the desired VOUTX. According to the topology: VOUT=VOUT1=VOUT2=VOUT3 IOUT=IOUT1+IOUT2+IOUT3 20/25 DocID18265 Rev 8 AN3319 SPV1040 parallel and series connection According to the light irradiation on each panel and to the system efficiency (η), the output power results: POUT = POUT1 + POUT 2 + POUT 3 POUTx = VOUTx * IOUTx [x = 1..3] PINx = VINx * IINx [x = 1..3] Therefore: POUT = VOUT (IOUT1 + IOUT 2 + IOUT 3 ) = ηPIN1 + ηPIN2 + ηPIN3 Each SPV1040 contributes to the output power providing IOUTX. Finally, the desired VOUT is guaranteed if at least one of the 3 PV panels provides enough power to turn-on the SPV1040 relating to it. SPV1040 series connection This topology provides an output voltage that is the sum of the output voltages of the SPV1040 connected in series. The objective of this section is to explain how the output power is impacted by the selected topology. Figure 16 shows the series connection topology: Figure 16. SPV1040 output series connection VOUT+ PV3+ PV3 Vo3+ SPV1040 PV3- Vo3- PV2+ Vo2+ PV2 SPV1040 PV1 PV2 PV2- Vo2- PV1+ Vo1+ SPV1040 PV1- Vo1- VOUT- AM06710v1 In this case, the topology imposes: IOUT = IOUT 1 = IOUT 2 = IOUT 3 VOUT = VOUT1 + VOUT 2 + VOUT 3 In case irradiation is the same for each panel: POUT 1 = POUT 2 = POUT 3 POUT = 3 * POUTx POUTx = [x = 1..3] 1 POUT 3 POUTx = VOUTx * IOUTx = VOUT1 * IOUT DocID18265 Rev 8 21/25 SPV1040 parallel and series connection AN3319 Therefore: VOUTx = 1 VOUT 3 For example, assuming POUT = 3 W and VOUT = 12 V, then VOUTx = 4 V. Lower irradiation for one panel, for example on panel 2, causes lower output power, so lower VOUT2 due to the IOUT imposed by the topology: VOUTx = POUTx IOUT The output voltage required by the load can be provided by the 1st and the 3rd SPV1040 but only up to the limit imposed by each of their R1/R2 partitionings. Some examples can help in understanding the various scenarios assuming that each R1/R2 limits VOUTx to 4.8 V. Example 1: Panel 2 has 75 % irradiation of panels 1 and 3: VOUT 2 = 3 3 * VOUT1 = * VOUT3 4 4 POUT 1 = POUT 3 = 1W POUT2 = 3 POUT1 = 0.75W 4 POUT = POUT1 + POUT 2 + POUT 3 = 2.75 W IOUT = POUT 2.75 = = 0.23A VOUT 12 VOUT1 = VOUT3 = VOUT 2 = 1 = 4.35 V 0 .23 0.75 = 3.26V 0.23 Two SPV1040s (1st and 3rd) supply the voltage drop caused by the lower irradiation on panel 2. Warning: 22/25 SPV1040 is a boost controller, so VOUTx must be higher than VINx, otherwise the SPV1040 turns off and the input power is transferred to the output stage through the integrated Pchannel MOS without entering the switching mode. DocID18265 Rev 8 AN3319 SPV1040 parallel and series connection Example 2: Panel 2 has 50 % irradiation of panels 1 and 3: 1 1 P OUT2 = --- ⋅ P OUT1 = --- ⋅ P OUT3 2 2 P OUT1 = POUT3 = 1W 1 P OUT2 = --- P OUT1 = 0.5W 2 P OUT = P OUT1 + P OUT2 + P OUT 3 = 2.5W P OUT 2.5 I OUT = -------------- = -------- = 0.21A V OUT 12 1 V OUT1 = V OUT3 = ----------- = 4.76V 0.21 0.5 V OUT2 = ----------- = 2.38V 0.21 In this case the system is close to its maximum voltage limit, in fact, a lower irradiation on panel 2 impacts VOUT1 and/or VOUT3 which are very close to the maximum output voltage threshold (4.8 V) imposed by R1/R2 partitioning. Example 3: Panel 2 completely shaded. In this case the maximum VOUT can be 9.6 V (VOUT1+VOUT3). The current flow is guaranteed by the body diodes of the power MOSFETs integrated in the SPV1040 (or by the bypass diodes, if any, placed between VOUT- and VOUT+). DocID18265 Rev 8 23/25 Revision history AN3319 Revision history Table 2. Document revision history 24/25 Date Revision Changes 02-Feb-2011 1 Initial release 18-Apr-2011 2 – Demonstration board changed: from STEVAL-ISV006V1 to STEVAL-ISV006V2 – Figure 9, 10, 11, 13 and 14 modified – Section 4 modified – Table 1 modified 04-May-2011 3 Modified: Table 1 08-Sep-2011 4 – – – – 12-Sep-2011 5 Minor text changes 21-Sep-2011 6 – Modified: Figure 5, 8 and 11 – Modified: text and equation for Input voltage sensing capacitor in Section 6: External component selection 18-Nov-2011 7 Modified: value of the component RS1 in Table 1 21-Mar-2013 8 Updated Figure 8. Modified: Section 3 and 4 Changed: Table 1: BOM Changed: Figure 5, 8, 9 and 11 Modified: Input voltage partitioning, Input voltage sensing capacitor DocID18265 Rev 8 AN3319 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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