AD AD6644ASTZ-65 Analog-to-digital converter Datasheet

14-Bit, 40 MSPS/65 MSPS
Analog-to-Digital Converter
AD6644
Designed for multichannel, multimode receivers, the AD6644
is part of the Analog Devices, Inc. new SoftCell® transceiver
chipset. The AD6644 achieves 100 dB multitone, spurious-free
dynamic range (SFDR) through the Nyquist band. This breakthrough performance eases the burden placed on multimode
digital receivers (software radios) which are typically limited by
the ADC. Noise performance is exceptional; typical signal-tonoise ratio is 74 dB.
FEATURES
65 MSPS guaranteed sample rate
40 MSPS version available
Sampling jitter < 300 fs
100 dB multitone SFDR
1.3 W power dissipation
Differential analog inputs
Pin compatible to AD6645
Twos complement digital output format
3.3 V CMOS compatible
Data-ready for output latching
The AD6644 is also useful in single channel digital receivers
designed for use in wide-channel bandwidth systems (CDMA,
WCDMA). With oversampling, harmonics can be placed
outside the analysis bandwidth. Oversampling also facilitates
the use of decimation receivers (such as the AD6620), allowing
the noise floor in the analysis bandwidth to be reduced. By
replacing traditional analog filters with predictable digital
components, modern receivers can be built using fewer RF
components, resulting in decreased manufacturing costs, higher
manufacturing yields, and improved reliability.
APPLICATIONS
Multichannel, multimode receivers
AMPS, IS-136, CDMA, GSM, WCDMA
Single channel digital receivers
Antenna array processing
Communications instrumentation
Radar, infrared imaging
Instrumentation
The AD6644 is built on the Analog Devices high speed
complementary bipolar process (XFCB) and uses an innovative,
multipass circuit architecture. Units are packaged in a 52-lead
plastic low profile quad flat package (LQFP) specified from –
25°C to +85°C.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD6644 is a high speed, high performance, monolithic 14-bit
analog-to-digital converter (ADC). All necessary functions,
including track-and-hold (TH) and reference, are included onchip to provide a complete conversion solution. The AD6644
provides CMOS-compatible digital outputs. It is the third
generation in a wideband ADC family, preceded by the AD9042
(12-bit 41 MSPS) and the AD6640 (12-bit 65 MSPS, IF
sampling).
1. Guaranteed sample rate is 65 MSPS.
2. Fully differential analog input stage.
3. Digital outputs can be run on 3.3 V supply for easy interface
to digital ASICs.
4. Complete solution: reference and track-and-hold.
5. Packaged in small, surface-mount, plastic, 52-lead LQFP.
FUNCTIONAL BLOCK DIAGRAM
AVCC DVCC
VREF
A1
TH1
2.4V
TH2
A2
ADC1
TH3
TH4
DAC1
ADC2
5
ENCODE
ENCODE
INTERNAL
TIMING
GND
TH5
ADC3
AD6644
DAC2
6
5
DIGITAL ERROR CORRECTION LOGIC
DMID OVR DRY D13 D12 D11 D10 D9
(MSB)
D8
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
00971-001
AIN
AIN
Figure 1.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
AD6644* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
REFERENCE MATERIALS
View a parametric search of comparable parts.
Technical Articles
• Buffer Adapts Single-ended Signals for Differential Inputs
DOCUMENTATION
Application Notes
• Correlating High-Speed ADC Performance to Multicarrier
3G Requirements
• AN-1142: Techniques for High Speed ADC PCB Layout
• DNL and Some of its Effects on Converter Performance
• AN-282: Fundamentals of Sampled Data Systems
• MS-2210: Designing Power Supplies for High Speed ADC
• AN-302: Exploit Digital Advantages in an SSB Receiver
• Redefining the Role of ADCs in Wireless
• AN-345: Grounding for Low-and-High-Frequency Circuits
• Soft Radio Runs into Hard Standards
• AN-501: Aperture Uncertainty and ADC System
Performance
DESIGN RESOURCES
• AN-586: LVDS Outputs for High Speed A/D Converters
• AD6644 Material Declaration
• AN-715: A First Approach to IBIS Models: What They Are
and How They Are Generated
• PCN-PDN Information
• AN-737: How ADIsimADC Models an ADC
• Symbols and Footprints
• Quality And Reliability
• AN-741: Little Known Characteristics of Phase Noise
• AN-756: Sampled Systems and the Effects of Clock Phase
Noise and Jitter
DISCUSSIONS
View all AD6644 EngineerZone Discussions.
• AN-807: Multicarrier WCDMA Feasibility
• AN-808: Multicarrier CDMA2000 Feasibility
SAMPLE AND BUY
• AN-835: Understanding High Speed ADC Testing and
Evaluation
Visit the product page to see pricing options.
• AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
TECHNICAL SUPPORT
• AN-935: Designing an ADC Transformer-Coupled Front
End
Data Sheet
• AD6644: 14-Bit, 40 MSPS/65 MSPS Analog-to-Digital
Converter Data Sheet
Submit a technical question or find your regional support
number.
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
TOOLS AND SIMULATIONS
• Visual Analog
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not
trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
AD6644
TABLE OF CONTENTS
Features .............................................................................................. 1
Explanation of Test Levels............................................................7
Applications....................................................................................... 1
Thermal Resistance .......................................................................7
General Description ......................................................................... 1
ESD Caution...................................................................................7
Product Highlights ........................................................................... 1
Pin Configuration and Function Descriptions..............................8
Functional Block Diagram .............................................................. 1
Typical Performance Characteristics ..............................................9
Revision History ............................................................................... 2
Equivalent Circuits......................................................................... 12
Specifications..................................................................................... 3
Terminology .................................................................................... 13
DC Specifications ......................................................................... 3
Theory of Operation ...................................................................... 15
Digital Specifications ................................................................... 4
Applying the AD6644 ................................................................ 15
Switching Specifications .............................................................. 4
Evaluation Board ............................................................................ 18
AC Specifications.......................................................................... 5
Outline Dimensions ....................................................................... 21
Timing Diagram ........................................................................... 6
Ordering Guide .......................................................................... 21
Absolute Maximum Ratings............................................................ 7
REVISION HISTORY
8/07—Rev. C to Rev. D
Changes to Table 5............................................................................ 5
Changes to Noise (for Any Range Within the ADC) Definition .. 13
Added Table 8.................................................................................. 16
Changes to Evaluation Board Section.......................................... 18
Changes to Ordering Guide .......................................................... 21
5/03—Data Sheet changed from Rev. B to Rev. C
Updated Outline Dimensions ....................................................... 19
3/03—Data Sheet changed from Rev. A to Rev. B
Change to Digital Specifications Note ........................................... 2
3/03—Data Sheet changed from Rev. 0 to Rev. A
Edits to Specifications ...................................................................... 2
Renumbering of Figures and TPCs ..................................Universal
Updated Outline Dimensions ....................................................... 19
Rev. D | Page 2 of 24
AD6644
SPECIFICATIONS
DC SPECIFICATIONS
AVCC = 5 V, DVCC = 3.3 V; TMIN = –25°C, TMAX = +85°C, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
POWER SUPPLY REJECTION RATIO (PSRR)
REFERENCE OUT (VREF)
ANALOG INPUTS (AIN, AIN)
Differential Input Voltage Span
Differential Input Resistance
Differential Input Capacitance
POWER SUPPLY
Supply Voltage
AVCC 2
DVCC
Supply Current
IAVCC (AVCC = 5.0 V)
IDVCC (DVCC = 3.3 V)
Rise Time 3
AVCC
POWER CONSUMPTION
AD6644AST-40
Typ
Max
14
AD6644AST-65
Typ
Max
14
Temp
Test Level 1
Min
Full
Full
Full
Full
Full
II
II
II
II
V
−10
−10
−1.0
Full
Full
Full
Full
V
V
V
V
10
95
±1.0
2.4
10
95
±1.0
2.4
ppm/°C
ppm/°C
mV/V
V
Full
Full
25°C
V
V
V
2.2
1
1.5
2.2
1
1.5
V p-p
kΩ
pF
Full
Full
II
II
Full
Full
Full
Full
Guaranteed
+3
−6
±0.25
±0.50
4.85
3.0
+10
+10
+1.5
5.0
3.3
5.25
3.6
II
II
245
30
IV
II
1.3
1
Min
−10
−10
−1.0
4.85
3.0
Rev. D | Page 3 of 24
+10
+10
+1.5
mV
% FS
LSB
LSB
5.0
3.3
5.25
3.6
V
V
276
36
245
30
276
36
mA
mA
1.5
1.3
15
1.5
ms
W
See the Explanation of Test Levels section.
AVCC can vary from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range AVCC = 5.0 V to 5.25 V.
3
Specified for dc supplies with linear rise time characteristics.
2
Guaranteed
+3
–6
±0.25
±0.50
Unit
Bits
AD6644
DIGITAL SPECIFICATIONS
AVCC = 5 V, DVCC = 3.3 V; TMIN = −25°C, TMAX = +85°C, unless otherwise noted.
Table 2.
Parameter
ENCODE INPUTS (ENCODE, ENCODE)
Differential Input Voltage2
Differential Input Resistance
Differential Input Capacitance
LOGIC OUTPUTS (D13 to D0, DRY, OVR)
Logic Compatibility
Logic 1 Voltage3
Logic 0 Voltage3
Output Coding
DMID
Temp
Test Level1
Min
Full
25°C
25°C
IV
V
V
0.4
Full
Full
V
V
Full
V
AD6644AST-40
Typ
Max
AD6644AST-65
Typ
Max
Min
0.4
10
2.5
V p-p
kΩ
pF
10
2.5
CMOS
2.5
0.4
Twos complement
DVCC/2
Unit
CMOS
2.5
0.4
Twos complement
DVCC/2
V
V
V
1
See the Explanation of Test Levels section.
All ac specifications tested by driving ENCODE and ENCODE differentially. Reference Figure 18 for performance vs. encode power.
3
Digital output logic levels: DVCC = 3.3 V, CLOAD = 10 pF. Capacitive loads >10 pF degrade performance.
2
SWITCHING SPECIFICATIONS
AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = maximum conversion rate MSPS; TMIN = –25°C, TMAX = +85°C, unless otherwise noted.
Table 3.
Parameter
Maximum Conversion Rate
Minimum Conversion Rate
ENCODE Pulse Width High
ENCODE Pulse Width Low
1
Temp
Full
Full
Full
Full
Test Level1
II
IV
IV
IV
Min
40
AD6644AST-40
Typ
Max
Min
65
AD6644AST-65
Typ
Max
15
15
10
10
6.5
6.5
Unit
MSPS
MSPS
ns
ns
See the Explanation of Test Levels section.
AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = maximum conversion rate MSPS; TMIN = −25°C, TMAX = +85°C, CLOAD = 10 Pf,
unless otherwise noted.
Table 4.
Parameter
ENCODE INPUT PARAMETERS2
Encode Period @ 65 MSPS
Encode Period @ 40 MSPS
Encode Pulse Width High3 @ 65 MSPS
Encode Pulse Width Low @ 65 MSPS
ENCODE/DATA READY
Encode Rising to Data Ready Falling
Encode Rising to Data Ready Rising
@ 65 MSPS (50% Duty Cycle)
@ 40 MSPS (50% Duty Cycle)
ENCODE/DATA (D13:0), OVR
ENCODE to DATA Falling Low
ENCODE to DATA Rising Low
ENCODE to DATA Delay (Hold Time)4
ENCODE to DATA Delay (Setup Time)5
Encode = 65 MSPS (50% Duty Cycle)
Encode = 40 MSPS (50% Duty Cycle)
Name
Temp
Test Level1
tENC
tENC
tENCH
tENCL
Full
Full
Full
Full
V
V
IV
IV
6.2
6.2
tDR
tE_DR
Full
IV
2.6
Full
Full
IV
IV
10.3
15.1
Full
Full
Full
IV
IV
IV
3.8
3.0
3.0
Full
Full
IV
IV
6.2
15.9
tE_FL
tE_RL
tH_E
tS_E
Rev. D | Page 4 of 24
Min
AD6644AST-40/65
Typ
Max
15.4
25
7.7
7.7
3.4
tENCH + tDR
11.1
15.9
5.5
4.3
4.3
tENC − tE_FL
9.8
19.4
Unit
9.2
9.2
ns
ns
ns
ns
4.6
ns
12.3
17.1
ns
ns
9.2
6.4
6.4
ns
ns
ns
11.6
21.2
ns
ns
AD6644
Parameter
DATA READY (DRY6)/DATA, OVR
Data Ready to DATA Delay (Hold Time)3
Encode = 65 MSPS (50% Duty Cycle)
Encode = 40 MSPS (50% Duty Cycle)
Data Ready to DATA Delay (Setup Time)3
@ 65 MSPS (50% Duty Cycle)
@ 40 MSPS (50% Duty Cycle)
APERTURE DELAY
APERTURE UNCERTAINTY (JITTER)
Name
Temp
Test Level1
Min
Full
Full
IV
IV
8.0
12.8
Full
Full
25°C
25°C
IV
IV
V
V
3.2
8.0
AD6644AST-40/65
Typ
Max
tH_DR
tS_DR
tA
tJ
See note7
8.6
13.4
See note7
5.5
10.3
100
0.2
Unit
9.4
14.2
ns
ns
6.5
11.3
ns
ns
ps
ps rms
1
See the Explanation of Test Levels section.
Several timing parameters are a function of tENC and tENCH.
To compensate for a change in duty cycle for tH_DR and tS_DR use the following equations:
NewtH_DR = (tH_DR − % Change(tENCH)) × tENC/2
NewtS_DR = (tS_DR − % Change(tENCH)) × tENC/2
4
ENCODE to data delay (hold time) is the absolute minimum propagation delay through the ADC.
5
ENCODE to data delay (setup time) is calculated relative to 65 MSPS (50% duty cycle). To calculate tS_E for a given encode, use the following equation:
NewtS_E = tENC(NEW) − tENC + tS_E (that is, for 40 MSPS, NewtS_E(TYP) = 25 × 10−9 − 15.38 × 10−9 + 9.8 × 10−9 = 19.4 × 10−9).
6
DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock correspondingly changes the duty cycle of DRY.
7
Data ready to data delay (tH_DR and tS_DR) is calculated relative to 65 MSPS (50% duty cycle) and is dependent on tENC and duty cycle. To calculate tH_DR and tS_DR for a
given encode, use the following equations:
NewtH_DR = tENC(NEW)/2 − tENCH + tH_DR (that is, for 40 MSPS, NewtH_DR(TYP) = 12.5 × 10−9 − 7.69 × 10−9 + 8.6 × 10−9 = 13.4 × 10−9).
NewtS_DR = tENC(NEW)/2 − tENCH + tS_DR (that is, for 40 MSPS, NewtS_DR(TYP) = 12.5 × 10−9 − 7.69 × 10−9 + 5.5 × 10−9 = 10.3 × 10−9).
2
3
AC SPECIFICATIONS
All ac specifications tested by driving ENCODE and ENCODE differentially.
AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = maximum conversion rate MSPS; TMIN = −25°C, TMAX = +85°C, unless otherwise noted.
Table 5.
Parameter
SNR
Analog Input
@ −1 dBFS
SINAD2
Analog Input
@ −1 dBFS
WORST HARMONIC (2ND or 3RD)2
Analog Input
@ −1 dBFS
WORST HARMONIC (4TH or Higher)2
Analog Input
@ −1 dBFS
AD6644AST-40
Min
Typ
Max
Conditions
Temp
Test Level1
2.2 MHz
15.5 MHz
30.5 MHz
25°C
25°C
25°C
V
II
II
74.5
74.0
73.5
2.2 MHz
15.5 MHz
30.5 MHz
25°C
25°C
25°C
V
II
V
74.5
74.0
73.0
2.2 MHz
15.5 MHz
30.5 MHz
25°C
25°C
25°C
V
II
V
92
90
85
2.2 MHz
15.5 MHz
30.5 MHz
25°C
25°C
25°C
Full
V
II
V
V
93
92
92
100
Full
25°C
V
V
90
250
TWO-TONE SFDR2, 3, 4
TWO-TONE IMD REJECTION2, 4
F1, F2 @ −7 dBFS
ANALOG INPUT BANDWIDTH
1
See the Explanation of Test Levels section.
AVCC = 5 V to 5.25 V for rated ac performance.
Analog input signal power swept from −7 dBFS to −100 dBFS.
4
F1 = 15 MHz, F2 = 15.5 MHz.
2
3
Rev. D | Page 5 of 24
AD6644AST-65
Min
Typ
Max
Unit
74.5
74.0
73.5
dB
dB
dB
72
74.5
74.0
73.0
dB
dB
dB
83
92
90
85
dBc
dBc
dBc
93
92
92
100
dBc
dBc
dBc
dBFS
90
250
dBc
MHz
72
72
85
AD6644
TIMING DIAGRAM
tA
N+3
N
AIN
N+1
N+2
ENCODE,
ENCODE
tE_RL
D[13:0], OVR
N
tENCL
N+1
N+4
N+2
tE_FL
N+3
tE_DR
N–3
N–2
N–1
tS_DR
DRY
tDR
Figure 2. Timing Diagram
Rev. D | Page 6 of 24
N+4
tS_E
tH_E
N
tH_DR
00971-002
tENCH
tENC
AD6644
ABSOLUTE MAXIMUM RATINGS
EXPLANATION OF TEST LEVELS
Table 6.
Parameter
Electrical
AVCC Voltage
DVCC Voltage
Analog Input Voltage
Analog Input Current
Digital Input Voltage
Digital Output Current
Environmental
Operating Temperature Range (Ambient)
Storage Temperature Range (Ambient)
Lead Temperature (Soldering, 10 sec)
Maximum Junction Temperature
Rating
Test Level
0 V to 7 V
0 V to 7 V
0 V to AVCC
25 mA
0 V to AVCC
4 mA
I. 100% production tested.
II. 100% production tested at 25°C, and guaranteed by design
and characterization at temperature extremes.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
−25°C to +85°C
150°C
300°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
The following measurements were taken on a 6-layer board in
still air with a solid ground plane.
Table 7. Thermal Resistance
Package Type
52-lead LQFP
ESD CAUTION
Rev. D | Page 7 of 24
θJA
33
θJC
11
Unit
°C/W
AD6644
D4
D5
GND
DVCC
D6
D7
D8
D9
D10
D11
D12
D13 (MSB)
DRY
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
52 51 50 49 48 47 46 45 44 43 42 41 40
DVCC 1
39 D3
PIN 1
IDENTIFIER
GND 2
38 D2
37 D1
3
GND 4
36 D0 (LSB)
ENCODE 5
ENCODE
35 DMID
AD6644
6
AVCC
8
AVCC
9
34 GND
TOP VIEW
(Not to Scale)
GND 7
33 DVCC
32 OVR
31 DNC
GND 10
30 AVCC
AIN 11
29 GND
AIN 12
28 AVCC
GND 13
27 GND
AVCC
GND
C2
GND
AVCC
GND
C1
GND
AVCC
GND
AVCC
GND
14 15 16 17 18 19 20 21 22 23 24 25 26
AVCC
DNC = DO NOT CONNECT
00971-003
VREF
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin Number
1, 33, 43
2, 4, 7, 10, 13, 15, 17, 19, 21, 23, 25, 27, 29,
34, 42
3
Mnemonic
DVCC
GND
Description
3.3 V Power Supply (Digital), Output Stage Only.
Ground.
VREF
5
6
8, 9, 14, 16, 18, 22, 26, 28, 30
11
12
20
ENCODE
ENCODE
AVCC
AIN
AIN
C1
24
C2
31
32
35
36
37 to 41, 44 to 50
DNC
OVR
DMID
D0 (LSB)
D1 to D5, D6 to
D12
D13 (MSB)
DRY
2.4 V (Analog Reference). Bypass to ground with 0.1 μF microwave chip
capacitor.
Encode Input. Conversion initiated on rising edge.
Complement of ENCODE. Differential input.
5 V Analog Power Supply.
Analog Input.
Complement of AIN. Differential analog input.
Internal Voltage Reference. Bypass to ground with 0.1 μF microwave chip
capacitor.
Internal Voltage Reference. Bypass to ground with 0.1 μF microwave chip
capacitor.
Do not connect this pin.
Overrange Bit. High indicates analog input exceeds ±FS.
Output Data Voltage Midpoint. Approximately equal to DVCC/2.
Digital Output Bit (Least Significant Bit). Twos complement.
Digital Output Bits in Twos Complement.
51
52
Digital Output Bit (Most Significant Bit). Twos complement.
Data Ready Output.
Rev. D | Page 8 of 24
AD6644
TYPICAL PERFORMANCE CHARACTERISTICS
0
75.0
ENCODE = 65MSPS
AIN = 2.2MHz @ –1dBFS
SNR = 74.5dB
SFDR = 92dBc
–10
–20
–30
T = –25°C
–40
74.0
SNR (dB)
–50
(dBFS)
ENCODE = 65MSPS, AIN = –1dBFS
TEMP = –25°C, +25°C, +85°C
74.5
–60
–70
–80
T = +85°C
73.5
T = +25°C
73.0
–90
–100
72.5
–110
0
5
10
15
20
FREQUENCY (MHz)
25
30
72.0
00971-004
–130
0
Figure 4. Single Tone at 2.2. MHz
–40
–50
(dBFS)
30
ENCODE = 65MSPS, AIN = –1dBFS
TEMP = –25°C, +25°C, +85°C
92
WORST-CASE HARMONIC (dBc)
–30
25
94
ENCODE = 65MSPS
AIN = 15.5MHz @ –1dBFS
SNR = 74dB
SFDR = 90dBc
–20
10
15
20
FREQUENCY (MHz)
Figure 7. Noise vs. Analog Frequency (Nyquist)
0
–10
5
00971-007
–120
–60
–70
–80
–90
–100
–110
90
T = +25°C
T = –25°C, +85°C
88
86
84
82
0
5
10
15
20
FREQUENCY (MHz)
25
30
80
00971-005
–130
0
10
15
20
25
ANALOG INPUT FREQUENCY (MHz)
30
Figure 8. Harmonics vs. Analog Frequency (Nyquist)
Figure 5. Single Tone at 15.5 MHz
0
75
ENCODE = 65MSPS
AIN = 30MHz @ –1dBFS
SNR = 73.5dB
SFDR = 85dBc
–10
–20
–30
LOW NOISE ANALOG SOURCE
74
73
–40
SNR (dB)
–50
–60
–70
–80
–90
72
PHASE NOISE OF ANALOG SOURCE
DEGRADES PERFORMANCE
71
70
–100
69
AIN = –1dBFS
ENCODE = 65MSPS
–120
–130
0
5
10
15
20
FREQUENCY (MHz)
25
30
68
Figure 6. Single Tone at 30 MHz
0
10
20
30
40
50
60
70
ANALOG FREQUENCY (MHz)
80
Figure 9. Noise vs. Analog Frequency (IF)
Rev. D | Page 9 of 24
90
100
00971-009
–110
00971-006
(dBFS)
5
00971-008
–120
AD6644
0
100
95
WORST OTHER SPUR
–20
90
–30
–40
85
–50
80
(dBFS)
HARMONICS (dBc)
ENCODE = 65MSPS
AIN = 15MHz,
15.5MHz @ –7dBFS
NO DITHER
–10
ENCODE = 65MSPS
AIN = –1dBFS
75
–60
–70
–80
70
–90
HARMONICS (SECOND, THIRD)
65
–100
–110
60
20
30
40
50
60
70
ANALOG FREQUENCY (MHz)
80
90
100
–130
0
Figure 10. Harmonics vs. Analog Frequency (IF)
10
110
WORST-CASE SPURIOUS (dBFS and dBc)
110
dBFS
100
ENCODE = 65MSPS
AIN = 15.5MHz
90
80
dBc
70
60
SFDR = 90dB
REFERENCE LINE
50
40
30
20
10
–70
–60
–50
–40
–30
–20
–10
ANALOG INPUT POWER LEVEL (dBFS)
0
ENCODE = 65MSPS
F1 = 15MHz
F2 = 15.5MHz
90
80
60
SFDR = 90dB
REFERENCE LINE
50
40
30
20
10
–67
–57
–47
–37
–27
–17
INPUT POWER LEVEL [(F1 = F2) dBFS]
SNR, WORST SPURIOUS (dB and dBc)
AIN = 2.2MHz @ –1dBFS
–60
–70
–80
–90
–100
–110
–120
25
30
95
Figure 12. Two Tones at 19 MHz and 19.5 MHz
WORST SPUR
90
85
80
75
SNR
70
65
60
00971-012
(dBFS)
–50
15
20
FREQUENCY (MHz)
–7
100
–40
10
dBc
Figure 14. Two-Tone SFDR
0
ENCODE = 65MSPS
–10 AIN = 19MHz,
19.5MHz @ –7dBFS
–20
NO DITHER
–30
5
30
70
Figure 11. Single-Tone SFDR
0
25
dBFS
100
0
–77
00971-011
0
–80
–130
15
20
FREQUENCY (MHz)
Figure 13. Two Tones at 15 MHz and 15.5 MHz
120
WORST-CASE SPURIOUS (dBFS and dBc)
5
00971-014
10
0
10
20
30
40
50
60
70
ENCODE FREQUENCY (MHz)
80
Figure 15. SNR, Worst Spurious vs. Encode
Rev. D | Page 10 of 24
90
00971-015
0
00971-013
–120
00971-010
55
AD6644
0
95
ENCODE = 65MSPS
AIN = 15.5MHz @ –29.5dBFS
NO DITHER
2.2MHz
–40
–60
–70
–80
–90
–100
–110
–120
0
5
10
15
20
FREQUENCY (MHz)
25
30
Figure 16. 1M FFT Without Dither
ENCODE = 65MSPS
85
30.5MHz
80
30.5MHz
70
10
15
ENCODE = 65MSPS
AIN = 15.5MHz @ –29.5dBFS
DITHER @ –19dBm
–10
–20
–30
–40
60
–50
(dBFS)
70
50
40
–60
–70
–80
SFDR = 90dB
REFERENCE LINE
30
–90
–100
20
–110
10
–120
–70
–60
–50
–40
–30
–20
–10
ANALOG INPUT POWER LEVEL (dBFS)
0
–130
0
5
Figure 17. SFDR Without Dither
10
15
20
FREQUENCY (MHz)
25
30
Figure 19. 1M FFT with Dither
100
90
WORST-CASE SPURIOUS (dBc)
–80
00971-017
WORST-CASE SPURIOUS (dBc)
–5
0
5
ENCODE INPUT POWER (dBm)
0
ENCODE = 65MSPS
AIN = 15.5MHz
NO DITHER
80
0
–90
–10
Figure 18. SNR, Worst Spurious vs. Clamped Encode Power (See Figure 27)
100
90
SNR
2.2MHz
75
65
–15
00971-016
–130
WORST SPUR
00971-019
(dBFS)
–50
90
00971-018
–30
80
ENCODE = 65MSPS
AIN = 15.5MHz
DITHER = –19dBm
70
60
50
SFDR = 100dB
REFERENCE LINE
40
30
SFDR = 90dB
REFERENCE LINE
20
10
0
–90
–80
–70
–60
–50
–40
–30
–20
–10
ANALOG INPUT POWER LEVEL (dBFS)
Figure 20. SFDR with Dither
Rev. D | Page 11 of 24
0
00971-020
–20
SNR, WORST SPURIOUS (dB and dBc)
–10
AD6644
EQUIVALENT CIRCUITS
VCH AVCC
AIN
BUF
TH
AVCC
500Ω
AVCC
VREF
BUF
VCH AVCC
2.4V
500Ω
VREF
BUF
TH
100µA
00971-021
AIN
VCL
00971-025
VCL
Figure 24. 2.4 V Reference
Figure 21. Analog Input Stage
LOADS
AVCC
AVCC
AVCC
AVCC
10kΩ
DVCC
10kΩ
10kΩ
ENCODE
ENCODE
10kΩ
10kΩ
LOADS
10kΩ
00971-026
00971-022
DMID
Figure 25. DMID Reference
Figure 22. ENCODE/ENCODE Inputs
AVCC
DVCC
CURRENT
MIRROR
VREF
AVCC
AVCC
DVCC
C1 OR C2
00971-023
CURRENT
MIRROR
VREF
D0 TO D13,
OVR, DRY
Figure 23. Compensation Pin, C1 or C2
00971-024
CURRENT
MIRROR
Figure 26. Digital Output Stage
Rev. D | Page 12 of 24
AD6644
TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180°
out of phase. Peak-to-peak differential is computed by rotating the
input phase 180° and taking the peak measurement again. The
difference is then computed between both peak measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Encode Pulse Width/Duty Cycle
Pulse width high is the minimum amount of time that the
ENCODE pulse should be left in the Logic 1 state to achieve
rated performance; pulse width low is the minimum time
ENCODE pulse should be left in a low state. Optimum
performance is achieved using a 50% duty cycle.
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
POWER Full Scale
⎡ V 2 Full − Scale rms ⎤
⎢
⎥
Z Input
⎢
⎥
= 10 log ⎢
⎥
0
.
001
⎢
⎥
⎢
⎥
⎣
⎦
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least-square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Noise (for Any Range Within the ADC)
VNOISE =
− SNRdBc − SignaldBFS ⎞
⎛ FS
Z × 0.001 × 10⎜ dBm
⎟
10
⎠
⎝
where:
Z is the input impedance.
FS is the full scale of the device for the frequency in question.
SNR is the value for the particular input level.
Signal is the signal level within the ADC reported in dB below
full scale.
VNOISE includes both thermal and quantization noise.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE, and the time when all output data bits are within
valid logic levels.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise and Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics, but excluding dc.
Signal-to-Noise Ratio (Without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral
components, excluding the first five harmonics and dc.
Rev. D | Page 13 of 24
AD6644
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of
the peak spurious spectral component. The peak spurious
component may or may not be a harmonic. Reported in
either dBc (that is, degrades as signal level is lowered), or
dBFS (always related back to converter full scale).
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. Reported in either dBc
(that is, degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third-order intermodulation product; reported in dBc.
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonics) reported in dBc.
Rev. D | Page 14 of 24
AD6644
THEORY OF OPERATION
Both analog inputs are buffered prior to the first track-and-hold,
TH1. The high state of the ENCODE pulse places TH1 in hold
mode. The held value of TH1 is applied to the input of a 5-bit
coarse ADC1. The digital output of ADC1 drives a 5-bit digitalto-analog converter (DAC1). DAC1 requires 14 bits of precision,
which is achieved through laser trimming. The output of DAC1
is subtracted from the delayed analog signal at the input of TH3
to generate a first residue signal. TH2 provides an analog
pipeline delay to compensate for the digital delay of ADC1.
APPLYING THE AD6644
Encoding the AD6644
The AD6644 encode signal must be a high quality, extremely
low phase noise source to prevent degradation of performance.
Maintaining 14-bit accuracy places a premium on encode clock
phase noise. SNR performance can easily degrade by 3 dB to
4 dB with 70 MHz input signals when using a high jitter clock
source. See the Analog Devices Application Note AN-501,
Aperture Uncertainty and ADC System Performance, for
complete details.
For optimum performance, the AD6644 must be clocked
differentially. The encode signal is usually ac-coupled into the
ENCODE and ENCODE pins via a transformer or capacitors.
These pins are biased internally and require no additional bias.
See Figure 27 for one preferred method for clocking the AD6644.
The clock source (low jitter) is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary windings of the transformer limit
clock excursions into the AD6644 to approximately 0.8 V p-p
differential. This helps prevent the large voltage swings of the
T1-4T
ENCODE
100Ω
AD6644
ENCODE
HSMS2812
DIODES
Figure 27. Crystal Clock Oscillator—Differential Encode
If a low jitter ECL/PECL clock is available, another option is to
ac-couple a differential ECL/PECL signal to the encode input
pins as shown in Figure 28. A device that offers excellent jitter
performance is the MC100LVEL16 (or another in the same
family) from Motorola.
VT
0.1µF
ECL/
PECL
ENCODE
AD6644
+
The digital outputs from ADC1, ADC2, and ADC3 are added
together and corrected in the digital error correction logic to
generate the final output data. The result is a 14-bit parallel
digital CMOS-compatible word, coded as twos complement.
0.1µF
+
The first residue signal is applied to a second conversion stage
consisting of a 5-bit ADC2, 5-bit DAC2, and pipeline TH4. The
second DAC requires 10 bits of precision, which is met by the
process with no trim. The input to TH5 is a second residue
signal generated by subtracting the quantized output of DAC2
from the first residue signal held by TH4. TH5 drives a final
6-bit ADC3.
CLOCK
SOURCE
00971-027
As shown in the functional block diagram, the AD6644 has
complementary analog input pins, AIN and AIN. Each analog
input is centered at 2.4 V and swings ±0.55 V around this
reference (Figure 21). Because AIN and AIN are 180° out of
phase, the differential analog input signal is 2.2 V peak-to-peak.
clock from feeding through to the other portions of the
AD6644, and limits the noise presented to the ENCODE inputs.
A crystal clock oscillator can also be used to drive the RF
transformer if an appropriate limiting resistor (typically 100 Ω)
is placed in series with the primary winding of the transformer.
ENCODE
0.1µF
VT
00971-028
The AD6644 analog-to-digital converter (ADC) employs a
three-stage subrange architecture. This design approach
achieves the required accuracy and speed while maintaining
low power and small die size.
Figure 28. Differential ECL for Encode
Analog Input
As with most new high speed, high dynamic range ADCs, the
analog input to the AD6644 is differential. Differential inputs
allow much improvement in performance on-chip as signals are
processed through the analog stages. Most of the improvement
is a result of differential analog stages having high rejection of
even-order harmonics. There are also benefits at the PCB level.
First, differential inputs have high common-mode rejection of
stray signals such as ground and power noise. In addition, they
provide good rejection of common-mode signals such as local
oscillator feedthrough.
The AD6644 input voltage range is offset from ground by 2.4 V.
Each analog input connects through a 500 Ω resistor to a 2.4 V
bias voltage and to the input of a differential buffer (Figure 21).
The resistor network on the input properly biases the followers
for maximum linearity and range. Therefore, the analog source
driving the AD6644 should be ac-coupled to the input pins.
Because the differential input impedance of the AD6644 is
1 kΩ, the analog input power requirement is only −2 dBm,
simplifying the driver amplifier in many cases. To take full
advantage of this high input impedance, a 20:1 transformer is
required. This is a large ratio and could result in unsatisfactory
performance. In this case, a lower step-up ratio can be used.
The recommended method for driving the analog input of the
AD6644 is to use a 4:1 RF transformer. For example, if RT is set
to 60.4 Ω and RS is set to 25 Ω, along with a 4:1 transformer, the
Rev. D | Page 15 of 24
AD6644
Digital Outputs
input matches to a 50 Ω source with a full-scale drive of
4.8 dBm. Series resistors (RS) on the secondary side of the
transformer should be used to isolate the transformer from the
ADC. This limits the amount of dynamic current from the
ADC flowing back into the secondary of the transformer. The
terminating resistor (RT) should be placed on the primary side
of the transformer.
AIN
RT
RS
+
AD6644
AIN
00971-029
RS
ADT4-1WT
ANALOG INPUT
SIGNAL
Care must be taken when designing the data receivers for the
AD6644. It is recommended that the digital outputs drive a
series resistor (for example, 100 Ω) followed by a gate like the
74LCX574. To minimize capacitive loading, there should only
be one gate on each output pin. An example of this is shown in
the evaluation board schematic of Figure 32. The digital outputs
of the AD6644 have a constant output slew rate of 1 V/ns.
0.1µF
Figure 29. Transformer-Coupled Analog Input Circuit
In applications where dc coupling is required, the AD8138
differential output op amp from Analog Devices can be used
to drive the AD6644 (see Figure 30). The AD8138 op amp
provides single-ended-to-differential conversion, which reduces
overall system cost and minimizes layout requirements.
CF
499Ω
5V
VIN
499Ω
VOCM
25Ω
AD8138
AD6644
25Ω
499Ω
If the analog input range is exceeded, the overrange (OVR) bit
toggles high and the digital outputs retain their respective
positive or negative full-scale values.
AIN
AIN
VREF
DIGITAL
OUTPUTS
Table 9. Twos Complement Output Coding
0.1µF
00971-030
499Ω
CF
A typical CMOS gate combined with a PCB trace have a load of
approximately 10 pF. Therefore, as each bit switches, 10 mA
(10 pF × 1 V ÷ 1 ns) of dynamic current per bit flow in or out
of the device. A full-scale transition can cause up to 140 mA
(14 bits × 10 mA/bit) of current to flow through the output
stages. The series resistors should be placed as close as possible
to the AD6644 to limit the amount of current that can flow into
the output stage. These switching currents are confined between
ground and the DVCC pin. Standard TTL gates should be avoided
because they can appreciably add to the dynamic switching
currents of the AD6644. Note that extra capacitive loading
increases output timing and invalidates timing specifications.
Digital output timing is guaranteed with 10 pF loads.
Figure 30. DC-Coupled Analog Input Circuit
AIN Level
AIN Level
Output State
Output Code
VREF + 0.55 V
VREF
VREF − 0.55 V
VREF − 0.55 V
VREF
VREF + 0.55 V
Positive FS
Midscale
Negative FS
01 1111 1111 1111
00…0/11…1
10 0000 0000 0000
Power Supplies
Layout Information
Care should be taken when selecting a power source. Linear
supplies are strongly recommended. Switching supplies tend to
have radiated components that may be received by the AD6644.
Each of the power supply pins should be decoupled as closely to
the package as possible using 0.1 μF chip capacitors.
The schematic of the evaluation board (see Figure 32) represents a
typical implementation of the AD6644. A multilayer board is
recommended to achieve the best results. It is highly recommended that high quality ceramic chip capacitors be used to
decouple each supply pin to ground directly at the device. The
pinout of the AD6644 facilitates ease of use in the implementation
of high frequency, high resolution design practices. All of the
digital outputs are segregated to two sides of the chip, with the
inputs on the opposite side for isolation purposes.
The AD6644 has separate digital and analog power supply pins.
The analog supplies are denoted AVCC and the digital supply
pins are denoted DVCC. AVCC and DVCC should have separate
power supplies. This is because the fast digital output swings
can couple switching current back into the analog supplies.
Note that AVCC must be held within 5% of 5 V. The AD6644 is
specified for DVCC = 3.3 V because this is a common supply for
digital ASICs.
Care should be taken when routing the digital output traces.
To prevent coupling through the digital outputs into the analog
portion of the AD6644, minimal capacitive loading should be
placed on these outputs. It is recommended that a fanout of
only one gate be used for all AD6644 digital outputs. The layout
of the encode circuit is equally critical. Any noise received on
this circuitry results in corruption in the digitization process
and lower overall performance. The encode clock must be
isolated from the digital outputs and the analog inputs.
Rev. D | Page 16 of 24
AD6644
Jitter Considerations
The signal-to-noise ratio (SNR) for an ADC can be predicted.
When normalized to ADC codes, Equation 1 accurately
predicts the SNR based on three terms. These are jitter, average
DNL error, and thermal noise. Each of these terms contributes
to the noise within the converter (see Equation 1).
⎞
⎟
⎟
⎠
2
+
80
2 1/ 2
⎤
⎥
⎥⎦
AIN = 30MHz
(1)
where:
fANALOG is the analog input frequency.
tj rms is the rms jitter of the encode (rms sum of encode source
and internal encode circuitry).
ε is the average DNL of the ADC (typically 0.41 LSB).
n is the number of bits in the ADC.
VNOISE rms is the V rms thermal noise referred to the analog input
of the ADC (typically 2.5 LSB).
AIN = 70MHz
75
SNR (dB)
⎛ VNOISE rms
⎜
⎜ 2n
⎝
)
For a complete review of aperture jitter, see Application Note
AN-756, Sampled Systems and the Effects of Clock Phase Noise
and Jitter, at www.analog.com.
70
AIN = 110MHz
65
AIN = 150MHz
60
AIN = 190MHz
55
0
0.1
0.2
0.3
JITTER (ps)
0.4
Figure 31. SNR vs. Jitter
Rev. D | Page 17 of 24
0.5
0.6
00971-031
(
⎡ 1+ ε
SNR = −20 × log ⎢⎛⎜ n ⎞⎟ + 2π × f ANALOG × t j rms
⎣⎝ 2 ⎠
2
For a 14-bit ADC like the AD6644, aperture jitter can greatly
affect the SNR performance as the analog frequency is
increased. Figure 31 shows a family of curves that demonstrates
the expected SNR performance of the AD6644 as jitter increases
and is derived from Equation 1.
AD6644
EVALUATION BOARD
The schematic of the evaluation board (see Figure 32) represents a typical implementation of the AD6644. A multilayer
board is recommended to achieve best results. It is highly
recommended that high quality, ceramic chip capacitors be
used to decouple each supply pin to ground directly at the
device. The pinout of the AD6644 facilitates ease of use in
the implementation of high frequency, high resolution design
practices. All of the digital outputs are segregated to two sides
of the chip, with the inputs on the opposite side for isolation
purposes.
Care should be taken when routing the digital output traces. To
prevent coupling through the digital outputs into the analog
portion of the AD6644, minimal capacitive loading should be
placed on these outputs. It is recommended that a fanout of
only one gate should be used for all AD6644 digital outputs.
The layout of the encode circuit is equally critical. Any noise
received on this circuitry results in corruption in the digitization
process and lower overall performance. The encode clock must be
isolated from the digital outputs and the analog inputs.
Table 10. AD6644/PCB Bill of Materials
Qty.
1
Reference ID 1
PCB
4
8
9
C1, C2, C31, C38
C3, C7 to C10, C16, C30 2 , C32
C4, C15, C22 to C26, C29, (C33) 3 ,
(C34)3, C39
(C5, C6)3
C11 to C14, C17 to 21, C40
(C27, 28)
CR13
E1
F1 to F5
J1-H
J1
J2
(J3), J4, J5
L1
(R1)3
(R2)
(R3 to R5)2, (R8)2, R9, R10
R6 and R7
(R11)3, (R13)3
(R12)3, (R14)3
R152
R35
RN1 to RN4
T23, T32
U1
U2, U7
(U3)2
U4, U6
(U8)3
Y1
Y1-PS
STDOFF
0
10
0
1
1
5
1
1
1
2
1
0
0
2
2
0
0
1
1
4
2
1
2
0
2
0
1
4
4
Description
Printed circuit board, AD6644/AD6645 engineering
evaluation board
Capacitor, tantalum, SMT BCAPTAJC, 10 μF, 16 V, 10%
Capacitor, ceramic, SMT 0508, 0.1 μF, 16 V, 10%
Capacitor, ceramic, SMT 0805, 0.1 μF, 25 V, 10%
Capacitor, ceramic, SMT 0805, 0.01 μF, 50 V, 10%
Capacitor, ceramic, SMT 0508, 0.01 μF, 50 V, 0.2%
Capacitor, ceramic, SMT 0805, select
Diode, dual Schottky HSMS2812, SOT-23, 30 V, 20 mA
Install jumper (across OPT_LAT and BUFLAT)
EMI suppression ferrite chip, SMT 0805
Header, 6-pin, pin strip, 5 mm pitch
Pin strip, 6-pin, 5 mm pitch
Header, 40-pin, male, right angle
Connector, gold, male, COAX., SMA, vertical
Inductor, SMT, 1008-ct package, 4.7 nH
Resistor, thick film, SMT 0402, 100 Ω, 1/16 W, 1%
Resistor, thick film, SMT 1206, 60.4 Ω, 1/8 W, 1%
Resistor, thick film, SMT 0805, 500 Ω, 1/10 W, 1%
Resistor, thick film, SMT 0805, 25.5 Ω, 1/10 W, 1%
Resistor, thick film, SMT 0805, 66.5 Ω, 1/10 W, 1%
Resistor, thick film, SMT 0805, 100 Ω, 1/10 W, 1%
Resistor, thick film, SMT 0402, 178 Ω, 1/16 W, 1%
Resistor, thick film, SMT 0805, 49.9 Ω, 1/10 W, 1%
Resistor array, SMT 0402; 100 Ω; 8 ISO RES.,1/4 W; 5%
Transformer, ADT4-1WT, CD542, 2 MHz to 775 MHz
IC, 14-bit, 65 MSPS ADC, LQFP-52
IC, SOIC-20, OCTAL D-type flip-flop
IC, SOIC-8, low distortion differential ADC driver
IC, SOT-23, tiny logic UHS 2-input or gate
IC, SOIC-8, differential receiver
Clock oscillator, 65 MHz
Pin sockets, closed end
Circuit board support
1
Manufacturer
Moog
Supplier Part No.
6645EE01D REV D
Kemet
Presidio Components
Panasonic
T491C106K016AS
0508X7R104K16VP3
ECJ-2VB1E104K
Panasonic
Presidio Components
ECJ-2YB1H103K
0508X7R103M2P3
Panasonic
MA716-(TX)
Steward
Wieland
Wieland
Samtec
Johnson Components™
Coilcraft®
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Mini-Circuits®
Analog Devices
Fairchild
Analog Devices
Fairchild
Motorola
CTS Reeves
AMP
RICHO
HZ0805E601R-00
Z5.530.0625.0
25.602.2653.0
TSW-120-08-T-D-RA
142-0701-201
1008CT-040X-J
ERJ-2RKF1000V
ERJ-8ENF60R4V
ERJ-6ENF4990V
ERJ-6ENF25R5V
ERJ-6ENF66R5V
ERJ-6ENF1000V
ERJ-2RKF1780X
ERJ-6ENF49R9V
EXB2HV101JV
ADT4-1WT
AD6644
74LCX574
AD8138ARM
NC7SZ32
MC100LVEL16
MX045-65
5-330808-3
CBSB-14-01
Reference designators in parentheses are not installed on standard units.
AC-coupled AIN is standard: R3, R4, R5, R8, and U3 are not installed. If dc-coupled AIN is required, C30, R15, and T3 are not installed.
3
AC-coupled encode is standard: C5, C6, C33, C34, R1, R11 to R14, and U8 are not installed. If PECL encode is required, CR1 and T2 are not installed.
2
Rev. D | Page 18 of 24
ENC
J5
J3
49.9
R35
AIN
(SEE NOTE 1)
DO NOT INSTALL
60.4
R2
DO NOT INSTALL
OPT_CLK
J4
C3
0.1U
C4
C5
0.01U
100
R1
0.1U
T2
OPTIONAL
VCC
OUT
14
L1
4.7NH
R10
500
8
10
12
6
5
4
7
0.1U
C29
5
6
U4
GND
3
R3
500
500
T3
V−
6
500
2
R5
C28
3
4
5
6
7
500
1
F5
F3
2
4
VAL
VREF
5
0.1U
C30
E1
178
R15
AIN
AIN
R14
100
R13
66.5
+3P3V
0.1U
C32
VREF
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
AIN
AIN
GND
AVCC
AVCC
GND
ENCODE
ENCODE
GND
VREF
GND
DVCC
U1
52
DR _OU T
14
51
50
15
16
48
47
46
45
44
17
AD6644/AD6645
49
18
19
0.1U
C8
20
21
22
43
23
42
0.1U
C7
24
41
25
40
GND
AVCC
GND
AVCC
DNC
OVR
DVCC
GND
DMID
D0
D1
D2
D3
26
27
28
29
30
31
32
33
34
35
36
37
38
39
+5VA
8
7
6
5
4
3
2
1
+5VA
10
7
J1
100
10
11
12
13
14
15
6
5
4
3
2
1
+3P3V
PREF
9
11
6
16
12
5
RN3
13
4
100
14
3
9
15
8
16
2
RN1
1
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
-5V
+5V
10U
C31
+3P3VIN
F1
F2
11
12
13
14
15
16
17
18
19
20
11
RN2
RN4
+3P3V
0.01U
C4 0
10U
C2
10U
0.1U
9
U6
10
11
12
13
14
15
1
0 .0 1 U
C18
0.01U
C11
0.1U
C23
NC7SZ32
4
10U
C38
0.01U
C17
2
E2
0.1U
C10
F4
GND
3
16
10
11
12
13
14
15
16
2
5
+V
+3P3VD
1
9
C39
0.1U
C16
0.1U
C9
BUFLAT 100
8
7
6
5
4
3
2
1
C1
+3P3VD
BUFLAT 100
8
12
5
15
7
4
16
6
3
17
13
2
14
1
18
+3P3VD
BUFLAT
19
20
+3P3V_XTL
3. AC-COUPLED ENCODE IS STANDARD. C5, C6, C33, C34, R1, R11−R14 AND U8 ARE NOT INSTALLED.
IF PECL ENCODE IS REQUIRED, CR1 AND T2 ARE NOT INSTALLED.
2. AC-COUPLED AIN IS STANDARD, R3, R4, R5, R8 AND U3 ARE NOT INSTALLED.
IF DC-COUPLED AIN IS REQUIRED, C30, R15 AND T3 ARE NOT INSTALLED.
Q7
Q6
Q5
Q4
Q3
Q2
Q1
+3P3VIN
74LCX574
GND
D7
D6
D5
D4
D3
D2
D1
Q0
VCC
CLOCK
U2
OUT_EN
D0
CLOCK
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
VCC
74LCX574
GND
D7
D6
D5
D4
D3
D2
D1
D0
OUT_EN
U7
1. R2 IS INSTALLED FOR INPUT MATCHING ON THE PRIMARY OF T3. R15 IS NOT INSTALLED.
R15 IS INSTALLED FOR INPUT MATCHING ON THE SECONDARY OF T3, R2 IS NOT INSTALLED.
NOTES:
+5VA
+5VA
(SEE NOTE 1)
R6
25.5
25.5
R7
+3P3V_XTL
2
+5VA
ENC
ENC
C34
0.1U
INSTALL JUMPER
C15
0.1U
BUFLAT
VOCM
AD8138ARM
U3
NC
V+
+5VA
8
1
-5V
R4
C27
1
C22
0.1U
2
CR1
OPT_LAT
3
C33
0.1U
DR_OUT
ADT4-1WT
4:1
IMPEDANCE RATIO
3
1
DO NOT INSTALL
R8
4
1
R12
100
R11
66.5
DC-COUPLED AIN OPTION
(SEE NOTE 2)
NC7SZ32
2
1
5
+V
+3P3VD
66.66MHz (AD6644)
80MHz (AD6645)
GN D
GND' OUT'
OE' VCC'
OE
Y1
+3P3V
7
R9
500
5
3
1
VEE
Q
Q
MC100LVEL16
VBB
D
D
VCC
ADT4-1WT
4:1
IMPEDANCE RATIO
1
3
4
3
2
NC
8
D13
U8
D12
GN D
1
+5VA
D11
GN D
+5VA
D9
GN D
DO NOT INSTALL
DC-COUPLED ENCODE OPTION (SEE NOTE 3)
D8
C1
+3P3V
DVC C
GN D
GN D
GN D
C2
+5VA
0.0
0.0
D7
GN D
DR Y
AVC C
+5V A
D10
AVC C
+5V A
AVC C
+5V A
D6
AVC C
+5V A
D5
GN D
D4
AVC C
Rev. D | Page 19 of 24
+5V A
Figure 32. Evaluation Board Schematic
B00
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
0.01U
C19
0.01U
C12
0.1U
C24
OVR
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
J2
0.01U
C20
+5VA
0.01U
C13
0.1U
C25
+3P3VD
E6
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
HEADER40
0 .0 1 U
C21
0.01U
C14
0.1U
C26
00971-032
C6
0.01U
AD6644
00971-035
00971-033
AD6644
Figure 35. Ground Plane Layer 2 and Ground Plane Layer 5
00971-034
00971-036
Figure 33. Top Signal Level
Figure 36. Bottom Signal Layer
Figure 34. 5.0 V Plane Layer 3 and 3.3 V Plane Layer 4
Rev. D | Page 20 of 24
AD6644
OUTLINE DIMENSIONS
0.75
0.60
0.45
12.20
12.00 SQ
11.80
1.60
MAX
52
40
39
1
PIN 1
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
0.15
0.05
SEATING
PLANE
VIEW A
0.20
0.09
7°
3.5°
0°
13
27
14
0.10
COPLANARITY
VIEW A
0.65
BSC
LEAD PITCH
26
0.38
0.32
0.22
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BCC
051706-A
1.45
1.40
1.35
Figure 37. 52-Lead Low Profile Quad Flat Package [LQFP]
(ST-52)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD6644AST-40
AD6644ASTZ-40 1
AD6644AST-65
AD6644ASTZ-651
AD6644ST/PCB
AD6644ST/PCBZ1
1
Temperature Range
−25°C to +85°C
−25°C to +85°C
−25°C to +85°C
−25°C to +85°C
Package Description
52-Lead Low Profile Quad Flat Package (LQFP)
52-Lead Low Profile Quad Flat Package (LQFP)
52-Lead Low Profile Quad Flat Package (LQFP)
52-Lead Low Profile Quad Flat Package (LQFP)
Evaluation Board with AD6644AST–65
Evaluation Board with AD6644AST–65
Z = RoHS Compliant Part.
Rev. D | Page 21 of 24
Package Option
ST-52
ST-52
ST-52
ST-52
AD6644
NOTES
Rev. D | Page 22 of 24
AD6644
NOTES
Rev. D | Page 23 of 24
AD6644
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00971-0-8/07(D)
Rev. D | Page 24 of 24