AD AD9430BSVZ-170 12-bit, 170/210 msps 3.3 v a/d converter Datasheet

12-Bit, 170/210 MSPS
3.3 V A/D Converter
AD9430
FUNCTIONAL BLOCK DIAGRAM
FEATURES
SENSE
VREF
AGND DRGND DRVDD AVDD
AD9430
SCALABLE
REFERENCE
VIN+
TRACKAND-HOLD
VIN–
ADC
12-BIT
PIPELINE
CORE
LVDS
OUTPUTS
12
CMOS
OUTPUTS
DS+
DS–
CLK+
SELECT CMOS
OR LVDS
CLOCK
MANAGEMENT
DCO–
S1
S2
S4
S5
Figure 1.
APPLICATIONS
The AD9430 is a 12-bit, monolithic, sampling analog-to-digital
converter (ADC) optimized for high performance, low power,
and ease of use. The product operates up to a 210 MSPS
conversion rate and is optimized for outstanding dynamic
performance in wideband carrier and broadband systems. All
necessary functions, including a track-and-hold (T/H) and
reference, are included on the chip to provide a complete
conversion solution.
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
Two output buses support demultiplexed data up to 105 MSPS
rates in CMOS mode. A data sync input is supported for proper
output data port alignment in CMOS mode, and a data clock
output is available for proper output data timing. In LVDS
mode, the chip provides data at the ENCODE clock rate.
Fabricated on an advanced BiCMOS process, the AD9430 is
available in a 100-lead, surface-mount plastic package
(100 e-PAD TQFP) specified over the industrial temperature
range (–40°C to +85°C).
DCO+
CLK–
GENERAL DESCRIPTION
The ADC requires a 3.3 V power supply and a differential
ENCODE clock for full performance operation. The digital
outputs are TTL/CMOS or LVDS compatible and support either
twos complement or offset binary format. Separate output
power supply pins support interfacing with 3.3 V CMOS logic.
DATA,
OVERRANGE
IN LVDS OR
2-PORT CMOS
02607-001
SNR = 65 dB @ fIN = 70 MHz @ 210 MSPS
ENOB of 10.6 @ fIN = 70 MHz @ 210 MSPS (–0.5 dBFS)
SFDR = 80 dBc @ fIN = 70 MHz @ 210 MSPS (–0.5 dBFS)
Excellent linearity:
DNL = ±0.3 LSB (typical)
INL = ±0.5 LSB (typical)
2 output data options:
Demultiplexed 3.3 V CMOS outputs each @ 105 MSPS
Interleaved or parallel data output option
LVDS at 210 MSPS
700 MHz full-power analog bandwidth
On-chip reference and track-and-hold
Power dissipation = 1.3 W typical @ 210 MSPS
1.5 V input voltage range
3.3 V supply operation
Output data format option
Data sync input and data clock output provided
Clock duty cycle stabilizer
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
High performance.
Maintains 65 dB SNR @ 210 MSPS with a 65 MHz input.
Low power.
Consumes only 1.3 W @ 210 MSPS.
Ease of use.
LVDS output data and output clock signal allow interface
to current FPGA technology. The on-chip reference and
sample-and-hold provide flexibility in system design. Use
of a single 3.3 V supply simplifies system power supply
design.
Out of range (OR) feature.
The OR output bit indicates when the input signal is
beyond the selected input range.
Pin compatible with 10-bit AD9411 (LVDS only).
.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2010 Analog Devices, Inc. All rights reserved.
AD9430
TABLE OF CONTENTS
DC Specifications ............................................................................. 4
Analog Inputs ............................................................................. 28
AC Specifications.............................................................................. 6
Gain.............................................................................................. 28
Digital Specifications........................................................................ 7
ENCODE..................................................................................... 28
Switching Specifications .................................................................. 8
Voltage Reference ....................................................................... 28
Timing Diagrams.............................................................................. 9
Data Format Select ..................................................................... 28
Absolute Maximum Ratings.......................................................... 10
I/P Timing Select........................................................................ 28
Explanation of Test Levels ......................................................... 10
Timing Controls ......................................................................... 28
ESD Caution................................................................................ 10
CMOS Data Outputs.................................................................. 29
Pin Configurations and Function Descriptions ......................... 11
Crystal Oscillator........................................................................ 29
Equivalent Circuits ......................................................................... 15
Optional Amplifier..................................................................... 29
Typical Performance Characteristics ........................................... 16
Troubleshooting.......................................................................... 30
Terminology .................................................................................... 23
Evaluation Board, LVDS Mode .................................................... 36
Application Notes ........................................................................... 25
Power Connector........................................................................ 36
Theory of Operation .................................................................. 25
Analog Inputs ............................................................................. 36
Encode Input............................................................................... 25
Gain.............................................................................................. 36
Analog Input ............................................................................... 26
Clock ............................................................................................ 36
DS Inputs (DS+, DS–)................................................................ 26
Voltage Reference ....................................................................... 36
CMOS Outputs ........................................................................... 26
Data Format Select ..................................................................... 36
LVDS Outputs............................................................................. 27
Data Outputs............................................................................... 36
Voltage Reference ....................................................................... 27
Crystal Oscillator........................................................................ 36
Noise Power Ratio Testing (NPR) ............................................ 27
Outline Dimensions ....................................................................... 42
Evaluation Board, CMOS Mode................................................... 28
Ordering Guide .......................................................................... 42
Power Connector........................................................................ 28
Rev. E | Page 2 of 44
AD9430
REVISION HISTORY
9/10—Rev. D to Rev. E
Change to General Description Section.........................................1
Change to Operating Temperature Range Parameter, Table 5..10
Change to Figure 4 ..........................................................................11
Change to Figure 5 ..........................................................................13
Added Exposed Pad Notation to Outline Dimensions ..............42
8/05—Rev. C to Rev. D
Change to IVREF Spec Units ...............................................................4
Changes to Minimum ENOB Specification...................................6
Added Footnote for Pin 33 in LVDS Mode ...................................7
Change to LVDS Output Section ..................................................27
Added New Evaluation Board, CMOS Mode Section................32
Updated Outline Dimensions........................................................42
11/04—Rev. B to Rev. C
Changes to Specifications ................................................................4
Changes to Figure 60 .................................................................... 31
Changes to LVDS PCB BOM ....................................................... 35
Changes to Figure 68 (Evaluation Board—LVDS Mode) ......... 36
Updated Outline Dimensions ...................................................... 40
7/03—Rev. A to Rev. B
Changed order of Figure 1 and Figure 2 ...................................... 5
Updated TPC 13 .............................................................................14
Changes to LVDS OUTPUTS section..........................................20
Add New AD9430 EVALUATION BOARD, LVDS MODE
Section ......................................................................................... 27
Updated OUTLINE DIMENSIONS ........................................... 32
3/03—Rev. 0 to Rev. A
Upgraded for AD9430-210 .............................................. Universal
Changes to FEATURES ................................................................. 1
Changes to PRODUCT HIGHLIGHTS ...................................... 1
Changes to SPECIFICATIONS ..................................................... 2
Changes to Figure 2 ........................................................................ 5
Changes to ORDERING GUIDE .................................................. 6
Change to PIN FUNCTION DESCRIPTIONS .......................... 7
Edits to Output Propagation Delay section. .............................. 10
Added TPCs 5–8, 10–12, 14, 16, 18, 20, 22, 27, 31–32, 34 ...... 12
Changes to TPCs............................................. 17, 19, 26, 35–36, 38
Added text to ENCODE INPUT section ................................... 18
Added DS INPUTS section ..........................................................19
Change to Table I ..........................................................................19
Changes to LVDS Outputs section.............................................. 20
Changes to Voltage Reference section .........................................20
Replaced Figure 12......................................................................... 20
Change to Troubleshooting section .............................................22
Updated OUTLINE DIMENSIONS.............................................27
5/02—Revision 0: Initial Version
Rev. E | Page 3 of 44
AD9430
DC SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, fIN = –0.5 dBFS, internal reference, full scale = 1.536 V, LVDS output mode,
unless otherwise noted.
Table 1.
AD9430-170
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
Reference Out (VREF)
REFERENCE
Reference Out (VREF)
Output Current 1
IVREF Input Current 2
ISENSE Input Current2
ANALOG INPUTS (VIN+, VIN–) 3
Differential Input Voltage Range
(S5 = GND)
Differential Input Voltage Range
(S5 = AVDD)
Input Common-Mode Voltage
Input Resistance
Input Capacitance
POWER SUPPLY (LVDS Mode)
AVDD
DRVDD
Supply Currents
IANALOG (AVDD = 3.3 V) 4
IDIGITAL (DRVDD = 3.3 V)4
Power Dissipation4
Power Supply Rejection
AD9430-210
Temp
Test
Level
Min
Full
25°C
25°C
25°C
Full
25°C
Full
VI
I
I
I
VI
I
VI
–3
–5
–1
–1
–1.5
–2.25
Full
Full
Full
V
V
V
25°C
25°C
25°C
25°C
I
IV
I
I
Full
V
1.536
1.536
V
Full
V
0.766
0.766
V
Full
Full
25°C
VI
VI
V
2.65
2.2
2.8
3
5
2.9
3.8
2.65
2.2
2.8
3
5
2.9
3.8
V
kΩ
pF
Full
Full
IV
IV
3.1
3.0
3.3
3.3
3.6
3.6
3.2
3.0
3.3
3.3
3.6
3.6
V
V
Full
Full
Full
25°C
VI
VI
VI
V
335
55
1.29
–7.5
372
62
1.43
390
55
1.5
–7.5
450
62
1.7
mA
mA
W
mV/V
Typ
12
Max
Min
+3
+5
+1
+1.5
+1.5
+2.25
–3
–5
–1
–1
–1.75
–2.5
Guaranteed
± 0.3
± 0.3
± 0.5
± 0.5
1.235
1.6
Rev. E | Page 4 of 44
Max
Unit
Bits
+3
+5
+1
+1.5
+1.75
+2.5
mV
% FS
LSB
LSB
LSB
LSB
Guaranteed
58
0.02
+0.12/–0.24
1.15
Typ
± 0.3
± 0.3
± 0.3
± 0.3
58
0.02
+0.12/–0.24
1.3
3.0
20
5.0
1.15
1.235
1.6
μV/°C
%/°C
mV/°C
1.3
3.0
20
5.0
V
mA
μA
mA
AD9430
AD9430-170
Parameter
POWER SUPPLY (CMOS Mode)
AVDD
DRVDD
Supply Currents
IAVDD (AVDD = 3.3 V) 5
IDRVDD (DRVDD = 3.3 V)5
Power Dissipation5
Power Supply Rejection
AD9430-210
Temp
Test
Level
Min
Typ
Max
Min
Typ
Max
Unit
Full
Full
IV
IV
3.1
3.0
3.3
3.3
3.6
3.6
3.2
3.0
3.3
3.3
3.6
3.6
V
V
Full
Full
Full
25°C
IV
IV
IV
V
335
24
1.1
–7.5
372
30
390
30
1.3
–7.5
450
30
mA
mA
W
mV/V
1
Internal reference mode; SENSE = Floats.
External reference mode; SENSE = DRVDD, VREF driven by external 1.23 V reference.
S5 (Pin 1) = GND. See the Analog Input section. S5 = GND in all dc and ac tests, unless otherwise noted.
4
IAVDD and IDRVDD are measured with an analog input of 10.3 MHz, –0.5 dBFS, sine wave, rated ENCODE rate, and in LVDS output mode. See Typical Performance
Characteristics and Application Notes sections for IDRVDD. Power consumption is measured with a dc input at rated ENCODE rate in LVDS output mode.
5
IAVDD and IDRVDD are measured with an analog input of 10.3 MHz, –0.5 dBFS, sine wave, rated ENCODE rate, and in CMOS output mode. See Typical Performance
Characteristics and Application Notes sections for IDRVDD. Power consumption is measured with a dc input at rated ENCODE rate in CMOS output mode.
2
3
Rev. E | Page 5 of 44
AD9430
AC SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, fIN = –0.5 dBFS, internal reference, full scale = 1.536 V, LVDS output mode,
unless otherwise noted. 1
Table 2.
Parameter
SNR
Analog Input @ –0.5 dBFS
SINAD
Analog Input @ –0.5 dBFS
AD9430-170
Typ
Max
Min
AD9430-210
Typ
Max
Temp
Test Level
Min
Unit
10 MHz
70 MHz
100 MHz
240 MHz
25°C
25°C
25°C
25°C
I
I
V
V
63.5
63
65
65
65
61
62.5
62.5
64.5
64.5
64.5
61
dB
dB
dB
dB
10 MHz
70 MHz
100 MHz
240 MHz
25°C
25°C
25°C
25°C
I
I
V
V
63.5
63
65
65
65
60
62.5
62.5
64.5
64.5
64.5
60
dB
dB
dB
dB
10 MHz
70 MHz
100 MHz
240 MHz
25°C
25°C
25°C
25°C
I
I
V
V
10.3
10.3
10.6
10.6
10.6
9.8
10.2
10.2
10.5
10.5
10.5
9.8
Bits
Bits
Bits
Bits
10 MHz
70 MHz
100 MHz
240 MHz
25°C
25°C
25°C
25°C
I
I
V
V
–85
–85
–77
–63
–75
–75
–84
–84
–77
–63
–74
–74
dBc
dBc
dBc
dBc
10 MHz
70 MHz
100 MHz
240 MHz
25°C
25°C
25°C
25°C
I
I
V
V
–87
–87
–77
–63
–78
–78
–87
–87
–77
–63
–77
–77
dBc
dBc
dBc
dBc
25°C
25°C
V
V
–75
700
EFFECTIVE NUMBER OF BITS (ENOB)
WORST HARMONIC (2nd or 3rd)
Analog Input @ –0.5 dBFS, 10 MHz
WORST HARMONIC (4th or Higher)
Analog Input @ –0.5 dBFS, 10 MHz
TWO-TONE IMD 2
F1, F2 @ −7 dBFS
ANALOG INPUT BANDWIDTH
D
1
2
All ac specifications tested by differentially driving CLK+ and CLK−.
F1 = 28.3 MHz, F2 = 29.3 MHz.
Rev. E | Page 6 of 44
–75
700
dBc
MHz
AD9430
DIGITAL SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.
Table 3.
Parameter
ENCODE AND DS INPUTS
(CLK+, CLK–, DS+, DS–) 1
Differential Input Voltage 2
Common-Mode Voltage 3
Input Resistance
Input Capacitance
LOGIC INPUTS (S1, S2, S4, S5)
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Input Current
Logic 0 Input Current
Input Resistance
Input Capacitance
LOGIC OUTPUTS (CMOS Mode)
Logic 1 Voltage 4
Temp
Test
Level
Full
Full
Full
25°C
IV
VI
VI
V
0.2
1.375
3.2
Full
Full
Full
Full
25°C
25°C
IV
IV
VI
VI
V
V
2.0
Full
IV
DRVDD
–0.05
Logic 0 Voltage4
LOGIC OUTPUTS (LVDS Mode)4, 5
VOD Differential Output Voltage
VOS Output Offset Voltage
Output Coding
Full
IV
Full
Full
VI
VI
Min
AD9430-170
Typ
Max
1.5
5.5
4
1.575
6.5
Min
0.2
1.375
3.2
AD9430-210
Typ
Max
1.5
5.5
4
1.575
6.5
2.0
0.8
190
10
0.8
190
10
30
4
30
4
DRVDD
–0.05
0.05
247
454
1.125
1.375
Twos complement or binary
1
ENCODE (Clock) and DS inputs identical on the chip. See the Equivalent Circuits section.
All ac specifications tested by driving CLK+ and CLK– differentially, |(CLK+) – (CLK–)| > 200 mV.
3
ENCODE (Clock) inputs’ common-mode can be externally set, such that 0.9 V < (CLK+ or CLK−) < 2.6 V.
4
Digital output logic levels: DRVDD = 3.3 V, CLOAD = 5 pF.
5
LVDS RTERM = 100 Ω, LVDS output current set resistor (RSET) = 3.74 kΩ (1% tolerance).
2
Rev. E | Page 7 of 44
Unit
V
V
kΩ
pF
V
V
μA
μA
kΩ
pF
V
0.05
247
454
1.125
1.375
Twos complement or binary
V
mV
V
AD9430
SWITCHING SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.
Table 4.
Parameter (Conditions)
Maximum Conversion Rate 1
Minimum Conversion Rate1
CLK+ Pulse Width High (tEH)1
CLK+ Pulse Width Low (tEL)1
DS Input Setup Time (tSDS) 2
DS Input Hold Time (tHDS)2
OUTPUT (CMOS Mode)
Valid Time (tV)
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
DCO Propagation Delay (tCPD)
Data to DCO Skew (tPD to tCPD)
Interleaved Mode (A, B Latency)
Parallel Mode (A, B Latency)
OUTPUT (LVDS Mode)
Valid Time (tV)
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
DCO Propagation Delay (tCPD)
Data to DCO Skew (tPD – tCPD)
Latency
APERTURE DELAY (tA)
APERTURE UNCERTAINTY (Jitter, tJ)
OUT OF RANGE RECOVERY TIME (CMOS and LVDS)
1
2
Temp
Full
Full
Full
Full
Full
Full
Test
Level
VI
V
IV
IV
IV
IV
Full
Full
25°C
25°C
Full
Full
Full
Full
IV
IV
V
V
IV
IV
IV
IV
Full
Full
25°C
25°C
Full
Full
Full
25°C
25°C
25°C
VI
VI
V
V
VI
IV
IV
V
V
V
Min
170
AD9430-170
Typ
Max
40
12.5
12.5
2
2
–0.5
1.75
2
–0.5
All ac specifications tested by differentially driving CLK+ and CLK−.
DS inputs used in CMOS mode only.
Rev. E | Page 8 of 44
AD9430-210
Typ
Max
40
12.5
12.5
2
2
–0.5
1.75
2
3.8
1
1
3.8
0
14, 14
15, 14
5
5
+0.5
2.0
1.8
0.2
Min
210
–0.5
3.8
1
1
3.8
0
14, 14
15, 14
5
3.2
0.5
0.5
2.7
0.5
14
1.2
0.25
4.3
5
+0.5
2.0
3.2
0.5
0.5
2.7
0.5
14
1.2
0.25
4.3
3.8
0.8
1
1.8
0.2
3.8
0.8
1
Unit
MSPS
MSPS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
Cycles
ns
ns
ns
ns
ns
ns
Cycles
ns
ps rms
Cycles
AD9430
TIMING DIAGRAMS
CLK+
CLK–
DS+
DS–
tSDS
tHDS
PORT A
DA11–DA0
STATIC
PORT B
DB11–DB0
STATIC
tPD
14 CYCLES
INTERLEAVED DATA OUT
INVALID
tV
N
N+2
INVALID
INVALID
N+1
N+3
PARALLEL DATA OUT
PORT A
DA11–DA0
STATIC
INVALID
INVALID
N
N+2
PORT B
DB11–DB0
STATIC
INVALID
INVALID
N+1
N+3
tCPD
02607-002
DCO–
STATIC
DCO+
Figure 2. CMOS Timing Diagram
N–1
N
N+1
AIN
tEL
tEH
1/fS
CLK+
CLK–
tPD
N–14
DATA OUT
N–13
N
N+1
14 CYCLES
02607-003
DCO+
DCO–
tCPD
Figure 3. LVDS Timing Diagram
Rev. E | Page 9 of 44
AD9430
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational section
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 5.
Parameter
AVDD, DRVDD
Analog Inputs
Digital Inputs
REFIN Inputs
Digital Output Current
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Maximum Case Temperature
θJA 1
1
Rating
4V
−0.5 V to AVDD + 0.5 V
−0.5 V to DRVDD + 0.5 V
–0.5 V to AVDD + 0.5 V
20 mA
−40°C to +85°C
−65°C to +150°C
150°C
150°C
25°C/W, 32°C/W
EXPLANATION OF TEST LEVELS
Table 6.
Level
I
II
Typical θJA = 32°C/W (heat slug not soldered); typical θJA = 25°C/W (heat slug
soldered) for multilayer board in still air with solid ground plane.
III
IV
V
VI
Description
100% production tested.
100% production tested at 25°C and sample tested at
specified temperatures.
Sample tested only.
Parameter is guaranteed by design and
characterization testing.
Parameter is a typical value only.
100% production tested at 25°C; guaranteed by
design and characterization testing for industrial
temperature range; 100% production tested at
temperature extremes for military devices.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. E | Page 10 of 44
AD9430
DA5
DA6
DA7
DA8
DA9
DA10
DRGND
DRVDD
DA11
OR_A
AGND
AGND
AVDD
AVDD
AVDD
AGND
AGND
AGND
AVDD
AVDD
AGND
AGND
AVDD
AVDD
AGND
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
DRVDD
74
DRGND
3
73
DA4
AGND 4
72
DA3
S2
5
71
DA2
S1
6
70
DA1
DNC
7
69
DA0
AVDD 8
68
DNC
67
DRGND
66
DNC
65
DNC
64
DCO+
AGND 13
63
DCO–
AVDD 14
62
DRVDD
AVDD 15
61
DRGND
AGND 16
60
OR_B
AGND 17
59
DB11
AVDD 18
58
DB10
AVDD 19
57
DB9
AGND 20
56
DB8
VIN+ 21
55
DB7
VIN– 22
54
DRVDD
AGND 23
53
DRGND
AVDD 24
52
DB6
AGND 25
51
DB5
S5
1
DNC
2
S4
PIN 1
AD9430
AGND 9
SENSE 10
CMOS PINOUT
TOP VIEW
(Not to Scale)
VREF 11
AGND 12
NOTES
1. THE AD9430 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE
DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
02607-004
DB4
DB3
DRGND
DRVDD
DB2
DB1
DB0
DNC
DNC
AGND
AVDD
AVDD
AGND
CLK–
CLK+
AGND
AVDD
DS–
DS+
AGND
AGND
AVDD
AVDD
AVDD
AGND
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Figure 4. CMOS Dual-Mode Pin Configuration
Table 7. CMOS Mode Pin Function Descriptions
Pin Number
1
Mnemonic
S5
2, 7, 42, 43, 65, 66, 68
3
4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 35, 38, 41, 86,
87, 91, 92, 93, 96, 97, 100
5
6
DNC
S4
AGND1
8, 14, 15, 18, 19, 24, 27, 28, 29, 34, 39, 40, 88, 89, 90, 94,
95, 98, 99
10
11
21
22
32
33
AVDD
Output Mode Select. Low = dual-port CMOS, high = LVDS.
Data Format Select. Low = binary, high = twos complement for
both CMOS and LVDS modes.
3.3 V Analog Supply.
SENSE
VREF
VIN+
VIN–
DS+
DS–2
Reference Mode Select Pin. Float for internal reference operation.
1.235 V Reference I/O—Function Dependent on SENSE.
Analog Input—True.
Analog Input—Complement.
Data Sync (Input)—True. Tie low if not used.
Data Sync (Input)—Complement. Tie high if not used.
S2
S1
Description
Full-Scale Adjust Pin. AVDD sets fS = 0.768 V p-p differential,
GND sets fS = 1.536 V p-p differential.
Do Not Connect.
Interleaved, Parallel Select Pin. High = interleaved.
Analog Ground.
Rev. E | Page 11 of 44
AD9430
Pin Number
36
37
44
45
46
47, 54, 62, 75, 83
48, 53, 61, 67, 74, 82
49
50
51
52
55
56
57
58
59
60
63
64
69
70
71
72
73
76
77
78
79
80
81
84
85
1
2
Mnemonic
CLK+
CLK–
DB0
DB1
DB2
DRVDD
DRGND1
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
OR_B
DCO–
DCO+
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
OR_A
Description
Clock Input—True.
Clock Input—Complement.
B Port Output Data Bit (LSB).
B Port Output Data Bit.
B Port Output Data Bit.
3.3 V Digital Output Supply (3.0 V to 3.6 V).
Digital Output Ground.
B Port Output Data Bit.
B Port Output Data Bit.
B Port Output Data Bit.
B Port Output Data Bit.
B Port Output Data Bit.
B Port Output Data Bit.
B Port Output Data Bit.
B Port Output Data Bit.
B Port Output Data Bit (MSB).
B Port Overrange.
Data Clock Output—Complement.
Data Clock Output—True.
A Port Output Data Bit (LSB).
A Port Output Data Bit.
A Port Output Data Bit.
A Port Output Data Bit.
A Port Output Data Bit.
A Port Output Data Bit.
A Port Output Data Bit.
A Port Output Data Bit.
A Port Output Data Bit.
A Port Output Data Bit.
A Port Output Data Bit.
A Port Output Data Bit (MSB).
A Port Overrange.
AGND and DRGND should be tied together to a common ground plane.
DS Complement (DS−); can be tied to AVDD (as recommended) or left floating with no ill effects.
Rev. E | Page 12 of 44
D9–
D9+
D10–
D10+
D11–
D11+
DRGND
DRVDD
OR–
OR+
AGND
AGND
AVDD
AVDD
AVDD
AGND
AGND
AGND
AVDD
AVDD
AGND
AGND
AVDD
AVDD
AGND
AD9430
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
DRVDD
74
DRGND
3
73
D8+
AGND 4
72
D8–
S2
5
71
D7+
S1
6
70
D7–
LVDSBIAS
7
69
D6+
AVDD
8
68
D6–
67
DRGND
66
D5+
65
D5–
64
DCO+
AGND 13
63
DCO–
AVDD 14
62
DRVDD
AVDD 15
61
DRGND
AGND 16
60
D4+
AGND 17
59
D4–
AVDD 18
58
D3+
AVDD 19
57
D3–
AGND 20
56
D2+
VIN+ 21
55
D2Ð
VIN– 22
54
DRVDD
AGND 23
53
DRGND
AVDD 24
52
D1+
AGND 25
51
D1–
S5
1
DNC
2
S4
PIN 1
AD9430
AGND 9
SENSE 10
LVDS PINOUT
TOP VIEW
(Not to Scale)
VREF 11
AGND 12
NOTES
1. THE AD9430 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE
DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
02607-005
D0+
D0–
DRGND
DRVDD
DNC
DNC
DNC
DNC
DNC
AGND
AVDD
AVDD
AGND
CLK–
CLK+
AGND
AVDD
AVDD
GND
AGND
AGND
AVDD
AVDD
AVDD
AGND
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Figure 5. LVDS Mode Pin Configuration
Table 8. LVDS Mode Pin Function Descriptions
Pin Number
1
Mnemonic
S5
2, 42 to 46
3
DNC
S4
4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 35, 38, 41, 86, 87, 91,
92, 93, 96, 97, 100
5
6
7
AGND1
8, 14, 15, 18, 19, 24, 27, 28, 29, 33, 34, 39, 40, 88, 89, 90, 94, 95,
98, 99
10
AVDD2
11
21
VREF
VIN+
S2
S1
LVDSBIAS
SENSE
Description
Full-Scale Adjust Pin. AVDD sets fS = 0.768 V p-p differential,
GND sets fS = 1.536 V p-p differential.
Do Not Connect.
Control Pin for CMOS Mode. Tie low when operating in LVDS
mode.
Analog Ground.
Output Mode Select. GND = dual-port CMOS; AVDD = LVDS.
Data Format Select. GND = binary, AVDD = twos complement.
Set Pin for LVDS Output Current. Place 3.74 kW resistor
terminated to ground.
3.3 V Analog Supply.
Reference Mode Select Pin. Float for internal reference
operation.
1.235 V Reference I/O—Function Dependent on SENSE.
Analog Input—True.
Rev. E | Page 13 of 44
AD9430
Pin Number
22
32
36
37
47, 54, 62, 75, 83
48, 53, 61, 67, 74, 82
49
50
51
52
55
56
57
58
59
60
63
64
65
66
68
69
70
71
72
73
76
77
78
79
80
81
84
85
1
2
Mnemonic
VIN–
GND
CLK+
CLK–
DRVDD
DRGND1
D0–
D0+
D1–
D1+
D2–
D2+
D3–
D3+
D4–
D4+
DCO–
DCO+
D5–
D5+
D6–
D6+
D7–
D7+
D8–
D8+
D9–
D9+
D10–
D10+
D11–
D11+
OR–
OR+
Description
Analog Input—Complement.
Data Sync (Input)—Not Used in LVDS Mode. Tie to GND.
Clock Input—True (LVPECL Levels).
Clock Input—Complement (LVPECL Levels).
3.3 V Digital Output Supply (3.0 V to 3.6 V).
Digital Output Ground.
D0 Complement Output Bit (LSB).
D0 True Output Bit (LSB).
D1 Complement Output Bit.
D1 True Output Bit.
D2 Complement Output Bit.
D2 True Output Bit.
D3 Complement Output Bit.
D3 True Output Bit.
D4 Complement Output Bit.
D4 True Output Bit.
Data Clock Output—Complement.
Data Clock Output—True.
D5 Complement Output Bit.
D5 True Output Bit.
D6 Complement Output Bit.
D6 True Output Bit.
D7 Complement Output Bit.
D7 True Output Bit.
D8 Complement Output Bit.
D8 True Output Bit.
D9 Complement Output Bit.
D9 True Output Bit.
D10 Complement Output Bit.
D10 True Output Bit.
D11 Complement Output Bit.
D11 True Output Bit.
Overrange Complement Output Bit.
Overrange True Output Bit.
AGND and DRGND should be tied together to a common ground plane.
Pin 33 can be tied to AVDD (as recommended) or left floating with no ill effects
Rev. E | Page 14 of 44
AD9430
EQUIVALENT CIRCUITS
FULL
SCALE
K
AVDD
S5 = 0 —> K = 1.24
S5 = 1 —> K = 0.62
12kΩ
CLK+
OR
DS+
150Ω
0.1μF
VREF
12kΩ
– +
CLK–
OR
DS–
150Ω
A1
1V
200Ω
10kΩ
SENSE
1kΩ
DISABLE
A1
VDD
02607-009
02607-080
10kΩ
Figure 6. ENCODE and DS Input
Figure 9. VREF, SENSE I/O
AVDD
DRVDD
3.5kΩ
3.5kΩ
DX
VIN–
VIN+
02607-007
20kΩ
Figure 7. Analog Inputs
02607-010
20kΩ
Figure 10. Data Outputs (CMOS Mode)
DRVDD
VDD
S1, S2,
S4, S5
V
V
DX–
DX+
V
V
02607-008
02607-011
30kΩ
Figure 8. S1 to S5 Inputs
Figure 11. Data Outputs (LVDS Mode)
Rev. E | Page 15 of 44
AD9430
TYPICAL PERFORMANCE CHARACTERISTICS
Charts at 170 MSPS, 210 MSPS for –170, –210 grades, respectively. AVDD, DRVDD = 3.3 V, T = 25°C, AIN differential drive, full
scale = 1.536 V, internal reference unless otherwise noted.
0
0
SNR = 65.2dB
SINAD = 65.1dB
H2 = –88.8dBc
H3 = –88.1dBc
SFDR = 87dBc
–20
–30
–20
–30
dB
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–100
–100
10
20
30
40
MHz
50
60
70
80 85
02607-012
–90
0
Figure 12. FFT: fs = 170 MSPS, AIN = 10.3 MHz @ −0.5 dBFS, LVDS Mode
30
40
MHz
50
60
80 85
70
0
SNR = 65.1dB
SINAD = 64.9dB
FUND = –0.50dBFS
H2 = –88.6dBc
H3 = –94.6dBc
SFDR = 85.9dBc
–10
–20
–30
SNR = 63.6dB
SINAD = 62.9dB
H2 = –82.5dBc
H3 = –78.6dBc
SFDR = 77.7dBc
–10
–20
–30
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
0
10
20
30
40
MHz
50
60
70
80 85
–100
02607-013
–100
Figure 13. FFT: fs = 170 MSPS, AIN = 65 MHz @ –0.5 dBFS, LVDS Mode
0
15
30
45
60
75
90
105
MHz
02607-016
dB
–40
dB
20
Figure 15. FFT: fs = 170 MSPS, AIN = 10.3 MHz @ –0.5 dBFS,
Single-Ended Input, Full Scale = 0.76 V, LVDS Mode
0
Figure 16. FFT: fs = 210 MSPS, AIN = 10.3 MHZ @ –0.5 dBFS, LVDS Mode
0
0
SNR = 64.93dB
SINAD = 64.85dB
FUND = –0.44dBFS
H2 = –92.1dBc
H3 = –90.1dBc
SFDR = 75.6dBc
–10
–20
–30
SNR = 63.1dB
SINAD = 62.8dB
H2 = –81.1dBc
H3 = –76dBc
SFDR = –76dBc
–10
–20
–30
–40
dB
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
0
10
20
30
40
MHz
50
60
70
80 85
–100
02607-015
dB
10
Figure 14. FFT: fs = 170 MSPS, AIN = 65 MHz @ –0.5 dBFS, CMOS Mode
0
15
30
45
60
MHz
75
90
105
02607-017
dB
–40
0
SNR = 62.99dBFS
SINAD = 61.45dBFS
H2 = –66.8dBc
H3 = –82.5dBc
SFDR = 66.1dBc
–10
02607-015
–10
Figure 17. FFT: fs = 210 MSPS, AIN = 65 MHz @ –0.5 dBFS, CMOS Mode
Rev. E | Page 16 of 44
AD9430
0
0
SNR = 63.5dB
SINAD = 62.6dB
H2 = –79dBc
H3 = –76.1dBc
SFDR = 75.2dBc
–20
–30
–30
–40
–40
dB
dB
–20
–50
–50
–60
–60
–70
–70
–80
–80
–90
–100
15
30
45
60
75
90
105
MHz
02607-018
–90
–100
0
SNR = 63.3dB
SINAD = 63.1dB
H2 = –80.38dBc
H3 = –81.8dBc
SFDR = 80.8dBc
–10
Figure 18. FFT: fs = 210 MSPS, AIN = 65 MHz @ –0.5 dBFS, LVDS Mode
0
15
30
45
60
75
90
105
MHz
02607-021
–10
Figure 21. FFT: fs = 213 MSP, AIN = 100 MHz @ –0.5 dBFS, LVDS Mode
85
85
80
80
SFDR
75
75
70
70
65
65
dB
dB
SNR
SNR
60
60
55
55
SINAD
SINAD
FULL SCALE = 0.75
50
45
45
0
50
100
150
200
250
300
350
400
AIN (MHz)
40
02607-019
40
0
50
100
150
200
250
300
350
400
AIN (MHz)
Figure 19. SNR, SINAD, and SFDR vs. AIN Frequency, fS = 210 MSPS,
AIN @ –0.5 dBFS, LVDS Mode
02607-022
FULL SCALE = 1.5
50
Figure 22. SNR and SINAD vs. AIN Frequency, fs = 210 MSPS,
AIN @ –0.5 dBFS, LVDS Mode, Full Scale = 0.76 V
100
100
THIRD
90
90
80
80
THIRD
70
60
60
50
50
40
50
100
150
200
250
AIN (MHz)
300
350
400
40
0
50
100
150
200
250
AIN (MHz)
300
350
Figure 23. Harmonic Distortion (2nd and 3rd) and
SFDR vs. AIN Frequency, fs = 170 MSPS, CMOS Mode
Figure 20. Harmonic Distortion (2nd and 3rd)
and SFDR vs. AIN Frequency
Rev. E | Page 17 of 44
400
02607-023
dB
SFDR
70
0
SECOND
SECOND
02607-020
dB
SFDR
AD9430
70
0
68
66
–170 SNR
–30
64
62
dB
dB
–210 SNR
60
–60
SFDR = 63dBc
58
–210 SINAD
56
–90
–170 SINAD
54
02607-024
52
0
50
100
150
200
250
AIN (MHz)
300
350
400
Figure 24. SNR and SINAD vs. AIN Frequency, fs = 170 MSPS/210 MSPS,
AIN @ –0.5 dBFS, LVDS Mode
–120
0
10
20
30
40
50
60
MHz
70
80
90
100
02607-027
50
Figure 27. Two-Tone Intermodulation Distortion (59 MHz and 60 MHz),
LVDS Mode, fs = 210 MSPS
85
95
80
90
75
85
SFDR
70
SFDR
80
65
75
dB
dB
SNR
60
70
55
65
SINAD
SINAD
50
60
45
0
50
100
150
200
250
300
350
400
AIN (MHz)
50
02607-025
40
0
50
100
150
200
250
MHz
02607-028
55
Figure 28. SINAD and SFDR vs. Clock Rate
(AIN = 10.3 MHz @ –0.5 dBFS, LVDS Mode), –170 Grade
Figure 25. SNR and SINAD, SFDR vs. AIN Frequency,
fs = 210 MSPS, AIN @ –0.5 dBFS, CMOS Mode
85
0
SFDR = 75dBc
–10
80
–20
75
70
–40
SNR
65
dB
dB
–30
SFDR
–50
SINAD
60
–60
55
–70
50
–80
0
10
20
30
40
50
MHz
60
70
80 85
02607-026
–100
40
0
50
100
150
200
MHz
Figure 26. Two-Tone Intermodulation Distortion
(28.3 MHz and 29.3 MHz, LVDS Mode, fs = 170 MSPS)
Figure 29. SNR and SINAD, SFDR vs. Clock Rate
(AIN = 10.3 MHz, @ –0.5 dBFS), LVDS Mode, –210 Grade
Rev. E | Page 18 of 44
250
02607-029
45
–90
AD9430
80
OUTPUT SUPPLY
CURRENT LVDS
MODE
200
40
150
100
20
OUTPUT SUPPLY
CURRENT CMOS
MODE
50
0
100
120
140
160
180
ENCODE (MSPS)
0
220
200
70
SINAD
55
50
20
60
250
50
OUTPUT SUPPLY
CURRENT LVDS MODE
200
40
150
30
OUTPUT SUPPLY
CURRENT CMOS MODE
100
20
50
10
0
100
0
120
140
160
180
200
220
60
70
80
1.2
RO = 13Ω TYP
1.0
VREFOUT (V)
300
70
50
1.4
IDRVDD (OUTPUT SUPPLY CURRENT) (mA)
ANALOG SUPPLY
CURRENT CMOS MODE
40
Figure 33. SNR, SINAD, and SFDR vs. ENCODE Pulse Width High,
(AIN = 10.3 MHz @ –0.5 dBFS, 210 MSPS, LVDS)
240
0.8
0.6
0.4
0.2
02607-031
80
350
0
0
1
2
ENCODE (MSPS)
3
5
4
6
7
8
ILOAD (mA)
Figure 34. VREFOUT vs. ILOAD
Figure 31. IAVDD and IDRVDD vs. Clock Rate
(AIN = 10.3 MHz @ –0.5 dBFS), 210 MSPS Grade, CLOAD = 5 pF
85
2.0
1.5
80
SFDR
1.0
GAIN ERROR (%)
75
70
dB
SNR
65
SINAD
60
0.5
% GAIN ERROR
USING EXT REF
0
–0.5
–1.0
55
50
10
20
30
40
50
60
70
ENCODE POSITIVE DUTY CYCLE (%)
80
90
–2.0
–50
–30
–10
10
30
50
TEMPERATURE (°C)
70
90 95
Figure 35. Full-Scale Gain Error vs. Temperature
(AIN = 10.3 MHz @ –0.5 dBFS, 170 MSPS/210 MSPS, LVDS)
Figure 32. SINAD and SFDR vs. Clock Pulse Width High
(AIN = 10.3 MHz @ –0.5 dBFS, 170 MSPS, LVDS)
Rev. E | Page 19 of 44
02607-035
–1.5
02607-032
IAVDD (ANALOG SUPPLY CURRENT) (mA)
400
30
ENCODE POSITIVE DUTY CYCLE (%)
90
ANALOG SUPPLY
CURRENT LVDS MODE
SNR
60
Figure 30. IAVDD and IDRVDD vs. Clock Rate (AIN = 10.3 MHz @ –0.5 dBFS)
170 MSPS Grade, CLOAD = 5 pF
450
65
02607-033
ANALOG SUPPLY
CURRENT LVDS
MODE
250
02607-034
60
300
SFDR
75
dB
350
IDRVDD (OUTPUT SUPPLY CURRENT) (mA)
80
ANALOG SUPPLY
CURRENT CMOS
MODE
02607-030
IAVDD (ANALOG SUPPLY CURRENT) (mA)
400
AD9430
1.250
1.00
0.75
1.245
0.25
1.240
LSB
VREF (V)
0.50
1.235
0
–0.25
–0.50
1.230
2.7
2.9
3.1
3.3
AVDD (V)
3.5
3.7
–1.00
02607-036
1.225
2.5
3.9
Figure 36. VREF Output Voltage vs. AVDD
0
500
1000
1500
2000
CODE
2500
3000
3500
4000
02607-039
–0.75
Figure 39. Typical INL Plot (AIN = 10.3 MHz @ –0.5 dBFS, 170 MSPS, LVDS)
95
1.00
THIRD
0.75
90
SECOND
0.50
85
SFDR
0.25
dB
LSB
80
0
75
–0.25
70
–0.50
SNR
60
–50
–30
–10
10
30
50
TEMPERATURE (°C)
70
90
–1.00
0
1000
1500
2000
CODE
2500
3000
3500
4000
Figure 40. Typical DNL Plot (AIN = 10.3 MHz @ –0.5 dBFS)
Figure 37. SNR, SINAD, and SFDR vs. Temperature
(AIN = 10.3 MHz @ –0.5 dBFS, 170 MSPS)
100
65
64
90
AVDD = 3.6
SFDR –dBFS
80
63
AVDD = 3.3
70
61
60
dB
62
60
50
AVDD = 3.135
40
58
30
SFDR –dBc
80dB
REFERENCE LINE
AVDD = 3.0
57
20
56
10
55
–45
–25
–5
15
35
55
TEMPERATURE (°C)
75
0
–100
–90
–80
–70 –60 –50 –40 –30 –20
ANALOG INPUT LEVEL (dBFS)
Figure 41. SFDR vs. AIN Input Level ,
AIN @ 10.3 MHz, 170 MSPS, LVDS Mode
Figure 38. SINAD vs. Temperature, AVDD
(AIN = 70 MHz @ –0.5 dB, 210 MSPS, LVDS Mode)
Rev. E | Page 20 of 44
–10
0
02607-041
59
02607-038
dB
500
02607-040
–0.75
SINAD
02607-037
65
AD9430
90
0
80
–20
70
SFDR dBc
LVDS MODE
FULL SCALE = 1.5
60
–40
dB
dB
50
SFDR dBc
CMOS MODE
FULL SCALE = 1.5
40
19.2
–60
30
–80
20
80dB REFERENCE LINE
10
–70
–60
–50
–40
–30
–20
0
–10
19.2
38.4
47.6
MHz
Figure 42. SFDR vs. AIN Input Level, AIN @ 10.3 MHz, 210 MSPS,
LVDS/CMOS Modes
02607-045
–80
–100
02607-042
0
–90
Figure 45. W-CDMA Four Channels Centered at 38.4 MHz,
fs = 153.6 MHz, LVDS Mode
90
90
80
80
SFDR
SNR
70
70
SFDR dBc
LVDS MODE
FULL SCALE = 1.5
60
60
SINAD
50
dB
dB
50
40
40
SFDR dBc
LVDS MODE
FULL SCALE = 0.75
30
30
20
20
80dB REFERENCE LINE
10
–70
–60
–50
–40
–30
–20
–10
0
0
0
0.5
1.0
1.5
2.0
2.5
FULL-SCALE RANGE (V)
Figure 46. SNR, SINAD, and SFDR vs. Full-Scale Range, S5 = 0,
Full-Scale Range Varied by Adjusting VREF, 170 MSPS
Figure 43. SFDR vs. AIN Input Level, AIN @ 10.3 MHz, 210 MSPS, LVDS Mode,
Full Scale = 0.76 V/1.536 V
4.5
0
NPR = 56.95dB
ENCODE = 170MSPS
NOTCH @ 19MHz
4.0
–40
ns
–60
3.5
–80
TPD
–100
3.0
–140
2.65
21.25
MHz
42.5
2.5
–40
–20
0
20
40
TEMPERATURE (°C)
60
80
100
Figure 47. Propagation Delay vs. Temperature, LVDS Mode,
170 MSPS/210 MSPS
Figure 44. Noise Power Ratio Plot
Rev. E | Page 21 of 44
02607-047
TCPD
–120
02607-044
NOISE INPUT LEVEL (dB)
–20
02607-046
–80
02607-043
10
0
–90
AD9430
4.5
900
1.4
800
1.3
TPDR (DATA RISING)
3.0
2.5
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
100
Figure 48. Propagation Delay vs. Temperature,
CMOS Mode, 170 MSPS/210 MSPS
700
1.2
600
1.1
500
1.0
400
0.9
VOD
300
0.8
200
0.7
100
0.6
0
0
2
4
6
8
10
12
0.5
14
RSET (kΩ)
Figure 49. LVDS Output Swing, Common-Mode Voltage vs. RSET,
Placed at LVDSBIAS, 170 MSPS/210 MSPS
Rev. E | Page 22 of 44
02607-049
VDIF (mV)
TPDF (DATA FALLING)
3.5
02607-048
ns
4.0
VOS (V)
VOS
TCPD (CLOCKOUT RISING)
AD9430
TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
PowerFULL SCALE
⎞
⎟
⎟
⎟
⎟
⎠
Gain Error
The difference between the measured and ideal full-scale input
voltage range of the ADC.
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Crosstalk
Coupling onto one channel being driven by a low level
(–40 dBFS) signal when the adjacent interfering channel is
driven by a full-scale signal.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is
180° out of phase. Peak-to-peak differential is computed by
rotating the input phase 180° and again taking the peak
measurement. The difference is then computed between both
peak measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least square curve fit.
Minimum Conversion Rate
The ENCODE rate at which the SNR of the lowest analog
signal frequency drops by no more than 3 dB below the
guaranteed limit.
Maximum Conversion Rate
The ENCODE rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of CLK+ and CLK– and
the time when all output data bits are within valid logic levels.
Noise (for Any Range Within the ADC)
Calculated as follows:
Effective Number of Bits (ENOB)
Calculated from the measured SNR based on the equation
ENOB =
⎛ 2
⎜ V FULL SCALE rms
= 10 log ⎜
Z INPUT
⎜
⎜
0.001
⎝
− SNRdBc − SignaldBFS ⎞
⎛ FS
VNOISE = Z × 0.001 × 10⎜ dBM
⎟
10
⎝
⎠
SNRMEASURED − 1.76 dB
6.02
where:
ENCODE Pulse Width/Duty Cycle
Pulse width high is the minimum amount of time the ENCODE
pulse (clock pulse) should be left in a Logic 1 state to achieve
rated performance; pulse width low is the minimum time the
ENCODE pulse should be left in a low state. See the timing
implications of changing tEH in the Encode Input section. At
a given clock rate, these specifications define an acceptable
ENCODE duty cycle.
Z is the input impedance.
FS is the full scale of the device for the frequency in question.
SNR is the value of the particular input level.
Signal is the signal level within the ADC, reported in dB below
full scale. This value includes input levels both thermal and
quantization noise.
Rev. E | Page 23 of 44
AD9430
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise and Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics but excluding dc.
Signal-to-Noise Ratio (Without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral
components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious
component may or may not be a harmonic. Reported in dBc
(degrades as signal level is lowered) or dBFS (always related
back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms
value of the worst third-order intermodulation product;
reported in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. Reported in dBc (degrades
as signal level is lowered) or in dBFS (always related back to
converter full scale).
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic) reported in dBc.
Transient Response Time
The time it takes for the ADC to reacquire the analog input
after a transient from 10% above negative full scale to
10% below positive full scale.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transient from 10% above positive full scale to 10% above
negative full scale, or from 10% below negative full scale to
10% below positive full scale.
Rev. E | Page 24 of 44
AD9430
APPLICATION NOTES
THEORY OF OPERATION
The AD9430 architecture is optimized for high speed and ease
of use. The analog inputs drive an integrated high bandwidth
track-and-hold circuit that samples the signal prior to
quantization by the 12-bit core. For ease of use, the part
includes an on-board reference and input logic that accepts
TTL, CMOS, or LVPECL levels. The digital output logic levels
are user selectable as standard 3 V CMOS or LVDS (ANSI-644
compatible) via Pin S2.
with it that needs to be considered in applications where the
clock rate can change dynamically, requiring a wait time of
1.5 μs to 5 μs after a dynamic clock frequency increase before
valid data is available. This circuit is always on and cannot be
disabled by the user.
The clock inputs are internally biased to 1.5 V (nominal) and
support either differential or single-ended signals. For best
dynamic performance, a differential signal is recommended. An
MC100LVEL16 performs well in the circuit to drive the clock
inputs, as illustrated in Figure 50. (For trace lengths >2 inches, a
standard LVPECL termination is recommended rather than the
simple pull-down as shown.) Note that for this low voltage
PECL device, the ac coupling is optional.
ENCODE INPUT
Any high speed ADC is extremely sensitive to the quality of the
sampling clock provided by the user. A track-and-hold circuit is
essentially a mixer, and any noise, distortion, or timing jitter on
the clock is combined with the desired signal at the A/D output.
For that reason, considerable care has been taken in the design
of the clock inputs of the AD9430, and the user is advised to
give careful thought to the clock source.
0.1μF
PECL
GATE
CLK–
The AD9430 has an internal clock duty cycle stabilization
circuit that locks to the rising edge of CLK+ and optimizes
timing internally. This allows for a wide range of input duty
cycles at the input without degrading performance. Jitter in
the rising edge of the input is still of paramount concern and
is not reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
30 MHz nominally. The loop has a time constant associated
0.1μF
510Ω
02607-050
510Ω
Figure 50. Driving Clock Inputs with LVEL16
In interleaved mode, output data on Port A is offset from output
data changes on Port B by one-half output clock cycle, as shown
in Figure 51.
PARALLEL MODE
02607-051
INTERLEAVED MODE
AD9430
CLK+
Figure 51.
Table 9. Output Select Coding
S1 1
(Data Format Select)
1
0
X
X
X
X
X
1
2
3
S21
(LVDS/CMOS Mode Select) 2
X
X
0
0
1
X
X
S41
(I/P Select)
X
X
1
0
X
X
X
X = don’t care.
S4 used in CMOS mode only (S2 = 0). S1 to S5 all have 30 kΩ resistive pull-downs on chip.
S5 full-scale adjust (see the Analog Input section).
Rev. E | Page 25 of 44
S51
(Full-Scale Select) 3
X
X
X
X
X
1
0
Mode
Twos complement
Offset binary
Dual-mode CMOS interleaved
Dual-mode CMOS parallel
LVDS mode
Full scale = 0.768 V
Full scale = 1.536 V
AD9430
ANALOG INPUT
DS INPUTS (DS+, DS–)
The analog input to the AD9430 is a differential buffer. For
best dynamic performance, impedances at VIN+ and VIN–
should match. The analog input is optimized to provide
superior wideband performance and requires that the analog
inputs be driven differentially. SNR and SINAD performance
degrades significantly if the analog input is driven with a singleended signal.
In CMOS output mode, the data sync inputs (DS+, DS–) can be
used in applications that require a given sample to appear at a
specific output port (A or B) relative to a given external timing
signal. The DS inputs can also be used to synchronize two or
more ADCs in a system to maintain phasing between Port A
and Port B on separate ADCs (in effect, synchronizing multiple
DCO outputs). When DS+ is held high (DS– low), the ADC
data outputs and clock do not switch and are held static.
Synchronization is accomplished by the assertion (falling edge)
of DS+ within the timing constraints tSDS and tHDS, relative to a
clock rising edge. (On initial synchronization, tHDS is not
relevant.) If DS+ falls within the required setup time (tSDS)
before a given clock rising edge, N, the analog value at that
point in time is digitized and available at Port A, 14 cycles later
in interleaved mode.
A wideband transformer such as the Mini-Circuit® ADT1-1WT
can provide the differential analog inputs for applications that
require a single-ended-to-differential conversion. Both analog
inputs are self-biased by an on-chip resistor divider to a
nominal 2.8 V. (See the Equivalent Circuits section.)
Special care was taken in the design of the analog input section
of the AD9430 to prevent damage and corruption of data when
the input is overdriven. The nominal differential input range is
approximately 1.5 V p-p ~ (768 mV × 2). Note that the best
SNR performance is achieved with S5 = 0 (full scale = 1.5).
S5 = GND
VIN+
768mV 2.8V
2.8V
VIN–
The very next sample, N + 1, is sampled by the next rising clock
edge and available at Port B, 14 cycles after that clock edge. In
dual-parallel mode, Port A has a 15-cycle latency and Port B
has a 14-cycle latency, but data is available at the same time.
Driving the DS inputs of each ADC by the same sync signal
accomplishes this. An easy way to accomplish synchronization
is by a one-time sync at power-on reset. Note that when
running the AD9430 in LVDS mode, set DS+ to ground and
DS– to 3.3 V, as the DS inputs are relevant only in CMOS
output mode, simplifying the design for some applications as
well as affording superior SNR/SINAD performance at higher
encode/analog frequencies.
CMOS OUTPUTS
DIGITALOUT = ALL 0s
02607-052
DIGITALOUT = ALL 1s
Figure 52. Differential Analog Input Range
S5 = AVDD
VIN+
2.8V
768mV 2.8V
02607-053
VIN– = 2.8V
The off-chip drivers on the chip can be configured to provide
CMOS-compatible output levels via Pin S2. The CMOS digital
outputs (S2 = 0) are TTL/CMOS compatible for lower power
consumption. The outputs are biased from a separate supply
(DRVDD), allowing easy interface to external logic. The outputs
are CMOS devices that swing from ground to DRVDD (with no
dc load). It is recommended to minimize the capacitive load the
ADC drives by keeping the output traces short (<1 inch, for a
total CLOAD < 5 pF). When operating in CMOS mode, it is also
recommended to place low value (20 Ω) series damping
resistors on the data lines to reduce switching transient effects
on performance.
Figure 53. Single-Ended Analog Input Range
Rev. E | Page 26 of 44
AD9430
LVDS OUTPUTS
CLOCK OUTPUTS (DCO+, DCO–)
The input ENCODE is divided by two (in CMOS mode) and
available off chip at DCO+ and DCO–. These clocks can
facilitate latching off chip, providing a low skew clocking
solution (see Figure 2). The on-chip clock buffers should not
drive more than 5 pF of capacitance to limit switching transient
effects on performance. Note that the output clocks are CMOS
levels when CMOS mode is selected (S2 = 0) and are LVDS
levels when in LVDS mode (S2 = VDD), requiring a 100 Ω
differential termination at receiver in LVDS mode. The output
clock in LVDS mode switches at the ENCODE rate.
K
FULL
SCALE
S5 = 0 —> K = 1.24
S5 = 1 —> K = 0.62
0.1μF
VREF
+
1V
A1
EXTERNAL 1.23V +
REFERENCE
200Ω
1kΩ
DISABLE
A1
SENSE
+
3.3V
VDD
02607-054
The off-chip drivers on the chip can be configured to provide
LVDS-compatible output levels via Pin S2. LVDS outputs are
available when S2 = VDD and a 3.74 kΩ RSET resistor is placed
at Pin 7 (LVDSBIAS) to ground. The RSET resistor current is
ratioed on-chip, setting the output current at each output equal
to a nominal 3.5 mA (11 × IRSET). A 100 Ω differential
termination resistor placed at the LVDS receiver inputs results
in a nominal 350 mV swing at the receiver. LVDS mode
facilitates interfacing with LVDS receivers in custom ASICs and
FPGAs that have LVDS capability for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended with a 100 Ω termination resistor
as close to the receiver as possible. It is recommended to keep
the trace length three to four inches maximum and to keep
differential output trace lengths as equal as possible.
Figure 54. Using an External Reference
NOISE POWER RATIO TESTING (NPR)
NPR is a test that is commonly used to characterize the return
path of cable systems where the signals are typically QAM
signals with a noise-like frequency spectrum. NPR performance
of the AD9430 was characterized in the lab yielding an effective
NPR = 56.9 dB at an analog input of 19 MHz. This agrees with
a theoretical maximum NPR of 57.1 dB for an 11-bit ADC at
13.6 dB backoff. The rms noise power of the signal inside the
notch is compared with the rms noise level outside the notch
using an FFT. Sufficiently long record lengths to guarantee a
sufficient number of samples inside the notch are a
requirement, as well as a high order band-stop filter that
provides the required notch depth for testing.
VOLTAGE REFERENCE
A stable and accurate 1.23 V voltage reference is built into the
AD9430 (VREF). The analog input full-scale range is linearly
proportional to the voltage at VREF. Note that an external
reference can be used by connecting the SENSE pin to VDD
(disabling internal reference) and driving VREF with the
external reference source. No appreciable degradation in
performance occurs when VREF is adjusted ±5%. A 0.1 μF
capacitor to ground is recommended at the VREF pin in
internal and external reference applications. Float the SENSE
pin for internal reference operation.
Rev. E | Page 27 of 44
AD9430
EVALUATION BOARD, CMOS MODE
The AD9430 evaluation board offers an easy way to test the
AD9430 in CMOS mode. It requires a clock source, an analog
input signal, and a 3.3 V power supply. The clock source is
buffered on the board to provide the clocks for the ADC,
latches, and data ready signals. The digital outputs and output
clocks are available at two 40-pin connectors, P3 and P23. The
PCB interfaces directly with ADI standard dual-channel data
capture board (HSC-ADC-EVAL-DC) which, together with
ADI ADC Analyzer software, allows for quick ADC evaluation.
The board has several different modes of operation and is
shipped in the following configurations:
•
•
•
•
Offset binary
Internal voltage reference
CMOS parallel timing
Full-scale adjust = low
Full scale is set at E17, E18, and E19. Connecting E17 to E18
sets S5 low, full scale = 1.5 V differential; connecting E17 to E19
sets S5 high, full scale = 0.75 V differential.
ENCODE
The ENCODE clock is terminated to ground through 50 Ω at
SMB Connector J5. The input is ac coupled to a high speed
differential receiver (LVEL16) that provides the required
low jitter, fast edge rates needed for optimum performance.
J5 input should be >0.5 V p-p. Power to the EL16 is set at
Jumper E47. Connecting E47 to E45 powers the buffer from
AVDD; connecting E47 to E46 powers the buffer from
VCLK/V_XTAL.
VOLTAGE REFERENCE
POWER CONNECTOR
Power is supplied to the board via a detachable 12-lead power
strip (three 4-pin blocks). AVDD, DRVDD, and VDL are the
minimum required power connections.
Table 10. Power Connector, CMOS Mode
AVDD 3.3 V
DRVDD 3.3 V
VDL 3.3 V
EXT_VREF
VCLK/V_XTAL
VAMP
GAIN
Analog supply for ADC (350 mA)
Output supply for ADC (28 mA)
Supply for support logic and DAC (350 mA)
Optional external reference input
Supply for clock buffer/optional CRYSTAL
Supply for optional amp
The AD9430 has an internal 1.23 V voltage reference. The ADC
uses the internal reference as the default when jumpers E24 to
E27 and E25 to E26 are left open. The full scale can be increased
by placing optional Resistor R3. The required value varies with
the process and needs to be tuned for the specific application.
Full scale can similarly be reduced by placing R4; tuning is
required here as well. An external reference can be used by
shorting the SENSE pin to 3.3 V (place Jumper E26 to E25).
The E27 to E24 jumper connects the ADC VREF pin to the
EXT_VREF pin at the power connector.
DATA FORMAT SELECT
Data format select sets the output data format of the ADC.
Setting DFS (E1 to E2) low sets the output format to be offset
binary; setting DFS high (E1 to E3) sets the output to twos
complement.
ANALOG INPUTS
The evaluation board accepts a 1.3 V p-p analog input signal
centered at ground at SMB connector J4. This signal is
terminated to ground through 50 Ω by R16. The input can be
alternatively terminated at the transformer T1 secondary by
R13 and R14. T1 is a wideband RF transformer providing the
single-ended-to-differential conversion, allowing the ADC to be
driven differentially and minimizing even-order harmonics.
An optional second transformer, T2, can be placed following
T1 if desired. This provides some performance advantage
(~1 dB to 2 dB) for high analog input frequencies (>100 MHz).
If T2 is placed, two shorting traces at the pads need to be cut.
The analog signal is low-pass filtered by R41, C12 and R42, and
C13 at the ADC input.
I/P TIMING SELECT
Output timing is set at E11, E12 and E13. E12 to E11 sets S4
low for parallel output timing mode. E11 to E13 sets S4 high
for interleaved timing mode.
TIMING CONTROLS
Flexibility in latch clocking and output timing is accomplished
by allowing for clock inversion at the timing controls section of
the PCB. Each buffered clock is buffered by an XOR and can be
inverted by moving the appropriate jumper for that clock.
Rev. E | Page 28 of 44
AD9430
CMOS DATA OUTPUTS
OPTIONAL AMPLIFIER
The ADC CMOS digital outputs are latched on the board by
four LVT574s; the latch outputs are available at the two 40-pin
connectors at Pin 11 through Pin 33 on P23 (Channel A) and
Pin 11 through Pin 33 on P3 (Channel B). The latch output
clocks (data ready) are available at Pin 37 on P23 (Channel A)
and Pin 37 on P3 (Channel B). The data-ready clocks can be
inverted at the timing controls section if needed.
The evaluation board as shipped uses a wideband RF
transformer in its analog path. A user can modify the board to
use the AD8351 op amp for ac- or dc-coupled applications
(see Figure 59 and Figure 60). Figure 60 shows the AD8351 in
an ac-coupled topology, while Figure 57 shows the AD8351 in
a dc-coupled application. Optimum performance is obtained
with the AD8351 ac coupled.
RF
INHI
SINGLEENDED
50
SOURCE
R1
50
100nF
OPHI
25
AIN+
5pF
RG
INLO
25 100nF
AD9430
AD8351
OPLO 25
VOCM
AIN–
2.8V
100nF
1
Figure 57. Using the AD8351 on the AD9430 PCB
CH1
2.00V
CH2
2.00V
M 5.00ns
CH2
02607-055
2
Figure 55. Data Output and Clock @ 80-Pin Connector
CRYSTAL OSCILLATOR
An optional crystal oscillator can be placed on the board to
serve as a clock source for the PCB. Power to the oscillator is
through the VCLK pin at the power connector (also called
VCLK/V_XTAL). If an oscillator is used, ensure proper
termination for best results. The board has been tested with a
Valpey Fisher VF561 and a Vectron JN00158-163.84. Test
results for the VF561 are shown in Figure 56.
0
ENCODE 163.84MHz
ANALOG 65.02MHz
SNR 63.93dB
SINAD 63.87dB
FUND –0.45dBFS
2ND –85.62dBc
3RD –91.31dBc
4TH –90.54dBc
5TH –90.56dBc
6TH –91.12dBc
THD –82.21dBc
SFDR 83.93dBc
SAMPLES 8k
NOISEFLR –100.44dBFS
WORSTSP –83.93dBc
–10
–20
–30
–50
–60
–70
–80
–90
–100
0
20
40
MHz
60
80
02607-057
dB
–40
Figure 56. FFT—Using VF561 Crystal as Clock Source
Rev. E | Page 29 of 44
DIGITAL
OUT
02607-078
∆: 4.6ns
C1 FREQ
84.65608MHz
AD9430
TROUBLESHOOTING
•
•
•
•
The AD9430 evaluation board is provided as a design
example for customers of Analog Devices, Inc. ADI makes
no warranties, express, statutory, or implied, regarding
merchantability or fitness for a particular purpose.
Verify power at IC pins.
Check that all jumpers are in the correct position for the
desired mode of operation.
Verify that VREF is at 1.23 V.
Run the clock and analog inputs at low speeds (10 MSPS/
1 MHz) and monitor latch and ADC for toggling.
3.3V
+
SIGNAL
GENERATOR
REFIN
BAND-PASS
FILTER
3.3V
–
AVDD GND
ANALOG
J4
+
3.3V
–
DRVDD GND
+
VDL GND
AD9430 EVALUATION BOARD
10MHz
REFOUT
SIGNAL
GENERATOR
CLOCK
J5
Figure 58. Evaluation Board Connections
Rev. E | Page 30 of 44
–
DATA
CAPTURE
AND
PROCESSING
02607-059
If the board does not seem to be working correctly, try the
following:
AD9430
Table 11. CMOS PCB Evaluation Board Bill of Material
No.
1
Quantity
47
Reference Designator
C1, C3–C11, C15–C44,
C47, C48, C58–C62
Device
Capacitor
Package
0402
Value
0.1 μF
2
3
4
1
1
29
Capacitor
Capacitor
Capacitor
0402
0402
0402
10 pF
20 pF
0.01 μF
5
6
6
8
Capacitor
3-pin
header/jumper
CAPL
10 μF
7
1
C2
C12
C13, C14, C45, C46, C50–C57,
C68-C84
C49, C63–C67
(E3, E1, E2),( E19, E17, E18),
(E13, E11, E12),( E46, E47, E45),
(E35, E33, E34),( E32, E30, E31),
(E29, E23, E28),( E22, E16, E21)
E26, E25, E27, E24
8
9
10
4
2
3
J1, J2, J4, J5
P3, P23 1
P4, P21, P22
11
3
P4, P21, P22
12
13
14
15
16
4
3
8
2
17
R1, R5, R16, R27
R2, R3, R4
R6–R8, R10, R33–R36
R9, R11
R12, R15, R21–R26, R28–R31, R37,
R38, R43, R46, R47
17
6
R13, R14, R41, R42, R44, R45
18
2
19
20
4-pin
header/jumper
SMA
Connector
4-pin power
connector
4-pin power
connector
Resistor
Resistor
Resistor
Resistor
Resistor
SMA
Comments
C11, C18, C30, C33,
C34, C39, C40, C48
Not placed
Not placed
Not placed
All .01uF caps not
placed
J2 not placed
Post
Z5.531.3425.0
Wieland
Detachable
connector
0402
0402
0603
0402
0402
25.602.5453.0
Wieland
50 Ω
3.8K Ω
100 Ω
0Ω
User selected
R1 not placed
R3, R4 not placed
R34 not placed
Resistor
0402
25 Ω
R17, R18
Resistor
0402
510 Ω
2
2
R19, R20
R39, R40
Resistor
Resistor
0402
0402
150 Ω
1 kΩ
21
8
RZ1, RZ2, RZ3, RZ4, RZ5, RZ6, RZ7,
RZ8
Resistor pack 220 Ω
SO16RES
742C163221JTR
CTS
22
23
1
2
L1
T1,T4
Inductor
Transformer
0603
CD542
Not placed
T4 not placed
24
2
T2,T3
SM-22
25
26
1
1
U1
U2
Optional Macom
Transformer
AD9430BSV (−210)
MC100LVEL16D
User selected
Mini-Circuits
ADT1–1WT
ETC1–1–13
TQFP100
SO8NB
ADC
Clock buffer
27
28
29
1
4
1
U3
U4, U5, U6, U7
U8
VCX86
LVT574
JN00158
SO14NB
SO20
XOR
30
1
U9
AD8351
1
P3 and P23 are implemented as one physical 80-pin connector, the SAMTEC TSW-140-08-L-D-RA.
Rev. E | Page 31 of 44
Optional XTAL
Amp
All 17 not placed
R13, R14, R44, R45 not
placed
Not placed
Not placed
P4
P21
PTMICA04
Figure 59. Evaluation Board Schematic—CMOS
02607-060
OPTIN
R16
50Ω
GND
GND
GND
C6
0.1μF
C7
0.1μF
GND
E15
COUT
E7
E20
5
4
INX
2
3 T1
ENCODE
C33
0.1μF
GND
J5
GND
R27
50Ω
R45
25Ω
C5
0.1μF
4
3
T4
5
6
R4
3.8KΩ
R3
3.8KΩ
GND
R11
0Ω
R9
0Ω
2
1
SEE NOTE 1 FOR
SINGLE ENDED INPUT
6
C34
0.1μF
1
R39
1kΩ
R40
1kΩ
H1
MTHOLES
H2
COUTB
MTHOLES
H3
MTHOLES
H4
MTHOLES
DRVDD
VDL
R44
25Ω
SEE NOTE 1 FOR
SINGLE ENDED INPUT
GND
E2
E3
E1
VCC
GND
E5
E6
E4
GND
VCC
E10
E12
E13
E18
E19
E9
E8
E11
E14
E17
GND
VCC
GND
VCC
GND
VCC
GND
DRVDD
GND
VCC
1
P1
2
P2
3
P3
4
P4
GND
VCLK
VREF
GND
VDL
1
P1
2
P2
3
P3
4
P4
NOTES
1. TO USE SINGLE ENDED ANALOG INPUT,
REMOVE C6, C43, AND C47
PLACE C33, C34, R44 AND R45
GND
J4
ANALOG
GND
P22
PTMICA04
PTMICA04
R17
510Ω
MC100L
VCLK
VDL
R18
510Ω
10EL16
E46
GND
5
VEE
VBB
DN
8
VCC
DQ
C8
0.1μF
4
3
2
U2
QN
Q
10
9
5
4
13
12
GND
J1
GND
VCC
GND
GND
GND
VCC
VCC
GND
GND
VCC
VCC
GND
VCC
GND
6 EL OUTB
7 EL OUT
C36
0.1μF
R42
25Ω
R6
100Ω
COUTAB
R7
100Ω
R2
3.8kΩ
C12
20pF
R41
25Ω
GND
AMPINB
E45
C47
0.1μF
C2
10pF
C3 AMPIN
0.1μF
GND
R8
100Ω
COUTA
R10
100Ω
COUTAB
C13
0.01μF
E21
E22
E28
E29
E31
E32
E34
GND
E16
E23
E30
C1
0.1μF
C43
0.1μF
E24
E26
GND
VDL
GND
VDL
GND
E47
OPINB
R13
25Ω
R14
25Ω
OPIN
E25
E27
VCC
VREF
VCC
COUTAB
COUTA
GND
2
1
11
8
6
3
R36
100Ω
R35
100Ω
R34
100Ω
R33
100Ω
DRB
CLKLATB
DRA
CLKLATA
GND
GROUND PAD UNDER PART
P16
J2
GND
GND
R20
150Ω
C10
0.1μF
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
U3
74AVC86
U3
74AVC86
U3
74AVC86
U3
74AVC86
R19
150Ω
C9
0.1μF
GND
R1
50Ω
R5
50Ω
GND
VCC
VCC
VCC
GND
GND
COUTA
VCC
GND
E35
U1
AD9430
–ENC
E33
GND
VCC
VCC
GND
GND
VCC
VCC
GND
GND
GND
VCC
VCC
VCC
GND
GND
GND
VCC
VDL
C4
0.1μF
GND
GNDAMP
VAMP
DRVDD
GND
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
GND
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VCC
Rev. E | Page 32 of 44
DR VDD
GND
1
P1
2
P2
3
P3
4
P4
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DRVDD
GND
COUT
COUTB
DRVDD
GND
GND
DR VDD
GND
R8
R7
R6
R5
R4
R3
R2
R8
R7
R6
R5
R4
R3
R2
R1
9
10
11
12
13
14
15
16
R8
R7
R6
R5
R4
R3
R2
R1
8
7
6
5
4
3
2
1
R8
R7
R6
R5
R4
R3
R2
R1
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
RZ4 220
RSO16ISO
8
7
6
5
4
3
2
1
RZ3 220
RSO16ISO
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
RZ2 220
RSO16ISO
8
7
6
5
4
3
2
1
R1
RZ1 220
RSO16ISO
GND
GND
GND
GND
GND
GND
GND
GND
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
74AC574M
GND
D7
D6
D5
D4
D3
D2
D1
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
VCC
CLOCK
U7
OUT_EN
D0
CLOCK
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
VCC
74AC574M
GND
D7
D6
D5
D4
D3
D2
D1
D0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
CLOCK
U6
OUT_EN
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
VCC
74AC574M
GND
D7
D6
D5
D4
D3
D2
D1
D0
OUT_EN
U5
74AC574M
GND
D7
D6
D5
D4
D3
D2
D1
D0
VCC
CLOCK
U4
OUT_EN
VDL
11
12
13
14
15
16
17
18
19
20
11
12
13
14
15
16
17
18
19
20
11
12
13
14
15
16
17
18
19
20
11
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
8
7
6
5
4
3
2
1
R8
R7
R6
R5
R4
R3
R2
R1
9
10
11
12
13
14
15
16
RZ5 220
RSO16ISO
R8
R7
R6
R5
R4
R3
R2
R1
CLKLATB
VDL
9
10
11
12
13
14
15
16
RZ6 220
RSO16ISO
CLKLATA
VDL
R8
R7
R6
R5
R4
R3
R2
R1
9
10
11
12
13
14
15
16
RZ7 220
RSO16ISO
CLKLATA
VDL
R8
R7
R6
R5
R4
R3
R2
R1
RZ8 220
RSO 16ISO
CLKLATA
12 DM5
13 DM6
14 DM7
15 DM8
16
17
18
19
20
DYB
DYA
DY0
DY1
DY2
DY3
DY4
DY5
DY6
DY7
DY8
DY9
DY10
DY11
ORY
DXB
DXA
DX0
DX1
DX2
DX3
DX4
DX5
DX6
DX7
DX8
DX9
DX10
DX11
ORX
GND
GND
P39
P37
P35
P33
P31
P29
P27
P25
P23
P21
P19
P17
P15
P13
P11
P9
P7
P5
P3
P1
P39
P37
P35
P33
P31
P29
P27
P25
P23
P21
P19
P17
P15
P13
P11
P9
P7
P5
P3
P1
C4OMS
P3
P40
P38
P36
P34
P32
P30
P28
P26
P24
P22
P20
P18
P16
P14
P12
P10
P8
P6
P4
P2
C4OMS
P23
P40
P38
P36
P34
P32
P30
P28
P26
P24
P22
P20
P18
P16
P14
P12
P10
P8
P6
P4
P2
GND
GND
DRB
GND
DY11
DY10
DY9
DY8
DY7
DY6
DY5
DY4
DY3
DY2
DY1
DY0
DYA
DYB
ORY
GND
GND
DRA
GND
DX11
DX10
DX9
DX8
DX7
DX6
DX5
DX4
DX3
DX2
DX1
DX0
DXA
DXB
ORX
AD9430
AD9430
VCC
C64 +
10μF
C16
0.1μF
C17
0.1μF
C19
0.1μF
C21
0.1μF
C20
0.1μF
C23
0.1μF
C22
0.1μF
C25
0.1μF
C24
0.1μF
C27
0.1μF
C26
0.1μF
C29
0.1μF
C28
0.1μF
C31
0.1μF
C32
0.1μF
C38
0.1μF
C35
0.1μF
GND
VCC
C68
0.01μF
C69
0.01μF
C70
0.01μF
C71
0.01μF
C72
0.01μF
C73
0.01μF
C74
0.01μF
C75
0.01μF
C76
0.01μF
C77
0.01μF
C78
0.01μF
C46
0.01μF
C50
0.01μF
C51
0.01μF
C52
0.01μF
C45
0.01μF
C44
0.1μF
C42
0.1μF
C41
0.1μF
C15
0.1μF
C37
0.1μF
C79
0.01μF
C80
0.01μF
C81
0.01μF
C82
0.01μF
C83
0.01μF
C84
0.01μF
GND
VCLK
VDL
C67 +
10μF
C49 +
10μF
C63 +
10μF
C14
0.01μF
GND
GND
VAMP
VREF
C66 +
10μF
C48
0.1μF
GND
GND
DRVDD
C65 +
10μF
C62
0.1μF
C61
0.1μF
C60
0.1μF
C59
0.1μF
C58
0.1μF
C53
0.01μF
C54
0.01μF
C55
0.01μF
C56
0.01μF
C57
0.01μF
GND
TO USE VF561C CRYSTAL
GND
GND
L IS OPTIONAL
VCLK
JN00158
1
2
R38
100Ω
GND
3
E/D
NC
VCC
OUTPUTB
GND
OUTPUT
6
VCLK
R21
100Ω
R37
25Ω
5
4
RGP1
GND
R29 C11
0Ω 0.1μF
U8
GND
R30
1kΩ
PWDN 1
RGP1 2
P1
R22
100Ω
GND
C18
0.1μF
VAMP
R31
1kΩ
R43
25Ω
R28
1kΩ
VAMP
10 VOCM
9 VPOS
INHI 3
8 OPHI
INLO 4
7 OPLO
RGP2 5
AD8351
6 COMM
C39
R46
0.1μF
25Ω
VAMP
AMPINB
AMPIN
GND
R47
25Ω
C40
0.1μF
U9
GND
RGP1
VCLK
R12
25Ω
R25
1.2kΩ
R23
100Ω
P2
GND
R24
100Ω
T2
ETC1-1-13
15
T3
ETC1-1-13
15
2
PR SEC
INX
Figure 60. Evaluation Board Schematic—CMOS (continued)
Rev. E | Page 33 of 44
GND
2
34
GND
OPIN
34
GND
PR SEC
OPINB
02607-077
R15
100Ω
L1
X
C30
0.1μF
R26
1kΩ
PLACE R30 OR R31
(POWER DOWN)
OPTIN
Figure 63. PCB Ground Layer
Figure 62. PCB Top-Side Copper
02607-084
02607-082
Figure 61. PCB Top-Side Silkscreen
02607-083
02607-081
AD9430
Figure 64. PCB Split Power Plane
Rev. E | Page 34 of 44
02607-085
02607-086
AD9430
Figure 65. PCB Bottom-Side Copper
Figure 66. PCB Bottom-Side Silkscreen
Rev. E | Page 35 of 44
AD9430
EVALUATION BOARD, LVDS MODE
The AD9430 evaluation board offers an easy way to test the
AD9430 in LVDS mode. (The board is also compatible with the
AD9411.) It requires a clock source, an analog input signal, and
a 3.3 V power supply. The clock source is buffered on the board
to provide the clocks for the ADC, latches, and a data-ready
signal. The digital outputs and output clocks are available at a
40-pin connector, P23. The board has several different modes of
operation and is shipped in the following configurations:
•
•
•
Offset binary
Internal voltage reference
Full-scale adjust = low
Note that the AD9430 LVDS evaluation board does not
interface directly with the standard Analog Devices dualchannel data capture board (HSC-ADC-EVAL-DC). An LVDSto-CMOS translation board is required and is available from
Analog Devices. (No translation board is required for the
AD9430 CMOS evaluation board.)
GAIN
Full scale is set at E17 to E19, E17 to E18 sets S5 low, full scale =
1.5 V differential; E17 to E19 sets S5 high, full scale = 0.75 V
differential. Best performance is obtained at 1.5 V full scale.
CLOCK
The CLOCK input is terminated to ground through a 50 Ω
resistor at SMB connector J5. The input is ac coupled to a high
speed differential receiver (LVEL16) that provides the required
low jitter, fast edge rates needed for optimum performance.
J5 input should be >0.5 V p-p. Power to the LVEL16 is set at
Jumper E47. E47 to E45 powers the buffer from AVDD; E47 to
E46 powers the buffer from VCLK/V_XTAL (not in Table 11).
VOLTAGE REFERENCE
Power is supplied to the board via a detachable 8-lead power
strip (two 4-pin blocks). In Table 12, VCC, DRVDD, and VDL
are the minimum required power connections, and the
LVEL16 clock buffer can be powered from VCC or VDL at
the E47 jumper.
The AD9430 has an internal 1.23 V voltage reference. The ADC
uses the internal reference as the default when jumpers E24 to
E27 and E25 to E26 are left open. The full scale can be increased
by placing optional resistor R3. The required value varies with
the process and needs to be tuned for the specific application.
Full scale can similarly be reduced by placing R4; tuning is
required here as well. An external reference can be used by
shorting the SENSE pin to 3.3 V (place jumper E26 to E25).
Jumper E27 to E24 connects the ADC VREF pin to the
EXT_VREF pin at the power connector.
Table 12. Power Connector, LVDS Mode
DATA FORMAT SELECT
VCC 3.3 V
DRVDD 3.3 V
VDL 3.3 V
EXT_VREF
Data format select (DFS) sets the output data format of the ADC.
Setting DFS low (E1 to E2) sets the output format to be offset
binary; setting DFS high (E1 to E3) sets the output to twos
complement.
POWER CONNECTOR
Analog supply for ADC (350 mA)
Output supply for ADC (50 mA)
Supply for support logic
Optional external reference input
ANALOG INPUTS
DATA OUTPUTS
The evaluation board accepts a 1.3 V p-p analog input signal
centered at ground at SMB Connector J4. This signal is
terminated to ground through 50 Ω by R16. The input can be
alternatively terminated at the T1 transformer secondary by
R13 and R14. T1 is a wideband RF transformer providing the
single-ended-to-differential conversion, allowing the ADC to
be driven differentially and minimizing even-order harmonics.
An optional second transformer, T2, can be placed following T1
if desired. This provides some performance advantage
(~1 to 2 dB) for high analog input frequencies (>100 MHz). If
T2 is placed, two shorting traces at the pads need to be cut. The
analog signal can be low-pass filtered by R41, C12 and R42, and
C13 at the ADC input. A wideband differential amplifier
(AD8351) can be configured on the PCB for dc-coupled
applications. Remove C6, C15, and C30 to prevent transformer
loading of the amp. See Figure 67, Figure 68, and Figure 69 for
more information.
The ADC LVDS digital outputs are routed directly to the
connector at the card edge. Resistor pads have been placed at
the output connector to allow for termination if the connector
receiving logic does not have the required differential
termination for the data bits and DCO. Each output trace pair
should be terminated differentially at the far end of the line
with a single 100 Ω resistor.
CRYSTAL OSCILLATOR
An optional crystal oscillator can be placed on the board to
serve as a clock source for the PCB. Power to the oscillator is
through the VDL pin at the power connector. If an oscillator is
used, ensure proper termination for best results. The board has
been tested with a Valpey Fisher VF561 and a Vectron JN00158163.84.
Rev. E | Page 36 of 44
AD9430
Table 13. LVDS PCB Evaluation Board Bill of Material
No.
1
Quantity
33
2
4
Reference Designator
C1, C4–C11, C15–C17, C19–C32,
C35, C36, C58–C62
C3, C18, C39, C40
C33, C34, C37, C38
Device
Capacitors
Package
0603
Value
0.1 μF
Comment
C3, C18, C39, C40 not
placed
Capacitor
0402
0.1 μF
C33, C34, C37, C38 not
placed
3
4
5
6
7
4
1
2
2
2
C63–C66
C2
C12, C13
J4, J5
P21, P22
Capacitor
Capacitor
Capacitor
Jacks
Power connectors
Top
Power connectors
Posts
40-pin right-angle
connector
10 uF
10 pF
20 pF
Resistor
TAJD CAPL
0603
0603
SMB
25.602.5453.0
Wieland
Z5.531.3425.0
Wieland
Digi-Key
S2131-20-ND
0402
8
2
P21, P22
9
1
P23
10
16
R1, R6–R12, R15, R31–R37
11
12
13
14
15
16
17
18
19
1
3
2
2
2
2
2
2
6
R2
R5, R16, R27
R17, R18
R19, R20
R29, R30
R41, R42
R3, R4
R13, R14
R22, R23, R24, R25, R26, R28
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
0603
0603
0603
0603
0603
0603
0603
0603
0603
3.8 kΩ
50 Ω
510 Ω
150 Ω
1 kΩ
25 Ω
3.8 kΩ
25 Ω
100 Ω
20
4
R39, R40, R45, R47
Resistor
0402
25 Ω
21
22
23
24
25
2
1
3
2
1
R43, R44
R46
R38, R48, R49
R50, R51
T1
T2
Resistor
Resistor
Resistor
Resistor
RF transformer
10 kΩ
1.2 kΩ
25 Ω
1 kΩ
26
27
1
1
U2
U9
28
29
1
1
U1
U3
RF amp
Optional crystal
oscillator
AD9430
MC100LVEL16
0402
0402
0402
0402
Mini-Circuits
ADT1-1WT
AD8351
JN00158 or
VF561
TQFP-100
SO8NB
Rev. E | Page 37 of 44
100 Ω
C2 not placed
C12, C13 not placed
R1, R6–R12, R15, R31–37
Not placed
R13, R14 not placed
R22, R23, R24, R25, R26,
R28 not placed
R39, R40, R45, R47
not placed
R43, R44 not placed
R46 not placed
R38, R48, R49 not placed
R50, R51 not placed
T2 not placed
02607-068
GND
NC
NC
R27
50Ω
R17
510Ω
C5
0.1μF
C30
0.1μF
AMPIN
14
15
16
17
18
19
20
VCC
VCC
GND
GND
VCC
VCC
GND
R18
510Ω
VDL
25
24
23
22
2
3
4
U3
VEE
5
Q
QN
GND
C8
0.1μF
D
DN
VBB
GND
GND
R5
50Ω
R19
150Ω
ELOUTB
ELOUT
R20
150Ω
6
7
GND
C36
0.1μF
VCC
8
E45
E46
GND
10EL16
E47
C13
20pF
GND
VCC
GND
13
GND
21
12
GND
11
10
9
7
6
5
4
3
GND
R30
1kΩ
2
1
8
VCC
R42 GND
25Ω
C2
10pF
C3
0.1μF
GND
C1
0.1μF
E24
E26
E19
E18
VCC
VCC
E17
GND
MTHOLE6
H1
MTHOLE6
H2
MTHOLE6
H3
MTHOLE6
H4
R29 GND
1kΩ
AMPINB
C15
R41
0.1μF
25Ω
R14
25Ω
GND
GND
J5
R13
25Ω
6 C11
0.1μF
3
PRI SEC
4
2
1
5
ENCODE
4
GND
2
6 C7
0.1μF
PRI SEC
1
5
3
E27
VREF
VCC
E25
E2
C12
20pF
GND
GND
T2
T2 OPTIONAL
R4
3.8kΩ
GND
VCC
E3
GND
E1
R3
GND 3.8kΩ
GND
VCC
GND
VCC
GND
DRVDD
VDL
GND
GND
VREF
ADT1-1WT
C6
0.1μF
AMP
GND
ANALOG R16
J4 50Ω
4
R2
3.8kΩ
3
1
P1
P4
4
P4
2
3
P3
P3
2
P2
P2
1
P1
T1
P21
P22
ADT1-1WT
PTM1CRO4
PTM1CRO4
GND
C9
0.1μF
C10
0.1μF
U1
GND
P16
C4
0.1μF
DRVDD
GROUND PAD UNDER PART
VCC
100
26
GND
VCC
99
27
VCC
GND
98
28
VCC
GND
97
29
VCC
VCC
96
30
GND
VCC
95
31
GND
GND
94
32
GND
93
33
GND
92
34
VCC
VCC
91
35
VCC
90
36
VCC
37
89
40
GND
GND
84
42
GND
83
43
82
44
88
~ENC
DORB
DOR
81
R7
100Ω
D11
R6
100Ω
D11B
R8
100Ω
D10B
D10
GND
55
56
57
58
59
60
DRVDD
61
GND
DRVDD
GND
62
63
64
65
66
67
68
69
70
71
72
73
74
75
D9B
D9
DR
R37
100Ω
DRB
D6
R10
100Ω
D6B
P19 19 D4
P17 17 D3
P15 15 D2
P13 13 D1
P11 11 D0
18 P18
16 P16
14 P14
12 P12
P1 1
2 P2
GND
P3 3
4 P4
6 P6
P7 7
D1F
D2F
P5 5 DOR
8 P8
10 P10
P9 9
P21 21 D5
P27 27 D8
20 P20
P29 29 D9
28 P28
P23 23 D6
P31 31 D10
30 P30
22 P22
P33 33 D11
32 P32
P25 25 D7
P35 35 GND
34 P34
24 P24
P37 37 DR
36 P36
26 P26
P39 39 GND
D4B
D4
D8B
D8
38 P38
R33
100Ω
R12
100Ω
40 P40
D3
R32
100Ω
D3B
D5
R9
100Ω
D5B
D7
R11
100Ω
D7B
D2
R31
100Ω GND
DRVDD
54
DRB
D2B
GND
53
GND
52
D1
D11B
R15
51
100Ω
D10B
D1B
D9B
D8B
D7B
D6B
D0
D5B
R36
D4B
100Ω
D3B
D0B
D1F
D2B
R35
D1B
100Ω
D1FB
D0B
D2F
D1FB
R34
100Ω
D2FB
D2FB
DORB
GND
CONNECTOR
GND
45
GND
38
80
46
87
GND
77
49
86
39
VCC
79
47
DRVDD
85
41
GND
78
48
Rev. E | Page 38 of 44
GND
Figure 67. Evaluation Board Schematic—LVDS
VCC
76
50
R1
100Ω
AD9430
AD9430
VCC
+
C64
10μF
C16
0.1μF
C17
0.1μF
C19
0.1μF
C21
0.1μF
C23
0.1μF
C20
0.1μF
C22
0.1μF
C25
0.1μF
C24
0.1μF
C27
0.1μF
C26
0.1μF
C29
0.1μF
C28
0.1μF
C31
0.1μF
C32
0.1μF
C35
0.1μF
GND
DRVDD
VDL
+
C65
10μF
C61
0.1μF
C62
0.1μF
C60
0.1μF
C59
0.1μF
C58
0.1μF
+
C66
10μF
VREF
C18
0.1μF
GND
GND
+
C63
10μF
GND
TO USE VF561 CRYSTAL
GND
VDL
R28
100Ω
E/D
VCC
6
2
NC
OUTPUTB
5
3
GND
OUTPUT
4
R23
100Ω
VDL
P4
R25
100Ω
U9
GND
VDL
R24
100Ω
P5
R26
100Ω
02607-069
GND
1
GND
Figure 68. Evaluation Board Schematic—LVDS (continued)
R51
1kΩ
R50
1kΩ
VDL
GND
VDL
POWER DOWN
USE R43 OR R44
VDL
GND
R38
0Ω
R43
10kΩ
C33
0.1μF
C38
0.1μF
GND
R44
10kΩ
R39
25Ω
AMP
R40
25Ω
PWUP
VOCM 10
2
RGP1
INHI
VPOS 9
OPHI
INLO
OPLO
5
R45
25Ω
R47
25Ω
1
4
C34
0.1μF
GND
U2
AD8351
3
AMP IN
C37
0.1μF
GND
R49
25Ω
C39
0.1μF
8
RPG2
AMPINB
7
COMM 6
GND
R48
25Ω
C40
0.1μF
AMPIN
R46
1.2kΩ
Figure 69. Evaluation Board Schematic—LVDS (continued)
Rev. E | Page 39 of 44
02607-079
R22
100Ω
JN00158
AD9430
02607-073
02607-071
F
Figure 72. PCB Ground Layer—LVDS
02607-074
02607-072
Figure 70. PCB Top-Side Silkscreen—LVDS
Figure 71. PCB Top-Side Copper—LVDS
Figure 73. PCB Split Power Plane—LVDS
Rev. E | Page 40 of 44
02607-075
02607-076
AD9430
Figure 74. PCB Bottom-Side Copper—LVDS
Figure 75. PCB Bottom-Side Silkscreen—LVDS
Rev. E | Page 41 of 44
AD9430
OUTLINE DIMENSIONS
0.75
0.60
0.45
16.00 BSC SQ
1.20
MAX
14.00 BSC SQ
100
1
SEATING
PLANE
76
76
75
100
1
75
PIN 1
BOTTOM VIEW
(PINS UP)
TOP VIEW
(PINS DOWN)
CONDUCTIVE
HEAT SINK
51
50
25
50
1.05
1.00
0.95
7°
3.5°
0°
0.50 BSC
0.27
0.22
0.17
0.15
0.05
26
6.50
NOM
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD
021809-A
51
25
26
0.20
0.09
Figure 76.100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-100-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD9430BSV-170
AD9430BSVZ-170
AD9430BSV-210
AD9430BSVZ-210
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
100-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP)
100-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP)
100-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP)
100-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP)
Z = RoHS Compliant Part.
Rev. E | Page 42 of 44
Package Option
SV-100-1
SV-100-1
SV-100-1
SV-100-1
AD9430
NOTES
Rev. E | Page 43 of 44
AD9430
NOTES
©2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02607-0-9/10(E)
Rev. E | Page 44 of 44