AD AD9218BSTZ-RL65 3v dual analog-to-digital converter Datasheet

10-Bit, 40/65/80/105 MSPS
3 V Dual Analog-to-Digital Converter
AD9218
Dual 10-bit, 40 MSPS, 65 MSPS, 80 MSPS, and 105 MSPS ADC
Low power: 275 mW at 105 MSPS per channel
On-chip reference and track-and-hold
300 MHz analog bandwidth each channel
SNR = 57 dB @ 41 MHz, Encode = 80 MSPS
1 V p-p or 2 V p-p analog input range each channel
3.0 V single-supply operation (2.7 V to 3.6 V)
Power-down mode for single-channel operation
Twos complement or offset binary output mode
Output data alignment mode
Pin compatible with the 8-bit AD9288
–75 dBc crosstalk between channels
FUNCTIONAL BLOCK DIAGRAM
ENCODE A
AINA
AINA
AD9218
TIMING
T/H
ADC
OUTPUT
/ REGISTER /
10
10
REFINA
REFOUT
AINB
ENCODE B
T/H
ADC
OUTPUT /
/
10 REGISTER 10
D9B TO D0B
TIMING
VD
APPLICATIONS
USER
SELECT NO. 1
USER
SELECT NO. 2
DATA
FORMAT/
GAIN
REF
REFINB
AINB
D9A TO D0A
GND
VDD
02001-001
FEATURES
Figure 1.
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
I and Q communications
Ultrasound equipment
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9218 is a dual 10-bit monolithic sampling analog-todigital converter with on-chip track-and-hold circuits. The
product is low cost, low power, and is small and easy to use. The
AD9218 operates at a 105 MSPS conversion rate with
outstanding dynamic performance over its full operating range.
Each channel can be operated independently.
1.
Low Power. Only 275 mW power dissipation per channel
at 105 MSPS. Other speed grades proportionally scaled
down while maintaining high ac performance.
2.
Pin Compatibility Upgrade. Allows easy migration from 8-bit
to 10-bit devices. Pin compatible with the 8-bit AD9288
dual ADC.
The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power
supply and a clock for full operation. No external reference or
driver components are required for many applications. The
digital outputs are TTL/CMOS compatible and a separate
output power supply pin supports interfacing with 3.3 V or
2.5 V logic.
3.
Easy to Use. On-chip reference and user controls provide
flexibility in system design.
4.
High Performance. Maintains 54 dB SNR at 105 MSPS
with a Nyquist input.
5.
Channel Crosstalk. Very low at –75 dBc.
The clock input is TTL/CMOS compatible and the 10-bit digital
outputs can be operated from 3.0 V (2.5 V to 3.6 V) supplies.
User-selectable options offer a combination of power-down
modes, digital data formats, and digital data timing schemes.
In power-down mode, the digital outputs are driven to a high
impedance state.
6.
Fabricated on an Advanced CMOS Process. Available in a
48-lead low profile quad flat package (7 mm × 7 mm
LQFP) specified over the industrial temperature range
(−40°C to +85°C).
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
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Fax: 781.461.3113
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AD9218* PRODUCT PAGE QUICK LINKS
Last Content Update: 09/27/2017
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Technical Articles
DOCUMENTATION
• Correlating High-Speed ADC Performance to Multicarrier
3G Requirements
Application Notes
• DNL and Some of its Effects on Converter Performance
• AN-282: Fundamentals of Sampled Data Systems
• MS-2210: Designing Power Supplies for High Speed ADC
• AN-345: Grounding for Low-and-High-Frequency Circuits
• Single Chip Realizes Direct-Conversion Rx
• AN-501: Aperture Uncertainty and ADC System
Performance
DESIGN RESOURCES
• AN-715: A First Approach to IBIS Models: What They Are
and How They Are Generated
• AD9218 Material Declaration
• AN-737: How ADIsimADC Models an ADC
• Quality And Reliability
• AN-741: Little Known Characteristics of Phase Noise
• Symbols and Footprints
• AN-756: Sampled Systems and the Effects of Clock Phase
Noise and Jitter
• PCN-PDN Information
DISCUSSIONS
• AN-835: Understanding High Speed ADC Testing and
Evaluation
View all AD9218 EngineerZone Discussions.
• AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
SAMPLE AND BUY
• AN-935: Designing an ADC Transformer-Coupled Front
End
Visit the product page to see pricing options.
Data Sheet
TECHNICAL SUPPORT
• AD9218: 10-Bit, 40/65/80/105 MSPS 3 V Dual Analog-toDigital Converter Data Sheet
Submit a technical question or find your regional support
number.
TOOLS AND SIMULATIONS
DOCUMENT FEEDBACK
• Visual Analog
Submit feedback for this data sheet.
• AD9218 IBIS Models
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AD9218
TABLE OF CONTENTS
Features .............................................................................................. 1
Using the AD9218 ENCODE Input......................................... 18
Applications....................................................................................... 1
Digital Outputs ........................................................................... 18
Functional Block Diagram .............................................................. 1
Analog Input ............................................................................... 18
General Description ......................................................................... 1
Voltage Reference ....................................................................... 19
Product Highlights ........................................................................... 1
Timing ......................................................................................... 19
Revision History ............................................................................... 2
User Select Options.................................................................... 19
Specifications..................................................................................... 3
Application Information ........................................................... 19
DC Specifications ......................................................................... 3
AD9218/AD9288 Customer PCB BOM...................................... 20
Digital Specifications ................................................................... 4
Evaluation Board ............................................................................ 21
AC Specifications.......................................................................... 5
Power Connector........................................................................ 21
Switching Specifications .............................................................. 6
Analog Inputs ............................................................................. 21
Timing Diagrams.......................................................................... 6
Voltage Reference ....................................................................... 21
Absolute Maximum Ratings............................................................ 8
Clocking....................................................................................... 21
Explanation of Test Levels ........................................................... 8
Data Outputs............................................................................... 21
ESD Caution.................................................................................. 8
Data Format/Gain ...................................................................... 21
Pin Configuration and Function Descriptions............................. 9
Timing ......................................................................................... 21
Terminology .................................................................................... 10
Troubleshooting.......................................................................... 21
Equivalent Circuits ......................................................................... 12
Outline Dimensions ....................................................................... 25
Typical Performance Characteristics ........................................... 13
Ordering Guide .......................................................................... 25
Theory of Operation ...................................................................... 18
REVISION HISTORY
12/06—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to DC Specifications......................................................... 3
1/04—Rev. A. to Rev. B
Updated format...................................................................Universal
Changes to General Description .................................................... 1
Changes to DC Specifications......................................................... 3
Changes to Switching Specifications.............................................. 6
Added AD9218/AD9288 Customer PCB BOM section ........... 20
Added Evaluation Board section .................................................. 21
7/03—Rev. 0 to Rev. A
Updated Ordering Guide................................................................. 6
Changes to Terminology section ................................................... .8
Changes to Figure 17b.................................................................... 19
Updated Outline Dimensions ....................................................... 24
Rev. C | Page 2 of 28
AD9218
SPECIFICATIONS
DC SPECIFICATIONS
VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes 1
Offset Error 2
Gain Error2
Differential Nonlinearity
(DNL)
Integral Nonlinearity
(INL)
TEMPERATURE DRIFT
Offset Error
Gain Error2
Reference
REFERENCE
Internal Reference Voltage
(REFOUT)
Input Resistance (REFINA,
REFINB)
ANALOG INPUTS
Differential Input Voltage
Range (AIN, AIN) 3
Common-Mode Voltage3
Input Resistance
Input Capacitance
POWER SUPPLY
VD
VDD
Supply Currents
IVD (VD = 3.0 V) 4
IVDD (VDD = 3.0 V)4
Power Dissipation DC 5
IVD Power-Down Current 6
Power Supply Rejection
Ratio
AD9218BST-40/-65
Typ
Max
10
AD9218BST-80/-105
Typ
Max
10
Temp
Test
Level
Min
Full
25°C
25°C
25°C
VI
I
I
I
–18
–2
–1
Full
25°C
VI
I
–1/–1.6
Full
VI
±1
±1/±2.3
LSB
Full
Full
Full
V
V
V
10
80
40
4
100
40
ppm/°C
ppm/°C
ppm/°C
25°C
I
1.18
1.24
1.28
1.18
1.24
1.28
V
Full
VI
9
11
13
9
11
13
kΩ
Full
V
Full
Full
25°C
V
VI
V
8
VD/3
10
3
14
8
VD/3
10
3
14
V
kΩ
pF
Full
Full
IV
IV
2.7
2.7
3
3
3.6
3.6
2.7
2.7
3
3
3.6
3.6
V
V
Full
25°C
Full
Full
25°C
VI
V
VI
VI
I
108/117
7/11
325/350
20
±1
113/130
172/183
13/17
515/550
22
±1
175/188
mA
mA
mW
mA
mV/V
Guaranteed, not tested
2
18
3
8
±0.3/±0.6
1/1.3
±0.8
±0.3/±1
1/1.6
Min
–18
–2
–1
Guaranteed, not tested
2
18
3.5
8
±0.5/±0.8
1.2/1.7
–1.35/–2.7
1 or 2
±0.6/±0.9
±0.75/±2
+1.35/2.7
1
340/390
1
Unit
Bits
LSB
% FS
LSB
LSB
LSB
V
525/565
No missing codes across industrial temperature range guaranteed for 40 MSPS, 65 MSPS, and 80 MSPS grades. No missing codes at room temperature guaranteed for
105 MSPS grade.
Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.25 V external reference) 65 grade in 2 V p-p range, 40, 80, 105 grades in 1 V p-p range.
3
(AIN –AIN) = ±0.5 V in 1 V range (full scale), (AIN – AIN) = ±1 V in 2 V range (full scale). The analog inputs self-bias to VD/3. This common-mode voltage can be overdriven
externally by a low impedance source by ±300 mV (differential drive, gain = 1) or ±150 mV (differential drive, gain = 2).
4
AC power dissipation measured with rated encode and a 10.3 MHz analog input @ 0.5 dBFS, CLOAD = 5 pF.
5
DC power dissipation measured with rated encode and a dc analog input (outputs static, IVDD = 0).
6
In power-down state, IVDD = ±10 μA typical (all grades).
2
Rev. C | Page 3 of 28
AD9218
DIGITAL SPECIFICATIONS
VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.
Table 2.
Parameter
DIGITAL INPUTS
Encode Input Common
Mode
Encode 1 Voltage
Encode 0 Voltage
Encode Input Resistance
Logic 1 Voltage—S1, S2,
DFS
Logic 0 Voltage—S1, S2,
DFS
Logic 1 Current—S1
Logic 0 Current—S1
Logic 1 Current—S2
Logic 0 Current—S2
Logic 1 Current—DFS
Logic 0 Current—DFS
Input Capacitance—S1,
S2, Encode Inputs
Input Capacitance DFS
DIGITAL OUTPUTS
Logic 1 Voltage
Logic 0 Voltage
Output Coding
Temp
Test
Level
Full
V
Full
Full
Full
Full
VI
VI
VI
VI
Full
VI
Full
Full
Full
Full
Full
Full
25°C
VI
VI
VI
VI
VI
VI
V
25°C
V
Full
Full
VI
VI
AD9218BST-40/-65
Typ
Max
Min
Min
VD/2
AD9218BST-80/-105
Typ
Max
VD/2
2
V
2
1.8
2
2.0
0.8
2.3
1.8
2
2.0
0.8
–50
–400
50
–50
30
–400
±0
–230
230
±0
100
–230
2
50
–50
400
50
200
–50
–50
–400
50
–50
30
–400
4.5
2.45
±0
–230
230
±0
100
–230
2
0.8
2.3
V
V
kΩ
V
0.8
V
50
–50
400
50
200
–50
μA
μA
μA
μA
μA
μA
pF
4.5
2.45
0.05
Twos complement or offset binary
Rev. C | Page 4 of 28
Unit
0.05
Twos complement or offset binary
pF
V
V
AD9218
AC SPECIFICATIONS
VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE 1
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
fIN = 10.3 MHz
fIN = Nyquist 2
Signal-to-Noise and Distortion (SINAD)
(With Harmonics)
fIN = 10.3 MHz
fIN = Nyquist2
Effective Number of Bits
fIN = 10.3 MHz
fIN = Nyquist2
Second Harmonic Distortion
fIN = 10.3 MHz
fIN = Nyquist2
Third Harmonic Distortion
fIN = 10.3 MHz
fIN = Nyquist2
Spurious Free Dynamic Range (SFDR)
fIN = 10.3 MHz
fIN = Nyquist2
Two-Tone Intermodulation Distortion (IMD)
fIN1 = 10 MHz, fIN2 = 11 MHz at –7 dBFS
fIN1 = 30 MHz, fIN2 = 31 MHz at –7 dBFS
Analog Bandwidth, Full Power
Crosstalk
Temp
Test
Level
Min
25°C
25°C
I
I
58/55
–/54
25°C
25°C
I
I
25°C
25°C
AD9218BST-40/-65
Typ
Max
AD9218BST-80/-105
Min
Typ
Max
Unit
59/57
59/56
57/53
55/52
58/55
57/54
dB
dB
58/54
–/53
59/56
59/55
56/52
55/51
58/53
57/53
dB
dB
I
I
9.4/8.8
–/8.6
9.6/9.1
9.6/8.9
9.1/8.4
9/8.3
9.4/8.6
9.3/8.6
Bits
Bits
25°C
25°C
I
I
–72/–66
–/–63
–89/–77
–89/–72
–69/–60
–65/–57
–77/–68
–76/–66
dBc
dBc
25°C
25°C
I
I
–68/–62
–/–60
–79/–68
–78/–64
–62/–57
–63/–57
–71/–63
–73/–69
dBc
dBc
25°C
25°C
I
I
–68/–62
–/–60
–79/–67
–78/–64
–62/–57
–63/–57
–69/–62
–70/–63
dBc
dBc
25°C
25°C
25°C
25°C
V
V
V
V
–77/–67
300
–75
dBc
dBc
MHz
dBc
–74/–73
–73/–73
300
–75
1
AC specifications based on an analog input voltage of –0.5 dBFS at 10.3 MHz, unless otherwise noted. AC specifications for 40, 80, 105 grades are tested in 1 V p-p
range and driven differentially. AC specifications for 65 grade are tested in 2 V p-p range and driven differentially.
2
The 65, 80, and 105 grades are tested close to Nyquist for that grade: 31 MHz, 39 MHz, and 51 MHz for the 65, 80, and 105 grades, respectively.
Rev. C | Page 5 of 28
AD9218
SWITCHING SPECIFICATIONS
VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.
Table 4.
Parameter
ENCODE INPUT PARAMETERS
Maximum Encode Rate
Minimum Encode Rate
Encode Pulse Width High (tEH)
Encode Pulse Width Low (tEL)
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
DIGITAL OUTPUT PARAMETERS
Output Valid Time (tV) 1
Output Propagation Delay (tPD)1
Output Rise Time (tR)
Output Fall Time (tF)
Out-of-Range Recovery Time
Transient Response Time
Recovery Time from Power-Down
Pipeline Delay
1
Temp
Test
Level
AD9218BST-40/-65
Min
Typ
Max
AD9218BST-80/-105
Min
Typ
Max
Full
Full
Full
Full
25°C
25°C
VI
IV
IV
IV
V
V
40/65
80/105
Full
Full
25°C
25°C
25°C
25°C
25°C
Full
VI
VI
V
V
V
V
V
IV
20/20
Unit
20/20
7/6
7/6
5/3.8
5/3.8
2
3
2
3
2.5
2.5
4.5
1
1.2
5
5
10
5
7
4.5
1.0
1.2
5
5
10
5
MSPS
MSPS
ns
ns
ns
ps rms
ns
ns
ns
ns
ns
ns
Cycles
Cycles
6
tV and tPD are measured from the 1.5 level of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is not to exceed
an ac load of 5 pF or a dc current of ±40 μA. Rise and fall times are measured from 10% to 90%.
TIMING DIAGRAMS
SAMPLE
N+1
SAMPLE N
SAMPLE
N+5
SAMPLE
N+6
AINA
AINB
tA
tEH
tEL
SAMPLE
N+2
SAMPLE
N+3
SAMPLE
N+4
1/fS
ENCODE A
ENCODE B
tV
D9A TO D0A
DATA N – 5
DATA N – 4
DATA N – 3
DATA N – 2
DATA N – 1
DATA N
D9B TO D0B
DATA N – 5
DATA N – 4
DATA N – 3
DATA N – 2
DATA N – 1
DATA N
Figure 2. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing
Rev. C | Page 6 of 28
02001-002
tPD
AD9218
SAMPLE
N
SAMPLE
N+1
SAMPLE
N+2
SAMPLE
N+7
SAMPLE
N+8
AINA
AINB
tA
SAMPLE SAMPLE SAMPLE SAMPLE
N+3
N+4
N+5
N+6
tEL
tEH
1/fS
ENCODE A
tV
tPD
ENCODE B
DATA N – 10
DATA N – 8
DATA N – 9
D9B TO D0B
DATA N – 6
DATA N – 7
DATA N – 4
DATA N – 5
DATA N – 2
DATA N – 3
DATA N
DATA N – 1
DATA N + 2
DATA N + 1
02001-003
D9A TO D0A
Figure 3. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing
SAMPLE
N
SAMPLE
N+1
SAMPLE
N+2
SAMPLE
N+7
SAMPLE
N+8
AINA
AINB
tA
tEH
tEL
SAMPLE SAMPLE SAMPLE SAMPLE
N+3
N+4
N+5
N+6
1/fS
ENCODE A
tV
tPD
D9A TO D0A
DATA N – 10
DATA N – 8
DATA N – 6
DATA N – 4
DATA N – 2
DATA N
DATA N + 2
D9B TO D0B
DATA N – 11
DATA N – 9
DATA N – 7
DATA N – 5
DATA N – 3
DATA N – 1
DATA N + 1
Figure 4. Data Align with Two Clock Sources (S1 = 1, S2 = 1) Channel Timing
Rev. C | Page 7 of 28
02001-004
ENCODE B
AD9218
ABSOLUTE MAXIMUM RATINGS
EXPLANATION OF TEST LEVELS
Table 5.
Parameter
VD, VDD
Analog Inputs
Digital Inputs
REFIN Inputs
Digital Output Current
Operating Temperature
Storage Temperature
Maximum Junction Temperature
Maximum Case Temperature
θA (measured on a 4-layer board with
solid ground plane)
Rating
4V
–0.5 V to VD + 0.5 V
–0.5 V to VDD + 0.5 V
–0.5 V to VD + 0.5 V
20 mA
–55°C to +125°C
–65°C to +150°C
150°C
150°C
I.
100% production tested.
II.
100% production tested at 25°C and sample tested at
specified temperatures.
III.
Sample tested only.
IV.
Parameter is guaranteed by design and characterization
testing.
V.
Parameter is a typical value only.
57°C/W
VI.
100% production tested at 25°C; guaranteed by design
and characterization testing for industrial temperature
range.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
100% production tested at temperature extremes for
military devices.
Table 6. User Select Modes
S1
0
0
1
1
S2
0
1
0
1
Power-Down and Data Alignment Settings
Power down both Channel A and Channel B.
Power down Channel B only.
Normal operation (data align disabled).
Data align enabled (data from both channels
available on rising edge of Clock A. Channel B data is
delayed by a ½ clock cycle.)
ESD CAUTION
Rev. C | Page 8 of 28
AD9218
GND 1
36
D1A
AINA 2
35
D0A
AINA 3
34
GND
DFS/GAIN 4
33
VDD
32
GND
31
30
VD
VD
S1 8
29
GND
S2 9
28
VDD
AINB 10
27
GND
AINB 11
26
D0B
GND 12
25
D1B
REFINA 5
AD9218
REFOUT 6
REFINB 7
D2B 24
D3B 23
D4B 22
D5B 21
D6B 20
D7B 19
D8B 18
(MSB) D9B 17
VDD 15
GND 16
VD 13
ENCB 14
TOP VIEW
(Not to Scale)
02001-005
37 D2A
38 D3A
39 D4A
40 D5A
41 D6A
42 D7A
43 D8A
44 D9A (MSB)
45 GND
46 VDD
48 VD
47 ENCA
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 5. Pin Configuration
Table 7. Pin Function Descriptions
Pin Number
1, 12, 16, 27, 29,
32, 34, 45
2
Mnemonic
GND
Description
Ground.
AINA
Analog Input for Channel A.
3
A IN A
Analog Input for Channel A (Complementary).
4
DFS/GAIN
5
6
7
8
9
10
REFINA
REFOUT
REFINB
S1
S2
Data Format Select and Analog Input Gain Mode. Low = offset binary output available, 1 V p-p supported;
high = twos complement output available, 1 V p-p supported; floating = offset binary output available,
2 V p-p supported; set to VREF = twos complement output available, 2 V p-p supported.
Reference Voltage Input for Channel A.
Internal Reference Voltage.
Reference Voltage Input for Channel B.
User Select No. 1. See Table 6.
User Select No. 2. See Table 6.
Analog Input for Channel B (Complementary).
11
13, 30, 31, 48
14
15, 28, 33, 46
17 to 26
35 to 44
47
AINB
VD
ENCB
VDD
D9B to D0B
D0A to D9A
ENCA
A INB
Analog Input for Channel B.
Analog Supply (3 V).
Clock Input for Channel B.
Digital Supply (2.5 V to 3.6 V).
Digital Output for Channel B (D9B = MSB).
Digital Output for Channel A (D9A = MSB).
Clock Input for Channel A.
Rev. C | Page 9 of 28
AD9218
TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Crosstalk
Coupling onto one channel being driven by a low level signal
(–40 dBFS) when the adjacent interfering channel is driven by a
full-scale signal.
Differential Analog Input Resistance,
Differential Analog Input Capacitance,
Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.
Full-Scale Input Power
Expressed in dbm. Computed using the following equation:
PowerFull − Scale
⎞
⎟
⎟
⎟
⎟
⎟
⎠
Gain Error
Gain error is the difference between the measured and the ideal
full-scale input voltage range of the ADC.
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least-square curve fit.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180
degrees out of phase. Peak-to-peak differential is computed by
rotating the input phase 180 degrees and again taking the peak
measurement. The difference is then computed between both
peak measurements.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between the 50% level crossing of ENCODE A or
ENCODE B and the 50% level crossing of the respective
channel’s output data bit.
Noise (for Any Range Within the ADC)
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB)
The effective number of bits is calculated from the measured
SNR based on the equation
ENOB =
⎛ V Full − Scale 2 rms
⎜
⎜
Z INPUT
= 10 log⎜
0.001
⎜
⎜
⎝
SNR MEASURED − 1.76 dB
6.02
ENCODE Pulse Width/Duty Cycle
Pulse width high is the minimum amount of time that the
ENCODE pulse should be left in Logic 1 state to achieve rated
performance; pulse width low is the minimum time ENCODE
pulse should be left in low state. See timing implications of
changing tENCH in text. At a given clock rate, these specifications
define an acceptable ENCODE duty cycle.
⎛ FS − SNRdBc − SignaldBFS ⎞
VNOISE = Z × 0.001× 10⎜ dBm
⎟
10
⎠
⎝
where Z is the input impedance, FS is the full scale of the device
for the frequency in question, SNR is the value for the particular
input level, and Signal is the signal level within the ADC
reported in dB below full scale. This value includes both
thermal and quantization noise.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Rev. C | Page 10 of 28
AD9218
Signal-to-Noise and Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics but excluding dc.
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral
components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component
may or may not be a harmonic. Reported in dBc (that is,
degrades as signal level is lowered) or dBFS (always related back
to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third-order intermodulation product; reported in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. Reported in dBc (that is,
degrades as signal level is lowered) or in dBFS (always related
back to converter full scale).
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonics) reported in dBc.
Transient Response Time
Transient response is defined as the time it takes for the ADC to
reacquire the analog input after a transient from 10% above
negative full scale to 10% below positive full scale.
Out-of-Range Recovery Time
Out-of-range recovery time is the time it takes for the ADC to
reacquire the analog input after a transient from 10% above
positive full scale to 10% above negative full scale or from 10%
below negative full scale to 10% below positive full scale.
Rev. C | Page 11 of 28
AD9218
EQUIVALENT CIRCUITS
VD
VD
30kΩ
40kΩ
40kΩ
15kΩ
REF
AIN
10kΩ
02001-010
02001-B-006
15kΩ
Figure 6. Analog Input Stage
Figure 10. Reference Inputs
VD
VD
2.6kΩ
ENCODE
600kΩ
S2
02001-011
10kΩ
02001-007
2.6kΩ
Figure 11. S2 Input
Figure 7. Encode Inputs
VD
VD
10kΩ
S1
02001-008
02001-012
OUT
Figure 8. Reference Output Stage
Figure 12. S1 Input
VD
VDD
15kΩ
40kΩ
DFS/GAIN
DX
VREF
Figure 9. Digital Output Stage
Figure 13. DFS/Gain Input
Rev. C | Page 12 of 28
02001-013
15kΩ
02001-009
AIN
30kΩ
AD9218
TYPICAL PERFORMANCE CHARACTERISTICS
0
0
ENCODE = 105MSPS
AIN = 50.1MHz AT –0.5dBFS
SNR = 53.8dB
SINAD = 53.4dB
H2 = –69dB
H3 = –65.8dB
–10
–20
–30
–20
–30
–40
(dB)
–50
–60
–60
–70
–70
–80
–80
–90
02001-014
–90
–100
0
52.5
Figure 14. FFT: FS = 105 MSPS, AIN = 50.1 MHz @ –0.5 dBFS, Differential,
1 V p-p Input Range
–100
0
Figure 17. FFT: FS = 40 MSPS, AIN = 19.75 MHz @ –0.5 dBFS, Differential,
1 V p-p Input Range
0
0
ENCODE = 80MSPS
AIN = 39MHz AT –0.5dBFS
SNR = 56.1dB
SINAD = 55.5dB
H2 = –71.8dB
H3 = –66.2dB
–10
–20
–30
ENCODE = 105MSPS
AIN = 70MHz AT –0.5dBFS
SNR = 51.9dB
SINAD = 51.8dB
H2 = –70.5dB
H3 = –76.3dB
–10
–20
–30
–40
(dB)
–40
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
0
40
–100
0
Figure 15. FFT: FS = 80 MSPS, AIN = 39 MHz @ –0.5 dBFS, Differential,
1 V p-p Input Range
40
02001-018
–50
02001-015
(dB)
20
02001-017
–50
Figure 18. FFT: FS = 105 MSPS AIN = 70 MHz @ –0.5 dBFS, Differential,
1 V p-p Input Range
0
0
ENCODE = 65MSPS
AIN = 30.3MHz AT –0.5dBFS
SNR = 56.1dB
SINAD = 55.9dB
SFDR = 72dB
H2 = –83.2dB
H3 = –79dB
–10
–20
–30
–20
–30
–40
(dB)
–40
ENCODE = 65MSPS
AIN = 15MHz AT –0.5dBFS
SNR = 56.4dB
SINAD = 55.9dB
H2 = –73.9dB
H3 = –71.7dB
–10
–50
–50
–60
–60
–70
–70
–80
–80
–90
02001-016
–90
–100
0
32.5
Figure 16. FFT: FS = 65 MSPS, AIN = 30.3 MHz @ –0.5 dBFS, Differential,
2 V p-p Input Range
–100
0
32.5
02001-019
(dB)
–40
(dB)
ENCODE = 40MSPS
AIN = 19.75MHz AT –0.5dBFS
SNR = 58.4dB
SINAD = 58.3dB
H2 = –87dB
H3 = –81dB
–10
Figure 19. FFT: FS = 65 MSPS, AIN = 15 MHz @ – 0.5 dBFS; with AD8138 Driving
ADC Inputs, 1 V p-p Input Range
Rev. C | Page 13 of 28
AD9218
0
0
ENCODE = 31MSPS
AIN = 8MHz AT –0.5dBFS
SNR = 59.23dB
SINAD = 59.1dB
H2 = –87dB
H3 = –81dB
–10
–20
–30
–20
–30
–40
–50
–50
–60
–60
–70
–70
–80
–80
0
15.5
–90
02001-020
–90
–100
Figure 20. FFT: FS = 31 MSPS, AIN = 8 MHz @ –0.5 dBFS, Differential,
1 V p-p Input Range
–100
0
15.5
02001-023
(dB)
–40
(dB)
ENCODE = 31MSPS
AIN = 8MHz AT –0.5dBFS
SNR = 59dB
SINAD = 58.8dB
H2 = –78.7dB
H3 = –72.9dB
–10
Figure 23. FFT: FS = 31 MSPS, AIN = 8 MHz @ –0.5 dBFS, Differential, with
AD8138 Driving ADC Inputs,1 V p-p Input Range
80
75
0
SECOND
THIRD
70
–20
65
–30
60
SFDR
–40
50
–50
45
–60
40
–70
35
–80
0
50
100
150
200
250
AIN FREQUENCY (MHz)
–90
02001-021
30
–100
0
52.5
02001-024
55
(dB)
(dB)
ENCODE = 105MSPS
AIN1 = 30.1MHz AT –7dBFS
AIN2 = 31.1MHz AT –7dBFS
SFDR = –67dBFS
–10
Figure 24. Two-Tone Intermodulation Distortion
(30.1 MHz and 31.1 MHz; 1 V p-p, FS = 105 MSPS)
Figure 21. Harmonic Distortion (Second and Third) and
SFDR vs. AIN Frequency (1 V p-p, FS = 105 MSPS)
80
THIRD
75
0
70
65
–20
60
–30
SFDR
55
–50
45
–60
40
–70
35
–80
30
0
50
100
150
200
250
AIN FREQUENCY (MHz)
–90
–100
0
Figure 22. Harmonic Distortion (Second and Third) and
SFDR vs. AIN Frequency (1 V p-p, FS = 80 MSPS)
40
Figure 25. Two-Tone Intermodulation Distortion
(29.3 MHz and 30.3 MHz; 1 V p-p, FS = 80 MSPS)
Rev. C | Page 14 of 28
02001-025
(dB)
–40
50
02001-022
(dB)
ENCODE = 80MSPS
AIN1 = 29.3MHz AT –7dBFS
AIN2 = 30.3MHz AT –7dBFS
SFDR = –77dBFS
–10
SECOND
AD9218
H2 1V
0
1V DIFFERENTIAL DRIVE
80
H3 1V
70
–20
SFDR 1V
60
–30
H2 2V
50
–40
(dB)
(dB)
ENCODE = 65MSPS
AIN1 = 28.1MHz AT –7dBFS
AIN2 = 29.1MHz AT –7dBFS
SFDR = –72.9dBFS
–10
40
H3 2V
–60
SFDR 2V
30
20
–50
–70
–80
2V SINGLE-ENDED DRIVE
–90
0
20
40
60
80
100
120
140
160
02001-026
10
180
AIN FREQUENCY (MHz)
–100
0
32.5
02001-029
90
Figure 29. Two-Tone Intermodulation Distortion
(28 MHz, 29 MHz; 1 V p-p, FS = 65 MSPS)
Figure 26. Harmonic Distortion (Second and Third) and
SFDR vs. AIN Frequency (FS = 65 MSPS)
90
0
85
SECOND
80
–30
–40
70
(dB)
65
–50
–60
60
–70
55
–80
–90
10
20
30
40
50
60
02001-027
50
70
AIN FREQUENCY (MHz)
–100
0
20
02001-030
(dB)
–20
THIRD
SFDR
75
ENCODE = 40MSPS
AIN1 = 10MHz AT –7dBFS
AIN2 = 11MHz AT –7dBFS
SFDR = 74dBc
–10
Figure 30. Two-Tone Intermodulation Distortion
(10 MHz, 11 MHz; 1 V p-p, FS = 40 MSPS)
Figure 27. Harmonic Distortion (Second and Third) and
SFDR vs. AIN Frequency (1 V p-p, FS = 40 MSPS)
75
80
70
75
SFDR
SFDR
70
65
(dB)
60
SINAD
SNR
55
55
45
SINAD
50
0
20
40
60
80
100
120
45
ENCODE RATE (MSPS)
Figure 28. SINAD and SFDR vs. Encode Rate (AIN = 10.3 MHz, 105 MSPS
Grade) AIN = –0.5 dBFS Differential, 1 V p-p Analog Input Range )
0
10
20
30
40
50
ENCODE RATE (MHz)
60
70
80
02001-031
50
02001-028
(dB)
65
60
Figure 31. SINAD and SFDR vs. Encode Rate (AIN = 10.3 MHz, 65 MSPS Grade)
AIN = –0.5 dBFS Differential, 1 V p-p Analog Input Range
Rev. C | Page 15 of 28
AD9218
75
75
70
SFDR
70
SFDR
65
65
60
55
(dB)
(dB)
60
50
SINAD
55
45
50
SINAD
40
0
1
2
3
4
5
6
7
8
ENCODE POSITIVE PULSEWIDTH (ns)
Figure 32. SINAD and SFDR vs. Encode Pulse Width High, AIN = –0.5 dBFS
Single-Ended, 1 V p-p Analog Input Range 105 MSPS
200
40
02001-032
30
0
2
4
6
8
10
12
14
ENCODE POSITIVE PULSEWIDTH (ns)
02001-035
45
35
Figure 35. SINAD and SFDR vs. Encode Pulse Width High, AIN = –0.5 dBFS
Single-Ended, 1 V p-p Analog Input Range 65 MSPS
4.5
50
45
180
GAIN –105
35
30
25
20
IVD – 65
120
3.5
(%)
–65/–105 IV DD
140
IVDD (mA)
160
(mA)
4.0
40
IVD – 105
3.0
GAIN –65
15
10
100
2.5
20
40
60
80
100
120
0
140
2.0
–40
02001-033
0
ENCODE CLOCK RATE (MSPS)
–20
0
20
40
60
80
TEMPERATURE (°C)
02001-036
5
80
Figure 36. Gain Error vs. Temperature, AIN = 10.3 MHz, –65 MSPS Grade,
–105 MSPS Grade, 1 V p-p
Figure 33. IVD and IVDD vs. Encode Rate (AIN = 10.3 MHz, @ –0.5 dBFS),
–65 MSPS/–105 MSPS Grade CI = 5 pF
68
1.131
66
1.129
64
1.127
SFDR –65
SFDR –105
62
SNR –65
(V)
(dB)
1.125
1.123
SINAD –65
58
1.121
56
–20
0
20
40
60
80
TEMPERATURE (°C)
02001-034
54
52
–40
SNR –105
SINAD –105
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 37. SNR, SINAD, SFDR vs. Temperature, AIN = 10.3 MHz,
–65 MSPS Grade, –105 MSPS Grade, 1 V p-p
Figure 34. VREF Output Voltage vs. Temperature (ILOAD = 300 μA)
Rev. C | Page 16 of 28
02001-037
1.119
–40
60
AD9218
1.50
90
1.45
80
1.40
70
SFDR – dBFS
1.35
60
SFDR – dBc
(dB)
1.25
1.20
50
40
70dB REF LINE
30
1.15
20
1.10
SNR – dBc
10
1.05
–0.5
0
0.5
1.0
1.5
2.0
2.5
ILOAD (mA)
0
–60
02001-038
1.00
–1.0
–50
–40
–30
–20
–10
0
AIN INPUT LEVEL (dBFS)
02001-040
(V)
1.30
Figure 40. SFDR vs. AIN Input Level, 10.3 MHz AIN @ 80 MSPS
Figure 38. VREF vs. ILOAD
1.0
2.0
0.8
1.5
0.6
1.0
0.4
(LSB)
0.2
0
0
–0.2
–0.5
–0.4
–1.0
–0.6
–1.5
–2.0
0
1024
CODES
–1.0
0
1024
CODES
Figure 41. Typical DNL Plot, 10.3 MHz AIN @ 80 MSPS
Figure 39. Typical INL Plot, 10.3 MHz AIN @ 80 MSPS
Rev. C | Page 17 of 28
02001-041
–0.8
02001-039
(LSB)
0.5
AD9218
THEORY OF OPERATION
The AD9218 ADC architecture is a bit-per-stage pipeline-type
converter utilizing switch capacitor techniques. These stages
determine the 7 MSBs and drive a 3-bit flash. Each stage
provides sufficient overlap and error correction, allowing
optimization of comparator accuracy. The input buffers are
differential, and both sets of inputs are internally biased. This
allows the most flexible use of ac-coupled or dc-coupled and
differential or single-ended input modes. The output staging
block aligns the data, carries out the error correction, and feeds
the data to output buffers. The set of output buffers are powered
from a separate supply, allowing adjustment of the output
voltage swing. There is no discernible difference in performance
between the two channels.
ANALOG INPUT
The analog input to the AD9218 is a differential buffer. For best
dynamic performance, impedance at AIN and AIN should match.
Special care was taken in the design of the analog input section
of the AD9218 to prevent damage and data corruption when
the input is overdriven. The nominal input range is 1.024 V p-p.
Optimum performance is obtained when the part is driven
differentially where common-mode noise is minimized and
even-order harmonics are reduced. Figure 42 shows an example
of the AD9218 being driven differentially via a wideband RF
transformer for ac-coupled applications. As shown in Figure 43,
applications that require dc-coupled differential drives can be
accommodated using the AD8138 differential output op amp.
USING THE AD9218 ENCODE INPUT
AIN
The digital outputs are TTL/CMOS compatible for lower power
consumption. During power-down, the output buffers transition to
a high impedance state. A data format selection option supports
either twos complement (set high) or offset binary output (set
low) formats.
25Ω
1:1
0.1µF
AD9218
25Ω
AIN
Figure 42. Using a Wideband Transformer to Drive the AD9218
500Ω
50Ω
ANALOG
SIGNAL
SOURCE
25Ω
500Ω
AVDD
VOCM
10kΩ
0.1µF
5kΩ
AD9218
AD8138
500Ω
AIN
15pF
25Ω
AIN
525Ω
Figure 43. Using the AD8138 to Drive the AD9218
Rev. C | Page 18 of 28
02001-043
DIGITAL OUTPUTS
50Ω
ANALOG
SIGNAL
SOURCE
02001-042
Any high speed ADC is extremely sensitive to the quality of the
sampling clock provided by the user. A track-and-hold circuit is
essentially a mixer. Any noise, distortion, or timing jitter on the
clock is combined with the desired signal at the analog-todigital output. For that reason, considerable care has been taken
in the design of the ENCODE input of the AD9218, and the
user is advised to give commensurate thought to the clock
source. The ENCODE input is fully TTL/CMOS compatible.
AD9218
VOLTAGE REFERENCE
APPLICATION INFORMATION
A stable and accurate 1.25 V voltage reference is built into the
AD9218 (VREF OUT). Typically, the internal reference is used
by strapping Pin 5 (REFINA) and Pin 7 (REFINB) to Pin 6
(REFOUT). The input range for each channel can be adjusted
independently by varying the reference voltage inputs applied to
the AD9218. No appreciable degradation in performance
occurs when the reference is adjusted ±5%. The full-scale range
of the ADC tracks reference voltage, which changes linearly
(a 5% change in VREF results in a 5% change in full scale).
The wide analog bandwidth of the AD9218 makes it very
attractive for a variety of high performance receiver and
encoder applications. Figure 44 shows the dual ADC in a
typical low cost I and Q demodulator implementation for cable,
satellite, or wireless LAN modem receivers. The excellent
dynamic performance of the ADC at higher analog input
frequencies and encode rates lets users employ direct IF
sampling techniques. IF sampling eliminates or simplifies analog
mixer and filter stages to reduce total system cost and power.
AD9218
TIMING
The minimum guaranteed conversion rate is 20 MSPS. At clock
rates below 20 MSPS, dynamic performance degrades.
USER SELECT OPTIONS
Two pins are available for a combination of operational modes,
enabling the user to power down both channels, excluding the
reference, or just the B channel. Both modes place the output
buffers in a high impedance state. Recovery from a power-down
state is accomplished in 10 clock cycles following power-on.
The other option allows the user to skew the B channel output
data by one-half a clock cycle. In other words, if two clocks are
fed to the AD9218 and are 180 degrees out of phase, enabling
the data align allows Channel B output data to be available at
the rising edge of Clock A. If the same encode clock is provided
to both channels and the data align pin is enabled, output data
from Channel B is 180 degrees out of phase with respect to
Channel A. If the same encode clock is provided to both
channels and the data align pin is disabled, both outputs are
delivered on the same rising edge of the clock.
Rev. C | Page 19 of 28
BPF
IF IN
Q
ADC
90°
BPF
VCO
I
ADC
VCO
Figure 44. Typical I/Q Demodulation Scheme
02001-044
The AD9218 provides latched data outputs, with five pipeline
delays. Data outputs are available one propagation delay (tPD)
after the rising edge of the encode command (see Figure 2
through Figure 4). The length of the output data lines and loads
placed on them should be minimized to reduce transients
within the AD9218. These transients can detract from the
dynamic performance of the converter.
AD9218
AD9218/AD9288 CUSTOMER PCB BOM
Table 8. Bill of Materials
No.
Qty
Reference Designator
Device
Package
Value
1
29
Capacitor
0603
0.1 μF
2
3
4
2
7
28
Capacitor
Capacitor
W-HOLE
0603
TAJD
W-HOLE
15 pF
10 μF
5
6
7
8
4
5
3
3
C1, C3 to C15, C20, C21, C24,
C25, C27, C30 to C35, C39 to C42
C2, C36
C16–C19, C26, C37, C38
E1, E2, E3, E4, E12 to E30,
E34 to E38
H1, H2, H3, H4
J1, J2, J3, J4, J5
P1, P4, P11
P1, P4, P11
MTHOLE
SMA
4-lead power connector
4-lead power connector
MTHOLE
SMA
Post
Detachable
connector
9
1
P2, P31
80-lead rt. angle male
10
4
R1, R2, R32, R34
Resistor
0603
TSW-140-08L-D-RA
36 Ω
11
9
R3, R7, R11, R14, R22, R23, R24,
R30, R51
Resistor
0603
50 Ω
12
17
Resistor
0603
0Ω
R43, R50
not placed
13
2
R4, R5, R8, R9, R10, R12, R13,
R20, R33, R35, R36, R37, R40,
R42, R43, R50, R53
R6, R38
Resistor
0603
25 Ω
14
6
R15, R16, R18, R26, R29, R31
Resistor
0603
500 Ω
R6, R38
not placed
R16, R29
not placed
15
16
17
2
2
12
R17, R25
R19, R27
R21, R28, R39, R41, R44,
R46 to R49, R52, R54, R55
Resistor
Resistor
Resistor
0603
0603
0603
525 Ω
4 kΩ
1 kΩ
18
19
20
21
22
23
2
1
2
2
4
2
T1, T2
U1
U2, U3
U5, U6
U7, U8, U9, U10
U11, U12
Transformer
AD9288 or AD92182
74LCX821
SN74VCX86
Resistor array
AD8138 op amp3
ADT1-1WT
LQFP48
1
CTS
Z5.531.3425.0
25.602.5453.0
Rev. C | Page 20 of 28
8138 out
J2, J3 not placed
Wieland
Wieland
Samtec
R1, R2, R32, R34,
not placed
R11, R22, R23,
R24, R30, R51
not placed
Minicircuits
47 Ω
P2, P3 are implemented as one physical 80-lead connector SAMTEC TSW-140-08-L-D-RA.
AD9288/PCB populated with AD9288-100, AD9218-65/PCB populated with AD9218-65, AD9218-105/PCB populated with AD9218-105.
3
To use optional amp place R22, R23, R30, R24, R16, R29, remove R4, R36.
2
Comments
768203470G
AD9218
EVALUATION BOARD
The AD9218/AD9288 customer evaluation board offers an easy
way to test the AD9218 or the AD9288. The compatible pinout
of the two parts facilitates the use of one PCB for testing either
part. The PCB requires power supplies, a clock source, and a
filtered analog source for most ADC testing required.
POWER CONNECTOR
Power is supplied to the board via a detachable 12-lead power
strip. The minimum 3 V supplies required to run the board are
VD, VDL, and VDD. To allow the use of the optional amplifier
path, ±5 V supplies are required.
ANALOG INPUTS
Each channel has an independent analog path that uses a
wideband transformer to drive the ADC differentially from a
single-ended sine source at the input SMAs. The transformer
paths can be bypassed to allow the use of a dc-coupled path
using two AD8138 op amps with a simple board modification.
The analog input should be band-pass filtered to remove any
harmonics in the input signal and to minimize aliasing.
VOLTAGE REFERENCE
The AD9218 has an internal 1.25 V voltage reference; an
external reference for each channel can be employed instead
by connecting two external voltage references at the power
connector and setting jumpers at E18 and E19. The evaluation
board is shipped configured for internal reference mode.
CLOCKING
Each channel can be clocked by a common clock input at SMA
inputs ENCODE A and ENCODE B. The channels can also be
clocked independently by a simple board modification. The
clock input should be a low jitter sine source for maximum
performance.
DATA OUTPUTS
The data outputs are latched on board by two 10-bit latches
and drive an 8-lead connector, which is compatible with the dualchannel FIFO board that is available from Analog Devices, Inc.
This board, together with ADC analyzer software, can greatly
simplify ADC testing.
DATA FORMAT/GAIN
The DFS/GAIN pin can be biased for desired operation at the
DFS jumper located at the S1, S2 jumpers.
TIMING
Timing on each channel can be controlled, if needed, on the
PCB. Clock signals at the latches or the data ready signals that
go to the output 80-lead connector can be inverted if required.
Jumpers also allow for biasing of Pin S1 and Pin S2 for powerdown and timing alignment control.
TROUBLESHOOTING
If the board does not seem to be working correctly, try the
following:
•
•
•
•
Verify power at the IC pins.
Check that all jumpers are in the correct position for the
desired mode of operation.
Verify that VREF is at 1.23 V.
Try running encode clock and analog inputs at low speeds
(20 MSPS/1 MHz) and monitor the LCX821 outputs, DAC
outputs, and ADC outputs for toggling.
The AD9218 evaluation board is provided as a design example
for customers of Analog Devices. Analog Devices makes no
warranties, express, statutory, or implied, regarding
merchantability or fitness for a particular purpose.
Rev. C | Page 21 of 28
P1
GND
TIEA
C31
0.1µF
C14
0.1µF
1
2
3
4
VDL
VDD
GND
VD
2
3
4
7
R5
0Ω
R4
0Ω
AMPOUTAB
R2
36Ω
GND
GND
R1
36Ω
AMPOUTA
1
2
3
4
VREFA
GND
GND
P11
R36
0Ω
R37
0Ω
AMPOUTB
R32
36Ω
GND
GND
R34
36Ω
VREFB
R35
0Ω
5
4
2
3
T1
6
1
AMPOUTBB
R SINGLE-ENDED
R SINGLE-ENDED
4
5
3
6
2
6
GND
R38
25Ω
GND
+5V
–5V
GND
E30
E25
C39
0.1µF
C30
0.1µF
VD
VDD
VDL
P6
P7
AIN B
AIN B
11
C18 +
10µF
VDL
C5
0.1µF
GND
S2
GND
GND
AD9218
U1
VREFB
C6
0.1µF
C26 +
10µF
VREFA
C8
0.1µF
GND
GND
R54
1kΩ
R52
1kΩ
VDL
C42
0.1µF
TIEB
R51
51Ω
ENCODE B
J2
C19 +
10µF
S1
9
10
8
REFOUT
REFIN A
REFIN B
12
VD
DFS/GAIN
AIN A
AIN A
GND
7
6
VDD
C17 +
10µF
VD
C16 +
10µF
GND
P5
+5V
C38 +
+ 10µF
–5V
GND
E19
5
4
3
2
1
C7
0.1µF
VDL
E15
VDL
E12
GND
GND
GND
R47
1kΩ
GND
E14
R46
1kΩ
E13
E1
E20
VREFA
E18
GND
E17
CLKLATA
DRA
VDL
VD E29 E24
E22
C37
10µF
GND
GND
E27
VD
E2
REFOUT
GND
R9
0Ω
C9
0.1µF
VD E28 E23
E26
R6
25Ω
3Y 8
R10
0Ω
C25
0.1µF
C10
0.1µF
3A 9
GND
3B 10
2B
2Y
4Y 11
2A
4
5
4A 12
4B 13
1Y
1B
VCC 14
ENCA
1A
3
2
1
ENCXA
GND
R44
1kΩ
E4
R33
0Ω
1
T2
E3
GND
1
C15
0.1µF
C13
0.1µF
C12
0.1µF
P4
R43
0Ω
VDL
C11
0.1µF
GND
AMPINB
GND
GND
AMPINA
R7
50Ω
GND
AIN B
GND
J1
GND
R41
1kΩ
R39
1kΩ
VDL
R3
50Ω
GND
C40
0.1µF
AIN A
GND
J4
GND
R11
50Ω
ENCODE A
J3
ENCA
VDD
R42
0Ω
GND
GND
2B 5
3B
GND
GND 32
GND
D0B
D1B
GND 29
VDD 28
GND 27
D0B 26
D1B 25
REFIN B
C24
0.1µF
GND
GND
VD 30
VD 31
VDD 33
GND
D0A
D0A 35
GND 34
GND
GND
J5
VD
MTHOLE6
H4
MTHOLE6
H2
MTHOLE6
H1
MTHOLE6
H3
GND
R14
50Ω
R8
0Ω
ENCB
R40
0Ω
R20
0Ω
TIEB
TIEA
GND
TO TIE CLOCKS TOGETHER
VDD
C3
0.1µF
R55
1kΩ
GND
E37
E34
R48
1kΩ
DRB
CLKLATB
GND R12
0Ω
VDL
E38
VDL
E16
**DUT CLOCK SELEC TABLE**
**TO BE DIRECT OR BUFFERED**
R13
0Ω
GND
ENCA
GND
C1
0.1µF
1A 1
VCC
VDD
1B 2
4B
13
GND
1Y 3
4A
12
14
2A 4
4Y
11
D1A
GND
C41
0.1µF
VDL
GND
R49
1kΩ
C4
0.1µF
2Y 6
3A
10
GND 7
3Y
E36
9
E35
SN74VCX86
8
U5
R50
0Ω
ENCB
ENCXB
R53
0Ω
D1A 36
VDL
REF INA
C27
0.1µF
GND
16
GND
ENCXA
GND
D9B
17
(MSB) D9B
GND
D9A (MSB)
18 D8B
D7B
D7 B
U6
SN74VCX86
D8A
D9A 44
20
D6B
VDD 46
ENCXB
D7A
21
D5 B
VD 48
VD
13
VD
D6A
D8A 43
D7A 42
19
22
D4 B
ENC A 47
ENCB
14
ENCB
D5A
D6A 41
D6B
23
D8 B
VDD
15
VDD
GND 45
GND
D4A
D5A 40
D5B
D3A
D4A 39
D4B
D2A
D3A 38
D3B
D2A 37
D2B
24
D3 B
Rev. C | Page 22 of 28
D2 B
Figure 45. PCB Schematic
02001-045
**DUT CLOCK SELEC TABLE**
**TO BE DIRECT OR BUFFERED**
AD9218
Figure 46. PCB Schematic (Continued)
Rev. C | Page 23 of 28
C34
0.1µF
–5V
R29
500Ω
5
5
V+ 3
R22
50Ω
R30
50Ω
GND
C35
0.1µF
R21
1kΩ
R19
4kΩ
+5V
GND
R28
1kΩ
R27
4kΩ
GND
+5V
R25
525Ω
GND
AMPOUTBB
U12
+OUT 4
C36
15pF
–OUT
V–
VOCM 2
NC
7
6
–IN 1
+IN
AD8138
C32
0.1µF
GND
+5V
+5V
R17
525Ω
AMPINA
AMPOUTA
U11
8
AMPOUTB
R24
50Ω
V+ 3
+OUT 4
C2
15pF
–OUT
V–
VOCM 2
NC
7
6
–IN 1
+IN
AD8138
8
AMPOUTAB
R23
50Ω
AMPINB
C33
0.1µF
–5V
NC = NO CONNECT
R31
500Ω
R15
500Ω
R16
500Ω
GND
OPAMP INPUT OFF PIN ONE OF TRANSFORMER
R26
500Ω
R18
500Ω
5 5
D5A
5 5
D4B
8 8
9 9
10 10
D7B
D8B
D9B
7 7
4 4
D3B
D6B
3 3
D2B
6 6
2 2
D5B
1 1
D1B
10 10
D0A
D0B
9 9
D1A
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
U8
CTS20
VALUE = 50
8 8
D2A
7 7
4 4
D6A
D3A
3 3
D7A
6 6
2 2
D8A
D4A
1 1
D9A
U7
CTS20
VALUE = 50
CLK 13
10 X8
11 X9
12 GND
D7N
D8N
D9N
GND
D8N
D9N
9 X7
D6N
8 X6
7 X5
6 X4
5 X3
4 X2
3 X1
2 X0
1 OE
Y9 14
Y8 15
Y7 16
Y6 17
Y5 18
Y4 19
Y3 20
Y2 21
Y1 22
Y0 23
VCC 24
CLK 13
Y9 14
Y8 15
Y7 16
Y6 17
Y5 18
Y4 19
Y3 20
Y2 21
Y1 22
Y0 23
VCC 24
U3
74LCX821
9 X7
D7N
D5N
D3N
D4N
D6N
D2N
D3N
D4N
D1N
D2N
D5N
D0N
GND
GND
12 GND
D0M
D1N
11 X9
D1M
D0M
D0N
10 X8
D2M
D1M
8 X6
7 X5
D3M
6 X4
5 X3
D2M
D6M
D5M
4 X2
D4M
D7M
D6M
3 X1
D3M
D8M
D7M
2 X0
1 OE
D5M
D9M
D8M
D4M
GND
D9M
U2
74LCX821
GND
5 5
3 3
1 1
6 6
4 4
2 2
GND
9 9
10 10
7 7
11 11
12 12
8 8
GND
13 13
GND
GND
GND
GND
GND
D0Q
D1Q
14 14
D2Q
D3Q
D4Q
D5Q
D6Q
D7Q
D8Q
D9Q
GND
DRB
GND
15 15
19 19
21 21
23 23
25 25
27 27
29 29
31 31
33 33
35 35
37 37
39 39
16 16
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
40 40
17 17
D9Q
D8Q
D7Q
D6Q
D5Q
D4Q
D3Q
D2Q
D1Q
D0Q
GND
GND
18 18
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
1 1
2 2
GND
CLKLATB
10 10
9 9
8 8
7 7
6 6
5 5
4 4
3 3
2 2
1 1
3 3
4 4
GND
20 20
D9Y
D8Y
D7Y
D6Y
D5Y
D4Y
D3Y
D2Y
D1Y
D0Y
5 5
6 6
P2
HEADER40
7 7
8 8
D0P
D9Y
D8Y
D7Y
D6Y
D5Y
D4Y
D3Y
D2Y
D1Y
D0Y
VDL
U10
CTS20
VALUE = 50
GND
9 9
10 10
C20
0.1µF
GND
GND
11 11
12 12
GND
GND
13 13
D1P
14 14
D2P
D3P
D4P
D5P
D6P
D7P
D8P
D9P
GND
DRA
GND
15 15
19 19
21 21
23 23
25 25
27 27
29 29
31 31
33 33
35 35
37 37
39 39
16 16
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
40 40
17 17
D0P
D1P
D2P
D3P
D4P
D5P
D6P
D7P
D8P
D9P
18 18
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
CLKLATA
10 10
9 9
8 8
7 7
6 6
5 5
4 4
3 3
2 2
1 1
P3
HEADER40
20 20
D0X
D1X
D2X
D3X
D4X
D5X
D6X
D7X
D8X
D9X
U9
CTS20
VALUE = 50
D0X
D1X
D2X
D3X
D4X
D5X
D6X
D7X
D8X
D9X
VDL
C21
0.1µF
GND
AD9218
02001-046
02001-050
02001-047
AD9218
Figure 47. Top Silkscreen
Figure 48. Top Routing
02001-051
02001-048
Figure 50. Split Power Plane
Figure 49. Ground Plane
02001-052
02001-049
Figure 51. Bottom Routing
Figure 52. Bottom Silkscreen
Rev. C | Page 24 of 28
AD9218
OUTLINE DIMENSIONS
9.20
9.00 SQ
8.80
1.60
MAX
37
48
36
1
PIN 1
0.15
0.05
7.20
7.00 SQ
6.80
TOP VIEW
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
SEATING
PLANE
VIEW A
(PINS DOWN)
25
12
13
VIEW A
0.50
BSC
LEAD PITCH
24
0.27
0.22
0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
051706-A
0.75
0.60
0.45
Figure 53. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9218BST-40
AD9218BST-RL40
AD9218BSTZ-40 1
AD9218BSTZ-RL401
AD9218BST-65
AD9218BST-RL65
AD9218BSTZ-651
AD9218BSTZ-RL651
AD9218BST-80
AD9218BST-RL80
AD9218BSTZ-801
AD9218BSTZ-RL801
AD9218BST-105
AD9218BST-RL105
AD9218BSTZ-1051
AD9218BSTZ-RL1051
AD9218-65PCB
AD9218-105PCB
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
−40°C to +85°C
Package Description
48-Lead Low Profile Quad Flat Pack (LQFP)
48-Lead Low Profile Quad Flat Pack (LQFP)
48-Lead Low Profile Quad Flat Pack (LQFP)
48-Lead Low Profile Quad Flat Pack (LQFP)
48-Lead Low Profile Quad Flat Pack (LQFP)
48-Lead Low Profile Quad Flat Pack (LQFP)
48-Lead Low Profile Quad Flat Pack (LQFP)
48-Lead Low Profile Quad Flat Pack (LQFP)
48-Lead Low Profile Quad Flat Pack (LQFP)
48-Lead Low Profile Quad Flat Pack (LQFP)
48-Lead Low Profile Quad Flat Pack (LQFP)
48-Lead Low Profile Quad Flat Pack (LQFP)
48-Lead Low Profile Quad Flat Pack (LQFP)
48-Lead Low Profile Quad Flat Pack (LQFP)
48-Lead Low Profile Quad Flat Pack (LQFP)
48-Lead Low Profile Quad Flat Pack (LQFP)
Evaluation Board (Supports -40/-65 Grade)
Evaluation Board (Supports -80/-105 Grade)
Z = Pb-free part.
Rev. C | Page 25 of 28
Package Option
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
AD9218
NOTES
Rev. C | Page 26 of 28
AD9218
NOTES
Rev. C | Page 27 of 28
AD9218
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02001-0-12/06(C)
Rev. C | Page 28 of 28