FER5VC4S1 Extra Low Capacitance for Integrated ESD Mechanical Data Notes Dice size AX:600um,BX:420um/P1,3,4,6-85*95um/Pin 5-270*105um Wafer size 4” (Gross die:27,500pcs/Good die>25,575pcs) Chip Thickness (A)138um±12um (B)470um±20um Scribe line width 60um Top metal Al/Au/Ag Back side metal Al/Au/Ag/Sn Parameter Symbol Reverse stand-off voltage Peak pulse power Peak pulse current VRWM PPP IPP Electrostatic discharge VESD Max.junction temp. Conditions Value Unit Tp=8/20us Tp=8/20us 5.0 150** 5.0** V W A ± 15(AIR) KV +150 ℃ IEC61000-4-2 Level 4 Tj Characteristics TA=25℃ Parameter Breakdown voltage Symbol VBR Reverse leakage current IR Forward Voltage VF Clamping Voltage VC Diode capacitance I/O-GND CI/O-GND Diode capacitance I/O-I/O CI/O-I/O Condition IT=1mA Pin 5 to 2 VR=5V Pin 1,3,4,5,6 to 2 1F=15mA Pin2 to Pin1,3,4,5,6 IPP=1A IPP=5A VR=0V f=1MHZ VR=0V f=1MHZ Min. Typ. Max. Unit 6.1 8.0 8.5 V 0.9 uA 0.95 V 15.0 28.0 V 0.8 pf 0.4 pf Notes: (1)sampling testing:no bad dice inking/guaranteed good die >93% (2)Testing follow customer (3)Tj=Ta+Rth(j-a)*(pf+pr),where Rth(j-a)-thermal resistance,Pf-forward power dissipation, Pr-revers power dissipation (4)**For device testing EW1608A5-FW-A Futurewafer Technology Co.,Ltd www.futurewafer.com.tw+886-3-3573583