TI1 AFE7686 Quad/dual-channel, rf sampling analog front-end with 14-bit 9gsps dacs and 14-bit 3gsps adc Datasheet

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AFE76xx Quad/Dual-Channel, RF Sampling Analog Front-End
with 14-Bit 9GSPS DACs and 14-Bit 3GSPS ADCs
1 Device Overview
1.1
Features
1
• 14-Bit Resolution
• Sample Rate:
– DAC: 9 GSPS
– ADC: 3 GSPS
• RF Frequency Range: Up to 5.2 GHz
• Maximum RF Signal Bandwidth
– Quad-Channel Mode (4T4R): 800 MHz (singleband); 300 MHz (dual-band)
– Dual-Channel Mode (2T2R): 1200 MHz
(TX)/1000 MHz (RX) (single-band);
800MHz(dual-band)
• On-Chip Dual Selectable DSAs per RX Channel
• Integrated TX DSA Functionality
• Digital:
– Dual Band Digital Up-Converters (DUCs)
– Dual Band Digital Down-Converters (DDCs)
1.2
•
•
•
•
•
Applications
Cellular Base Stations
Wideband Communications
1.3
•
– 32-Bit NCOs for DUCs/DDCs
– Interpolation Ratio: 6x, 8x, 9x, 12x, 16x, 18x,
24x, 36x
– Decimation Ratio: /2, /3, /4, /6, /8, /9, /12, /16,
/18, /24, /32
– RX/FB Dynamic Switching for TDD
Interface:
– 8 SerDes Transceivers up to 15Gbps
– 16-Bit and 12-Bit JESD204B Transport Layer
Formatting with 8b/10b Encoding
– Subclass 1 Multi-Device Synchronization
Clock:
– Internal PLL/VCO to Generate DAC and ADC
Clocks
Package: 17mm x 17mm FC BGA, 0.8mm Pitch
Power Supplies: 1.85 V, 1.15 V, 1.0 V, –1.8 V
•
•
Microwave Backhaul
Distributed Antenna Systems (DAS)
Description
The AFE76xx is a family of high performance, quad/dual channel, 14-bit, integrated RF sampling analog
front ends (AFEs) with 9 GSPS DACs and 3 GSPS ADCs, capable of synthesizing and digitizing wideband
signals. High dynamic range allows the AFE76xx to generate and digitize 3G/4G signals for wireless base
stations. In TDD mode, the receiver channel can be configured to dynamically switching between traffic
receiver (TDD RX) status and wideband feedback receiver (TDD FB) status to assist DPD (Digital PreDistortion) of the Power Amplifier (PA) on the transmitter path.
The AFE76xx family has integrated DSA on the receiver channels and also supports DSA equivalent
functionality on the transmitter channels. Each receiver channel has one analog RF peak power detector
and various digital power detectors to assist AGC control for receiver channels, and two RF overload
detectors for device reliability protection. The AFE76xx family has 8 of JESD204B compatible SerDes
transceivers running up to 15 Gbps. The devices have up to two DUCs per TX channel and two DDCs per
RX channel, with multiple interpolation/decimation rates and digital quadrature modulators/demodulators
with independent, frequency flexible NCOs. The devices support more than 1000 MHz (800 MHz as
4T4R) RF signal bandwidth in single-band mode, and up to 800 MHz (300 MHz as 4T4R) RF signal
bandwidth per band in dual-band mode. A low jitter PLL/VCO simplifies the sampling clock generation by
allowing use of a lower frequency reference clock.
Table 1-1. Device Information (1)
PART NUMBER
AFE7685
(1)
(2)
1
(2)
PACKAGE
BODY SIZE
FC-BGA
17.00 mm x 17.00 mm
For all available packages, see the orderable addendum at the end of the data sheet.
Product Preview
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains ADVANCE
INFORMATION for pre-production products; subject to change without notice.
AFE7683, AFE7684
AFE7685, AFE7686
SLASEQ7 – MAY 2018
www.ti.com
Table 1-1. Device Information(1) (continued)
PACKAGE
BODY SIZE
AFE7686
PART NUMBER
FC-BGA
17.00 mm x 17.00 mm
AFE7683 (2)
FC-BGA
17.00 mm x 17.00 mm
AFE7684 (2)
FC-BGA
17.00 mm x 17.00 mm
VDDTX18AB
VDDTXAB
TXB DSA
DUC
NCO
NCO
DAC
TXAP/M
DUC
NCO
NCO
NCO
NCO
DUC
Traffic Controller
TXA DSA
DSA
RXADSA1P/M
MUX
DSA
ADC
ADC
DDC
SYNCB2CMOS
SYNCB3CMOS
TX2ENABLE
ALARMTX2
RXCDSAFAST
RXDDSAFAST
TXTDD2
RXTDD2
RXFBSW2
FBBANDSEL2
RXCDSA1PD
RXCDSA2PD
RXDDSA1PD
RXDDSA2PD
RXCPD2H
RXCPD2L
RXDPD2H
RXDPD2L
TXDP/M
DAC
NCO
NCO
DUC
RX1P8V
RX1P2V
Buffer
SHA
VEE18CD
VDDL1CD
VDDL2CD
DVDD
TXD DSA
DAC
TXBP/M
SPIBSEN
SPIBSCLK
SPIBSDIO
SPIBSDO
RESET
SLEEPMODE
PLLCLKLD
PLLREFLD
VDDGPIO18
VDDCLK
RXDSASW
TXDSASW
CLKOUTP/M
Temp Sensor
TXCP/M
DAC
TXC DSA
RX1P8V
RX1P2V
DSA
RXCDSA1P/M
DDC
ADC
Buffer SHA
MUX
VDDL2AB
DVDD
VDDTX18CD
VDDTXCD
Divider
/2, /3, /4
Low jitter PLL
VEE18AB
VDDL1AB
VDDATX
VDDATX18
VDDCLK
SYSREFP/M
VDDAPLL
VDDAVCO18
VDDAPLL18
CLKP/M
SPIASDO
SPIASDIO
SPIASCLK
SPIASEN
RXBDSA2PD
RXBDSA1PD
RXADSA2PD
RXADSA1PD
FBBANDSEL1
RXFBSW1
RXTDD1
TXTDD1
RXBDSAFAST
RXADSAFAST
RXBPD2L
RXBPD2H
RXAPD2L
RXAPD2H
ALARMTX1
TX1ENABLE
Functional Block Diagram
SYNCB0CMOS
SYNCB1CMOS
1.4
DSA
RXCDSA2P/M
RXADSA2P/M
DVDD
NCO NCO
NCO
NCO
FSPICLKA
FSPIDA
DVDD
FSPICLKD
FSPIDD
NCO NCO
NCO
NCO
DSA
DSA
RXDDSA1P/M
MUX
DSA
Buffer
SHA
ADC
ADC
ADC
DDC
DDC
Buffer SHA
MUX
RXBDSA1P/M
DSA
RXDDSA2P/M
RXBDSA2P/M
FSPICLKC
FSPIDC
FSPICLKB
FSPIDB
TCLK
TCLK
TDI
TDO
TRSTB
VDDT
VDDR
VDDA
DVDD
SRX8P/M
SRX5P/M
SYNCBOUT1P/M
SYNCBIN1P/M
JTAG
STX8P/M
STX5P/M
STX4P/M
STX1P/M
SYNCBINP/M
SYNCBOUT0P/M
SRX4P/M
SRX1P/M
SerDes
Figure 1-1. Functional Block Diagram of AFE76xx
2
Device Overview
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Divider
/2, /3, /4
Low jitter PLL
SYNCB2CMOS
SYNCB3CMOS
TX2ENABLE
ALARMTX2
RXCDSAFAST
RXDDSAFAST
RXCDSA1PD
RXCDSA2PD
RXDDSA1PD
RXDDSA2PD
RXCPD2H
RXCPD2L
RXDPD2H
RXDPD2L
TXTDD2
RXTDD2
RXFBSW2
FBBANDSEL2
SPIBSEN
SPIBSCLK
SPIBSDIO
SPIBSDO
RESET
SLEEPMODE
PLLCLKLD
PLLREFLD
VDDGPIO18
VDDCLK
RXDSASW
TXDSASW
CLKOUTP/M
VDDATX
VDDATX18
VDDCLK
SYSREFP/M
VDDAPLL
VDDAVCO18
VDDAPLL18
CLKP/M
SPIASDO
SPIASDIO
SPIASCLK
SPIASEN
RXBDSA2PD
RXBDSA1PD
RXADSA2PD
RXADSA1PD
FBBANDSEL1
RXFBSW1
RXTDD1
TXTDD1
RXBDSAFAST
RXADSAFAST
RXBPD2L
RXBPD2H
RXAPD2L
RXAPD2H
ALARMTX1
TX1ENABLE
SLASEQ7 – MAY 2018
SYNCB0CMOS
SYNCB1CMOS
www.ti.com
Temp Sensor
VDDTX18AB
VDDTXAB
VDDTX18CD
VDDTXCD
VEE18AB
VDDL1AB
NCO
NCO
VDDL2AB
DVDD
DAC
NCO
NCO
DUC
NCO
NCO
DUC
TXC DSA
TXA DSA
Traffic Controller
RX1P8V
RX1P2V
DSA
RXADSA1P/M
MUX
DSA
Buffer
SHA
TXCP/M
DAC
ADC
ADC
DDC
RXADSA2P/M
DVDD
DSA
RXCDSA1P/M
DDC
ADC
Buffer SHA
DSA
RXCDSA2P/M
NCO NCO
NCO
NCO
FSPICLKA
FSPIDA
RX1P8V
RX1P2V
MUX
TXAP/M
NCO
NCO
VEE18CD
VDDL1CD
VDDL2CD
DVDD
DVDD
FSPICLKD
FSPIDD
NCO NCO
NCO
NCO
DSA
DSA
RXDDSA1P/M
MUX
DSA
Buffer
SHA
ADC
ADC
ADC
DDC
DDC
Buffer SHA
MUX
RXBDSA1P/M
DSA
RXDDSA2P/M
RXBDSA2P/M
FSPICLKC
FSPIDC
FSPICLKB
FSPIDB
TCLK
TCLK
TDI
TDO
TRSTB
VDDT
VDDR
VDDA
DVDD
SRX8P/M
SRX5P/M
SYNCBOUT1P/M
SYNCBIN1P/M
JTAG
STX8P/M
STX5P/M
STX4P/M
STX1P/M
SYNCBINP/M
SYNCBOUT0P/M
SRX4P/M
SRX1P/M
SerDes
Figure 1-2. Functional Block Diagram of AFE7683/AFE7684
2 Revision History
DATE
REVISION
NOTES
May 2018
*
AFE7686 Advance Information Release
Revision History
Copyright © 2018, Texas Instruments Incorporated
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3
AFE7683, AFE7684
AFE7685, AFE7686
SLASEQ7 – MAY 2018
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3 Device Comparison
Table 3-1. Device Features Comparison
# of TXs/RXs
# of DUCs/TX
# of DDCs/RX
MAX INPUT/OUTPUT
DATA RATE (MSPS)
AFE7685 (1)
4T4R
1
1
750
AFE7686
4T4R
2
2
1500
AFE7683 (1)
2T4R
1
1
750
AFE7684 (1)
2T4R
2
2
1500
DEVICE
(1)
4
Product Preview
Device Comparison
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AFE7683, AFE7684
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SLASEQ7 – MAY 2018
4 Device and Documentation Support
4.1
4.1.1
Device Support
Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES
NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR
SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR
SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
4.2
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To receive notification of documentation updates, navigate to the device product folder on ti.com. In the
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has changed. For change details, review the revision history included in any revised document.
The current documentation that describes the DSP, related peripherals, and other technical collateral is
listed below.
4.2.1
Related Documentation
AFE76xx EVM Design Document User's Guide (SLAU761)
AFE76xx Technical Reference Manual (SLAU744)
AFE76xx Programmer's User's Guide (SLAU767)
4.3
Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4-1. Related Links
4.4
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AFE7686
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Community Resources
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respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
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All other trademarks are the property of their respective owners.
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4.6
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Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
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Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
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extent required by those laws.
4.8
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
6
Device and Documentation Support
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5 Mechanical, Packaging, and Orderable Information
5.1
Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2018, Texas Instruments Incorporated
Mechanical, Packaging, and Orderable Information
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PACKAGE OPTION ADDENDUM
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30-May-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
PAFE7686ABJ
ACTIVE
Package Type Package Pins Package
Drawing
Qty
FCBGA
ABJ
400
90
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
TBD
Call TI
Call TI
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
XAFE76XX
B0
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
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