AD ADP2138CB-0.8EVALZ Compact, 800 ma, 3 mhz, step-down dc-to-dc converter Datasheet

Compact, 800 mA, 3 MHz,
Step-Down DC-to-DC Converter
ADP2138/ADP2139
Data Sheet
FEATURES
GENERAL DESCRIPTION
Input voltage: 2.3 V to 5.5 V
Peak efficiency: 95%
3 MHz fixed frequency operation
Typical quiescent current: 24 μA
Very small solution size
6-lead, 1 mm × 1.5 mm WLCSP package
Fast load and line transient response
100% duty cycle low dropout mode
Internal synchronous rectifier, compensation, and soft start
Current overload and thermal shutdown protections
Ultralow shutdown current: 0.2 μA (typical)
Forced PWM and automatic PWM/PSM modes
Supported by ADIsimPower™ design tool
The ADP2138 and ADP2139 are high efficiency, low quiescent
current, synchronous step-down dc-to-dc converters. The
ADP2139 has the additional feature of an internal discharge
switch. The total solution requires only three tiny external
components. When the MODE pin is set high, the buck
regulator operates in forced PWM mode, which provides low
peak-to-peak ripple for power supply noise sensitive loads at
the expense of light load efficiency. When the MODE pin is set
low, the buck regulator automatically switches operating modes,
depending on the load current level. At higher output loads, the
buck regulator operates in PWM mode. When the load current
falls below a predefined threshold, the regulator operates in power
save mode (PSM), improving light load efficiency.
APPLICATIONS
The ADP2138/ADP2139 operate on input voltages of 2.3 V to
5.5 V, which allows for single lithium or lithium polymer cell,
multiple alkaline or NiMH cell, PCMCIA, USB, and other
standard power sources. The maximum load current of 800 mA
is achievable across the input voltage range.
PDAs and palmtop computers
Wireless handsets
Digital audio, portable media players
Digital cameras, GPS navigation units
The ADP2138/ADP2139 are available in fixed output voltages of
3.3 V, 3.0 V, 2.8 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V, and 0.8 V. All
versions include an internal power switch and synchronous rectifier for minimal external part count and high efficiency. The
ADP2138/ADP2139 have internal soft start and they are internally
compensated. During logic controlled shutdown, the input is
disconnected from the output and the ADP2138/ADP2139
draw 0.2 μA (typical) from the input source.
Other key features include undervoltage lockout to prevent deep
battery discharge, and soft start to prevent input current overshoot at startup. The ADP2138/ADP2139 are available in a 6-ball
wafer level chip scale package (WLCSP).
TYPICAL APPLICATIONS CIRCUIT
1.0µH
2.3V TO 5.5V
VIN
4.7µF
VOUT
SW
ADP2138/
ADP2139
4.7µF
ON
OFF
EN
VOUT
FORCE
PWM
MODE
GND
09496-001
AUTO
Figure 1.
Rev. C
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ADP2138/ADP2139
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Short-Circuit Protection............................................................ 12
Applications ....................................................................................... 1
Undervoltage Lockout ............................................................... 12
General Description ......................................................................... 1
Thermal Protection .................................................................... 12
Typical Applications Circuit............................................................ 1
Soft Start ...................................................................................... 12
Revision History ............................................................................... 2
Current Limit .............................................................................. 12
Specifications..................................................................................... 3
100% Duty Operation ................................................................ 12
Input and Output Capacitor, Recommended Specifications .. 3
Discharge Switch ........................................................................ 12
Absolute Maximum Ratings ............................................................ 4
Applications Information .............................................................. 13
Thermal Resistance ...................................................................... 4
ADIsimPower Design Tool ....................................................... 13
ESD Caution .................................................................................. 4
External Component Selection ................................................ 13
Pin Configuration and Function Descriptions ............................. 5
Thermal Considerations............................................................ 14
Typical Performance Characteristics ............................................. 6
PCB Layout Guidelines.............................................................. 14
Theory of Operation ...................................................................... 11
Evaluation Board ............................................................................ 15
Control Scheme .......................................................................... 11
Evaluation Board Layout ........................................................... 15
PWM Mode ................................................................................. 11
Outline Dimensions ....................................................................... 16
Power Save Mode ........................................................................ 11
Ordering Guide .......................................................................... 17
Enable/Shutdown ....................................................................... 11
REVISION HISTORY
1/13—Rev. B to Rev. C
Change to Figure 18, Caption ........................................................ 8
Change to Figure 28, Caption ....................................................... 10
6/12—Rev. A to Rev. B
Change to Features Section ............................................................. 1
Added ADIsimPower Design Tool Section ................................. 13
Changes to Ordering Guide .......................................................... 17
4/11—Rev. 0 to Rev. A
Change to Features Section ............................................................. 1
Added Figure 32, Renumbered Figures Sequentially ................ 10
Changes to Ordering Guide .......................................................... 16
1/11—Revision 0: Initial Version
Rev. C | Page 2 of 20
Data Sheet
ADP2138/ADP2139
SPECIFICATIONS
VIN = 3.6 V, VOUT = 0.8 V − 3.3 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications,
unless otherwise noted. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
Table 1.
Parameter
INPUT CHARACTERISTICS
Input Voltage Range
Undervoltage Lockout Threshold
OUTPUT CHARACTERISTICS
Output Voltage Accuracy
Line Regulation
Load Regulation
Test Conditions/Comments
Min
SW CHARACTERISTICS
SW On Resistance
Current Limit
Discharge Switch (ADP2139)
ENABLE AND MODE CHARACTERISTICS
Input High Threshold
Input Low Threshold
Input Leakage Current
Max
Unit
2.15
5.5
2.3
2.25
V
V
V
+2
0.25
−0.95
%
%/V
%/A
100
mA
2.3
VIN rising
VIN falling
2.00
PWM mode
VIN = 2.3 V to 5.5 V, PWM mode
ILOAD = 0 mA − 800 mA
−2
PWM TO POWER SAVE MODE CURRENT THRESHOLD
INPUT CURRENT CHARACTERISTICS
DC Operating Current
Shutdown Current
Typ
ILOAD = 0 mA, device not switching
EN = 0 V, TA = TJ = −40°C to +85°C
23
0.2
30
1.0
μA
μA
PFET
NFET
PFET switch peak current limit
155
115
1500
100
240
200
1650
mΩ
mΩ
mA
Ω
1100
1.2
EN/MODE = 0 V (min), 3.6 V (max )
OSCILLATOR FREQUENCY
−1
0
0.4
+1
2.6
3.0
3.4
V
V
μA
MHz
START-UP TIME
250
μs
THERMAL CHARACTERISTICS
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
150
20
°C
°C
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
TA = −40°C to +125°C, unless otherwise specified. All limits at temperature extremes are guaranteed via correlation using standard
statistical quality control (SQC).
Table 2.
Parameter
MINIMUM INPUT AND OUTPUT CAPACITANCE
CAPACITOR ESR
Symbol
CMIN
RESR
Rev. C | Page 3 of 20
Min
4.7
0.001
Typ
Max
1
Unit
µF
Ω
ADP2138/ADP2139
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN, EN, MODE
VOUT, SW to GND
Temperature Range
Operating Ambient
Operating Junction
Storage Temperature
Lead Temperature Range
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
ESD Model
Human Body
Charged Device
Machine
Rating
−0.4 V to +6.5 V
−1.0 V to (VIN + 0.2 V)
−40°C to +85°C
−40°C to +125°C
−65°C to +150°C
−65°C to +150°C
300°C
215°C
220°C
±1500 V
±500 V
±100 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending on
PCB material, layout, and environmental conditions. The specified
values of θJA are based on a 4-layer, 4 in. × 3 in., circuit board. Refer
to JEDEC JESD 51-9 for detailed information pertaining to board
construction. For additional information, see AN-617 Application
Note, MicroCSPTM Wafer Level Chip Scale Package.
ΨJB is the junction-to-board thermal characterization parameter
measured in units of °C/W. ΨJB of the package is based on modeling
and calculation using a 4-layer board. The JESD51-12, Guidelines
for Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as thermal
resistances. ΨJB measures the component power flowing through
multiple thermal paths rather than through a single path, which
is the procedure for measuring thermal resistance, θJB. Therefore, ΨJB thermal paths include convection from the top of the
package as well as radiation from the package; factors that make
ΨJB more useful in real-world applications than θJB. Maximum
junction temperature (TJ) is calculated from the board temperature
(TB) and power dissipation (PD) using the formula
TJ = TB + (PD × ΨJB)
Refer to JEDEC JESD51-8 and JESD51-12 for more detailed
information about ΨJB.
Absolute maximum ratings apply individually only, not in
combination.
ADP2138/ADP2139 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does
not guarantee that the junction temperature (TJ) is within the
specified temperature limits. In applications with high power
dissipation and poor thermal resistance, the maximum ambient
temperature may need to be derated. In applications with moderate power dissipation and low printed circuit board (PCB)
thermal resistance, the maximum ambient temperature can
exceed the maximum limit for as long as the junction temperature
is within specification limits. The junction temperature (TJ) of
the device is dependent on the ambient temperature (TA), the
power dissipation of the device (PD), and the junction-to-ambient
thermal resistance of the package (θJA). Maximum junction
temperature (TJ) is calculated from the ambient temperature
(TA) and power dissipation (PD) using the formula
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
6-Ball WLCSP
ESD CAUTION
TJ = TA + (PD × θJA)
Rev. C | Page 4 of 20
θJA
170
ΨJB
80
Unit
°C/W
Data Sheet
ADP2138/ADP2139
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VIN
EN
1
4
SW
MODE
2
5
GND VOUT
6
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
09496-002
3
Figure 2. Pin Configuration (Top View)
Table 5. Pin Function Descriptions
Pin No.
1
Mnemonic
VIN
2
SW
3
4
5
GND
EN
MODE
6
VOUT
Description
Power Source Input. VIN is the source of the PFET high-side switch. Bypass VIN to GND with a 4.7 μF or greater
capacitor as close to the ADP2138/ADP2139 as possible.
Switch Node Output. SW is the drain of the P-channel MOSFET switch and N-channel synchronous rectifier.
Connect the output LC filter between SW and the output voltage.
Ground. Connect the input and output capacitors to GND.
Buck Activation. To turn on the buck, set EN to high. To turn off the buck, set EN to low.
Mode Input. Drive the MODE pin high for the operating mode to force continuous PWM switching. Drive the MODE
pin low to allow automatic PWM/PSM operating mode.
Output Voltage Sensing Input.
Rev. C | Page 5 of 20
ADP2138/ADP2139
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
100
100
90
90
80
80
70
70
EFFICIENCY (%)
60
50
40
0.01
0.1
10
1
IOUT (A)
0
0.001
100
90
90
80
80
70
70
EFFICIENCY (%)
1
60
50
40
30
60
50
40
30
VIN = 2.3V
VIN = 3.6V
VIN = 4.2V
VIN = 5.5V
10
0.01
0.1
20
VIN = 3.9V
VIN = 4.2V
VIN = 5.5V
10
1
IOUT (A)
0
0.001
09496-004
20
0.01
0.1
1
IOUT (A)
Figure 4. Efficiency vs. Load Current, Across Input Voltage,
VOUT = 1.8 V, PWM Mode
09496-007
EFFICIENCY (%)
0.1
Figure 6. Efficiency vs. Load Current, Across Input Voltage,
VOUT = 0.8 V, PWM Mode
100
Figure 7. Efficiency vs. Load Current, Across Input Voltage,
VOUT = 3.3 V, PSM Mode
100
90
90
80
80
70
70
EFFICIENCY (%)
100
60
50
40
60
50
40
30
30
VIN = 2.3V
VIN = 3.6V
VIN = 4.2V
VIN = 5.5V
10
0.01
0.1
IOUT (A)
20
VIN = 3.9V
VIN = 4.2V
VIN = 5.5V
10
1
0
0.001
09496-005
20
0
0.001
0.01
IOUT (A)
Figure 3. Efficiency vs. Load Current, Across Input Voltage,
VOUT = 1.8 V, PSM Mode
0
0.001
VIN = 2.3V
VIN = 3.6V
VIN = 4.2V
VIN = 5.5V
20
09496-003
10
EFFICIENCY (%)
40
30
VIN = 2.3V
VIN = 3.6V
VIN = 4.2V
VIN = 5.5V
20
0
0.001
50
09496-006
30
60
0.01
0.1
IOUT (A)
Figure 5. Efficiency vs. Load Current, Across Input Voltage,
VOUT = 0.8 V, PSM Mode
Figure 8. Efficiency vs. Load Current, Across Input Voltage,
VOUT = 3.3 V, PWM Mode
Rev. C | Page 6 of 20
1
09496-008
EFFICIENCY (%)
VIN = 3.6 V, TA = 25°C, VEN = VIN, unless otherwise noted.
Data Sheet
ADP2138/ADP2139
1.825
3.5
VIN = 2.3V
VIN = 3.6V
VIN = 4.2V
VIN = 5.5V
3.3
3.2
FREQUENCY (MHz)
VOUTA (V)
1.815
–40°C
+25°C
+85°C
+125°C
3.4
1.805
1.795
3.1
3.0
2.9
2.8
2.7
1.785
2.6
0.1
0.2
0.3
0.4
IOUT (A)
0.5
0.6
0.7
0.8
2.5
0
Figure 9. Load Regulation Across Input Voltage, VOUT = 1.8 V, PWM Mode
0.2
0.3
0.4
IOUT (A)
0.5
0.7
3.5
VIN = 2.3V
VIN = 3.6V
VIN = 4.2V
VIN = 5.5V
3.4
3.3
FREQUENCY (MHz)
0.805
0.800
0.795
0.790
3.2
3.1
3.0
2.9
2.8
VIN = 2.3V
VIN = 3.6V
VIN = 4.2V
VIN = 5.5V
2.7
0.785
2.6
0
0.1
0.2
0.3
0.4
IOUT (A)
0.5
0.6
0.7
0.8
2.5
09496-010
0.780
0
Figure 10. Load Regulation Across Input Voltage, VOUT = 0.8 V, PWM Mode
0.1
0.2
0.3
0.4
IOUT (A)
0.5
0.6
09496-013
0.810
0.7
Figure 13. Frequency vs. Output Current, Across Supply Voltage,
VOUT = 1.8 V
90
3.378
VIN = 3.9V
VIN = 4.2V
VIN = 5.5V
3.358
80
IOUT = 100µA
IOUT = 25mA
IOUT = 500mA
70
OUTPUT VOLTAGE (mV)
3.338
3.318
3.298
3.278
3.258
60
50
40
30
20
3.238
10
0
0.1
0.2
0.3
0.4
IOUT (A)
0.5
0.6
0.7
0.8
0
2.3
09496-011
3.218
Figure 11. Load Regulation Across Input Voltage, VOUT = 3.3 V, PWM Mode
Rev. C | Page 7 of 20
2.8
3.3
3.8
4.3
INPUT VOLTAGE (V)
4.8
Figure 14. Output Voltage Ripple vs. Input Voltage,
Across Output Current, VOUT = 1.8 V
5.3
09496-034
VOUTA (V)
0.6
Figure 12. Frequency vs. Output Current, Across Temperature,
VOUT = 1.8 V, PWM Mode
0.815
VOUTA (V)
0.1
09496-012
0
09496-009
1.775
ADP2138/ADP2139
Data Sheet
350
T
–40°C
+25°C
+125°C
300
SW
4
250
RDSON (mΩ)
VOUT
200
1
150
IOUT
100
2.8
3.3
3.8
4.3
INPUT VOLTAGE (V)
4.8
09496-036
0
2.3
5.3
CH1 100mV
CH2 250mA Ω
CH4 5.00V
M 40.0µs A CH2
215mA
T 26.00%
Figure 15. RDSON PFET vs. Input Voltage, Across Temperature
09496-015
2
50
Figure 18. Response to Load Transient, 50 mA to 500 mA,
VOUT = 1.8 V, Automatic Mode
250
T
–40°C
+25°C
+125°C
SW
200
VOUT
150
1
IOUT
100
50
2.8
3.3
3.8
4.3
INPUT VOLTAGE (V)
4.8
5.3
CH1 100mV
CH2 250mA Ω
CH4 5.00V
M 40.0µs A CH2
215mA
T 26.00%
Figure 16. RDSON NFET vs. Input Voltage, Across Temperature
09496-016
0
2.3
09496-037
2
Figure 19. Response to Load Transient, 150 mA to 500 mA,
VOUT = 0.8 V, PWM Mode
T
T
SW
SW
4
4
VOUT
VOUT
1
1
IOUT
IOUT
2
CH1 100mV
CH2 250mA Ω
CH4 5.00V
M 40.0µs A CH2
215mA
T 26.00%
CH1 100mV
CH2 100mA Ω
CH4 5.00V
M 40.0µs A CH2
T 26.00%
Figure 17. Response to Load Transient, 150 mA to 500 mA,
VOUT = 1.8 V, PWM Mode
134mA
09496-017
2
09496-014
RDSON (mΩ)
4
Figure 20. Response to Load Transient, 50 mA to 200 mA, VOUT = 0.8 V,
Automatic Mode
Rev. C | Page 8 of 20
Data Sheet
ADP2138/ADP2139
T
T
SW
VIN
4
VOUT
1
IOUT
VOUT
1
2
CH2 250mA Ω
CH4 5.00V
M 40.0µs A CH2
275mA
T 26.00%
CH1 20.0mV
CH3 1.00V
M 40.0µs
T
Figure 21. Response to Load Transient, 150 mA to 500 mA,
VOUT = 3.3 V, PWM Mode
A CH3
4.50V
–84.0000µs
09496-021
CH1 100mV
09496-018
3
Figure 24. Response to Line Transient, VOUT = 0.8 V,
VIN = 4.0 V to 4.8 V, PWM Mode
T
T
SW
VIN
4
VOUT
1
IOUT
VOUT
1
2
CH2 100mA Ω
CH4 5.00V
M 40.0µs A CH2
114mA
T 26.00%
CH1 20.0mV
CH3 1.00V
M 40.0µs
T
Figure 22. Response to Load Transient, 50 mA to 200 mA,
VOUT = 3.3 V, Automatic Mode
A CH3
4.50V
–84.0000µs
09496-033
CH1 100mV
09496-019
3
Figure 25. Response to Line Transient, VOUT = 1.8 V,
VIN = 4.0 V to 4.8 V, PWM Mode
T
T
SW
VIN
4
IIN
2
VOUT
VOUT
1
1
3
31
M 40.0µs
T
A CH3
–84.0000µs
4.50V
CH1 2.00V Ω
CH3 5.00V
CH2 500mA Ω
CH4 5.00V
M 40.0µs
A CH3
T 10.40%
Figure 23. Response to Line Transient, VOUT = 3.3 V, VIN = 4.0 V to 4.8 V,
PWM Mode
Figure 26. Startup, VOUT = 1.8 V, IOUT = 10 mA
Rev. C | Page 9 of 20
2.50V
09496-022
CH1 20.0mV
CH3 1.00V
09496-020
EN
ADP2138/ADP2139
Data Sheet
T
T
SW
SW
4
IIN
4
VOUT
2
2
IL
VOUT
1
EN
1
CH2 500mA Ω
CH4 5.00V
M 40.0µs
A CH3
2.50V
T 10.40%
CH1 10.0mVΩ
CH2 500mA Ω
CH4 2.00V
M 40.0µs
A CH4
1.32V
T 50.00%
Figure 27. Startup, VOUT = 0.8 V, IOUT = 10 mA
09496-026
CH1 1.00V Ω
CH3 5.00V
09496-023
31
Figure 30. Typical Waveform, VOUT = 1.8 V, PWM Mode, IOUT = 200 mA
T
T
SW
VOUT
1
4
IIN
MODE
2
31
SW
VOUT
1
EN
CH2 500mA Ω
CH4 5.00V
M 40.0µs
A CH3
2.50V
T 10.40%
09496-024
CH1 5.00V Ω
CH3 5.00V
CH1 100mV
CH3 2.00V
T 29.60%
Figure 28. Startup, VOUT = 3.3 V, IOUT = 10 mA
SW
M 40.0µs
CH4 2.00V
A CH3
1.36V
09496-035
4
31
Figure 31. Mode Transition from PSM to PWM to PSM, VOUT = 1.8 V
130
T
120
110
VOUT RIPPLE (mV)
100
4
IL
2
VOUT
90
1.8V,
1.8V,
1.8V,
1.8V,
1.8V,
1.8V,
VIN = 5.5V,
VIN = 3.6V,
VIN = 2.3V,
VIN = 5.5V,
VIN = 3.6V,
VIN = 2.3V,
AUTO
AUTO
AUTO
PWM
PWM
PWM
80
70
60
50
40
30
1
20
CH2 500mA Ω
CH4 2.00V
M 1.00µs A CH1
T 50.00%
3.80mV
0
0.001
09496-025
CH1 10.0mVΩ
0.01
0.1
IOUT (A)
1
09496-100
10
Figure 32. VOUT Peak-to-Peak Ripple vs. Output Current, VOUT = 1.8 V
Figure 29. Typical Waveform, VOUT = 1.8 V, PSM Mode, IOUT = 10 mA
Rev. C | Page 10 of 20
Data Sheet
ADP2138/ADP2139
THEORY OF OPERATION
PWM
COMP
GM ERROR
AMP
SOFT START
VIN
ILIMIT
VOUT
PSM
COMP
PWM/
PSM
CONTROL
LOW
CURRENT
OSCILLATOR
UNDERVOLTAGE
LOCK OUT
DRIVER
AND
ANTISHOOT
THROUGH
ADP2138
THERMAL
SHUTDOWN
SW
MODE
09496-027
EN
GND
Figure 33. ADP2138 Functional Block Diagram
The ADP2138 and ADP2139 are step-down dc-to-dc converters
that use a fixed frequency and high speed current-mode architecture. The high switching frequency and tiny 6-ball WLCSP
package allow for a small step-down dc-to-dc converter solution.
The ADP2138/ADP2139 operate with an input voltage of 2.3 V
to 5.5 V, and regulate an output voltage down to 0.8 V.
CONTROL SCHEME
The ADP2138/ADP2139 operate with a fixed frequency, currentmode PWM control architecture at medium to high loads for
high efficiency, but shift to a power save mode control scheme
at light loads to lower the regulation power losses. When operating
in PWM mode, the duty cycle of the integrated switches is adjusted
and regulates the output voltage. When operating in power save
mode at light loads, the output voltage is controlled in a hysteretic manner, with higher VOUT ripple. During part of this time,
the converter is able to stop switching and enters an idle mode,
which improves conversion efficiency. Each ADP2138/ADP2139
has a MODE pin, which determines the operation of the buck
regulator in either PWM mode (when the MODE pin is set
high) or power save mode (when the mode pin is set low).
PWM MODE
In PWM mode, the ADP2138/ADP2139 operate at a fixed
frequency of 3 MHz, set by an internal oscillator. At the start
of each oscillator cycle, the PFET switch is turned on, sending
a positive voltage across the inductor. Current in the inductor
increases until the current sense signal crosses the peak inductor
current threshold that turns off the PFET switch and turns on
the NFET synchronous rectifier. This sends a negative voltage
across the inductor, causing the inductor current to decrease.
The synchronous rectifier stays on for the rest of the cycle.
The ADP2138/ADP2139 regulate the output voltage by adjusting
the peak inductor current threshold.
POWER SAVE MODE
The ADP2138/ADP2139 smoothly transition to the power save
mode of operation when the load current decreases below the
power save mode current threshold. When the ADP2138 and
ADP2139 enter power save mode, an offset is induced in the PWM
regulation level, which makes the output voltage rise. When the
output voltage reaches a level approximately 1.5% above the PWM
regulation level, PWM operation turns off. At this point, both
power switches are off, and the ADP2138/ ADP2139 enter into
idle mode. COUT discharges until VOUT falls to the PWM regulation
voltage, at which point the device drives the inductor to cause
VOUT to rise again to the upper threshold. This process is repeated
for as long as the load current is below the power save mode
current threshold.
Power Save Mode Current Threshold
The power save mode current threshold is set to 100 mA. The
ADP2138/ADP2139 employ a scheme that enables this current
to remain accurately controlled, independent of VIN and VOUT
levels. This scheme also ensures that there is very little hysteresis
between the power save mode current threshold for entry to and
exit from the power save mode. The power save mode current
threshold is optimized for excellent efficiency across all load
currents.
ENABLE/SHUTDOWN
The ADP2138/ADP2139 start operating with soft start when
the EN pin is toggled from logic low to logic high. Pulling the
EN pin low forces the device into shutdown mode, reducing the
shutdown current to 0.2 μA (typical).
Rev. C | Page 11 of 20
ADP2138/ADP2139
Data Sheet
SHORT-CIRCUIT PROTECTION
possible input voltage drops when a battery or a high impedance
power source is connected to the input of the converter.
The ADP2138/ADP2139 include frequency fold back to prevent
output current runaway on a hard short. When the voltage at
the feedback pin falls below half the target output voltage, indicating the possibility of a hard short at the output, the switching
frequency is reduced to half the internal oscillator frequency.
The reduction in the switching frequency allows more time for
the inductor to discharge, preventing a runaway of output current.
After the EN pin is driven high, internal circuits begin to power
up. Start-up time in the ADP2138/ADP2139 is the measure of
when the output is in regulation after the EN pin is driven high.
Start-up time consists of the power-up time and the soft start time.
CURRENT LIMIT
Each ADP2138/ADP2139 has protection circuitry to limit the
amount of positive current flowing through the PFET switch
and the synchronous rectifier. The positive current limit on the
power switch limits the amount of current that can flow from
the input to the output. The negative current limit prevents the
inductor current from reversing direction and flowing out of
the load.
UNDERVOLTAGE LOCKOUT
To protect against battery discharge, undervoltage lockout
(UVLO) circuitry is integrated on the ADP2138/ADP2139. If
the input voltage drops below the 2.15 V UVLO threshold, the
ADP2138/ADP2139 shut down, and both the power switch and
the synchronous rectifier turn off. When the voltage rises above
the UVLO threshold, the soft start period is initiated, and the
part is enabled.
100% DUTY OPERATION
With a drop in VIN or with an increase in ILOAD, the ADP2138/
ADP2139 reach a limit where, even with the PFET switch on
100% of the time, VOUT drops below the desired output voltage.
At this limit, the ADP2138/ADP2139 smoothly transition to a
mode where the PFET switch stays on 100% of the time. When the
input conditions change again and the required duty cycle falls,
the ADP2138/ADP2139 immediately restart PWM regulation
without allowing overshoot on VOUT.
THERMAL PROTECTION
In the event that the ADP2138/ADP2139 junction temperature
rises above 150°C, the thermal shutdown circuit turns off the
converter. Extreme junction temperatures can be the result of
high current operation, poor circuit board design, or high ambient
temperature. A 20°C hysteresis is included so that when thermal
shutdown occurs, the ADP2138/ADP2139 do not return to
operation until the on-chip temperature drops below 130°C.
When coming out of thermal shutdown, soft start is initiated.
DISCHARGE SWITCH
The ADP2139 has an integrated switched resistor (of typically
100 Ω) to discharge the output capacitor when the EN pin goes
low or when the device enters undervoltage lockout or thermal
shutdown. The time to discharge is typically 200 μs.
SOFT START
The ADP2138/ADP2139 have an internal soft start function
that ramps the output voltage in a controlled manner upon
startup, thereby limiting the inrush current. This prevents
PWM
COMP
GM ERROR
AMP
SOFT START
VIN
ILIMIT
VOUT
PSM
COMP
PWM/
PSM
CONTROL
LOW
CURRENT
OSCILLATOR
SW
DRIVER
AND
ANTISHOOT
THROUGH
UNDER-VOLTAGE
LOCK OUT
MODE
EN
Figure 34. ADP2139 Functional Block Diagram
Rev. C | Page 12 of 20
GND
09496-028
THERMAL
SHUTDOWN
ADP2139
Data Sheet
ADP2138/ADP2139
APPLICATIONS INFORMATION
ADIsimPower DESIGN TOOL
The ADP2138/ADP2139 is supported by ADIsimPower design
tool set. ADIsimPower is a collection of tools that produce
complete power designs optimized for a specific design goal.
The tools enable the user to generate a full schematic, bill of
materials, and calculate performance in minutes. ADIsimPower
can optimize designs for cost, area, efficiency, and parts count
while taking into consideration the operating conditions and
limitations of the IC and all real external components. For
more information about ADIsimPower design tools, refer to
www.analog.com/ADIsimPower. The tool set is available from
this website, and users can also request an unpopulated board
through the tool.
EXTERNAL COMPONENT SELECTION
Trade-offs between performance parameters such as efficiency
and transient response can be made by varying the choice of
external components in the applications circuit, as shown in
Figure 1.
Inductor
The high switching frequency of the ADP2138/ADP2139 allows
for the selection of small chip inductors. For best performance,
use inductor values between 0.7 μH and 3 μH. Recommended
inductors are shown in Table 6.
The peak-to-peak inductor current ripple is calculated using
the following equation:
I RIPPLE
V
× (VIN − VOUT )
= OUT
VIN × f SW × L
Vendor
Murata
Taiyo Yuden
Coilcraft TDK
Coilcraft
Toko
Model
LQM2MPN1R0NG0B
LQM18PN1R0
CBMF1608T1R0M
EPL2014-102ML
GLFR1608T1R0M-LR
0603LS-102
MDT2520-CN
Dimensions
(mm)
2.0 × 1.6 × 0.9
1.6 × 0.8 × 0.33
1.6 × 0.8 × 0.8
2.0 × 2.0 × 1.4
1.6 × 0.8 × 0.8
1.8 × 1.27 × 1.1
2.5 × 2.0 × 1.2
ISAT
(mA)
1400
700
290
900
360
400
1800
DCR
(mΩ)
85
52
90
59
80
81
100
Output Capacitor
Higher output capacitor values reduce the output voltage ripple
and improve load transient response. When choosing this value,
it is also important to account for the loss of capacitance due to
output voltage dc bias.
Ceramic capacitors are manufactured with a variety of dielectrics,
each with different behavior over temperature and applied voltage.
Capacitors must have a dielectric adequate to ensure the
minimum capacitance over the necessary temperature range
and dc bias conditions. X5R or X7R dielectrics with a voltage
rating of 6.3 V or 10 V are recommended for best performance.
Y5V and Z5U dielectrics are not recommended for use with any
dc-to-dc converter because of their poor temperature and dc bias
characteristics.
The worst-case capacitance accounting for capacitor variation
over temperature, component tolerance, and voltage is calculated using the following equation:
CEFF = COUT × (1 − TEMPCO) × (1 − TOL)
where:
fSW is the switching frequency.
L is the inductor value.
The minimum dc current rating of the inductor must be greater
than the inductor peak current. The inductor peak current is
calculated using the following equation:
I PEAK = I LOAD( MAX ) +
Table 6. Suggested 1.0 μH Inductors
I RIPPLE
2
Inductor conduction losses are caused by the flow of current
through the inductor, which has an associated internal DCR.
Larger sized inductors have smaller DCR, which may decrease
inductor conduction losses. Inductor core losses are related to
the magnetic permeability of the core material. Because the
ADP2138/ADP2139 are high switching frequency dc-to-dc
converters, shielded ferrite core material is recommended for its
low core losses and low electromagnetic interference (EMI).
where:
CEFF is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
COUT is 4.0466 μF at 1.8 V, as shown in Figure 35.
Substituting these values in the equation yields
CEFF = 4.0466 μF × (1 − 0.15) × (1 − 0.1) = 3.0956 μF
To guarantee the performance of the ADP2138/ADP2139, it is
imperative that the effects of dc bias, temperature, and tolerances
on the behavior of the capacitors be evaluated for each application.
Rev. C | Page 13 of 20
ADP2138/ADP2139
Data Sheet
THERMAL CONSIDERATIONS
6
Because of the high efficiency of the ADP2138/ADP2139, only a
small amount of power is dissipated inside the ADP2138/ADP2139
package, which reduces thermal constraints.
CAPACITANCE (µF)
5
4
However, in applications with maximum loads at high ambient
temperature, low supply voltage, and high duty cycle, the heat
dissipated in the package is great enough that it may cause the
junction temperature of the die to exceed the maximum junction temperature of 125°C. If the junction temperature exceeds
150°C, the converter enters thermal shutdown. It recovers when
the junction temperature falls below 130°C.
3
2
0
0
1
2
3
4
DC BIAS VOLTAGE (V)
5
6
09496-029
1
Figure 35. Typical Capacitor Performance
The peak-to-peak output voltage ripple for the selected output
capacitor and inductor values is calculated using the following
equation:
VRIPPLE
I RIPPLE
V IN
=
=
(2π × f SW ) × 2 × L × C OUT 8 × f SW × C OUT
Capacitors with lower equivalent series resistance (ESR) are
preferred to guarantee low output voltage ripple, as shown in
the following equation:
ESRCOUT ≤
VRIPPLE
I RIPPLE
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is 3 µF.
Table 7. Suggested 4.7 μF Capacitors
Vendor
Murata
Taiyo Yuden
Coilcraft TDK
Type
X5R
X5R
X5R
Model
GRM188R60J475
JMK107BJ475
C1608X5R0J475
Case
Size
0603
0603
0603
Voltage
Rating (V)
6.3
6.3
6.3
Input Capacitor
Higher value input capacitors help to reduce the input voltage
ripple and improve transient response. Maximum input
capacitor current is calculated using the following equation:
I CIN ≥ I LOAD( MAX )
Model
GRM188R60J475
JMK107BJ475
C1608X5R0J475
where:
TJ is the junction temperature.
TA is the ambient temperature.
TR is the rise in temperature of the package due to power
dissipation.
The rise in temperature of the package is directly proportional
to the power dissipation in the package. The proportionality
constant for this relationship is the thermal resistance from the
junction of the die to the ambient temperature, as shown in the
following equation:
TR = θJA × PD
where:
TR is the rise in temperature of the package.
θJA is the thermal resistance from the junction of the die to the
ambient temperature of the package.
PD is the power dissipation in the package.
PCB LAYOUT GUIDELINES
Poor layout can affect ADP2138/ADP2139 performance, causing
EMI and electromagnetic compatibility problems, ground
bounce, and voltage losses. Poor layout can also affect regulation
and stability. To implement a good layout, use the following rules:
•
•
•
Table 8. Suggested 4.7 μF Capacitors
Type
X5R
X5R
X5R
TJ = TA + TR
•
VOUT (VIN − VOUT )
VIN
To minimize supply noise, place the input capacitor as close to
the VIN pin of the ADP2138/ADP2139 as possible. As with the
output capacitor, a low ESR capacitor is recommended. The list
of recommended capacitors is shown in Table 8.
Vendor
Murata
Taiyo Yuden
Coilcraft TDK
The junction temperature of the die is the sum of the ambient
temperature of the environment and the temperature rise of the
package due to power dissipation, as shown in the following
equation:
Case
Size
0603
0603
0603
Voltage
Rating (V)
6.3
6.3
6.3
Rev. C | Page 14 of 20
Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies, and large tracks act as antennas.
Route the output voltage path away from the inductor and
SW node to minimize noise and magnetic interference.
Maximize the size of ground metal on the component side
to help with thermal dissipation.
Use a ground plane with several vias connecting to the component side ground to further reduce noise interference on
sensitive circuit nodes.
Data Sheet
ADP2138/ADP2139
EVALUATION BOARD
TB1
1
VIN
VIN
3
CIN
4.7µF
TB2
EN
4
VIN
SW
2
1
L1
1µH
VOUT
U1
GND
EN
VOUT
6
EN
5
TB3
2
COUT
4.7µF
MODE
TB6
TB4
T5
GND IN
GND OUT
09496-030
MODE
Figure 36. Evaluation Board Schematic
09496-031
09496-032
EVALUATION BOARD LAYOUT
Figure 38. Bottom Layer
Figure 37. Top Layer
Rev. C | Page 15 of 20
ADP2138/ADP2139
Data Sheet
OUTLINE DIMENSIONS
1.070
1.030
0.990
2
1
A
BALL A1
IDENTIFIER
1.545
1.505
1.465
1.00
REF
(BALL SIDE DOWN)
0.50 REF
BOTTOM VIEW
0.370
0.355
0.340
SIDE VIEW
(BALL SIDE UP)
COPLANARITY
0.05
0.340
0.320
0.300
0.270
0.240
0.210
Figure 39. 6-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-6-12)
Dimensions shown in millimeters
Rev. C | Page 16 of 20
08-10-2012-A
SEATING
PLANE
C
0.50
REF
TOP VIEW
0.640
0.595
0.550
B
Data Sheet
ADP2138/ADP2139
ORDERING GUIDE
Model 1
ADP2138ACBZ-0.8-R7
ADP2138ACBZ-1.0-R7
ADP2138ACBZ-1.2-R7
ADP2138ACBZ-1.5-R7
ADP2138ACBZ-1.8-R7
ADP2138ACBZ-2.5-R7
ADP2138ACBZ-2.8-R7
ADP2138ACBZ-3.0-R7
ADP2138ACBZ-3.3-R7
ADP2139ACBZ-0.8-R7
ADP2139ACBZ-1.0-R7
ADP2139ACBZ-1.2-R7
ADP2139ACBZ-1.5-R7
ADP2139ACBZ-1.8-R7
ADP2139ACBZ-2.5-R7
ADP2139ACBZ-2.8-R7
ADP2139ACBZ-3.0-R7
ADP2139ACBZ-3.3-R7
ADP2138CB-0.8EVALZ
ADP2138CB-1.0EVALZ
ADP2138CB-1.2EVALZ
ADP2138CB-1.5EVALZ
ADP2138CB-1.8EVALZ
ADP2138CB-2.5EVALZ
ADP2138CB-2.8EVALZ
ADP2138CB-3.0EVALZ
ADP2138CB-3.3EVALZ
ADP2139CB-0.8EVALZ
ADP2139CB-1.0EVALZ
ADP2139CB-1.2EVALZ
ADP2139CB-1.5EVALZ
ADP2139CB-1.8EVALZ
ADP2139CB-2.5EVALZ
ADP2139CB-2.8EVALZ
ADP2139CB-3.0EVALZ
ADP2139CB-3.3EVALZ
1
Temperature
Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Output
Voltage (V)
0.8
1.0
1.2
1.5
1.8
2.5
2.8
3.0
3.3
0.8
1.0
1.2
1.5
1.8
2.5
2.8
3.0
3.3
Package Description
6-Ball Wafer Level Chip Scale Package [WLCSP]
6-Ball Wafer Level Chip Scale Package [WLCSP]
6-Ball Wafer Level Chip Scale Package [WLCSP]
6-Ball Wafer Level Chip Scale Package [WLCSP]
6-Ball Wafer Level Chip Scale Package [WLCSP]
6-Ball Wafer Level Chip Scale Package [WLCSP]
6-Ball Wafer Level Chip Scale Package [WLCSP]
6-Ball Wafer Level Chip Scale Package [WLCSP]
6-Ball Wafer Level Chip Scale Package [WLCSP]
6-Ball Wafer Level Chip Scale Package [WLCSP]
6-Ball Wafer Level Chip Scale Package [WLCSP]
6-Ball Wafer Level Chip Scale Package [WLCSP]
6-Ball Wafer Level Chip Scale Package [WLCSP]
6-Ball Wafer Level Chip Scale Package [WLCSP]
6-Ball Wafer Level Chip Scale Package [WLCSP]
6-Ball Wafer Level Chip Scale Package [WLCSP]
6-Ball Wafer Level Chip Scale Package [WLCSP]
6-Ball Wafer Level Chip Scale Package [WLCSP]
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Z = RoHS Compliant Part.
Rev. C | Page 17 of 20
Package
Option
CB-6-12
CB-6-12
CB-6-12
CB-6-12
CB-6-12
CB-6-12
CB-6-12
CB-6-12
CB-6-12
CB-6-12
CB-6-12
CB-6-12
CB-6-12
CB-6-12
CB-6-12
CB-6-12
CB-6-12
CB-6-12
Branding
LJH
L88
L89
L8A
L8C
L93
LDH
LDJ
LDP
LJJ
LHN
LHP
LHQ
LHR
LHS
LHT
LHU
LHV
ADP2138/ADP2139
Data Sheet
NOTES
Rev. C | Page 18 of 20
Data Sheet
ADP2138/ADP2139
NOTES
Rev. C | Page 19 of 20
ADP2138/ADP2139
Data Sheet
NOTES
©2011–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09496-0-01/13(C)
Rev. C | Page 20 of 20