TI1 DS100MB203SQ/NOPB 10.3125 gbps dual lane 2:1/1:2 mux/buffer Datasheet

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DS100MB203
SNLS396D – JANUARY 2012 – REVISED JANUARY 2016
DS100MB203 10.3125 Gbps Dual Lane 2:1/1:2 Mux/Buffer
With Equalization and De-Emphasis
1 Features
•
1
•
•
•
•
•
10.3125 Gbps Dual Lane 2:1 Mux, 1:2 Switch or
Fan-Out
Low 390 mW Total Power (Typical)
Advanced Signal Conditioning Features:
– Receive Equalization Up to 36 dB at 5 GHz
– Transmit De-Emphasis Up to –12 dB
– Transmit Output Voltage Control: 600 mV to
1300 mV
Programmable Through Pin Selection, EEPROM
or SMBus Interface
Selectable 2.5-V or 3.3-V Supply Voltage
–40°C to 85°C Operating Temperature Range
2 Applications
•
•
•
•
The continuous time linear equalizer (CTLE) of the
receiver provides necessary boost to compensate up
to 40” FR-4 or 10m cable (AWG-24) at 10.3125 Gbps
- This on-chip feature eliminates the need for external
signal conditioners. The transmitter features a
programmable amplitude voltage levels to be
selectable from 600 mVp-p to 1300 mVp-p and DeEmphasis of up to 12 dB.
The DS100MB203 can be configured to support
PCIe, SAS/SATA, 10G-KR or other signaling
protocols. When operating in 10G-KR and PCIe Gen3 mode, the DS100MB203 transparently allows the
host controller and the end point to optimize the full
link and negotiate transmit equalizer coefficients. This
seamless management of the link training protocol
ensures system level interoperability with minimum
latency.
The programmable settings can be applied through
pin settings, SMBus (I2C) protocol or loaded directly
from an external EEPROM. When operating in the
EEPROM mode, the configuration information is
automatically loaded on power up, which eliminates
the need for an external microprocessor or software
driver.
10GE, 10G-KR
PCIe Gen-1/2/3
SAS2/SATA3 (Up to 6 Gbps)
XAUI, RXAUI
3 Description
The DS100MB203 device is a dual port 2:1
multiplexer and 1:2 switch or fan-out buffer with
signal conditioning suitable for 10GE, 10G-KR
(802.3ap),
Fibre
Channel,
PCIe,
Infiniband,
SATA3/SAS2 and other high-speed bus applications
with data rates up to 10.3125 Gbps.
Device Information(1)
PART NUMBER
DS100MB203
PACKAGE
WQFN (54)
10.00 mm × 5.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
Simplified Functional Block Diagram
MB203
MB203
SEL0
DRIVE 0
S_INA0
S_INA+
S_INA-
D_OUT+
D_OUT-
BODY SIZE (NOM)
EXPANDER
TXA_0
DRIVE 1
D_OUT0
RX
S_INB0
S_INB+
S_INBS_OUTA+
S_OUTA-
D_IN+
D_IN-
TXB_0
TX
S_INA1
TXA_1
D_OUT1
S_OUTB+
S_OUTB-
AD0
Address straps
(pull-up to VIN or
pull-down to
GND)(1)
AD1
S_INA1
TXB_1
GND
1 OF 2
AD2
AD3
SATA/SAS
Mode(4)
MODE
RX
S_OUTA0
VIN
SMBus Slave Mode
(1)
SMBus Slave Mode(1)
SMBus
Slave Mode(1)
3.3V(3)
SMBus Slave
Mode(1)
SEL0
READ_EN / SEL1
ALL_DONE
1 F
VDD_SEL
0.1 F
(x5)
VDD (2.5 V)
S_OUTB0
RXB_0
ENSMB
SDA(2)
SCL(2)
VIN (3.3 V)
10 F
RXA_0
D_IN0
TX
S_OUTA1
To SMBus/I2C
Host Controller
INPUT_EN
RESET
D_IN1
RXA_1
S_OUTB1
SEL1
RXB_1
GND (DAP)
(1) Schematic shows connection for SMBus Slave Mode (ENSMB = 1 k: to VIN)
For SMBus Master Mode or Pin Mode configuration, the connections are different.
(2) SMBus signals must be pulled up elsewhere in the system.
(3) Schematic requires different connections for 2.5 V mode.
(4) Schematic requires pullup resistor for 10G-KR Mode.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS100MB203
SNLS396D – JANUARY 2012 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
7
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
Electrical Characteristics........................................... 8
Electrical Characteristics – Serial Management Bus
Interface .................................................................. 11
6.7 Timing Requirements – Serial Bus Interface .......... 11
6.8 Typical Characteristics ............................................ 13
7
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 15
7.5 Programming .......................................................... 19
7.6 Register Maps ......................................................... 20
8
Application and Implementation ........................ 40
8.1 Application Information............................................ 40
8.2 Typical Application .................................................. 41
9
Power Supply Recommendations...................... 42
9.1 Power Supply Bypassing ........................................ 42
10 Layout................................................................... 44
10.1 Layout Guidelines ................................................. 44
10.2 Layout Example .................................................... 45
11 Device and Documentation Support ................. 46
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
46
46
46
46
46
12 Mechanical, Packaging, and Orderable
Information ........................................................... 46
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (November 2015) to Revision D
•
Changed Signal detect pattern at 8 Gbps .............................................................................................................................. 8
Changes from Revision B (April 2013) to Revision C
•
2
Page
Changed data sheet flow and layout to conform with new TI standards. Added the following sections: Application
and Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical,
Packaging, and Ordering Information .................................................................................................................................... 1
Changes from Revision A (April 2013) to Revision B
•
Page
Page
Changed layout of National Data Sheet to TI format ............................................................................................................. 1
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5 Pin Configuration and Functions
RESET
VDD
DEM_S1/SCL
DEM_S0/SDA
ENSMB
EQ_S1/AD2
EQ_S0/AD3
51
50
49
48
47
46
DEM_D0/AD1
53
52
DEM_D1/AD0
54
NJY Package
54-Pin WQFN
Top View (looking down through package)
SMBUS AND CONTROL
NC
1
45
S_INA0+
NC
2
44
S_INA0-
D_OUT0+
3
43
S_INB0+
D_OUT0-
4
42
S_INB0-
NC
5
41
VDD
NC
6
40
S_INA1+
D_OUT1+
7
39
S_INA1-
D_OUT1-
8
38
S_INB1+
37
S_INB1-
TOP VIEW
DAP = GND
VDD
9
D_IN0+
10
36
VDD
D_IN0-
11
35
S_OUTA0+
NC
12
34
S_OUTA0-
NC
13
33
S_OUTB0+
VDD
14
32
S_OUTB0-
D_IN1+
15
31
S_OUTA1+
D_IN1-
16
30
S_OUTA1-
NC
17
29
S_OUTB1+
NC
18
28
S_OUTB1-
19
20
21
22
23
24
25
26
27
EQ_D1
EQ_D0
MODE
INPUT_EN
SEL0
VIN
VDD_SEL
SEL1 / READ_EN
ALL_DONE
LDO REG
3.3V to 2.5V
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Pin Functions: Common Connections (1)
PIN
NAME
NO.
TYPE
DESCRIPTION
DIFFERENTIAL HIGH-SPEED INPUTS AND OUTPUTS
D_IN0+,
D_IN0-,
D_IN1+,
D_IN1D_OUT0+, D_
OUT0-,
D_OUT1+,
D_OUT1S_INA0+,
S_INA0-,
S_INA1+,
S_INA1S_INB0+,
S_INB0-,
S_INB1+,
S_INB1S_OUTA0+,
S_OUTA0-,
S_OUTA1+,
S_OUTA1S_OUTB0+,
S_OUTB0-,
S_OUTB1+,
S_OUTB1-
10, 11, 15, 16
I
3, 4, 7, 8
O
45, 44, 40, 39
I
43, 42, 38, 37
I
35, 34, 31, 30
O
33, 32, 29, 28
O
Inverting and noninverting CML differential inputs to the equalizer. A gated on-chip 50Ω termination resistor connects D_INn+ to VDD and D_INn- to VDD when enabled. AC
coupling required on high-speed I/O.
Inverting and noninverting low power differential signaling 50-Ω outputs with deemphasis. Fully compatible with AC-coupled CML inputs. AC coupling required on
high-speed I/O.
Inverting and noninverting CML differential inputs to the equalizer. An on-chip 50-Ω
termination resistor connects S_INAn+ to VDD and S_INAn- to VDD. AC coupling
required on high-speed I/O.
Inverting and noninverting CML differential inputs to the equalizer. An on-chip 50-Ω
termination resistor connects S_INBn+ to VDD and S_INBn- to VDD. AC coupling
required on high-speed I/O.
Inverting and noninverting low power differential signaling 50-Ω outputs with deemphasis. Fully compatible with AC-coupled CML inputs.
Inverting and noninverting low power differential signaling 50-Ω outputs with deemphasis. Fully compatible with AC-coupled CML inputs. AC coupling required on
high-speed I/O.
CONTROL PINS - SHARED (LVCMOS)
ENSMB
48
I, FLOAT,
LVCMOS
System Management Bus (SMBus) enable pin
Tie 1 kΩ to VDD = register access SMBus slave mode
FLOAT = read external EEPROM (master SMBUS mode)
Tie 1 kΩ to GND = Pin Mode
CONTROL PINS—BOTH PIN AND SMBus MODES (LVCMOS)
0: Normal operation (device is enabled).
1: low power mode.
RESET
52
I, LVCMOS
VDD_SEL
25
I, FLOAT
GND
DAP
Power
Ground pad (DAP - die attach pad).
VDD
9, 14,36, 41,
51
Power
Power supply pins CML/analog
2.5-V mode, connect to 2.5 V ±5%
3.3-V mode, connect 0.1-uF cap to each VDD pin
VIN
24
Power
In 3.3-V mode, feed 3.3 V ±10% to VIN
In 2.5-V mode, leave floating.
Controls the internal regulator
FLOAT: 2.5-V mode
Tied to GND: 3.3-V mode
POWER
(1)
4
LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not ensured.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
For 3.3-V mode operation, VIN pin = 3.3 V and the "VDD" for the 4-level input is 3.3 V.
For 2.5-V mode operation, VDD pin = 2.5 V and the "VDD" for the 4-level input is 2.5 V.
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Pin Functions: SMBus/EEPROM Control
PIN
NAME
NO.
TYPE
DESCRIPTION
ENSMB = 1 (SMBUS SLAVE MODE), FLOAT (SMBUS MASTER MODE)
AD0-AD3
54, 53, 47,
46
I, LVCMOS
ENSMB master or slave mode
SMBus slave address Inputs. In SMBus mode, these pins are the user set SMBus slave
address inputs.
READ_EN
26
I, LVCMOS
ENSMB = FLOAT (SMBUS master mode)
When using an external EEPROM, a transition from high to low starts the load from the
external EEPROM
SCL
50
I, LVCMOS,
O, Opendrain
ENSMB master or slave mode
SMBUS clock input pin is enabled (slave mode)
SMBUS clock output when loading configuration from EEPROM (master mode)
SDA
49
I, LVCMOS,
O, Opendrain
ENSMB Master or Slave mode
The SMBus bidirectional SDA pin is enabled. Data input or open drain (pulldown only)
output.
CONTROL PINS—BOTH PIN AND SMBus MODES (LVCMOS)
INPUT_EN
22
I, 4-LEVEL,
LVCMOS
0: Normal operation, FANOUT is disabled, use SEL0/1 to select the A or B input/output (see
SEL0/1 pin), input always enabled with 50 Ω.
20kΩ to GND: Reserved
FLOAT: AUTO - Use RX Detect, SEL0/1 to determine which input or output to enable,
FANOUT is disable
1: Normal operation, FANOUT is enabled (both S_OUT0/1 are ON). Input always enabled
with 50 Ω.
MODE
21
I, 4-LEVEL,
LVCMOS
0: SATA/SAS, PCIe GEN 1/2 and 10GE
FLOAT: AUTO (PCIe GEN 1/2 or GEN 3)
1: 10-KR
23
I, 4-LEVEL,
LVCMOS
Select pin for Lane 0.
0: selects input S_INB0±, output S_OUTB0±.
20 kΩ to GND: selects input S_INB0±, output S_OUTA0±.
FLOAT: selects input S_INA0±, output S_OUTB0±.
1: selects input S_INA0±, output S_OUTA0±.
26
I, 4-LEVEL,
LVCMOS
Select pin for Lane 1.
0: selects input S_INB1±, output S_OUTB1±.
20 kΩ to GND: selects input S_INB1±, output S_OUTA1±.
FLOAT: selects input S_INA1±, output S_OUTB1±.
1: selects input S_INA1±, output S_OUTA1±.
27
0, LVCMOS
Valid Register Load Status Output
0: External EEPROM load passed
1: External EEPROM load failed
SEL0
SEL1
OUTPUT (LVCMOS)
ALL_DONE
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Pin Functions: Pin Control
PIN
NAME
NO.
TYPE
DESCRIPTION
ENSMB = 0 (PIN MODE)
DEM_S0,
DEM_S1
DEM_D0,
DEM_D1
49, 50, 53,
54
I, 4-LEVEL,
LVCMOS
DEM_D[1:0] and DEM_S[1:0] control the level of VOD and de-emphasis on the high-speed
output. The outputs are organized into two sides. The D side is controlled with the
DEM_D[1:0] pins and the S side is controlled with the DEM_S[1:0] pins. See Table 3.
EQ_D0,
EQ_D1
EQ_S0,
EQ_S1
20, 19, 46,
47
I, 4-LEVEL,
LVCMOS
EQ_D[1:0] and EQ_S[1:0] control the level of equalization on the high-speed input pins. The
inputs are organized into two sides. The D side is controlled with the EQ_D[1:0] pins and the
S side is controlled with the EQ_S[1:0] pins. See Table 2.
CONTROL PINS—BOTH PIN AND SMBus MODES (LVCMOS)
INPUT_EN
22
I, 4-LEVEL,
LVCMOS
0: Normal operation, FANOUT is disabled, use SEL0/1 to select the A or B input/output (see
SEL0/1 pin), input always enabled with 50 Ω.
20kΩ to GND: Reserved
FLOAT: AUTO - Use RX Detect, SEL0/1 to determine which input or output to enable,
FANOUT is disable
1: Normal operation, FANOUT is enabled (both S_OUT0/1 are ON). Input always enabled
with 50 Ω.
MODE
21
I, 4-LEVEL,
LVCMOS
0: SATA/SAS, PCIe GEN 1/2 and 10GE
FLOAT: AUTO (PCIe GEN 1/2 or GEN 3)
1: 10-KR
23
I, 4-LEVEL,
LVCMOS
Select pin for lane 0.
0: selects input S_INB0±, output S_OUTB0±.
20kΩ to GND: selects input S_INB0±, output S_OUTA0±.
FLOAT: selects input S_INA0±, output S_OUTB0±.
1: selects input S_INA0±, output S_OUTA0±.
26
I, 4-LEVEL,
LVCMOS
Select pin for Lane 1.
0: selects input S_INB1±, output S_OUTB1±.
20kΩ to GND: selects input S_INB1±, output S_OUTA1±.
FLOAT: selects input S_INA1±, output S_OUTB1±.
1: selects input S_INA1±, output S_OUTA1±.
SEL0
SEL1
6
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6 Specifications
6.1 Absolute Maximum Ratings
(1) (2) (3)
See
.
MIN
MAX
UNIT
Supply voltage (VDD – 2.5-V mode)
–0.5
2.75
V
Supply voltage (VIN – 3.3-V mode)
–0.5
4
V
LVCMOS input / output voltage
–0.5
4
V
CML input voltage
–0.5
(VDD + 0.5)
V
CML input current
–30
Junction temperature
Soldering (4 sec.) (3)
Lead temperature
Storage temperature, Tstg
(1)
(2)
(3)
–40
30
mA
125
°C
260
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Soldering Information: SNOA549
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
2.5-V mode
Supply voltage
3.3-V mode
Ambient temperature
MIN
NOM
MAX
UNIT
2.375
2.5
2.625
V
3
3.3
3.6
V
–40
25
85
°C
3.6
V
100
mVp-p
SMBus (SDA, SCL)
Supply noise up to 50 MHz
(1)
(1)
Allowed supply noise (mVp-p sine wave) under typical conditions.
6.4 Thermal Information
DS100MB203
THERMAL METRIC (1)
NYJ (WQFN)
UNIT
54 PINS
RθJA
Junction-to-ambient thermal resistance, No Airflow, 4 layer JEDEC
26.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
10.8
°C/W
RθJB
Junction-to-board thermal resistance
4.4
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
4.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics (1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 2.5-V supply
390
499
mW
VIN = 3.3-V supply
515
684
mW
POWER
PD
Power dissipation
EQ Enabled, VOD = 1 Vp-p,
RESET = 0
LVCMOS / LVTTL DC SPECIFICATIONS
Vih
High-level input
voltage
2
VDD
V
Vil
Low-level input
voltage
0
0.8
V
Voh
High-level output
voltage (ALL_DONE
pin)
Ioh= −4mA
Vol
Low-level output
voltage (ALL_DONE
pin)
Iol= 4mA
Input high current
(RESET pin)
VIN = 3.6 V,
LVCMOS = 3.6 V
Input high current
with internal resistors
(4–level input pin)
VIN = 3.6 V,
LVCMOS = 3.6 V
Input low current
(RESET pin)
Input low current with
internal resistors
(4–level input pin)
Iih
Iil
2
V
0.4
V
–15
15
µA
20
150
µA
VIN = 3.6 V,
LVCMOS = 0 V
–15
15
µA
VIN = 3.6 V,
LVCMOS = 0 V
–160
–40
µA
CML RECEIVER INPUTS (IN_n+, IN_n–)
RX differential return
loss
RLrx-diff
0.05 - 1.25 GHz
–16
dB
1.25 - 2.5 GHz
–16
dB
2.5 - 4.0 GHz
–14
dB
0.05 - 2.5 GHz
–12
dB
2.5 - 4.0 GHz
–8
dB
RLrx-cm
RX common-mode
return loss
Zrx-dc
RX DC commonmode impedance
Tested at VDD = 2.5 V
40
50
60
Ω
Zrx-diff-dc
RX DC differntial
mode impedance
Tested at VDD = 2.5 V
80
100
120
Ω
Vrx-signal-detdiff-pp
Signal detect assert
level for active data
signal
0101 pattern at 8 Gbps
180
mVp-p
0101 pattern at 8 Gbps
110
mVp-p
Signal detect deVrx-idle-det-diffassert level for
pp
electrical idle
HIGH-SPEED OUTPUTS
Vtx-diff-pp
Output voltage
differential swing
Differential measurement with OUT_n+ and OUT_n-,
terminated by 50 Ω to GND,
AC-Coupled, VID = 1 Vp-p,
DEM_x[1:0] = R, F (3)
Vtx-de-ratio_3.5
TX de-emphasis ratio
VOD = 1 Vp-p,
DEM_x[1:0] = R, F
(1)
(2)
(3)
8
0.8
1
–3.5
1.2
Vp-p
dB
Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
In GEN3 mode, the output VOD level is not fixed. It will be adjusted automatically based on the VID input amplitude level. The output
VOD level set by DEM_x[1:0] in GEN3 mode is dependent on the VID level and the frequency content. The DS100MB203 repeater in
GEN3 mode is designed to be transparent, so the TX-FIR (de-emphasis) is passed to the RX to support the PCIe GEN3 handshake
negotiation link training.
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Electrical Characteristics(1)(2) (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Vtx-de-ratio_6
TX de-emphasis ratio
VOD = 1 Vp-p,
DEM_x[1:0] = F, 0
tTX-DJ
Deterministic jitter
VID = 800 mV, PRBS15 pattern, 8.0 0.05 Gbps, VOD
= 1 V, UIpp EQ = 0x00, DE = 0 dB (no input or output
trace loss)
0.05
UIpp
tTX-RJ
Random jitter
VID = 800 mV, 0101 pattern, 8.0 Gbps, 0.3 VOD = 1
V, ps RMS EQ = 0x00, DE = 0 dB, (no input or output
trace loss)
0.3
ps RMS
TTX-RISE-FALL
TX rise/fall time
20% to 80% of differential output voltage
TRF-MISMATCH
TX rise/fall mismatch
20% to 80% of differential output voltage
0.01
0.05 - 1.25 GHz
–16
dB
RLTX-DIFF
TX differential return
loss
1.25 - 2.5 GHz
–12
dB
2.5 - 4 GHz
–11
dB
0.05 - 2.5 GHz
–12
dB
–8
dB
100
Ω
–6
35
dB
45
ps
0.1
UI
RLTX-CM
TX common-mode
return loss
ZTX-DIFF-DC
DC differential TX
impedance
VTX-CM-AC-PP
TX AC commonmode voltage
VOD = 1 Vp-p,
DEM_x[1:0] = R, F
ITX-SHORT
TX short circuit
current limit
Total current the transmitter can supply when shorted
to VDD or GND
VTX-CM-DC-
Absolute delta of DC
common-mode
voltage during L0 and
electrical idle
100
mV
Absolute delta of DC
common-mode
voltage between TX+
and TX-
25
mV
ACTIVE-IDLE-DELTA
VTX-CM-DC-LINEDELTA
2.5 - 4 GHz
100
20
mVpp
mA
TTX-IDLE-DATA
Max time to transition
to differential DATA
signal after IDLE
VID = 1 Vp-p, 8 Gbps
3.5
ns
TTX-DATA-IDLE
Max time to transition
to IDLE after
differential DATA
signal
VID = 1 Vp-p, 8 Gbps
6.2
ns
TPLHD/PHLD
High-to-low and lowto-high differential
propagation delay
EQ = 00 (4)
200
ps
TLSK
Lane-to-lane skew
T = 25°C, VDD = 2.5 V
25
ps
TPPSK
Part-to-part
propagation delay
skew
T = 25°C, VDD = 2.5 V
40
ps
TMUX-SWITCH
Mux / switch time
100
ns
DJE1
35-in 4 mils FR4,
Residual deterministic VID = 0.8 Vp-p,
jitter at 10.3125 Gbps PRBS15, EQ = 1F'h,
DEM = 0 dB
0.3
UI
DJE2
35-in 4 mils FR4,
Residual deterministic VID = 0.8 Vp-p,
jitter at 8 Gbps
PRBS15, EQ = 1F'h,
DEM = 0 dB
0.14
UI
EQUALIZATION
(4)
Propagation Delay measurements will change slightly based on the level of EQ selected. EQ = 00 will result in the shortest propagation
delays.
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Electrical Characteristics(1)(2) (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DJE3
35-in 4 mils FR4,
Residual deterministic VID = 0.8 Vp-p,
jitter at 5 Gbps
PRBS15,EQ = 1F'h,
DEM = 0 dB
0.1
UI
DJE4
35-in 4 mils FR4,
Residual deterministic VID = 0.8 Vp-p,
jitter at 2.5 Gbps
PRBS15, EQ = 1F'h,
DEM = 0 dB
0.05
UI
DJE5
10 meters 30 awg cable,
Residual deterministic VID = 0.8 Vp-p,
jitter at 10.3125 Gbps PRBS15, EQ = 2F'h,
DEM = 0 dB
0.3
UI
DJE6
10 meters 30 awg cable,
Residual deterministic VID = 0.8 Vp-p,
jitter at 8 Gbps
PRBS15, EQ = 2F'h,
DEM = 0 dB
0.16
UI
DJE7
10 meters 30 awg cable,
Residual deterministic VID = 0.8 Vp-p,
jitter at 5 Gbps
PRBS15, EQ = 2F'h,
DEM = 0 dB
0.1
UI
DJE8
10 meters 30 awg cable,
Residual deterministic VID = 0.8 Vp-p,
jitter at 2.5 Gbps
PRBS15, EQ = 2F'h,
DEM = 0 dB
0.05
UI
DJD1
10-in 4 mils FR4,
Residual deterministic VID = 0.8 Vp-p,
jitter at 2.5 Gbps and PRBS15, EQ = 00,
5.0 Gbps
VOD = 1 Vp-p,
DEM = −3.5 dB
0.1
UI
DJD2
20-in 4 mils FR4,
Residual deterministic VID = 0.8 Vp-p,
jitter at 2.5 Gbps and PRBS15, EQ = 00,
5.0 Gbps
VOD = 1 Vp-p,
DEM = −9 dB
0.1
UI
DJD3
20-in 4 mils FR4,
VID = 0.8 Vp-p,
Residual deterministic
PRBS15, EQ = 00,
jitter at 10.3125 Gbps
VOD = 1 Vp-p,
DEM = −9 dB
0.1
UI
DE-EMPHASIS (MODE = 0)
10
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6.6 Electrical Characteristics – Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
Data, clock input low voltage
VIH
Data, clock input high voltage
IPULLUP
Current through pullup resistor or
current source
VDD
Nominal bus voltage
ILEAK-Bus
Input leakage per bus segment
ILEAK-Pin
Input leakage per device Pin
CI
RTERM
(1)
(2)
(3)
2.1
High power specification
0.8
V
3.6
V
4
mA
2.375
3.6
V
–200
200
µA
See
(1)
Capacitance for SDA and SCL
See
(1) (2)
External termination resistance pull
to VDD = 2.5 V ± 5% OR 3.3 V ±
10%
Pullup VDD = 3.3 V (1) (2) (3)
2000
Ω
(1) (2) (3)
1000
Ω
–15
Pullup VDD = 2.5 V
µA
10
pF
Recommended value.
Recommended maximum capacitance load per bus segment is 400pF.
Maximum termination voltage should be identical to the device supply voltage.
6.7 Timing Requirements – Serial Bus Interface
MIN
NOM
280
400
ENSMB = VDD (slave mode)
MAX
UNIT
400
kHz
520
kHz
FSMB
Bus operating frequency
TBUF
Bus free time between stop and start condition
1.3
µs
THD:STA
Hold time after (repeated) start
condition. After this period, the first
clock is generated.
0.6
µs
TSU:STA
Repeated start condition set-up time
0.6
µs
TSU:STO
Stop condition set-up time
0.6
µs
THD:DAT
Data hold time
0
ns
TSU:DAT
Data set-up time
100
ns
TLOW
Clock low period
1.3
THIGH
Clock high period
0.6
tF
Clock / data fall time
tR
Clock / data rise time
tPOR
Time in which a device must be
operational after power-on reset
(1)
(2)
ENSMB = FLOAT (master mode)
At IPULLUP, maximum
See
See
(1)
(1) (2)
µs
50
µs
300
ns
300
ns
500
ms
Compatible with SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus Common AC Specifications for details
Specified by Design. Parameter not tested in production.
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(OUT+)
80%
80%
VOD (p-p) = (OUT+) ± (OUT-)
0V
20%
20%
(OUT-)
tRISE
tFALL
Figure 1. CML Output and Rise and FALL Transition Time
+
IN
0V
tPHLD
tPLHD
+
0V
OUT
-
Figure 2. Propagation Delay Timing Diagram
+
IN
0V
DATA
tIDLE-DATA
tDATA-IDLE
+
OUT
0V
DATA
IDLE
IDLE
Figure 3. Transmit IDLE-DATA and DATA-IDLE Response Time
tLOW
tR
tHIGH
SCL
tHD:STA
tBUF
tHD:DAT
tF
tSU:STA
tSU:DAT
tSU:STO
SDA
SP
ST
SP
ST
Figure 4. SMBus Timing Parameters
12
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6.8 Typical Characteristics
1050
460.0
VDD = 2.625V
450.0
T = 25°C
VDD = 2.5V
440.0
1040
VDD = 2.375V
420.0
VOD (mVp-p)
PD (mW)
430.0
410.0
400.0
390.0
1030
1020
380.0
1010
T = 25°C
370.0
360.0
1000
2.375
350.0
0.8
0.9
1
1.1
1.2
1.3
2.5
2.625
VDD (V)
VOD (Vp-p)
Figure 6. Output Differential Voltage (VOD = 1 Vp-p) vs
Supply Voltage (VDD)
Figure 5. Power Dissipation (PD) vs Output Differential
Voltage (VOD)
1040
VDD = 2.5V
VOD (mVp-p)
1030
1020
1010
1000
- 40
-15
10
35
60
85
TEMPERATURE (°C)
Figure 7. Output Differential Voltage (VOD = 1 Vp-p) vs Temperature
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7 Detailed Description
7.1 Overview
The DS100MB203 is a dual lane 2:1 multiplexer and 1:2 switch or fan-out buffer with signal conditioning. The
DS100MB203 compensates for lossy FR-4 printed-circuit-board backplanes and balanced cables. The
DS100MB203 operates in 3 modes: Pin Control Mode (ENSMB = 0), SMBus Slave Mode (ENSMB = 1) and
SMBus Master Mode (ENSMB = float) to load register information from external EEPROM; please refer to
SMBUS Master Mode for additional information.
7.2 Functional Block Diagram
One of Two 2:1 / 1:2 Ports
VDD
S_INA_n+
EQ
S_INA_nOUTA_n+
VDD
Predriver
Driver
OUTA_n-
S_INB_n+
EQ
S_INB_n-
SEL[1:0]
VDD
D_INn+
EQ
D_INn-
S_OUTA_n+
Predriver
Driver
Predriver
Driver
S_OUTA_n-
ENSMB
EQ_D[1:0]
S_OUTB_n+
S_OUTB_n-
DEM_D[1:0]
EQ_S[1:0]
DEM_S[1:0]
READ_EN
ALL_DONE
AD[3:0]
SCL
SDA
Digital Core and SMBus Registers
Internal voltage
regulator
RESET
SEL[1:0]
VDD_SEL
VIN
14
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7.3 Feature Description
7.3.1 4-Level Input Configuration Guidelines
The 4-level input pins use a resistor divider to help set the four valid control levels and provide a wider range of
control settings when ENSMB = 0. There is an internal 30-kΩ pullup and a 60-kΩ pulldown connected to the
package pin. These resistors, together with the external resistor connection, combine to achieve the desired
voltage level. By using the 1-kΩ pulldown, 20-kΩ pulldown, no connect, and 1-kΩ pullup, the optimal voltage
levels for each of the four input states are achieved as shown in Table 1.
Table 1. 4–Level Control Pin Settings
RESULTING PIN VOLTAGE
LEVEL
SETTING
0
Tie 1 kΩ to GND
0.1 V
0.08 V
R
Tie 20 kΩ to GND
1/3 x VIN
1/3 x VDD
3.3-V MODE
2.5-V MODE
F
Float (leave pin open)
2/3 x VIN
2/3 x VDD
1
Tie 1 kΩ to VIN or VDD
VIN – 0.05 V
VDD – 0.04 V
The typical 4-Level input thresholds are as follows:
• Internal Threshold between 0 and R = 0.2 × VIN or VDD
• Internal Threshold between R and F = 0.5 × VIN or VDD
• Internal Threshold between F and 1 = 0.8 × VIN or VDD
In order to minimize the start-up current associated with the integrated 2.5-V regulator, the 1-kΩ pullup and
pulldown resistors are recommended. If several four level inputs require the same setting, it is possible to
combine two or more 1-kΩ resistors into a single lower value resistor. As an example, combining two inputs with
a single 500-Ω resistor is a valid way to save board space.
7.4 Device Functional Modes
7.4.1 Pin Control Mode
When in pin mode (ENSMB = 0) , the repeater is configurable with external pins. Equalization and de-emphasis
can be selected through pin for each side independently. When de-emphasis is asserted VOD is automatically
adjusted per Table 3. The receiver electrical idle detect threshold is also adjustable via the SD_TH pin.
7.4.2 SMBUS Mode
When in SMBus mode (ENSMB = 1), the VOD (output amplitude), equalization, de-emphasis, and termination
disable features are all programmable on a individual lane basis, instead of grouped by A or B as in the pin mode
case. Upon assertion of ENSMB the MODE, EQx and DEMx functions revert to register control immediately. The
EQx and DEMx pins are converted to AD0-AD3 SMBus address inputs. The other external control pins remain
active unless their respective registers are written to and the appropriate override bit is set, in which case they
are ignored until ENSMB is driven low (pin mode). On power up and when ENSMB is driven low all registers are
reset to their default state. If RESET is asserted while ENSMB is high, the registers retain their current state.
Equalization settings accessible through the pin controls were chosen to meet the needs of most applications. If
additional fine tuning or adjustment is needed, additional equalization settings can be accessed through the
SMBus registers. Each input has a total of 256 possible equalization settings. The tables show the 16 setting
when the device is in pin mode. When using SMBus mode, the equalization, VOD and de-Emphasis levels are
set by registers.
The input control pins have been enhanced to have 4 different levels and provide a wider range of control
settings when ENSMB=0.
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Device Functional Modes (continued)
Table 2. Equalizer Settings
LEVEL
EQ_D1
EQ_S1
EQ_D0
EQ_S0
EQ – 8 BITS [7:0]
dB AT
1.25 GHz
dB AT
2.5 GHz
dB AT
4 GHz
dB AT
5 GHz
SUGGESTED USE (1)
1
0
0
0000 0000 = 0x00
2.1
3.7
4.9
5.3
FR4 < 5 inch trace
2
0
R
0000 0001 = 0x01
3.4
5.8
7.9
8.7
FR4 5 inch 5–mil trace
3
0
Float
0000 0010 = 0x02
4.8
7.7
9.9
10.6
FR4 5 inch 4–mil trace
4
0
1
0000 0011 = 0x03
5.9
8.9
11.0
11.7
FR4 10 inch 5–mil trace
5
R
0
0000 0111 = 0x07
7.2
11.2
14.3
15.6
FR4 10 inch 4–mil trace
6
R
R
0001 0101 = 0x15
6.1
11.4
14.6
16.6
FR4 15 inch 4–mil trace
7
R
Float
0000 1011 = 0x0B
8.8
13.5
17.0
18.3
FR4 20 inch 4–mil trace
8
R
1
0000 1111 = 0x0F
10.2
15.0
18.5
19.7
FR4 25 to 30 inch 4–mil trace
(1)
9
Float
0
0101 0101 = 0x55
7.5
12.8
18.0
20.3
FR4 30 inch 4–mil trace
10
Float
R
0001 1111 = 0x1F
11.4
17.4
22.0
23.6
FR4 35 inch 4–mil trace
11
Float
Float
0010 1111 = 0x2F
13.0
19.7
24.4
25.8
10-m, 30-awg cable
12
Float
1
0011 1111 = 0x3F
14.2
21.1
25.8
27.0
13
1
0
1010 1010 = 0xAA
13.8
21.7
27.4
29.1
14
1
R
0111 1111 = 0x7F
15.6
23.5
29.0
30.7
15
1
Float
1011 1111 = 0xBF
17.2
25.8
31.4
32.7
16
1
1
1111 1111 = 0xFF
18.4
27.3
32.7
33.8
10-m – 12-m cable
FR4 lengths are for reference only. FR4 lengths based on a 100-Ω differential stripline with 5-mil traces and 8-mil trace separation.
Table 3. De-Emphasis and Output Voltage Settings
(1)
16
LEVEL
DEM_D1
DEM_S1
DEM_D0
DEM_S0
VOD Vp-p
DEM dB
INNER AMPLITUDE Vp-p
SUGGESTED USE (1)
1
2
0
0
0.6
0
0.6
FR4 <5 inch 4–mil trace
0
R
0.8
0
0.8
3
FR4 <5 inch 4–mil trace
0
Float
0.8
–3.5
0.55
FR4 10 inch 4–mil trace
4
0
1
0.9
0
1.0
FR4 <5 inch 4–mil trace
5
R
0
0.9
–3.5
0.45
FR4 10 inch 4–mil trace
6
R
R
0.9
–6
0.5
FR4 15 inch 4–mil trace
7
R
Float
1.0
0
1.0
FR4 <5 inch 4–mil trace
8
R
1
1.0
–3.5
0.7
FR4 10 inch 4–mil trace
9
Float
0
1.0
–6
0.5
FR4 15 inch 4–mil trace
10
Float
R
1.1
0
1.1
FR4 <5 inch 4–mil trace
11
Float
Float
1.1
–3.5
0.7
FR4 10 inch 4–mil trace
12
Float
1
1.1
–6
0.55
FR4 15 inch 4–mil trace
13
1
0
1.2
0
1.2
FR4 <5 inch 4–mil trace
14
1
R
1.2
–3.5
0.8
FR4 10 inch 4–mil trace
15
1
Float
1.2
–6
0.6
FR4 15 inch 4–mil trace
16
1
1
1.2
–9
0.45
FR4 20 inch 4–mil trace
The VOD output amplitude and DEM de-emphasis levels are set with the DEMD/S[1:0] pins.
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Table 4. Input Termination Condition with RESET, INPUT_EN and SEL0 / SEL1
RESET
INPUT_EN
SEL0
SEL1
1
X
X
Low Power
High Z
High Z
High Z
0
0
X
Manual Mux
Mode
50 Ω
50 Ω
50 Ω
0
R
X
Reserved
Reserved
Reserved
Reserved
High Z
Auto RX-Detect, output
tests every 12 msec until
detection occurs, input
termination is high-z until
detection; once detected
input termination is 50 Ω
Auto RX-Detect, output
tests every 12 msec until
detection occurs, input
termination is high-z until
detection; once detected
input termination is 50 Ω
Auto - continuous
poll, DIN_B
High Z
Auto RX-Detect, output
tests every 12 msec until
detection occurs, input
termination is high-z until
detection; once detected
input termination is 50 Ω
Auto RX-Detect, output
tests every 12 msec until
detection occurs, input
termination is high-z until
detection; once detected
input termination is 50 Ω
Auto - continuous
poll, DIN_A
Auto RX-Detect, output
tests every 12 msec until
detection occurs, input
High Z
termination is high-z until
detection; once detected
input termination is 50 Ω
Auto RX-Detect, output
tests every 12 msec until
detection occurs, input
termination is high-z until
detection; once detected
input termination is 50 Ω
Auto RX-Detect, output
tests every 12 msec until
detection occurs, input
termination is high-z until
detection; once detected
input termination is 50 Ω
50 Ω
0
0
0
F
F
F
0
R
F
INPUT_TERM
S_INA0, S_INA1
MODE
Auto - continuous
poll, DIN_B
INPUT_TERM
S_INB0, S_INB1
0
F
1
Auto - continuous
poll, DIN_A
Auto RX-Detect, output
tests every 12 msec until
detection occurs, input
High Z
termination is high-z until
detection; once detected
input termination is 50 Ω
0
1
X
Manual Fanout
Mode
50 Ω
50 Ω
INPUT_TERM
D_IN0, D_IN1
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Table 5. Mux/Switch and FANOUT Control
SEL0
18
SEL1
INPUT_EN
DESCRIPTION OF CONNECTION PATH
0
0
0
D_OUT0 connects to S_INB0.
D_OUT1 connects to S_INB1.
D_IN0 connects to S_OUTB0. S_OUTA0 is in IDLE (output muted).
D_IN1 connects to S_OUTB1. S_OUTA1 is in IDLE (output muted).
0
0
R
Reserved
0
0
F
D_OUT0 connects to S_INB0.
D_OUT1 connects to S_INB1.
D_IN0 connects to S_OUTB0. S_OUTA0 is in IDLE (output muted).
D_IN1 connects to S_OUTB1. S_OUTA1 is in IDLE (output muted).
0
0
1
D_OUT0 connects to S_INB0.
D_OUT1 connects to S_INB1.
D_IN0 connects to S_OUTB0 and S_OUTA0.
D_IN1 connects to S_OUTB1 and S_OUTA1.
R
R
0
D_OUT0 connects to S_INB0.
D_OUT1 connects to S_INB1.
D_IN0 connects to S_OUTA0. S_OUTB0 is in IDLE (output muted).
D_IN1 connects to S_OUTA1. S_OUTB1 is in IDLE (output muted).
R
R
R
Reserved
R
R
F
D_OUT0 connects to S_INB0.
D_OUT1 connects to S_INB1.
D_IN0 connects to S_OUTA0. S_OUTB0 is in IDLE (output muted).
D_IN1 connects to S_OUTA1. S_OUTB1 is in IDLE (output muted).
R
R
1
D_OUT0 connects to S_INB0.
D_OUT1 connects to S_INB1.
D_IN0 connects to S_OUTB0 and S_OUTA0.
D_IN1 connects to S_OUTB1 and S_OUTA1.
F
F
0
D_OUT0 connects to S_INA0.
D_OUT1 connects to S_INA1.
D_IN0 connects to S_OUTB0. S_OUTA0 is in IDLE (output muted).
D_IN1 connects to S_OUTB1. S_OUTA1 is in IDLE (output muted).
F
F
R
Reserved
F
F
F
D_OUT0 connects to S_INA0.
D_OUT1 connects to S_INA1.
D_IN0 connects to S_OUTB0. S_OUTA0 is in IDLE (output muted).
D_IN1 connects to S_OUTB1. S_OUTA1 is in IDLE (output muted).
F
F
1
D_OUT0 connects to S_INA0.
D_OUT1 connects to S_INA1.
D_IN0 connects to S_OUTB0 and S_OUTA0.
D_IN1 connects to S_OUTB1 and S_OUTA1.
1
1
0
D_OUT0 connects to S_INA0.
D_OUT1 connects to S_INA1.
D_IN0 connects to S_OUTA0. S_OUTB0 is in IDLE (output muted).
D_IN1 connects to S_OUTA1. S_OUTB1 is in IDLE (output muted).
1
1
R
Reserved
1
1
F
D_OUT0 connects to S_INA0.
D_OUT1 connects to S_INA1.
D_IN0 connects to S_OUTA0. S_OUTB0 is in IDLE (output muted).
D_IN1 connects to S_OUTA1. S_OUTB1 is in IDLE (output muted).
1
1
1
D_OUT0 connects to S_INA0.
D_OUT1 connects to S_INA1.
D_IN0 connects to S_OUTA0 and S_OUTB0.
D_IN1 connects to S_OUTA1 and S_OUTB1.
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7.5 Programming
7.5.1 SMBUS Master Mode
The DS100MB203 devices support reading directly from an external EEPROM device by implementing SMBus
Master mode. When using the SMBus master mode, the DS100MB203 will read directly from specific location in
the external EEPROM. When designing a system for using the external EEPROM, the user needs to follow these
specific guidelines below.
NOTE
SEL0, SEL1 and INPUT_EN control are to be set with the external strap pins because
there are no register bits to configure them.
•
•
•
Set ENSMB = Float – enable the SMBUS master mode.
The external EEPROM device address byte must be 0xA0'h and capable of 1-MHz operation at 2.5-V and
3.3-V supply. The maximum allowed size is 8 kbits (1024 bytes).
Set the AD[3:0] inputs for SMBus address byte. When the AD[3:0] = 0000'b, the device address byte is B0'h.
When tying multiple DS100MB203 devices to the SDA and SCL bus, use these guidelines to configure the
devices.
• Use SMBus AD[3:0] address bits so that each device can loaded its configuration from the EEPROM.
Example below is for 4 device.
U1: AD[3:0] = 0000 = 0xB0'h,
U2: AD[3:0] = 0001 = 0xB2'h,
U3: AD[3:0] = 0010 = 0xB4'h,
U4: AD[3:0] = 0011 = 0xB6'h
• Use a pull-up resistor on SDA and SCL; value = 2 kΩ
• Daisy-chain READEN# (pin 26) and ALL_DONE# (pin 27) from one device to the next device in the sequence
so that they do not compete for the EEPROM at the same time.
1. Tie READEN# of the 1st device in the chain (U1) to GND
2. Tie ALL_DONE# of U1 to READEN# of U2
3. Tie ALL_DONE# of U2 to READEN# of U3
4. Tie ALL_DONE# of U3 to READEN# of U4
5. Optional: Tie ALL_DONE# output of U4 to a LED to show the devices have been loaded successfully
Below is an example of a 2 kbits (256 x 8-bit) EEPROM in hex format for the DS100MB203 device. The first 3
bytes of the EEPROM always contain a header common and necessary to control initialization of all devices
connected to the I2C bus. CRC enable flag to enable/disable CRC checking. If CRC checking is disabled, a fixed
pattern (8’hA5) is written/read instead of the CRC byte from the CRC location, to simplify the control. There is a
MAP bit to flag the presence of an address map that specifies the configuration data start in the EEPROM. If the
MAP bit is not present the configuration data start address is derived from the DS100MB203 address and the
configuration data size. A bit to indicate an EEPROM size > 256 bytes is necessary to properly address the
EEPROM. There are 37 bytes of data size for each DS100MB203 device.
:2000000000001000000407002FAD4002FAD4002FAD4002FAD409805F5A8005F5A8005F5AD0
:200020008005F5A800005454000000000000000000000000000000000000000000000000F6
:20006000000000000000000000000000000000000000000000000000000000000000000080
:20008000000000000000000000000000000000000000000000000000000000000000000060
:2000A000000000000000000000000000000000000000000000000000000000000000000040
:2000C000000000000000000000000000000000000000000000000000000000000000000020
:2000E000000000000000000000000000000000000000000000000000000000000000000000
:200040000000000000000000000000000000000000000000000000000000000000000000A0
NOTE
The maximum EEPROM size supported is 8 kbits (1024 × 8 bits). For more information in
regards to EEPROM programming and the hex format, see SNLA228.
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7.6 Register Maps
7.6.1 System Management Bus (SMBus) and Configuration Registers
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB = 1 kΩ
to VDD to enable SMBus slave mode and allow access to the configuration registers.
The DS100MB203 has the AD[3:0] inputs in SMBus mode. These pins are the user set SMBUS slave address
inputs. The AD[3:0] pins have internal pulldown. When left floating or pulled low the AD[3:0] = 0000'b, the device
default address byte is B0'h. Based on the SMBus 2.0 specification, the DS100MB203 has a 7-bit slave address.
The LSB is set to 0'b (for a WRITE). The device supports up to 16 address bytes, which can be set with the
AD[3:0] inputs. Below are the 16 addresses.
Table 6. Device Slave Address Bytes
AD[3:0] SETTINGS
ADDRESS BYTES (HEX)
0000
B0
0001
B2
0010
B4
0011
B6
0100
B8
0101
BA
0110
BC
0111
BE
1000
C0
1001
C2
1010
C4
1011
C6
1100
C8
1101
CA
1110
CC
1111
CE
The SDA, SCL pins are 3.3-V tolerant, but are not 5-V tolerant. External pullup resistor is required on the SDA.
The resistor value can be from 1 kΩ to 5 kΩ depending on the voltage, loading and speed. The SCL may also
require an external pullup resistor and it depends on the Host that drives the bus.
7.6.1.1 Transfer of Data Through the SMBus
During normal operation the data on SDA must be stable during the time when SCL is high.
There are three unique states for the SMBus:
• START: A high-to-low transition on SDA while SCL is high indicates a message START condition.
• STOP: A low-to-high transition on SDA while SCL is high indicates a message STOP condition.
• IDLE: If SCL and SDA are both high for a time exceeding tBUF from the last detected STOP condition or if
they are high for a total exceeding the maximum specification for tHIGH then the bus will transfer
to the IDLE state.
7.6.1.2 SMBus Transactions
The device supports WRITE and READ transactions. See Table 8 for register address, type (Read/Write, Read
Only), default value and function information.
20
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7.6.1.3 Writing a Register
To
1.
2.
3.
4.
5.
6.
7.
write a register, the following protocol is used (see SMBus 2.0 specification).
The host drives a START condition, the 7-bit SMBus address, and a 0 indicating a WRITE.
The device (slave) drives the ACK bit (0).
The host drives the 8-bit register address.
The device drives an ACK bit (0).
The host drive the 8-bit data byte.
The device drives an ACK bit (0).
The host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices
may now occur.
7.6.1.4 Reading a Register
To read a register, the following protocol is used (see SMBus 2.0 specification).
1. The host drives a START condition, the 7-bit SMBus address, and a 0 indicating a WRITE.
2. The device (Slave) drives the ACK bit (0).
3. The host drives the 8-bit register address.
4. The device drives an ACK bit (0).
5. The host drives a START condition.
6. The host drives the 7-bit SMBus Address, and a 1 indicating a READ.
7. The device drives an ACK bit 0.
8. The device drives the 8-bit data value (register contents).
9. The host drives a NACK bit 1 indicating end of the READ transfer.
10. The host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices
may now occur.
Please see Table 7 for more information.
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Table 7. SMBUS Slave Mode Register Map
ADDRESS
0x00
0x01
0x02
FIELD
TYPE
7
Reserved
R/W
6:3
Address Bit
AD[3:0]
R
2
EEPROM Read
Done
R
1 = Device completed the read from external EEPROM
1
Block Reset
R/W
1: Block bit 0 from resetting the registers; self clearing.
0
Reset
R/W
SMBus reset
1: Reset registers to default value; self clearing.
R/W
Power down per channel
[7]: CH7 (NC – S_OUTB1)
[6]: CH6 (D_IN1 – S_OUTA1)
[5]: CH5 (NC – S_OUTB0)
[4]: CH4 (D_IN0 – S_OUTA0)
[3]: CH3 (D_OUT1 – S_INB1)
[2]: CH2 (NC – S_INA1)
[1]: CH1 (D_OUT0 – S_INB0)
[0]: CH0 (NC – S_INA0)
0x00 = all channels enabled
0xFF = all channels disabled
Note: Override PWDN pin and enable register control through Reg 0x02[0]
Observation
PWDN Channels
Override RESET
Control
DEFAULT
Observation of AD[3:0] bits
[6]: AD3
[5]: AD2
[4]: AD1
[3]: AD0
0x00
7:0
PWDN CHx
7
Reserved
6
Reserved
5:2
Reserved
1
Reserved
0
Override RESET
DESCRIPTION
Set bit to 0
0x00
Yes
Set bit to 0
Set bit to 0
R/W
0x00
Yes
Set bits to 0
Set bit to 0
Yes
Reserved
7:0
Reserved
R/W
0x00
0x04
Reserved
7:0
Reserved
R/W
0x00
0x05
Reserved
7:0
Reserved
R/W
0x00
7:5
Reserved
4
Reserved
3
Register Enable
2:0
Reserved
Slave Register Control
EEPROM
REG BIT
BIT
0x03
0x06
22
REGISTER
NAME
1: Block RESET pin control; use Reg_01 to configure.
0: Allow RESET pin control.
Set bits to 0
Yes
Set bits to 0
Reserved
Set bits to 0
Yes
R/W
0x10
Set bit to 1
1 = Enable SMBus slave mode register control
0 = Disable SMBus register control
Note: In order to change VOD, DEM, and EQ of the channels in slave
mode, this bit must be set to 1.
Set bits to 0
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Table 7. SMBUS Slave Mode Register Map (continued)
ADDRESS
REGISTER
NAME
0x07
Reserved
0x08
Override
Pin Control
BIT
FIELD
7:1
Reserved
0
Reserved
7
Reserved
6:4
Reserved
3
Override RXDET
2
TYPE
DEFAULT
R/W
0x01
Yes
1 = Block RXDET pin control (register control enabled)
0 = Allow RXDET pin control (register control disabled)
Override MODE
Yes
1: Block MODE pin control; use register to configure.
0: Allow MODE pin control
1:0
Reserved
Yes
Set bits to 0
R/W
0x00
7:0
Reserved
R/W
0x00
Reserved
7:0
Reserved
R
0x00
0x0B
Reserved
7
Reserved
R/W
6:0
Reserved
R/W
0x0C-0x0D
Reserved
7:0
Reserved
R/W
7:6
Reserved
5:4
Reserved
0x0F
0x10
Set bit to 1
Set bits to 0
Reserved
CH0
NC – S_INA0
EQ
Set bits to 0
Set bit to 0
0x09
CH0
NC – S_INA0
RXDET
DESCRIPTION
Yes
0x0A
0x0E
EEPROM
REG BIT
0x70
Set bits to 0
Set bit to 0
Yes
0x00
Set bits to 0
Set bits to 0
R/W
0x00
Yes
Set bits to 0
Yes
00'b = Input is Hi-Z impedance
01'b = Auto Rx-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination is Hi-Z
until detection; once detected input termination is 50 Ω
10'b = Auto Rx-Detect,
outputs test every 12 ms until detection occurs; termination is Hi-Z until
detection; once detected input termination is 50 Ω
11'b = Input is 50 Ω
Note: Override RXDET pin and enable register control via Reg 0x08[3]
3:2
RXDET
1:0
Reserved
7:0
EQ Control
R/W
0x2F
Yes
Reserved
7:0
Reserved
R/W
0xAD
Yes
7:3
Reserved
0x11
CH0
NC – S_INA0
Reserved
R/W
0x02
0x12
CH0
NC – S_INA0
Reserved
2:0
Reserved
7
Reserved
6:4
Reserved
3:2
Reserved
1:0
Reserved
Set bits to 111 0000'b
Set bits to 0
EQ Control - total of 256 levels.
See Table 2.
Set bits to 0
Yes
Yes
R/W
0x00
Set bit to 0
Set bits to 0
Yes
Set bits to 0
Yes
Set bits to 0
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Table 7. SMBUS Slave Mode Register Map (continued)
ADDRESS
REGISTER
NAME
BIT
FIELD
TYPE
DEFAULT
0x13-0x14
Reserved
7:0
Reserved
R/W
0x00
7:6
Reserved
5:4
Reserved
0x15
0x16
0x17
CH1
D_OUT0 – S_INB0
RXDET
CH1
D_OUT0 – S_INB0
EQ
CH1
D_OUT0 – S_INB0
VOD
3:2
RXDET
1:0
Reserved
7:0
EQ Control
7
DESCRIPTION
Set bits to 0
Set bits to 0
R/W
0x00
Yes
Set bits to 0
Yes
00'b = Input is Hi-Z impedance
01'b = Auto Rx-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination is Hi-Z
until detection; once detected input termination is 50 Ω
10'b = Auto Rx-Detect,
outputs test every 12 ms until detection occurs; termination is Hi-Z until
detection; once detected input termination is 50 Ω
11'b = Input is 50 Ω
Note: Override RXDET pin and enable register control through Reg 0x08[3]
Set bits to 0
Yes
EQ Control - total of 256 levels.
See Table 2.
Short Circuit
Protection
Yes
1 = Enable the short circuit protection
0 = Disable the short circuit protection
6
MODE Control
Yes
1 = PCIe GEN 1/2, 10GE
0 = PCIe GEN 3, 10G-KR
Note: Override the MODE pin in Reg_08.
5:3
Reserved
Yes
Set bits to 101'b
Yes
VOD Control:
000'b = 0.6 V
001'b = 0.7 V
010'b = 0.8 V
011'b = 0.9 V
100'b = 1.0 V
101'b = 1.1 (default)
110'b = 1.2
111'b = 1.3
R/W
R/W
2:0
24
EEPROM
REG BIT
VOD Control
0x2F
0xAD
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Table 7. SMBUS Slave Mode Register Map (continued)
ADDRESS
0x18
REGISTER
NAME
TYPE
FIELD
7
RXDET Status
6:5
Reserved
Set bits to 0
4:3
Reserved
Set bits to 0
0x19
0x1A-0x1B
Reserved
0x1C
CH2
NC – S_INA1
RXDET
0x1D
CH2
NC – S_INA1
EQ
0x1E
Reserved
0x1F
Reserved
Yes
DEM Control
000'b = 0 dB
001'b = –1.5 dB
010'b = –3.5 dB (default)
011'b = –5 dB
100'b = –6 dB
101'b = –8 dB
110'b = –9 dB
111'b = –12 dB
Yes
Set bit to 0
0x02
2:0
DEM Control
7
Reserved
6:4
Reserved
3:2
Reserved
1:0
Reserved
7:0
Reserved
7:6
Reserved
5:4
Reserved
R/W
R/W
0x00
R/W
0x00
Set bits to 0
Yes
Set bits to 0
Yes
Set bits to 0
Set bits to 0
Set bits to 0
R/W
0x00
Yes
Set bits to 0
Yes
00'b = Input is Hi-Z impedance
01'b = Auto Rx-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination is Hi-Z
until detection; once detected input termination is 50 Ω
10'b = Auto Rx-Detect,
outputs test every 12 ms until detection occurs; termination is Hi-Z until
detection; once detected input termination is 50 Ω
11'b = Input is 50 Ω
Note: Override RXDET pin and enable register control through Reg 0x08[3]
3:2
RXDET
1:0
Reserved
7:0
EQ Control
R/W
0x2F
Yes
7:0
Reserved
R/W
0xAD
Yes
Reserved
R/W
0x02
7:3
2:0
DESCRIPTION
Observation bit for RXDET CH1
1 = Input 50 Ω terminated to VDD
0 = Input is Hi-Z
R
CH1
D_OUT0 – S_INB0
DEM
CH1
D_OUT0 – S_INB0
Reserved
DEFAULT
EEPROM
REG BIT
BIT
Set bits to 0
EQ Control - total of 256 levels.
See Table 2.
Yes
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Table 7. SMBUS Slave Mode Register Map (continued)
ADDRESS
REGISTER
NAME
0x20
CH2
NC – S_INA1
Reserved
0x21-0x22
0x23
0x24
0x25
Reserved
CH3
D_OUT1 – S_INB1
RXDET
CH3
D_OUT1 – S_INB1
EQ
CH3
D_OUT1 – S_INB1
VOD
BIT
FIELD
7
Reserved
6:4
Reserved
3:2
Reserved
1:0
Reserved
7:0
Reserved
7:6
Reserved
5:4
Reserved
3:2
RXDET
1:0
Reserved
7:0
EQ Control
7
DEFAULT
EEPROM
REG BIT
Yes
R/W
R/W
0x00
DESCRIPTION
Set bit to 0
Set bits to 0
Yes
Set bits to 0
Yes
Set bits to 0
0x00
Set bits to 0
Set bits to 0
R/W
0x00
Yes
Set bits to 0
Yes
00'b = Input is Hi-Z impedance
01'b = Auto Rx-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination is Hi-Z
until detection; once detected input termination is 50 Ω
10'b = Auto Rx-Detect,
outputs test every 12 ms until detection occurs; termination is Hi-Z until
detection; once detected input termination is 50 Ω
11'b = Input is 50 Ω
Note: Override RXDET pin and enable register control through Reg 0x08[3]
Set bits to 0
Yes
EQ Control - total of 256 levels.
See Table 2.
Short Circuit
Protection
Yes
1 = Enable the short circuit protection
0 = Disable the short circuit protection
6
MODE Control
Yes
1 = PCIe GEN 1/2, 10GE
0 = PCIe GEN 3, 10G-KR
Note: override the MODE pin in Reg_08.
5:3
Reserved
Yes
Set bits to 101'b
Yes
VOD Control:
000'b = 0.6 V
001'b = 0.7 V
010'b = 0.8 V
011'b = 0.9 V
100'b = 1.0 V
101'b = 1.1 (default)
110'b = 1.2
111'b = 1.3
R/W
R/W
2:0
26
TYPE
VOD Control
0x2F
0xAD
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Table 7. SMBUS Slave Mode Register Map (continued)
ADDRESS
0x26
0x27
0x28
0x29-0x2A
REGISTER
NAME
TYPE
FIELD
7
RXDET Status
6:5
Reserved
Set bits to 0
4:3
Reserved
Set bits to 0
DEM Control
R/W
Yes
Set bit to 0
7
Reserved
6:4
Reserved
3:2
Reserved
1:0
Reserved
7
Reserved
6
Reserved
Yes
Set bit to 0
5:4
High SD_TH Status
Yes
Enable higher range of signal detect status thresholds
[5]: CH0 - CH3
[4]: CH4 - CH7
R/W
0x00
Set bits to 0
Yes
Set bits to 0
Yes
Set bits to 0
Set bit to 0
3:2
Fast Signal Detect
Status
Yes
Enable fast signal detect status
[3]: CH0 - CH3
[2]: CH4 - CH7
Note: In fast signal detect, assert/de-assert response occurs after
approximately 3-4 ns
1:0
Reduced SD Status
Gain
Yes
Enable reduced signal detect status gain
[1]: CH0 - CH3
[0]: CH4 - CH7
7:0
Reserved
Signal Detect Status
Control
Reserved
Yes
DEM Control
000'b = 0 dB
001'b = –1.5 dB
010'b = –3.5 dB (default)
011'b = –5 dB
100'b = –6 dB
101'b = –8 dB
110'b = –9 dB
111'b = –12 dB
0x02
2:0
DESCRIPTION
Observation bit for RXDET CH3 - CHB_3
1 = Input 50 Ω terminated to VDD
0 = Input is Hi-Z
R
CH3
D_OUT1 – S_INB1
DEM
CH3
D_OUT1 – S_INB1
Reserved
DEFAULT
EEPROM
REG BIT
BIT
R/W
R/W
0x0C
0x00
Set bits to 0
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Table 7. SMBUS Slave Mode Register Map (continued)
ADDRESS
REGISTER
NAME
0x2B
CH4
D_IN0 – S_OUTA0
RXDET
0x2C
CH4
D_IN0 – S_OUTA0
EQ
0x2D
CH4
D_IN0 – S_OUTA0
VOD
BIT
FIELD
7:6
Reserved
5:4
Reserved
3:2
RXDET
1:0
Reserved
7:0
EQ Control
7
DEFAULT
EEPROM
REG BIT
DESCRIPTION
Set bits to 0
R/W
0x00
Yes
Set bits to 0
Yes
00'b = Input is Hi-Z impedance
01'b = Auto Rx-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination is Hi-Z
until detection; once detected input termination is 50 Ω
10'b = Auto Rx-Detect,
outputs test every 12 ms until detection occurs; termination is Hi-Z until
detection; once detected input termination is 50 Ω
11'b = Input is 50 Ω
Note: Override RXDET pin and enable register control through Reg 0x08[3]
Set bits to 0
Yes
EQ Control - total of 256 levels.
See Table 2.
Short Circuit
Protection
Yes
1 = Enable the short circuit protection
0 = Disable the short circuit protection
6
MODE Control
Yes
1 = PCIe GEN 1/2, 10GE
0 = PCIe GEN 3, 10G-KR
Note: override the MODE pin in Reg_08.
5:3
Reserved
Yes
Set bits to 101'b
Yes
VOD Control:
000'b = 0.6 V
001'b = 0.7 V
010'b = 0.8 V
011'b = 0.9 V
100'b = 1.0 V
101'b = 1.1 (default)
110'b = 1.2
111'b = 1.3
R/W
R/W
2:0
28
TYPE
VOD Control
0x2F
0xAD
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Table 7. SMBUS Slave Mode Register Map (continued)
ADDRESS
0x2E
REGISTER
NAME
0x2F
0x30-0x31
Reserved
0x33
FIELD
7
RXDET Status
Reserved
CH5
NC – S_OUTB0
Reserved
DEFAULT
6:5
Reserved
Set bits to 0
4:3
Reserved
Set bits to 0
Yes
DEM Control
000'b = 0 dB
001'b = –1.5 dB
010'b = –3.5 dB (default)
011'b = –5 dB
100'b = –6 dB
101'b = –8 dB
110'b = –9 dB
111'b = –12 dB
Yes
Set bit to 0
0x02
2:0
DEM Control
7
Reserved
6:4
Reserved
3:2
Reserved
1:0
Reserved
7:0
Reserved
7:6
Reserved
5:4
Reserved
3:2
Reserved
1:0
Reserved
7:0
Reserved
DESCRIPTION
Observation bit for RXDET CH4 - CHA_0
1 = Input 50 Ω terminated to VDD
0 = Input is Hi-Z
R
CH4
D_IN0 – S_OUTA0
DEM
CH4
D_IN0 – S_OUTA0
Reserved
0x32
TYPE
EEPROM
REG BIT
BIT
R/W
R/W
0x00
R/W
0x00
Set bits to 0
Yes
Set bits to 0
Yes
Set bits to 0
Set bits to 0
Set bits to 0
R/W
0x00
Yes
Set bits to 0
Yes
Set bits to 0
Set bits to 0
R/W
0x2F
Yes
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Table 7. SMBUS Slave Mode Register Map (continued)
ADDRESS
0x34
0x35
REGISTER
NAME
CH5
NC – S_OUTB0
VOD
FIELD
7
Short Circuit
Protection
Yes
1 = Enable the short circuit protection
0 = Disable the short circuit protection
6
MODE Control
Yes
1 = PCIe GEN 1/2, 10GE
0 = PCIe GEN 3, 10G-KR
Note: Override the MODE pin in Reg_08.
5:3
Reserved
Yes
Set bits to 101'b
Yes
VOD Control:
000'b = 0.6 V
001'b = 0.7 V
010'b = 0.8 V
011'b = 0.9 V
100'b = 1.0 V
101'b = 1.1 (default)
110'b = 1.2
111'b = 1.3
R/W
0x36
0x37-0x38
Reserved
DEFAULT
0xAD
DESCRIPTION
2:0
VOD Control
7
RXDET Status
6:5
Reserved
Set bits to 0
4:3
Reserved
Set bits to 0
Observation bit for RXDET CH5 - CHA1
1 = Input 50 Ω terminated to VDD
0 = Input is Hi-Z
R
CH5
NC – S_OUTB0
DEM
CH5
NC – S_OUTB0
Reserved
30
TYPE
EEPROM
REG BIT
BIT
Yes
DEM Control
000'b = 0 dB
001'b = –1.5 dB
010'b = –3.5 dB (default)
011'b = –5 dB
100'b = –6 dB
101'b = –8 dB
110'b = –9 dB
111'b = –12 dB
Yes
Set bit to 0
0x02
2:0
DEM Control
7
Reserved
6:4
Reserved
3:2
Reserved
1:0
Reserved
7:0
Reserved
R/W
R/W
0x00
R/W
0x00
Set bits to 0
Yes
Set bits to 0
Yes
Set bits to 0
Set bits to 0
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SNLS396D – JANUARY 2012 – REVISED JANUARY 2016
Table 7. SMBUS Slave Mode Register Map (continued)
ADDRESS
REGISTER
NAME
0x39
CH6
D_IN1 – S_OUTA1
RXDET
0x3A
CH6
D_IN1 – S_OUTA1
EQ
0x3B
CH6
D_IN1 – S_OUTA1
VOD
BIT
FIELD
7:6
Reserved
5:4
Reserved
3:2
RXDET
1:0
Reserved
7:0
EQ Control
7
TYPE
DEFAULT
EEPROM
REG BIT
DESCRIPTION
Set bits to 0
R/W
0x00
Yes
Set bits to 0
Yes
00'b = Input is Hi-Z impedance
01'b = Auto Rx-Detect,
outputs test every 12 ms for 600 ms (50 times) then stops; termination is Hi-Z
until detection; once detected input termination is 50 Ω
10'b = Auto Rx-Detect,
outputs test every 12 ms until detection occurs; termination is Hi-Z until
detection; once detected input termination is 50 Ω
11'b = Input is 50 Ω
Note: Override RXDET pin and enable register control through Reg 0x08[3]
Set bits to 0
Yes
EQ Control - total of 256 levels.
See Table 2.
Short Circuit
Protection
Yes
1 = Enable the short circuit protection
0 = Disable the short circuit protection
6
MODE Control
Yes
1 = PCIe GEN 1/2, 10GE
0 = PCIe GEN 3, 10G-KR
Note: override the MODE pin in Reg_08.
5:3
Reserved
Yes
Set bits to 0101'b
Yes
VOD Control:
000'b = 0.6 V
001'b = 0.7 V
010'b = 0.8 V
011'b = 0.9 V
100'b = 1.0 V
101'b = 1.1 (default)
110'b = 1.2
111'b = 1.3
R/W
R/W
2:0
VOD Control
0x2F
0xAD
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Table 7. SMBUS Slave Mode Register Map (continued)
ADDRESS
0x3C
REGISTER
NAME
0x3D
0x3E-0x3F
Reserved
0x41
32
FIELD
7
RXDET Status
Reserved
CH7
NC – S_OUTB1
EQ
DEFAULT
6:5
Reserved
Set bits to 0
4:3
Reserved
Set bits to 0
Yes
DEM Control
000'b = 0 dB
001'b = –1.5 dB
010'b = –3.5 dB (default)
011'b = –5 dB
100'b = –6 dB
101'b = –8 dB
110'b = –9 dB
111'b = –12 dB
Yes
Set bit to 0
0x02
2:0
DEM Control
7
Reserved
6:4
Reserved
3:2
Reserved
1:0
Reserved
7:0
Reserved
7:6
Reserved
5:4
Reserved
3:2
Reserved
1:0
Reserved
7:0
EQ Control
DESCRIPTION
Observation bit for RXDET CH6 - CHA_2
1 = Input 50 Ω terminated to VDD
0 = Input is Hi-Z
R
CH6
D_IN1 – S_OUTA1
DEM
CH6
D_IN1 – S_OUTA1
Reserved
0x40
TYPE
EEPROM
REG BIT
BIT
R/W
R/W
0x00
R/W
0x00
Set bits to 0
Yes
Set bits to 0
Yes
Set bits to 0
Set bits to 0
Set bits to 0
R/W
0x00
Yes
Set bits to 0
Yes
Set bits to 0
Set bits to 0
R/W
0x2F
Yes
EQ Control - total of 256 levels.
See Table 2.
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SNLS396D – JANUARY 2012 – REVISED JANUARY 2016
Table 7. SMBUS Slave Mode Register Map (continued)
ADDRESS
0x42
0x43
REGISTER
NAME
CH7
NC – S_OUTB1
VOD
FIELD
7
Short Circuit
Protection
Yes
1 = Enable the short circuit protection
0 = Disable the short circuit protection
6
MODE Control
Yes
1 = PCIe GEN 1/2, 10GE
0 = PCIe GEN 3, 10G-KR
Note: Override the MODE pin in Reg_08.
5:3
Reserved
Yes
Set bits to 101'b
Yes
VOD Control:
000'b = 0.6 V
001'b = 0.7 V
010'b = 0.8 V
011'b = 0.9 V
100'b = 1.0 V
101'b = 1.1 (default)
110'b = 1.2
111'b = 1.3
R/W
7
RXDET Status
6:5
Reserved
Set bits to 0
4:3
Reserved
Set bits to 0
2:0
DEM Control
7
Reserved
6:4
Reserved
3:2
Reserved
1:0
Reserved
0x45
Reserved
7:0
0x46
Reserved
Reserved
0x49-0x4B
Reserved
Observation bit for RXDET CH7 - CHA_3
1 = Input 50 Ω terminated to VDD
0 = Input is Hi-Z
R
Yes
DEM Control
000'b = 0 dB
001'b = –1.5 dB
010'b = –3.5 dB (default)
011'b = –5 dB
100'b = –6 dB
101'b = –8 dB
110'b = –9 dB
111'b = –12 dB
Yes
Set bit to 0.
0x02
0x44
0x48
0xAD
DESCRIPTION
VOD Control
CH7
NC – S_OUTB1
DEM
Reserved
DEFAULT
2:0
CH7
NC – S_OUTB1
Reserved
0x47
TYPE
EEPROM
REG BIT
BIT
R/W
Set bits to 0.
R/W
0x00
Reserved
R/W
0x00
Set bits to 0.
7:0
Reserved
R/W
0x38
Set bits to 0x38
7:4
Reserved
3:0
Reserved
R/W
0x00
7:6
Reserved
R/W
5:0
Reserved
R/W
7:0
Reserved
R/W
0x05
0x00
Yes
Set bits to 0.
Yes
Set bits to 0.
Set bits to 0.
Yes
Set bits to 0.
Yes
Set bits to 0.
Set bits to 00 0101'b
Set bits to 0.
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Table 7. SMBUS Slave Mode Register Map (continued)
ADDRESS
REGISTER
NAME
0x4C
Reserved
0x4D-0x50
Reserved
7:5
VERSION
BIT
FIELD
TYPE
DEFAULT
7:3
Reserved
R/W
2:1
Reserved
R/W
0
Reserved
R/W
7:0
Reserved
R/W
0x00
R
0x46
EEPROM
REG BIT
Yes
0x00
DESCRIPTION
Set bits to 0.
Set bits to 0.
Yes
Set bits to 0.
Set bits to 0.
010'b
0x51
Device ID
4:0
ID
0x52-0x55
Reserved
7:0
Reserved
R/W
0x00
Set bits to 0.
0x56
Reserved
7:0
Reserved
R/W
0x10
Set bits to 0x10
0x57
Reserved
7:0
Reserved
R/W
0x64
Set bits to 0x64
0x58
Reserved
7:0
Reserved
R/W
0x21
Set bits to 0x21
7:1
Reserved
0
Reserved
R/W
0x00
0x59
Reserved
0x5A
Reserved
7:0
Reserved
R/W
0x5B
Reserved
7:0
Reserved
R/W
0x5C-0x5D
Reserved
7:0
Reserved
R/W
0x00
7:3
Reserved
2
Override SEL1 pin
1
Override SEL0 pin
0
Override INPUT_EN
pin
0x5E
Override SEL[1:0] and
INPUT_EN
0x5F
34
Set bits to 0.
Yes
Set bit to 0.
0x54
Yes
Set bits to 0x54
0x54
Yes
Set bits to 0x54
Set bits to 0.
Set bits to 0.
1: Block SEL1 pin control; use Reg_5F to configure.
0: Allow SEL1 pin control
R/W
0x00
1: Block SEL0 pin control; use Reg_5F to configure.
0: Allow SEL0 pin control
1: Block INPUT_EN pin control; use Reg_5F to configure.
0: Allow INPUT_EN pin control
SEL1 Control
Select for Lane 1.
00: 0 - selects input S_INB1±, output S_OUTB1±.
01: 20 kΩ to GND - selects input S_INB1±, output S_OUTA1±
10: FLOAT - selects input S_INA1±, output S_OUTB1±
11: 1 - selects input S_INA1±, output S_OUTA1±.
5:4
SEL0 Control
Select for Lane 0.
00: 0 - selects input S_INB0±, output S_OUTB0±.
01: 20kΩ to GND - selects input S_INB0±, output S_OUTA0±
10: FLOAT - selects input S_INA0±, output S_OUTB0±
11: 1 - selects input S_INA0±, output S_OUTA0±.
3:2
INPUT_EN Control
1:0
Reserved
7:6
Control SEL[1:0] and
INPUT_EN
0 0110'b
R/W
0x00
1: Block SEL0 pin control; use Reg_5F to configure.
0: Allow SEL0 pin control
1: Block INPUT_EN pin control; use Reg_5F to configure.
0: Allow INPUT_EN pin control
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SNLS396D – JANUARY 2012 – REVISED JANUARY 2016
Table 8. EEPROM Register Map With Default Value
EEPROM ADDRESS
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CRC_EN
Address Map
Present
EEPROM > 256
Bytes
Reserved
DEVICE
COUNT[3]
DEVICE
COUNT[2]
DEVICE
COUNT[1]
DEVICE
COUNT[0]
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
Max EEPROM
Burst size[7]
Max EEPROM
Burst size[6]
Max EEPROM
Burst size[5]
Max EEPROM
Burst size[4]
Max EEPROM
Burst size[3]
Max EEPROM
Burst size[2]
Max EEPROM
Burst size[1]
Max EEPROM
Burst size[0]
0
0
0
0
0
0
0
0
Description
PWDN_CH7
PWDN_CH6
PWDN_CH5
PWDN_CH4
PWDN_CH3
PWDN_CH2
PWDN_CH1
PWDN_CH0
SMBus Register
0x01[7]
0x01[6]
0x01[5]
0x01[4]
0x01[3]
0x01[2]
0x01[1]
0x01[0]
0
0
0
0
0
0
0
0
Description
Reserved
Reserved
Reserved
Reserved
Ovrd_RESET
Reserved
Reserved
Reserved
SMBus Register
0x02[5]
0x02[4]
0x02[3]
0x02[2]
0x02[0]
0x04[7]
0x04[6]
0x04[5]
0
0
0
0
0
0
0
0
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SMBus Register
0x04[4]
0x04[3]
0x04[2]
0x04[1]
0x04[0]
0x06[4]
0x08[6]
0x08[5]
0
0
0
0
0
1
0
0
Reserved
Ovrd_RXDET
Ovrd_MODE
Reserved
Reserved
Reserved
Reserved
Reserved
0x08[4]
0x08[3]
0x08[2]
0x08[1]
0x08[0]
0x0B[6]
0x0B[5]
0x0B[4]
0
0
0
0
0
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CH0_RXDET_1
CH0_RXDET_0
0x0B[3]
0x0B[2]
0x0B[1]
0x0B[0]
0x0E[5]
0x0E[4]
0x0E[3]
0x0E[2]
0
0
0
0
0
0
0
0
Description
CH0_EQ_7
CH0_EQ_6
CH0_EQ_5
CH0_EQ_4
CH0_EQ_3
CH0_EQ_2
CH0_EQ_1
CH0_EQ_0
SMBus Register
0x0F[7]
0x0F[6]
0x0F[5]
0x0F[4]
0x0F[3]
0x0F[2]
0x0F[1]
0x0F[0]
0
0
1
0
1
1
1
1
Description
Default
Value
0x00
0x00
Description
Default
Value
0x00
0x01
Description
Default
Value
Default
Value
Default
Value
Default
Value
0x02
0x00
0x03
0x00
0x04
0x00
0x05
0x04
Description
SMBus Register
Default
Value
0x06
0x07
Description
SMBus Register
Default
Value
Default
Value
0x07
0x00
0x2F
0x08
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Table 8. EEPROM Register Map With Default Value (continued)
EEPROM ADDRESS
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SMBus Register
0x10[7]
0x10[6]
0x10[5]
0x10[4]
0x10[3]
0x10[2]
0x10[1]
0x10[0]
1
0
1
0
1
1
0
1
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SMBus Register
0x11[2]
0x11[1]
0x11[0]
0x12[7]
0x12[3]
0x12[2]
0x12[1]
0x12[0]
0
1
0
0
0
0
0
0
Reserved
Reserved
CH1_RXDET_1
CH1_RXDET_0
CH1_EQ_7
CH1_EQ_6
CH1_EQ_5
CH1_EQ_4
0x15[5]
0x15[4]
0x15[3]
0x15[2]
0x16[7]
0x16[6]
0x16[5]
0x16[4]
0
0
0
0
0
0
1
0
CH1_EQ_3
CH1_EQ_2
CH1_EQ_1
CH1_EQ_0
CH1_SCP
CH1_Sel_MODE
Reserved
Reserved
0x16[3]
0x16[2]
0x16[1]
0x16[0]
0x17[7]
0x17[6]
0x17[5]
0x17[4]
1
1
1
1
1
0
1
0
Description
Reserved
CH1_VOD_2
CH1_VOD_1
CH1_VOD_0
CH1_DEM_2
CH1_DEM_1
CH1_DEM_0
Reserved
SMBus Register
0x17[3]
0x17[2]
0x17[1]
0x17[0]
0x18[2]
0x18[1]
0x18[0]
0x19[7]
1
1
0
1
0
1
0
0
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CH2_RXDET_1
CH2_RXDET_0
SMBus Register
0x19[3]
0x19[2]
0x19[1]
0x19[0]
0x1C[5]
0x1C[4]
0x1C[3]
0x1C[2]
0
0
0
0
0
0
0
0
Description
CH2_EQ_7
CH2_EQ_6
CH2_EQ_5
CH2_EQ_4
CH2_EQ_3
CH2_EQ_2
CH2_EQ_1
CH2_EQ_0
SMBus Register
0x1D[7]
0x1D[6]
0x1D[5]
0x1D[4]
0x1D[3]
0x1D[2]
0x1D[1]
0x1D[0]
0
0
1
0
1
1
1
1
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SMBus Register
0x1E[7]
0x1E[6]
0x1E[5]
0x1E[4]
0x1E[3]
0x1E[2]
0x1E[1]
0x1E[0]
1
0
1
0
1
1
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x1F[2]
0x1F[1]
0x1F[0]
0x20[7]
0x20[3]
0x20[2]
0x20[1]
0x20[0]
0
1
0
0
0
0
0
0
Default
Value
0x09
0xAD
Default
Value
0x0A
0x40
Description
SMBus Register
Default
Value
0x0B
0x02
Description
SMBus Register
Default
Value
0x0C
0xFA
Default
Value
0x0D
0xD4
Default
Value
0x0E
0x00
Default
Value
0x0F
0x2F
Default
Value
0x10
0xAD
Description
SMBus Register
Default
Value
36
0x40
0x11
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Table 8. EEPROM Register Map With Default Value (continued)
EEPROM ADDRESS
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Description
Reserved
Reserved
CH3_RXDET_1
CH3_RXDET_0
CH3_EQ_7
CH3_EQ_6
CH3_EQ_5
CH3_EQ_4
SMBus Register
0x23[5]
0x23[4]
0x23[3]
0x23[2]
0x24[7]
0x24[6]
0x24[5]
0x24[4]
0
0
0
0
0
0
1
0
Description
CH3_EQ_3
CH3_EQ_2
CH3_EQ_1
CH3_EQ_0
CH3_SCP
CH3_Sel_MODE
Reserved
Reserved
SMBus Register
0x24[3]
0x24[2]
0x24[1]
0x24[0]
0x25[7]
0x25[6]
0x25[5]
0x25[4]
1
1
1
1
1
0
1
0
Reserved
CH3_VOD_2
CH3_VOD_1
CH3_VOD_0
CH3_DEM_2
CH3_DEM_1
CH3_DEM_0
Reserved
0x25[3]
0x25[2]
0x25[1]
0x25[0]
0x26[2]
0x26[1]
0x26[0]
0x27[7]
1
1
0
1
0
1
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
hi_idle_SD CH0-3
hi_idle_SD CH4-7
fast_SD CH0-3
0x27[3]
0x27[2]
0x27[1]
0x27[0]
0x28[6]
0x28[5]
0x28[4]
0x28[3]
0
0
0
0
0
0
0
1
Description
fast_SD CH4-7
lo_gain_SD CH0-3 lo_gain_SD CH4-7 Reserved
Reserved
CH4_RXDET_1
CH4_RXDET_0
CH4_EQ_7
SMBus Register
0x28[2]
0x28[1]
0x28[0]
0x2B[5]
0x2B[4]
0x2B[3]
0x2B[2]
0x2C[7]
1
0
0
0
0
0
0
0
Description
CH4_EQ_6
CH4_EQ_5
CH4_EQ_4
CH4_EQ_3
CH4_EQ_2
CH4_EQ_1
CH4_EQ_0
CH4_SCP
SMBus Register
0x2C[6]
0x2C[5]
0x2C[4]
0x2C[3]
0x2C[2]
0x2C[1]
0x2C[0]
0x2D[7]
0
1
0
1
1
1
1
1
Description
CH4_Sel_MODE
Reserved
Reserved
Reserved
CH4_VOD_2
CH4_VOD_1
CH4_VOD_0
CH4_DEM_2
SMBus Register
0x2D[6]
0x2D[5]
0x2D[4]
0x2D[3]
0x2D[2]
0x2D[1]
0x2D[0]
0x2E[2]
0
1
0
1
1
0
1
0
Description
CH4_DEM_1
CH4_DEM_0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SMBus Register
0x2E[1]
0x2E[0]
0x2F[7]
0x2F[3]
0x2F[2]
0x2F[1]
0x2F[0]
0x32[5]
1
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x32[4]
0x32[3]
0x32[2]
0x33[7]
0x33[6]
0x33[5]
0x33[4]
0x33[3]
0
0
0
0
0
1
0
1
Default
Value
Default
Value
0x12
0x02
0x13
0xFA
Description
SMBus Register
Default
Value
0x14
0xD4
Description
SMBus Register
Default
Value
Default
Value
Default
Value
Default
Value
Default
Value
0x15
0x01
0x16
0x80
0x17
0x5F
0x18
0x5A
0x19
0x80
Description
SMBus Register
Default
Value
0x05
0x1A
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Table 8. EEPROM Register Map With Default Value (continued)
EEPROM ADDRESS
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Description
Reserved
Reserved
Reserved
CH5_SCP
CH5_Sel_MODE
Reserved
Reserved
Reserved
SMBus Register
0x33[2]
0x33[1]
0x33[0]
0x34[7]
0x34[6]
0x34[5]
0x34[4]
0x34[3]
1
1
1
1
0
1
0
1
Description
CH5_VOD_2
CH5_VOD_1
CH5_VOD_0
CH5_DEM_2
CH5_DEM_1
CH5_DEM_0
Reserved
Reserved
SMBus Register
0x34[2]
0x34[1]
0x34[0]
0x35[2]
0x35[1]
0x35[0]
0x36[7]
0x36[3]
1
0
1
0
1
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
CH6_RXDET_1
CH6_RXDET_0
CH6_EQ_7
0x36[2]
0x36[1]
0x36[0]
0x39[5]
0x39[4]
0x39[3]
0x39[2]
0x3A[7]
0
0
0
0
0
0
0
0
CH6_EQ_6
CH6_EQ_5
CH6_EQ_4
CH6_EQ_3
CH6_EQ_2
CH6_EQ_1
CH6_EQ_0
CH6_SCP
0x3A[6]
0x3A[5]
0x3A[4]
0x3A[3]
0x3A[2]
0x3A[1]
0x3A[0]
0x3B[7]
0
1
0
1
1
1
1
1
Description
CH6_Sel_MODE
Reserved
Reserved
Reserved
CH6_VOD_2
CH6_VOD_1
CH6_VOD_0
CH6_DEM_2
SMBus Register
0x3B[6]
0x3B[5]
0x3B[4]
0x3B[3]
0x3B[2]
0x3B[1]
0x3B[0]
0x3C[2]
0
1
0
1
1
0
1
0
Description
CH6_DEM_1
CH6_DEM_0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SMBus Register
0x3C[1]
0x3C[0]
0x3D[7]
0x3D[3]
0x3D[2]
0x3D[1]
0x3D[0]
0x40[5]
1
0
0
0
0
0
0
0
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SMBus Register
0x40[4]
0x40[3]
0x40[2]
0x41[7]
0x41[6]
0x41[5]
0x41[4]
0x41[3]
0
0
0
0
0
1
0
1
Description
Reserved
Reserved
Reserved
CH7_SCP
CH7_Sel_MODE
Reserved
Reserved
Reserved
SMBus Register
0x41[2]
0x41[1]
0x41[0]
0x42[7]
0x42[6]
0x42[5]
0x42[4]
0x42[3]
1
1
1
1
0
1
0
1
CH7_VOD_2
CH7_VOD_1
CH7_VOD_0
CH7_DEM_2
CH7_DEM_1
CH7_DEM_0
Reserved
Reserved
0x42[2]
0x42[1]
0x42[0]
0x43[2]
0x43[1]
0x43[0]
0x44[7]
0x44[3]
1
0
1
0
1
0
0
0
Default
Value
0x1B
0xF5
Default
Value
0x1C
0xA8
Description
SMBus Register
Default
Value
0x1D
0x00
Description
SMBus Register
Default
Value
0x1E
0x5F
Default
Value
0x1F
0x5A
Default
Value
0x20
0x80
Default
Value
0x21
0x05
Default
Value
0x22
0xF5
Description
SMBus Register
Default
Value
38
0xA8
0x23
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Table 8. EEPROM Register Map With Default Value (continued)
EEPROM ADDRESS
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SMBus Register
0x44[2]
0x44[1]
0x44[0]
0x47[3]
0x47[2]
0x47[1]
0x47[0]
0x48[7]
0
0
0
0
0
0
0
0
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SMBus Register
0x48[6]
0x4C[7]
0x4C[6]
0x4C[5]
0x4C[4]
0x4C[3]
0x4C[0]
0x59[0]
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x5A[7]
0x5A[6]
0x5A[5]
0x5A[4]
0x5A[3]
0x5A[2]
0x5A[1]
0x5A[0]
0
1
0
1
0
1
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x5B[7]
0x5B[6]
0x5B[5]
0x5B[4]
0x5B[3]
0x5B[2]
0x5B[1]
0x5B[0]
0
1
0
1
0
1
0
0
Default
Value
Default
Value
0x24
0x00
0x25
0x00
Description
SMBus Register
Default
Value
0x26
0x54
Description
SMBus Register
Default
Value
0x54
0x27
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8 Application and Implementation
8.1 Application Information
8.1.1 General Recommendations
The DS100MB203 is a high-performance circuit capable of delivering excellent performance. Pay careful
attention to the details associated with high-speed design as well as providing a clean power supply. Refer to the
information below and Revision 4 of the LVDS Owner's Manual for more detailed information on high speed
design tips to address signal integrity design issues.
Pattern
Generator
VID = 1.0 Vp-p,
DE = 0 dB
PRBS15
TL
Lossy Channel
IN
DS100MB203
OUT
Scope
BW = 60 GHz
Figure 8. Test Set-Up Connections Diagram
Pattern
Generator
VID = 1.0 Vp-p,
DE = 0 dB
PRBS15
TL1
Lossy Channel
IN
DS100MB203
OUT
TL2
Lossy Channel
Scope
BW = 60 GHz
Figure 9. Test Set-Up Connections Diagram
40
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8.2 Typical Application
MB203
SEL0
DRIVE 0
S_INA0
EXPANDER
TXA_0
DRIVE 1
D_OUT0
RX
S_INB0
TXB_0
TX
S_INA1
TXA_1
D_OUT1
S_INA1
TXB_1
EXPANDER
RX
S_OUTA0
RXA_0
D_IN0
TX
S_OUTB0
RXB_0
S_OUTA1
D_IN1
RXA_1
S_OUTB1
RXB_1
SEL1
Figure 10. Storage Application
8.2.1 Design Requirements
As with any high-speed design, there are many factors which influence the overall performance. Below are a list
of critical areas for consideration and study during design.
• Use 100-Ω impedance traces. Generally these are very loosely coupled to ease routing length differences.
• Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.
• The maximum body size for AC-coupling capacitors is 0402.
• Back-drill connector vias and signal vias to minimize stub length.
• Use Reference plane vias to ensure a low inductance path for the return current.
8.2.2 Detailed Design Procedure
The DS100MB203 is designed to be placed at an offset location with respect to the overall channel attenuation.
In order to optimize performance, the repeater requires tuning to extend the reach of the cable or trace length
while also recovering a solid eye opening. To tune the mux-buffer, the settings mentioned in Table 2 and Table 3
are recommended as a default starting point for most applications. Once these settings are configured, additional
tuning of the EQ and, to a lesser extent, VOD may be required to optimize the repeater performance for each
specific application environment.
Examples of the repeater performance as a generic high-speed datapath repeater are shown in the performance
curves in the Application Curves section.
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Typical Application (continued)
8.2.3 Application Curves
Figure 11. TL = 10-inch 5-mil FR4 Trace, 8 Gbps
MB203 Settings: EQ[1:0] = 0, F = 02'h, DEM[1:0] = 0, 1
Figure 12. TL = 20-inch 5–mil FR4 Trace, 8 Gbps
MB203 Settings: EQ[1:0] = 0, 1 = 03'h, DEM[1:0] = 0, 1
Figure 13. TL = 30-inch 5-mil FR4 Trace, 8 Gbps
MB203 Settings: EQ[1:0] = R, 0 = 07'h, DEM[1:0] = 0, 1
Figure 14. TL1 = 20-inch 5–mil FR4 Trace, TL2 = 10-inch
5–mil FR4 trace, 8 Gbps
MB203 Settings: EQ[1:0] = R, 1 = 03'h, DEM[1:0] = R, 0
9 Power Supply Recommendations
9.1 Power Supply Bypassing
The DS100MB203 has an optional internal voltage regulator to provide the 2.5-V supply to the device. In 3.3-V
mode, the VIN pin = 3.3 V is used to supply power to the device and the VDD pins should be left open. The
internal regulator will provide the 2.5 V to the VDD pins of the device and a 0.1-μF capacitor is needed at each of
the five VDD pins for power supply de-coupling (total capacitance should be ≤ 0.5 μF), and the VDD pins should
be left open. The VDD_SEL pin must be tied to GND to enable the internal regulator. In 2.5-V mode, the VIN pin
should be left open and 2.5-V supply must be applied to the VDD pins. The VDD_SEL pin must be left open (no
connect) to disable the internal regulator.
The DS100MB203 can be configured for 2.5-V operation or 3.3-V operation. The lists below outline required
connections for each supply selection.
42
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Power Supply Bypassing (continued)
For 3.3-V mode of operation, use the following steps:
1. Tie VDD_SEL = 0 with 1-kΩ resistor to GND.
2. Feed 3.3-V supply into VIN pin. Local 1.0-μF decoupling at VIN is recommended.
3. See information on VDD bypass below.
4. SDA and SCL pins should connect pullup resistor to VIN
5. Any 4-Level input which requires a connection to Logic 1 should use a 1-kΩ resistor to VIN
For 2.5-V mode of operation, use the following steps:
1. VDD_SEL = Float
2. VIN = Float
3. Feed 2.5-V supply into VDD pins.
4. See information on VDD bypass below.
5. SDA and SCL pins connect pullup resistor to VDD for 2.5-V uC SMBus IO
6. SDA and SCL pins connect pullup resistor to VDD for 3.3-V uC SMBus IO
7. Any 4-Level input which requires a connection to Logic 1 should use a 1-kΩ resistor to VDD
3.3 V mode
2.5 V mode
VDD_SEL
Enable
VDD_SEL
open
VIN
open
Disable
3.3 V
Capacitors can be
either tantalum or an
ultra-low ESR ceramic.
Internal
voltage
regulator
2.5 V
0.1 µF
0.1 µF
VDD
VDD
0.1 µF
0.1 µF
1 µF
VDD
VDD
10 µF
2.5 V
1 µF
VIN
10 µF
Internal
voltage
regulator
Capacitors can be
either tantalum or an
ultra-low ESR ceramic.
VDD
VDD
0.1 µF
0.1 µF
VDD
VDD
0.1 µF
0.1 µF
VDD
VDD
0.1 µF
0.1 µF
Place 0.1 µF close to VDD Pin
Total capacitance should be 7 0.5 µF
Place capacitors close to VDD Pin
Figure 15. 3.3-V or 2.5-V Supply Connection Diagram
Two approaches are recommended to ensure that the DS100MB203 is provided with an adequate power supply
bypass. First, the supply ( VDD) and ground (GND) pins should be connected to power planes routed on adjacent
layers of the printed-circuit-board. Second, pay careful attention to supply bypassing through the proper use of
bypass capacitors is required. A 0.1-μF bypass capacitor should be connected to each VDD pin such that the
capacitor is placed as close as possible to the device. Small body size capacitors (such as 0402) reduce the
parasitic inductance of the capacitor and also help in placement close to the VDD pin. If possible, the layer
thickness of the dielectric should be minimized so that the VDD and GND planes create a low inductance supply
with distributed capacitance.
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10 Layout
10.1 Layout Guidelines
The differential inputs and outputs are designed with 100-Ω differential terminations. Therefore, they should be
connected to interconnects with controlled differential impedance of approximately 85-110 Ω. It is preferable to
route differential lines primarily on one layer of the board, particularly for the input traces. The use of vias should
be avoided if possible. If vias must be used, they should be used sparingly and must be placed symmetrically for
each side of a given differential pair. Whenever differential vias are used, the layout must also provide for a low
inductance path for the return currents as well. Route the differential signals away from other signals and noise
sources on the printed-circuit-board. To minimize the effects of crosstalk, a 5:1 ratio or greater should be
maintained between inter-pair spacing and trace width. See AN-1187 Leadless Leadframe Package (LLP)
Application Report (SNOA401) for additional information on QFN (WQFN) packages.
The DS100MB203 pinout promotes easy high-speed routing and layout. To optimize DS100MB203 performance
refer to the following guidelines:
1. Place local VIN and VDD capacitors as close as possible to the device supply pins. Often the best location is
directly under the DS100MB203 pins to reduce the inductance path to the capacitor. In addition, bypass
capacitors may share a via with the DAP GND to minimize ground loop inductance.
2. Differential pairs going into or out of the DS100MB203 should have adequate pair-to-pair spacing to minimize
crosstalk.
3. Use return current via connections to link reference planes locally. This ensures a low inductance return
current path when the differential signal changes layers.
4. Optimize the via structure to minimize trace impedance mismatch.
5. Place GND vias around the DAP perimeter to ensure optimal electrical and thermal performance.
6. Use small body size AC coupling capacitors when possible—0402 or smaller size is preferred. The ACcoupling capacitors should be placed closer to the Rx on the channel.
Figure 16 depicts different transmission line topologies which can be used in various combinations to achieve the
optimal system performance. Impedance discontinuities at the differential via can be minimized or eliminated by
increasing the swell around each hole and providing for a low inductance return current path. When the via
structure is associated with thick backplane PCB, further optimization such as back drilling is often used to
reduce the detrimental high-frequency effects of stubs on the signal path.
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10.2 Layout Example
20 mils
EXTERNAL MICROSTRIP
100 mils
20 mils
INTERNAL STRIPLINE
VDD
VDD
18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
19
54
20
53
21
52
51
22
BOTTOM OF PKG
23
VDD
50
GND
24
49
25
48
26
47
46
27
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
VDD
VDD
Figure 16. Typical Routing Options
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Absolute Maximum Ratings for Soldering (SNOA549)
• Understanding EEPROM Programming for High Speed Repeaters and Mux Buffers (SNLA228)
• AN-1187 Leadless Leadframe Package (LLP) Application Report (SNOA401)
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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20-Jan-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DS100MB203SQ/NOPB
ACTIVE
WQFN
NJY
54
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
DS100MB203
DS100MB203SQE/NOPB
ACTIVE
WQFN
NJY
54
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
DS100MB203
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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20-Jan-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jan-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DS100MB203SQ/NOPB
WQFN
NJY
54
2000
330.0
16.4
5.8
10.3
1.0
12.0
16.0
Q1
DS100MB203SQE/NOPB
WQFN
NJY
54
250
178.0
16.4
5.8
10.3
1.0
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jan-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS100MB203SQ/NOPB
WQFN
NJY
54
2000
367.0
367.0
38.0
DS100MB203SQE/NOPB
WQFN
NJY
54
250
213.0
191.0
55.0
Pack Materials-Page 2
PACKAGE OUTLINE
NJY0054A
WQFN
SCALE 2.000
WQFN
5.6
5.4
B
A
PIN 1 INDEX AREA
0.5
0.3
0.3
0.2
10.1
9.9
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8 MAX
C
SEATING PLANE
2X 4
SEE TERMINAL
DETAIL
3.51±0.1
19
(0.1)
27
28
18
50X 0.5
7.5±0.1
2X
8.5
1
45
54
PIN 1 ID
(OPTIONAL)
46
54X
54X
0.5
0.3
0.3
0.2
0.1
0.05
C A
C
B
4214993/A 07/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
NJY0054A
WQFN
WQFN
(3.51)
SYMM
54X (0.6)
54
54X (0.25)
SEE DETAILS
46
1
45
50X (0.5)
(7.5)
SYMM
(9.8)
(1.17)
TYP
2X
(1.16)
28
18
( 0.2) TYP
VIA
19
27
(1) TYP
(5.3)
LAND PATTERN EXAMPLE
SCALE:8X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214993/A 07/2013
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
NJY0054A
WQFN
WQFN
SYMM
METAL
TYP
(0.855) TYP
46
54
54X (0.6)
54X (0.25)
1
45
50X (0.5)
(1.17)
TYP
SYMM
(9.8)
12X (0.97)
18
28
19
27
12X (1.51)
(5.3)
SOLDERPASTE EXAMPLE
BASED ON 0.125mm THICK STENCIL
EXPOSED PAD
67% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
4214993/A 07/2013
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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