CY27020
Spread Spectrum Clock Generator
Spread Spectrum Clock Generator
Features
Functional Description
■
Supports clock requirements for printers
■
48-MHz spread spectrum clock output
■
48-MHz reference clock output
The CY27020 clock generator provides a low EMI clock output
for printers. It features spread spectrum technology, a
modulation technique designed specifically for reducing EMI at
the fundamental frequency and its harmonics.
■
Two selectable spread percentages: –1% and –3%
For a complete list of related documentation, click here.
■
Integrated loop filter
■
48-MHz crystal or external clock input
■
3.3-V supply operation (2.5-V functional)
■
8-pin small outline integrated circuit (SOIC) package
Logic Block Diagram
XIN
Oscillator
REFOUT
XOUT
PLL
CLKOUT
SSON#
SSSEL
SSCG
Frequency Table
XIN
SSON#
SSSEL
REFOUT
CLKOUT
48.00 MHz
0
0
48.00 MHz
48.00 MHz at –1%
48.00 MHz
0
1
48.00 MHz
48.00 MHz at –3%
48.00 MHz
1
0
48.00 MHz
48.00 MHz (No Spread)
48.00 MHz
1
1
48.00 MHz
48.00 MHz (No Spread)
Cypress Semiconductor Corporation
Document Number: 38-07273 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 2, 2016
CY27020
Pin Configuration
Figure 1. 8-pin SOIC pinout
1
VDD
2
VSS
3
XIN
4
CY27020
CLKOUT
8
SSON#
7
REFOUT
6
SSSEL
5
XOUT
Pin Description
Type [1]
Pin
Name
I/o
Description
1
CLKOUT
O
2
VDD
PWR
3.3-V power supply
3
VSS
PWR
Ground
4
XIN
I
Oscillator buffer input. Connect to an external parallel resonant crystal (nominally
48.00 MHz) or externally generated 48 MHz reference clock.
5
XOUT
O
Oscillator buffer output. Connect to an external parallel resonant crystal. Do not
connect when an externally generated reference clock is applied at XIN.
Fixed frequency 48.00 MHz spread spectrum clock output. See Table on page 1
for frequency selections
6
SSSEL
I
PU
7
REFOUT
O
–
8
SSON#
I
PD
Spread spectrum percentage select input. See Table on page 1 for details.
Buffered output of XIN.
Spread spectrum enable input. When asserted LOW, spread spectrum is
enabled.
Spread Spectrum Clock Generation (SSCG)
Figure 2. No Spread vs Down Spread Example
Spread spectrum clock generation (SSCG) is a frequency
modulation technique used to reduce electromagnetic
interference radiation generated by repetitive digital signals,
mainly clocks. A clock accumulates electromagnetic energy at its
center frequency and its harmonics. Spread spectrum distributes
this energy over a small frequency band and decreases the peak
value of radiated energy over the spectrum. This technique is
achieved by modulating the clock around or below the center of
its nominal frequency by a certain percentage (which also
determines the energy distribution band).
The SSCG function is enabled when SSON# pin is asserted low,
resulting in a spread bandwidth that is down spread by either
–1% or –3%, selected by SSSEL (see Table on page 1).
Note
1. PU = Internal pull-up resistor, PD = Internal pull-down resistor.
Document Number: 38-07273 Rev. *H
Page 2 of 9
CY27020
Absolute Maximum Conditions
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.[2]
Minimum input voltage relative to VSS: ...............VSS – 0.3 V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
care should be taken to avoid application of any voltage higher
than the maximum rated voltages to this circuit. For proper
operation, the I/O pins should be constrained to the range:
VSS < I/O < VDD
Maximum input voltage relative to VDD: ............. VDD + 0.3 V
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
Storage temperature: ................................. –65 °C to 150 °C
Operating temperature: .................................. 0 °C to 70 °C
Maximum electrostatic discharge (ESD) protection: ...... 2 kV
Maximum power supply: ............................................... 5.5 V
Operating voltage: ..............................................2.5 V–3.6 V
DC Electrical Specifications
(VDD = 3.3 V ± 10%, TA = 0 °C to 70 °C) [3]
Parameter
Description
VIL
Input low voltage
VIH
Input high voltage
VthXIN
XIN threshold voltage
Conditions
SSON#, SSSEL
Min
Typ
Max
Unit
–
–
0.8
V
2.2
–
–
V
0.3 × VDD
0.5 × VDD
0.7 × VDD
V
IIL1
Input low current
SSON# = VSS
–5
0
5
A
IIH1
Input high current
SSON# = VDD
3
8
20
A
IIL2
Input low current
SSEL = VSS
–36
–16.5
–7.4
A
IIH2
Input high current
SSEL = VDD
–5
0
5
A
IDD3.3V
Dynamic supply current
No output load
–
20
25
mA
VOL
Output low voltage
IOL = 4.0 mA
–
–
0.4
V
VOH
Output high voltage
IOH = –4.0 mA
Cin
Input capacitance
Pins 6 and 8
Cx
XIN, XOUT capacitance
Pins 4 and 5
PU/PD
Pull-up/pull-down resistance
SSON#, SSSEL
2.4
–
–
V
–
3
5
pF
–
3
5
pF
100
200
400
k
Notes
2. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. In applications where a crystal is used for the input reference clock, refer to the crystal manufacturer’s specifications for the required crystal load capacitor value.
Document Number: 38-07273 Rev. *H
Page 3 of 9
CY27020
AC Electrical Specifications
(VDD = 3.3 V ± 10%, TA = 0 °C to 70 °C)
Parameter
IFR
tr
tf
Description
Min
Typ
Max
Unit
Input frequency range
44
48
52
MHz
Rise time [4, 5]
–
1
2
ns
Fall time
Conditions
[4, 5]
–
1
2
ns
–
–1
–
%
SSON# = 0, SSSEL = 1
–
–3
–
%
All output clocks
–
–
3
ms
CL = 15 pF
45
50
55
%
REFOUT cycle-to-cycle jitter [4, 6] CL = 15 pF
–
–
350
ps
–
100
250
ps
SS%
Spread spectrum percentage
SSON# = 0, SSSEL = 0
tPU
Power-up to stable output[6]
tDC
Clock duty cycle [4, 6]
tCCJ
CLKOUT cycle-to-cycle jitter [4, 6]
Application Schematic Example
Figure 3. Application Schematic Example [7, 8]
VDD
0 .1 u F
VDD
2
X IN
7
4
CL1
REFOUT
33
C LKO U T
33
1
48 M H z
C Y27020
XOUT
5
CL2
6
VSS
SSSEL
8
3
VSS
SSON#
VSS
Notes
4. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs. All outputs loaded with
15 pF.
5. Measured between 0.1 x VDD and 0.9 x VDD volts.
6. Triggering is done at 1.5 V.
7. The circuit shows -1.0% spread. Refer to Frequency Table on page 1 for details.
8. Use the crystal manufacturer’s recommended values for CL1 and CL2 load capacitors.
Document Number: 38-07273 Rev. *H
Page 4 of 9
CY27020
Ordering Information
Part Number
Package Type
Production Flow
Pb-free
CY27020SXC
8-pin SOIC
Commercial, 0 °C to 70 °C
CY27020SXCT
8-pin SOIC - Tape and Reel
Commercial, 0 °C to 70 °C
Ordering Code Definitions
CY
27020
S
X
C
X
X = blank or T
blank = Tube; T = Tape and Reel
Temperature Range:
C = Commercial = 0 C to +70 C
X = Pb-free; X Absent = Leaded
Package Type:
S = 8-pin SOIC
Base Part Number
Company ID: CY = Cypress
Document Number: 38-07273 Rev. *H
Page 5 of 9
CY27020
Package Drawing and Dimension
Figure 4. 8-pin SOIC (150 Mils) S0815/SZ815/SW815 Package Outline, 51-85066
51-85066 *H
Document Number: 38-07273 Rev. *H
Page 6 of 9
CY27020
Acronyms
Document Conventions
Table 1. Acronyms Used in this Document
Acronym
Description
Units of Measure
Table 2. Units of Measure
CLKOUT
Reference Clock Out
EMI
Electromagnetic Interference
°C
ESD
Electrostatic Discharge
k
kilohm
PD
Power Down
MHz
megahertz
PLL
Phase Locked Loop
µA
microampere
PPM
Parts Per Million
µs
microsecond
SS
Spread Spectrum
mA
milliampere
SSC
Spread Spectrum Clock
ms
millisecond
SSCG
Spread Spectrum Clock Generation
mW
milliwatt
SSON
Spread Spectrum ON
ns
nanosecond
ohm
pF
picofarad
ps
picosecond
V
volt
W
watt
Document Number: 38-07273 Rev. *H
Symbol
Unit of Measure
degree Celsius
Page 7 of 9
CY27020
Document History Page
Document Title: CY27020, Spread Spectrum Clock Generator
Document Number: 38-07273
Rev.
ECN No.
Submission
Date
Orig. of
Change
**
110661
02/19/02
XHT
New data sheet.
Description of Change
*A
122868
12/21/02
RBI
Add power up requirements to maximum rating information
*B
279429
See ECN
RGL
Added Lead-free Devices
*C
2759365
09/02/2009
TSAI
Updated template.
Post to external web.
*D
2899304
03/25/2010
CXQ
Removed inactive parts from Ordering Information
Updated Package Drawing and Dimension.
*E
3041840
09/29/2010
CXQ
Removed “IC” from end of document title.
Fixed various formatting and typographical errors.
Change all SSON pin references to SSON#.
Added row to Table 1 for explicit select pin functional explanation.
Removed references to Cera-lock input.
Removed redundant Note 3.
*F
4162220
10/16/2013
CINM
Updated Package Drawing and Dimension:
spec 51-85066 – Changed revision from *D to *F.
Updated in new template.
Completing Sunset Review.
*G
4587350
12/05/2014
AJU
*H
5507104
11/02/2016
PAWK
Document Number: 38-07273 Rev. *H
Added related documentation hyperlink in page 1.
Updated the template.
Page 8 of 9
CY27020
Sales, Solutions, and Legal Information
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closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2002-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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Document Number: 38-07273 Rev. *H
Revised November 2, 2016
Page 9 of 9