14-Bit, 1.25 GSPS JESD204B, Dual Analog-to-Digital Converter AD9691 Data Sheet FUNCTIONAL BLOCK DIAGRAM FD_A FD_B VIN+B VIN–B V_1P0 BUFFER ADC CORE AVDD3 (3.3V) 14 AVDD_SR (1.25V) DVDD (1.25V) DIGITAL DOWNCONVERTER SIGNAL MONITOR ADC CORE 14 DIGITAL DOWNCONVERTER CONTROL REGISTERS BUFFER AD9691 AGND DRGND DGND JESD204B SUBCLASS 1 CONTROL SPI CONTROL ÷2 ÷4 ÷8 SDIO 8 SERDOUT0± SERDOUT1± SERDOUT2± SERDOUT3± SERDOUT4± SERDOUT5± SERDOUT6± SERDOUT7± FAST DETECT SIGNAL MONITOR CLOCK GENERATION CLK+ CLK– SPIVDD DRVDD (1.25V) (1.8V TO 3.3V) SCLK SYNCINB± SYSREF± PDWN/ STBY CSB 13092-001 VIN+A VIN–A AVDD2 (2.50V) Tx OUTPUTS AVDD1 (1.25V) FAST DETECT JESD204B (Subclass 1) coded serial digital outputs 1.9 W total power per channel (default settings) SFDR = 77 dBFS at 340 MHz SNR = 63.4 dBFS at 340 MHz (AIN = −1.0 dBFS) Noise density = −152.6 dBFS/Hz 1.25 V, 2.50 V, and 3.3 V dc supply operation No missing codes 1.58 V p-p differential full scale input voltage Flexible termination impedance 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential 1.5 GHz usable analog input full power bandwidth 95 dB channel isolation/crosstalk Amplitude detection bits for efficient AGC implementation 2 integrated wideband digital processors per channel 12-bit NCO, up to 4 cascaded half-band filters Integer clock divide by 1, 2, 4, or 8 Flexible JESD204B lane configurations Timestamp feature Small signal dither JESD204B HIGH SPEED SERIALIZER FEATURES Figure 1. APPLICATIONS Communications (wideband receivers and digital predistortion) Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions) DOCSIS 3.x CMTS upstream receive paths High speed data acquisition systems GENERAL DESCRIPTION The AD9691 is a dual, 14-bit, 1.25 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. The device is designed for sampling wide bandwidth analog signals of up to 1.5 GHz. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO) and four half-band decimation filters. In addition to the DDC blocks, the AD9691 has a programmable threshold detector that allows monitoring of the incoming signal power using the fast detect output bits of the ADC. Because Rev. 0 this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, four- or eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF± input pins. The AD9691 is available in a Pb-free, 88-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. Low power consumption analog core, 14-bit, 1.25 GSPS dual ADC with 1.9 W per channel. Wide full power bandwidth supports intermediate frequency (IF) sampling of signals up to 1.5 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 12 mm × 12 mm, 88-lead LFCSP. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9691 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DDC NCO Plus Mixer Loss and SFDR ................................... 34 Applications ....................................................................................... 1 Numerically Controlled Oscillator .......................................... 34 General Description ......................................................................... 1 FIR Filters ........................................................................................ 36 Functional Block Diagram .............................................................. 1 General Description ................................................................... 36 Product Highlights ........................................................................... 1 Half-Band Filters ........................................................................ 37 Revision History ............................................................................... 2 DDC Gain Stage ......................................................................... 39 Specifications..................................................................................... 3 DDC Complex to Real Conversion Block............................... 39 DC Specifications ......................................................................... 3 DDC Example Configurations ................................................. 40 AC Specifications.......................................................................... 4 Digital Outputs ............................................................................... 43 Digital Specifications ................................................................... 5 Introduction to the JESD204B Interface ................................. 43 Switching Specifications .............................................................. 6 JESD204B Overview .................................................................. 43 Timing Specifications .................................................................. 7 Functional Overview ................................................................. 44 Absolute Maximum Ratings ............................................................ 9 JESD204B Link Establishment ................................................. 45 Thermal Characteristics .............................................................. 9 Physical Layer (Driver) Outputs .............................................. 47 ESD Caution .................................................................................. 9 Configuring the JESD204B Link .............................................. 48 Pin Configuration and Function Descriptions ........................... 10 Multichip Synchronization............................................................ 51 Typical Performance Characteristics ........................................... 12 SYSREF± Setup/Hold Window Monitor ................................. 52 Equivalent Circuits ......................................................................... 16 Test Modes ....................................................................................... 54 Theory of Operation ...................................................................... 18 ADC Test Modes ........................................................................ 54 ADC Architecture ...................................................................... 18 JESD204B Block Test Modes .................................................... 54 Analog Input Considerations.................................................... 18 Serial Port Interface ........................................................................ 57 Voltage Reference ....................................................................... 20 Configuration Using the SPI ..................................................... 57 Clock Input Considerations ...................................................... 21 Hardware Interface ..................................................................... 57 Power-Down/Standby Mode .................................................... 22 SPI Accessible Features .............................................................. 57 Temperature Diode .................................................................... 22 Memory Map .................................................................................. 58 ADC Overrange and Fast Detect .................................................. 23 Reading the Memory Map Register Table............................... 58 ADC Overrange .......................................................................... 23 Memory Map Register Table ..................................................... 59 Fast Threshold Detection (FD_A and FD_B) ........................ 23 Applications Information .............................................................. 71 Signal Monitor ................................................................................ 24 Power Supply Recommendations............................................. 71 Digital Downconverters (DDCs).................................................. 27 Exposed Pad Thermal Heat Slug Recommendations ............ 71 DDC I/Q Input Selection .......................................................... 27 AVDD1_SR (Pin 78) and AGND (Pin 77 and Pin 81) .............. 71 DDC I/Q Output Selection ....................................................... 27 Outline Dimensions ....................................................................... 72 DDC General Description ........................................................ 27 Ordering Guide .......................................................................... 72 Frequency Translation ................................................................... 33 General Description ................................................................... 33 REVISION HISTORY 7/15—Revision 0: Initial Version Rev. 0 | Page 2 of 72 Data Sheet AD9691 SPECIFICATIONS DC SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate (1250 MSPS), 1.58 V p-p full-scale differential input, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Voltage INPUT REFERRED NOISE VREF = 1.0 V ANALOG INPUTS Differential Input Voltage Range Common-Mode Voltage (VCM) Differential Input Capacitance Analog Input Full Power Bandwidth POWER SUPPLY AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD SPIVDD IAVDD1 IAVDD2 IAVDD3 IAVDD1_SR IDVDD 1 IDRVDD 2 ISPIVDD POWER CONSUMPTION Total Power Dissipation (Including Output Drivers)1 Power-Down Dissipation Standby 3 1 2 3 Temperature Full Full Full Full Full Full Full Full Min 14 −0.31 −6 −0.8 −6.5 Typ Max Unit Bits Guaranteed 0 0 0 1 ±0.5 ±2.6 +0.31 0.3 +6 3.9 +0.8 +6.5 % FSR % FSR % FSR % FSR LSB LSB 25°C 25°C −26 ±9.8 ppm/°C ppm/°C Full 1.0 V 25°C 3.53 LSB rms Full 25°C 25°C 25°C 1.58 2.05 1.5 2 V p-p V pF GHz Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Default mode. No DDCs used. L = 8, M = 2, and F = 1. All lanes running. Power dissipation on DRVDD changes with the lane rate and number of lanes used. Standby mode can be controlled by the SPI. Rev. 0 | Page 3 of 72 1.22 2.44 3.2 1.22 1.22 1.22 1.7 1.25 2.50 3.3 1.25 1.25 1.25 1.8 800 670 125 15 250 310 5 3.8 0.9 1.5 1.28 2.56 3.4 1.28 1.28 1.28 3.4 840 770 140 18 290 380 6 V V V V V V V mA mA mA mA mA mA mA W mW W AD9691 Data Sheet AC SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate (1250 MSPS), 1.58 V p-p full-scale differential input, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted. Table 2. Parameter 1 ANALOG INPUT FULL SCALE NOISE DENSITY 2 SIGNAL-TO-NOISE RATIO (SNR) 3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 750 MHz fIN = 985 MHz fIN = 1205 MHz fIN = 1600 MHz fIN = 1950 MHz SNR AND DISTORTION RATIO (SINAD)3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 750 MHz fIN = 985 MHz fIN = 1205 MHz fIN = 1600 MHz fIN = 1950 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 750 MHz fIN = 985 MHz fIN = 1205 MHz fIN = 1600 MHz fIN = 1950 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR)3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 750 MHz fIN = 985 MHz fIN = 1205 MHz fIN = 1600 MHz fIN = 1950 MHz Temperature Full Full 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C Rev. 0 | Page 4 of 72 Min 60.8 60.5 9.7 72 Typ 1.58 −152.6 Max Unit V p-p dBFS/Hz 64.6 64.2 63.4 62.9 61.7 59.7 58.3 56.5 55.1 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS 64.5 64.0 63.0 62.3 61.3 59.4 57.5 55.8 54.7 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS 10.4 10.3 10.2 10.1 9.9 9.6 9.2 9.0 8.8 Bits Bits Bits Bits Bits Bits Bits Bits Bits 87 79 77 72 73 72 66 66 69 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS Data Sheet AD9691 Parameter 1 WORST HARMONIC, SECOND OR THIRD3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 750 MHz fIN = 985 MHz fIN = 1205 MHz fIN = 1600 MHz fIN = 1950 MHz WORST OTHER, EXCLUDING SECOND OR THIRD HARMONIC3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 750 MHz fIN = 985 MHz fIN = 1205 MHz fIN = 1600 MHz fIN = 1950 MHz TWO-TONE INTERMODULATION DISTORTION (IMD), AIN1 AND AIN2 = −7 dBFS fIN1 = 185 MHz, fIN2 = 188 MHz, Buffer Current Setting = 3.5× fIN1 = 449 MHz, fIN2 = 452 MHz, Buffer Current Setting = 6.5× CHANNEL ISOLATION/CROSSTALK 4 FULL POWER BANDWIDTH 5 Temperature Min Typ 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C −87 −84 −77 −72 −73 −72 −66 −66 −69 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C −93 −81 −79 −81 −77 −76 −72 −72 −73 25°C 25°C 25°C 25°C 82 78 95 1.5 Max −72 −76 Unit dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dB GHz See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Noise density is measured at a low analog input frequency (30 MHz). 3 See Table 10 for the recommended settings for full-scale voltage and buffer current control. 4 Crosstalk is measured at 170 MHz with a −1.0 dBFS analog input on one channel and no input on the adjacent channel. 5 Measured with the circuit shown in Figure 41. 1 2 DIGITAL SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate (1250 MSPS), 1.58 V p-p full-scale differential input, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted. Table 3. Parameter CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance SYSTEM REFERENCE INPUTS (SYSREF+, SYSREF−) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance (Differential) Temperature Full Full Full Full Full Full Full Full Full Full Rev. 0 | Page 5 of 72 Min 600 Typ LVDS/LVPECL 1200 0.85 35 Max Unit 1800 mV p-p V kΩ pF 2.5 400 0.6 LVDS/LVPECL 1200 0.85 35 1800 2.0 2.5 mV p-p V kΩ pF AD9691 Parameter LOGIC INPUTS (SDIO, SCLK, CSB, PDWN/STBY) Logic Compliance Logic 1 Voltage Logic 0 Voltage Input Resistance LOGIC OUTPUT (SDIO) Logic Compliance Logic 1 Voltage (IOH = 800 µA) Logic 0 Voltage (IOL = 50 µA) SYNC INPUTS (SYNCINB+, SYNCINB−) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC OUTPUTS (FD_A, FD_B) Logic Compliance Logic 1 Voltage Logic 0 Voltage Input Resistance DIGITAL OUTPUTS (SERDOUTx±, x = 0 TO 7) Logic Compliance Differential Output Voltage Output Common-Mode Voltage (VCM), AC-Coupled Short-Circuit Current (IDSHORT) Differential Return Loss (RLDIFF) 1 Common-Mode Return Loss (RLCM)1 Differential Termination Impedance 1 Data Sheet Temperature Min Typ Full Full Full Full 0.8 × SPIVDD 0 Max Unit 0.5 V V kΩ CMOS 30 Full Full Full CMOS 0.8 × SPIVDD 0 Full Full Full Full Full 400 0.6 Full Full Full Full V V 0.5 LVDS/LVPECL/CMOS 1200 1800 0.85 2.0 35 2.5 mV p-p V kΩ pF CMOS 0.8 × SPIVDD 0 V V kΩ 0.5 30 Full Full 25°C 25°C 25°C 25°C Full CML 360 0 −100 8 6 80 770 1.8 +100 100 mV p-p V mA dB dB Ω 120 Differential and common-mode return loss is measured from 100 MHz to 0.75 MHz × baud rate. SWITCHING SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate (1250 MSPS), 1.58 V p-p full-scale differential input, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted. Table 4. Parameter CLOCK Clock Rate (at CLK+/CLK− Pins) Maximum Sample Rate 1 Minimum Sample Rate 2 Clock Pulse Width High Low OUTPUT PARAMETERS Unit Interval (UI) 3 Rise Time (tR) (20% to 80% into 100 Ω Load) Fall Time (tF) (20% to 80% into 100 Ω Load) PLL Lock Time Data Rate per Channel (NRZ) 4 Temperature Min Full Full Full 0.3 1250 300 Full Full 400 400 Full 25°C 25°C 25°C 25°C 320 24 24 Rev. 0 | Page 6 of 72 3.125 Typ Max Unit 4 GHz MSPS MSPS ps ps 160 32 32 2 6.25 12.5 ps ps ps ms Gbps Data Sheet AD9691 Parameter LATENCY 5 Pipeline Latency Fast Detect Latency Wake-Up Time 6 Standby Power-Down APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter, tj) Out-of-Range Recovery Time Temperature Min Typ Full Full 55 25°C 25°C 1 Full Full Full 530 55 1 Max Unit 28 Clock cycles Clock cycles 4 ms ms ps fs rms Clock cycles The maximum sample rate is the clock rate after the divider. The minimum sample rate operates at 300 MSPS with L = 1. 3 Baud rate = 1/UI. A subset of this range is supported by the AD9691. 4 Default L = 8. This number can be changed based on the sample rate and decimation ratio. 5 No DDCs used. L = 8, M = 2, and F = 1. 6 Wake-up time is the time required to return to normal operation from power-down mode. 1 2 TIMING SPECIFICATIONS Table 5. Parameter CLK+ to SYSREF+ TIMING REQUIREMENTS tSU_SR tH_SR SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO Test Conditions/Comments See Figure 2 Device clock to SYSREF+ setup time Device clock to SYSREF+ hold time See Figure 3 Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK signal Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK must be in a logic high state Minimum period that SCLK must be in a logic low state Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 3) Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 3) Min Typ 117 −96 Max Unit ps ps 2 2 40 2 2 10 10 10 ns ns ns ns ns ns ns ns 10 ns Timing Diagrams CLK– CLK+ tSU_SR tH_SR 13092-002 SYSREF– SYSREF+ Figure 2. SYSREF+ Setup and Hold Timing Diagram Rev. 0 | Page 7 of 72 AD9691 Data Sheet tHIGH tDS tS tCLK tDH tH tLOW CSB SDIO DON’T CARE DON’T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 13092-003 SCLK DON’T CARE DON’T CARE Figure 3. SPI Timing Diagram APERTURE DELAY SAMPLE N N – 55 ANALOG INPUT SIGNAL N+1 N – 54 N–1 N – 53 N – 52 CLK– CLK+ CLK– CLK+ SERDOUT0– A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER0 MSB A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER0 MSB A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER0 LSB A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER0 LSB A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER1 MSB A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER1 MSB A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER1 LSB A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER1 LSB SERDOUT0+ SERDOUT1– SERDOUT1+ SERDOUT2– SERDOUT2+ SERDOUT3– SERDOUT3+ SERDOUT4– SERDOUT4+ SERDOUT5– SERDOUT5+ SERDOUT6– SERDOUT6+ SERDOUT7– SAMPLE N – 55 ENCODED INTO 1 8B/10B SYMBOL SAMPLE N – 54 ENCODED INTO 1 8B/10B SYMBOL SAMPLE N – 53 ENCODED INTO 1 8B/10B SYMBOL Figure 4. Data Output Timing (Full Bandwidth Mode, L = 8, M = 2, F = 1) Rev. 0 | Page 8 of 72 13092-004 SERDOUT7+ Data Sheet AD9691 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter Electrical AVDD1 to AGND AVDD1_SR to AGND AVDD2 to AGND AVDD3 to AGND DVDD to DGND DRVDD to DRGND SPIVDD to AGND AGND to DRGND VIN±x to AGND SCLK, SDIO, CSB to AGND PDWN/STBY to AGND Environmental Operating Temperature Range Maximum Junction Temperature Storage Temperature Range (Ambient) Rating 1.32 V 1.32 V 2.75 V 3.63 V 1.32 V 1.32 V 3.63 V −0.3 V to +0.3 V 3.2 V −0.3 V to SPIVDD + 0.3 V −0.3 V to SPIVDD + 0.3 V −40°C to +85°C 115°C −65°C to +150°C Typical θJA, ΨJB, θJC_TOP, and θJC_BOT values are specified vs. the number of printed circuit board (PCB) layers in different airflow velocities (in m/sec). Airflow increases heat dissipation effectively reducing θJA and ΨJB. The use of appropriate thermal management techniques is recommended to ensure that the maximum junction temperature does not exceed the limits shown in Table 7. Table 7. PCB Type JEDEC 2s2p Board Airflow Velocity (m/sec) 0.0 1.0 2.5 ΨJB1, 3 4.70 4.32 4.21 θJC_TOP1, 4 6.01 N/A5 N/A5 θJC_BOT1, 4 1.12 N/A5 N/A5 Per JEDEC 51-7, plus JEDEC 51-5 2s2p test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per JEDEC JESD51-8 (still air). 4 Per MIL-STD 883, Method 1012.1. 5 N/A means not applicable. 1 2 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. θJA1, 2 17.41 13.83 12.47 ESD CAUTION Rev. 0 | Page 9 of 72 Unit °C/W °C/W °C/W AD9691 Data Sheet 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 DNC AVDD1 AVDD2 DNC AVDD2 AVDD1 DNC AGND SYSREF– SYSREF+ AVDD1_SR AGND AVDD1 CLK– CLK+ DNC AVDD1 AVDD2 DNC AVDD2 AVDD1 DNC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 AD9691 TOP VIEW (Not to Scale) AVDD1 AVDD1 AVDD2 AVDD3 VIN–B VIN+B AVDD3 AVDD2 AVDD2 AVDD2 SPIVDD CSB SCLK SDIO DVDD DGND DNC DNC DNC DNC FD_B DNC NOTES 1. DNC = DO NOT CONNECT. THESE PINS MUST BE LEFT UNCONNECTED. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE GROUND REFERENCE FOR AVDDX. THE EXPOSED THERMAL PAD MUST BE CONNECTED TO AGND. 13092-005 DRGND DRVDD SYNCINB– SYNCINB+ SERDOUT0– SERDOUT0+ SERDOUT1– SERDOUT1+ SERDOUT2– SERDOUT2+ SERDOUT3– SERDOUT3+ SERDOUT4– SERDOUT4+ SERDOUT5– SERDOUT5+ SERDOUT6– SERDOUT6+ SERDOUT7– SERDOUT7+ DRVDD DRGND 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 AVDD1 AVDD1 AVDD2 AVDD3 VIN–A VIN+A AVDD3 AVDD2 AVDD2 AVDD2 AVDD2 V_1P0 SPIVDD PWDN/STBY DVDD DGND DNC DNC DNC DNC FD_A DNC Figure 5. Pin Configuration Table 8. Pin Function Descriptions Pin No. Power Supplies 0 Mnemonic Type Description EPAD Ground 1, 2, 65, 66, 68, 72, 76, 83, 87 3, 8, 9, 10, 11, 57, 58, 59, 64, 69, 71, 84, 86 4, 7, 60, 63 13, 56 15, 52 16, 51 23, 44 24, 43 77, 81 78 Analog 5, 6 12 AVDD1 AVDD2 Supply Supply Exposed Pad. The exposed thermal pad on the bottom of the package provides the ground reference for AVDDx. The exposed thermal pad must be connected to AGND. Analog Power Supply (1.25 V Nominal). Analog Power Supply (2.50 V Nominal). AVDD3 SPIVDD DVDD DGND DRGND DRVDD AGND 1 AVDD1_SR1 Supply Supply Supply Ground Ground Supply Ground Supply Analog Power Supply (3.3 V Nominal). Digital Power Supply for SPI (1.8 V to 3.3 V). Digital Power Supply (1.25 V Nominal). Ground Reference for DVDD. Ground Reference for DRVDD. Digital Driver Power Supply (1.25 V Nominal). Ground Reference for SYSREF±. Analog Power Supply for SYSREF± (1.25 V Nominal). VIN−A, VIN+A V_1P0 Input Input/DNC VIN+B, VIN−B CLK+, CLK− Input Input ADC A Analog Input Complement/True. 1.0 V Reference Voltage Input/Do Not Connect. This pin is configurable through the SPI as a no connect or as an input. Do not connect this pin if using the internal reference. This pin requires a 1.0 V reference voltage input if using an external voltage reference source. ADC B Analog Input True/Complement. Clock Input True/Complement. 61, 62 74, 75 Rev. 0 | Page 10 of 72 Data Sheet Pin No. CMOS Outputs 21, 46 Digital Inputs 25, 26 79, 80 Data Outputs 27, 28 29, 30 31, 32 33, 34 35, 36 37, 38 39, 40 41, 42 Device Under Test (DUT) Controls 14 53 54 55 No Connections 17, 18, 19, 20, 22, 45, 47, 48, 49, 50, 67, 70, 73, 82, 85, 88 1 AD9691 Mnemonic Type Description FD_A, FD_B Output Fast Detect Outputs for Channel A and Channel B, respectively. SYNCINB−, SYNCINB+ SYSREF+, SYSREF− Input Input Active Low JESD204B LVDS Sync Input Complement/True. Active Low JESD204B LVDS System Reference Input True/Complement. SERDOUT0−, SERDOUT0+ SERDOUT1−, SERDOUT1+ SERDOUT2−, SERDOUT2+ SERDOUT3−, SERDOUT3+ SERDOUT4−, SERDOUT4+ SERDOUT5−, SERDOUT5+ SERDOUT6−, SERDOUT6+ SERDOUT7−, SERDOUT7+ Output Output Output Output Output Output Output Output Lane 0 Output Data Complement/True. Lane 1 Output Data Complement/True. Lane 2 Output Data Complement/True. Lane 3 Output Data Complement/True. Lane 4 Output Data Complement/True. Lane 5 Output Data Complement/True. Lane 6 Output Data Complement/True. Lane 7 Output Data Complement/True. PDWN/STBY Input SDIO SCLK CSB Input/output Input Input Power-Down Input (Active High). The operation of this pin depends on the SPI mode and can be configured as powerdown or standby. SPI Serial Data Input/Output. SPI Serial Clock. SPI Chip Select (Active Low). DNC Do No Connect. These pins must be left unconnected. To ensure proper ADC operation, connect AVDD1_SR and AGND separately from the AVDD1 and EPAD connection. For more information, see the Applications Information section. Rev. 0 | Page 11 of 72 AD9691 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AVDD1 = 1.25 V, AVDD1_SR = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate (1250 MSPS), 1.58 V p-p full-scale differential input, AIN = −1.0 dBFS, default SPI settings, clock divider = 2, TA = 25°C, 128k FFT sample, unless otherwise noted. 0 0 AIN = –1dBFS SNR = 64.6dBFS ENOB = 10.4 BITS SFDR = 87dBFS BUFFER CURRENT = 3.5× –40 –60 –80 –40 –60 –80 13092-006 0 125 375 250 FREQUENCY (MHz) 500 –120 625 13092-009 –100 –100 –120 AIN = –1dBFS SNR = 62.9dBFS ENOB = 10.0 BITS SFDR = 72dBFS BUFFER CURRENT = 3.5× –20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –20 0 Figure 6. Single-Tone FFT with fIN = 10.3 MHz AIN = –1dBFS SNR = 64.2dBFS ENOB = 10.3 BITS SFDR = 79dBFS BUFFER CURRENT = 3.5× –40 AMPLITUDE (dBFS) –60 –80 –40 –60 –80 –100 13092-007 0 125 375 250 FREQUENCY (MHz) 500 –120 625 13092-010 AMPLITUDE (dBFS) 625 AIN = –1dBFS SNR = 61.7dBFS ENOB = 9.9 BITS SFDR = 73dBFS BUFFER CURRENT = 4.5× –20 –100 0 125 375 250 FREQUENCY (MHz) 500 625 Figure 10. Single-Tone FFT with fIN = 752.3 MHz Figure 7. Single-Tone FFT with fIN = 170.3 MHz 0 0 AIN = –1dBFS SNR = 63.4dBFS ENOB = 10.2 BITS SFDR = 77dBFS BUFFER CURRENT = 3.5× AIN = –1dBFS SNR = 59.7dBFS ENOB = 6.9 BITS SFDR = 72dBFS BUFFER CURRENT = 4.5× –20 AMPLITUDE (dBFS) –20 –40 –60 –80 –40 –60 –80 –100 13092-008 –100 0 125 375 250 FREQUENCY (MHz) 500 –120 625 13092-011 AMPLITUDE (dBFS) 500 0 –20 –120 375 250 FREQUENCY (MHz) Figure 9. Single-Tone FFT with fIN = 450.3 MHz 0 –120 125 0 125 375 250 FREQUENCY (MHz) 500 Figure 11. Single-Tone FFT with fIN = 985.3 MHz Figure 8. Single-Tone FFT with fIN = 340.3 MHz Rev. 0 | Page 12 of 72 625 Data Sheet AD9691 0 85 –40 SFDR 75 SNR/SFDR (dBFS) –60 –80 65 SNR 60 –100 13092-012 55 –120 0 125 250 375 FREQUENCY (MHz) 500 50 1000 625 1050 1100 1150 1200 1250 SAMPLE RATE (MHz) Figure 15. SNR/SFDR vs. Sample Rate (fS), fIN = 170.3 MHz, Buffer Current = 3.0× Figure 12. Single-Tone FFT with fIN = 1205.3 MHz 90 0 AIN = –1dBFS SNR = 56.5dBFS ENOB = 9.0 BITS SFDR = 66dBFS BUFFER CURRENT = 5.5× –20 85 80 –40 SNR/SFDR (dBFS) AMPLITUDE (dBFS) 70 13092-015 AMPLITUDE (dBFS) 80 AIN = –1dBFS SNR = 58.2dBFS ENOB = 9.3 BITS SFDR = 67dBFS BUFFER CURRENT = 4.5× –20 –60 –80 SFDR 75 70 SNR 65 60 –100 600.3 500.3 470.3 440.3 410.3 380.3 350.3 320.3 290.3 260.3 230.3 200.3 50 625 170.3 500 130.3 250 375 FREQUENCY (MHz) 100.3 125 9.6 0 70.3 –120 13092-016 13092-013 55 INPUT FREQUENCY (MHz) Figure 13. Single-Tone FFT with fIN = 1600.3 MHz Figure 16. SNR/SFDR vs. Input Frequency (fIN), fIN < 600 MHz, Buffer Current = 3.5× (See Figure 41 and Table 9) 80 0 AIN = –1dBFS SNR = 56.5dBFS ENOB = 9.0 BITS SFDR = 66dBFS BUFFER CURRENT = 7.5× 75 SFDR SNR/SFDR (dBFS) –40 –60 –80 70 65 SNR 60 –120 0 125 250 375 FREQUENCY (MHz) 500 Figure 14. Single-Tone FFT with fIN = 1950.3 MHz 50 700.3 625 13092-017 55 –100 13092-014 AMPLITUDE (dBFS) –20 800.3 900.3 1000.3 1100.3 1200.3 INPUT FREQUENCY (MHz) Figure 17. SNR/SFDR vs. Input Frequency (fIN), 700 MHz < fIN < 1200 MHz, Buffer Current = 4.5× (See Figure 41 and Table 9) Rev. 0 | Page 13 of 72 AD9691 Data Sheet 0 75 SFDR SFDR (dBc) –20 65 60 SNR –40 –60 IMD3 (dBc) –80 SFDR (dBFS) –100 55 IMD3 (dBFS) 50 1300.3 13092-018 –120 1400.3 1500.3 1600.3 1700.3 1800.3 1900.3 –140 –80 –74 –68 –62 –56 –50 –44 –38 –32 –26 –20 –14 1990.3 Figure 21. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 184 MHz and fIN2 = 187 MHz Figure 18. SNR/SFDR vs. Input Frequency (fIN), 1300 MHz < fIN < 2000 MHz, Buffer Current = 7.5× (See Figure 41 and Table 9) 0 0 SFDR/IMD3 (dBc AND dBFS) –40 –60 –80 –100 500 625 Figure 22. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 449 MHz and fIN2 = 452 MHz 110 AIN1 AND AIN2 = –7dBFS SFDR = 78dBFS IMD2 = 77dBFS IMD3 = 78dBFS BUFFER CURRENT = 6.5× –80 13092-020 –100 SNR (dBFS) 60 50 SFDR (dBc) 40 30 SNR (dBc) 20 10 ANALOG INPUT LEVEL (dBFS) Figure 20. Two-Tone FFT, fIN1 = 449 MHz, fIN2 = 452 MHz Figure 23. SNR/SFDR vs. Analog Input Level, fIN = 170.3 MHz, Buffer Current = 3.5× Rev. 0 | Page 14 of 72 0 –5 –10 –15 –20 –25 –30 –35 –40 0 625 –45 500 70 –65 –120 80 13092-023 SNR/SFDR (dBc AND dBFS) 90 –60 250 375 FREQUENCY (MHz) SFDR (dBFS) 100 –40 125 –8 INPUT AMPLITUDE (dBFS) 0 0 SFDR (dBFS) –100 IMD3 (dBFS) –140 –80 –74 –68 –62 –56 –50 –44 –38 –32 –26 –20 –14 Figure 19. Two-Tone FFT, fIN1 = 184 MHz, fIN2 = 187 MHz –20 –80 –50 250 375 FREQUENCY (MHz) IMD3 (dBc) –55 125 –60 –60 0 –40 –120 13092-019 –120 SFDR (dBc) –20 13092-022 AIN1 AND AIN2 = –7dBFS SFDR = 82dBFS IMD2 = 82dBFS IMD3 = 84dBFS BUFFER CURRENT = 3.5× –20 AMPLITUDE (dBFS) –8 INPUT AMPLITUDE (dBFS) INPUT FREQUENCY (MHz) AMPLITUDE (dBFS) 13092-021 SFDR/IMD3 (dBc AND dBFS) SNR/SFDR (dBFS) 70 Data Sheet 80 1000000 78 900000 SFDR 800000 NUMBER OF HITS 74 72 70 68 66 SNR 64 13092-024 600000 500000 400000 300000 20 60 40 100000 0 80 N – 10 N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 0 –20 700000 200000 62 60 –40 3.53 LSB RMS 13092-027 76 SNR/SFDR (dBFS) AD9691 TEMPERATURE (°C) OUTPUT CODE Figure 24. SNR/SFDR vs. Temperature, fIN = 170.3 MHz Figure 27. Input Referred Noise Histogram 4.00 2.5 2.0 3.95 1.5 0.5 POWER (W) INL (LSB) 1.0 0 –0.5 3.90 3.85 –1.0 0 2000 4000 8000 10000 6000 OUTPUT CODE 12000 14000 3.75 –40 16000 60 80 Figure 28. Power vs. Temperature 4.05 0.8 4.00 13092-029 SAMPLE RATE (MHz) Figure 26. DNL, fIN = 10 MHz Figure 29. Power Dissipation vs. Sample Rate (fS) Rev. 0 | Page 15 of 72 1300 3.60 1280 16000 1260 14000 1240 12000 1220 6000 8000 10000 OUTPUT CODE 1180 4000 1200 2000 3.65 1160 0 3.70 1000 13092-026 –0.6 3.75 1140 –0.4 3.80 1120 –0.2 3.85 1100 0 3.90 1080 0.2 1040 POWER DISSIPATION (W) 0.4 3.95 1020 0.6 DNL (LSB) 40 20 TEMPERATURE (°C) Figure 25. INL, fIN = 10.3 MHz –0.8 0 –20 1060 –2.5 13092-025 –2.0 13092-028 3.80 –1.5 AD9691 Data Sheet EQUIVALENT CIRCUITS AVDD3 AVDD3 VIN+x AVDD3 200Ω EMPHASIS/SWING CONTROL (SPI) VCM BUFFER DRVDD 200Ω DATA+ AVDD3 AVDD3 SERDOUTx+ x = 0 TO 7 3pF SERDOUTx– x = 0 TO 7 DRGND Figure 30. Analog Inputs Figure 33. Digital Outputs AVDD1 DVDD 25Ω SYNCINB+ 1kΩ DGND AVDD1 25Ω CLK– DRVDD DATA– 13092-030 AIN CONTROL (SPI) CLK+ DRGND OUTPUT DRIVER VIN–x VCM = 0.85V 13092-031 20kΩ SYNCINB– LEVEL TRANSLATOR VCM 1kΩ DGND Figure 31. Clock Inputs VCM = 0.85V 20kΩ DVDD 20kΩ 20kΩ SYNCINB± PIN CONTROL (SPI) 13092-034 200Ω 67Ω 10pF 28Ω 400Ω Figure 34. SYNCINB± Inputs AVDD1_SR SYSREF+ 1kΩ SPIVDD 20kΩ LEVEL TRANSLATOR AVDD1_SR ESD PROTECTED VCM = 0.85V 20kΩ SCLK SPIVDD 1kΩ 30kΩ 1kΩ ESD PROTECTED 13092-035 13092-032 SYSREF– 13092-033 67Ω 200Ω 28Ω 3pF Figure 35. SCLK Input Figure 32. SYSREF± Inputs Rev. 0 | Page 16 of 72 Data Sheet AD9691 SPIVDD ESD PROTECTED 30kΩ 1kΩ CSB 30kΩ 1kΩ PDWN/ STBY ESD PROTECTED 13092-036 ESD PROTECTED Figure 36. CSB Input PDWN CONTROL (SPI) Figure 39. PDWN/STBY Input AVDD2 SPIVDD ESD PROTECTED SDO ESD PROTECTED SPIVDD 1kΩ SDIO 13092-039 ESD PROTECTED SPIVDD SDI V_1P0 ESD PROTECTED 13092-037 ESD PROTECTED V_1P0 PIN CONTROL (SPI) Figure 37. SDIO Input Figure 40. V_1P0 Input SPIVDD FD_A/FD_B ESD PROTECTED FD JESD204B LMFC JESD204B SYNC~ TEMPERATURE DIODE (FD_A ONLY) FD_x PIN CONTROL (SPI) 13092-038 ESD PROTECTED Figure 38. FD_A/FD_B Outputs Rev. 0 | Page 17 of 72 13092-040 30kΩ AD9691 Data Sheet THEORY OF OPERATION The dual ADC cores feature multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The AD9691 has several functions that simplify the AGC function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. The Subclass 1 JESD204B-based, high speed serialized output data rate can be configured in one-lane (L = 1), two-lane (L = 2), fourlane (L = 4), and eight-lane (L = 8) configurations, depending on the sample rate and the decimation ratio (DCM). Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins. ADC ARCHITECTURE The architecture of the AD9691 consists of an input buffered pipelined ADC. The input buffer provides a termination impedance to the analog input signal. This termination impedance can be changed using the SPI to meet the termination needs of the driver or amplifier. The default termination value is set to 400 Ω. The equivalent circuit diagram of the analog input termination is shown in Figure 30. The input buffer is optimized for high linearity, low noise, and low power. The input buffer provides a linear high input impedance (for ease of drive) and reduces the kickback from the ADC. The buffer is optimized for high linearity, low noise, and low power. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample; at the same time, the remaining stages operate with the preceding samples. Sampling occurs on the rising edge of the clock. and settling within one-half of a clock cycle. A small resistor, in series with each input, helps reduce the peak transient current injected from the output stage of the driving source. In addition, place low Q inductors or ferrite beads on each section of the input to reduce high differential capacitance at the analog inputs and, thus, achieve the maximum bandwidth of the ADC. Such use of low Q inductors or ferrite beads is required when driving the converter front end at high IF frequencies. Place either a differential capacitor or two single-ended capacitors on the inputs to provide a matching passive network. This configuration ultimately creates a low-pass filter at the input, which limits unwanted broadband noise. For more information, see the AN-742 Application Note, the AN-827 Application Note, and the Analog Dialogue article “Transformer-Coupled FrontEnd for Wideband A/D Converters” (Volume 39, April 2005). In general, the precise values depend on the application. For best dynamic performance, the source impedances driving VIN+x and VIN−x must be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference buffer creates a differential reference that defines the span of the ADC core. The maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD9691, the available span is 1.58 V p-p differential. Differential Input Configurations There are several ways to drive the AD9691, either actively or passively. However, optimum performance is achieved by driving the analog input differentially. For applications where SNR and SFDR are key parameters, differential transformer coupling is the recommended input configuration (see Figure 41 and Table 9) because the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9691. For low to midrange frequencies, a double balun or double transformer network (see Figure 41) is recommended for optimum performance of the AD9691. For higher frequencies in the second and third Nyquist zones, it is better to remove some of the front-end passive components to ensure wideband operation (see Table 9). 0.1µF R1 ANALOG INPUT CONSIDERATIONS BALUN The analog input to the AD9691 is a differential buffer. The internal common-mode voltage of the buffer is 2.05 V. The clock signal alternately switches the input circuit between sample mode and hold mode. When the input circuit is switched into sample mode, the signal source must be capable of charging the sample capacitors R2 R1 R3 R2 C1 C2 0.1µF 0.1µF ADC R3 C1 NOTES 1. SEE TABLE 9 FOR COMPONENT VALUES. Rev. 0 | Page 18 of 72 Figure 41. Differential Transformer-Coupled Configuration 13092-041 The AD9691 has two analog input channels and four JESD204B output lane pairs. The ADC is designed to sample wide bandwidth analog signals of up to 1.5 GHz. The AD9691 is optimized for wide input bandwidth, a high sampling rate, excellent linearity, and low power in a small package. Data Sheet AD9691 Table 9. Differential Transformer-Coupled Input Configuration Component Values Frequency Range <625 MHz >625 MHz Transformer/Balun BAL-0006/BAL-0006SMG/ETC1-1-13 BAL-0006/BAL-0006SMG R1 (Ω) 10 10 Input Common Mode The analog inputs of the AD9691 are internally biased to the common mode as shown in Figure 42. The common-mode buffer has a limited range in that the performance suffers greatly if the common-mode voltage drops by more than 100 mV. Therefore, in dc-coupled applications, set the common-mode voltage to 2.05 V ± 100 mV to ensure proper ADC operation. R2 (Ω) 50 50 R3 (Ω) 15 0 C1 (pF) Open Open C2 (pF) 3 Open Figure 44, Figure 45, and Figure 46 show how the SFDR can be optimized using the buffer current setting in Register 0x018 for different Nyquist zones. At frequencies greater than 1 GHz, it is better to run the ADC at input amplitudes less than −1 dBFS (−3 dBFS, for example). This greatly improves the linearity of the converted signal without sacrificing SNR performance. 90 Analog Input Controls and SFDR Optimization 85 The AD9691 offers flexible controls for the analog inputs, such as input termination and buffer current. All of the available controls are shown in Figure 42. SFDR (dBFS) 80 AVDD3 AVDD3 4.5x 75 2.5x 70 VIN+x 3.5x 13092-045 600.3 500.3 470.3 440.3 410.3 380.3 350.3 320.3 290.3 260.3 230.3 200.3 170.3 Figure 44. Buffer Current Sweeps, SFDR vs. Analog Input Frequency vs. IBUFF; fIN < 600 MHz VIN–x 78 3pF 7.5x 76 13092-043 6.5x 74 SFDR (dBFS) Figure 42. Analog Input Controls Using Register 0x018, the buffer currents on each channel can be scaled to optimize the SFDR over various input frequencies and bandwidths of interest. As the input buffer currents are set, the amount of current required by the AVDD3 supply changes. This relationship is shown in Figure 43. For a complete list of buffer current settings, see Table 35. 72 5.5x 70 4.5x 68 66 64 62 700.3 270 13092-046 AIN CONTROL (SPI) REGISTERS (REG 0x008, REG 0x015, REG 0x016, REG0x018) 800.3 900.3 1000.3 1100.3 1200.3 ANALOG INPUT FREQUENCY (MHz) 250 Figure 45. Buffer Current Sweeps, SFDR vs. Analog Input Frequency vs. IBUFF; 700 MHz < fIN < 1200 MHz 225 200 175 150 125 100 75 1.5× 2.0× 2.5× 3.0× 3.5× 4.0× 4.5× 5.0× 5.5× 6.0× 6.5× 7.0× 7.5× 8.0× 8.5× BUFFER CURRENT SETTING 13092-044 IAVDD3 (mA) 130.3 9.6 ANALOG INPUT FREQUENCY (MHz) AVDD3 AVDD3 100.3 60 VCM BUFFER 70.3 200Ω 200Ω 28Ω 67Ω 400Ω 10pF 65 AVDD3 200Ω 67Ω 200Ω 28Ω 3pF Figure 43. AVDD3 Power (IAVDD3) vs. Buffer Current Setting Rev. 0 | Page 19 of 72 AD9691 Data Sheet 76 VIN+A/ VIN+B 74 7.5x 68 66 INTERNAL V_1P0 GENERATOR 6.5x V_1P0 ADJUST SPI REGISTER (REG 0x024) 64 5.5x 62 V_1P0 60 1500.3 1600.3 1700.3 1800.3 1900.3 ANALOG INPUT FREQUENCY (MHz) 1990.3 Figure 47. Internal Reference Configuration and Controls Figure 46. Buffer Current Sweeps, SFDR vs. Analog Input Frequency vs. IBUFF; 1300 MHz < fIN < 2000 MHz Table 10 shows the recommended buffer current and full-scale voltage settings for the different analog input frequency ranges. Table 10. SFDR Optimization for Input Frequencies Input Frequency <500 MHz 500 MHz to 1 GHz >1 GHz Input Buffer Current Control Setting (Register 0x018) 3.5× 5.5× or 6.5× 6.5× or higher Buffer Control 2 Register (Register 0x935) 0x04 0x00 0x00 Register 0x024 enables the user to either use this internal 1.0 V reference, or to provide an external 1.0 V reference. When using an external voltage reference, provide a 1.0 V reference. The full-scale adjustment is made using the SPI, irrespective of the reference voltage. For more information on adjusting the full-scale level of the AD9691, see the Memory Map Register Table section. The use of an external reference may be necessary, in some applications, to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 48 shows the typical drift characteristics of the internal 1.0 V reference. 1.0010 1.0009 Absolute Maximum Input Swing 1.0008 The absolute maximum input swing allowed at the inputs of the AD9691 is 4.3 V p-p differential. Signals operating near or at this level can cause permanent damage to the ADC. V_1P0 VOLTAGE (V) 1.0007 VOLTAGE REFERENCE A stable and accurate 1.0 V voltage reference is built into the AD9691. This internal 1.0 V reference sets the full-scale input range of the ADC. For more information on adjusting the input swing, see Table 35. Figure 47 shows the block diagram of the internal 1.0 V reference controls. 1.0006 1.0005 1.0004 1.0003 1.0002 1.0001 1.0000 0.9999 0.9998 –50 0 25 TEMPERATURE (°C) 90 Figure 48. Typical V_1P0 Drift The external reference must be a stable 1.0 V reference. The ADR130 is a good option for providing the 1.0 V reference. Figure 49 shows how the ADR130 can be used to provide the external 1.0 V reference to the AD9691. The grayed out areas show unused blocks within the AD9691 when using the ADR130 to provide the external reference. INTERNAL V_1P0 GENERATOR ADR130 INPUT 1 NC 2 GND SET 5 3 VIN 0.1µF V_1P0 ADJUST NC 6 VOUT 4 V_1P0 0.1µF V_1P0 ADJUST Figure 49. External Reference Using the ADR130 Rev. 0 | Page 20 of 72 13092-050 56 1400.3 V_1P0 PIN CONTROL SPI REGISTER (REG 0x024) 13092-047 58 ADC CORE FULL-SCALE VOLTAGE ADJUST 13092-048 70 SFDR (dBFS) VIN–A/ VIN–B 8.5x 13092-049 72 Data Sheet AD9691 CLOCK INPUT CONSIDERATIONS Input Clock Divider ½ Period Delay Adjust For optimum performance, drive the AD9691 sample clock inputs (CLK+ and CLK−) with a differential signal. This signal is typically ac-coupled to the CLK+ and CLK− pins via a transformer or clock drivers. These pins are biased internally and require no additional biasing. The input clock divider inside the AD9691 provides phase delay in increments of ½ the input clock cycle. Register 0x10C can be programmed to enable this delay independently for each channel. Changing this register does not affect the stability of the JESD204B link. Figure 50 shows a preferred method for clocking the AD9691. The low jitter clock source is converted from a single-ended signal to a differential signal using an RF transformer. Input Clock Divider 0.1µF 1:1Z CLK+ ADC 100Ω CLK– 0.1µF Figure 50. Transformer-Coupled Differential Clock Another option is to ac couple a differential CML or LVDS signal to the sample clock input pins, as shown in Figure 51 and Figure 52. The maximum frequency at the CLK± inputs is 4 GHz. This is the limit of the divider. In applications where the clock input is a multiple of the sample clock, the appropriate divider ratio must be programmed into the clock divider before applying the clock signal. This ensures that the current transients during device startup are controlled. CLK+ CLK– ÷2 3.3V ÷4 71Ω 10pF 33Ω 33Ω ÷8 0.1µF Z0 = 50Ω REG 0x10B CLK+ 0.1µF Z0 = 50Ω Figure 53. Clock Divider Circuit 13092-052 ADC CLK– The AD9691 clock divider can be synchronized using the external SYSREF± input. A valid SYSREF± signal causes the clock divider to reset to a programmable state. Enable this feature by setting Bit 7 of Register 0x10D. This synchronization feature allows multiple devices to have their clock dividers aligned to guarantee simultaneous input sampling. See the Multichip Synchronization section for more information. Figure 51. Differential CML Sample Clock 0.1µF CLK+ 0.1µF CLOCK INPUT 50Ω1 150Ω LVDS DRIVER CLK– 50Ω1 CLK+ 100Ω 0.1µF RESISTORS ARE OPTIONAL. ADC CLK– Clock Fine Delay Adjust 13092-053 0.1µF CLOCK INPUT 13092-054 50Ω 13092-051 CLOCK INPUT The AD9691 contains an input clock divider with the ability to divide the Nyquist input clock by 1, 2, 4, or 8. The divider ratios can be selected using Register 0x10B. This is shown in Figure 53. Figure 52. Differential LVDS Sample Clock Clock Duty Cycle Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. In applications where the clock duty cycle cannot be guaranteed to be 50%, a higher multiple frequency clock can be supplied to the device. The AD9691 can be clocked at 1.5 GHz with the internal clock divider set to 2. The output of the divider offers a 50% duty cycle, high slew rate (fast edge) clock signal to the internal ADC. See the Memory Map section for more details on using this feature. The AD9691 sampling edge instant can be adjusted by writing to Register 0x117 and Register 0x118. Setting Bit 0 of Register 0x117 enables the feature, and Register 0x118, Bits[7:0] set the value of the delay. This value can be programmed individually for each channel. The clock delay can be adjusted from −151.7 ps to +150 ps in 1.7 ps increments. The clock delay adjust takes effect immediately when it is enabled via SPI writes. Enabling the clock fine delay adjust in Register 0x117 causes a datapath reset. However, the contents of Register 0x118 can be changed without affecting the stability of the JESD204B link. Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by Rev. 0 | Page 21 of 72 SNR = 20log10(2 × π × fA × tJ) AD9691 Data Sheet In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter (see Figure 54). 12.5fS 25fS 50fS 100fS 200fS 400fS 800fS 120 110 SNR (dB) 100 90 70 60 50 1000 10000 ANALOG INPUT FREQUENCY (MHz) 13092-055 40 100 The AD9691 contains a diode-based temperature sensor for measuring the temperature of the die. This diode can output a voltage and serve as a coarse temperature sensor to monitor the internal die temperature. The temperature diode voltage can be output to the FD_A pin using the SPI. Use Register 0x028, Bit 0 to enable or disable the diode. Register 0x028 is a local register; therefore, Channel A must be selected in the device index register (Register 0x008) to enable the temperature diode readout. Configure the FD_A pin to output the diode voltage by programming Register 0x040, Bits[2:0]. See Table 35 for more information. 80 30 10 TEMPERATURE DIODE The voltage response of the temperature diode (SPIVDD = 1.8 V) is shown in Figure 55. 0.90 Figure 54. Ideal SNR vs. Analog Input Frequency and Jitter 0.85 DIODE VOLTAGE (V) Treat the clock input as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9691. Separate power supplies for clock drivers from the ADC output driver supplies to avoid modulating the clock signal with digital noise. If the clock is generated from another type of source (by gating, dividing, or other methods), retime the clock by the original clock at the last step. For more in-depth information about jitter performance as it relates to ADCs, see the AN-501 Application Note and the AN-756 Application Note. POWER-DOWN/STANDBY MODE 0.80 0.75 0.70 0.65 0.60 The AD9691 has a PDWN/STBY pin that configures the device in power-down or standby mode. The default operation is the power-down function. The PDWN/STBY pin is a logic high pin. When in power-down mode, the JESD204B link is disrupted. The power-down option can also be set via Register 0x03F and Register 0x040. Rev. 0 | Page 22 of 72 –55 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 95 105 115 125 TEMPERATURE (°C) Figure 55. Diode Voltage vs. Temperature 13092-056 130 In standby mode, the JESD204B link is not disrupted and transmits zeros for all converter samples. This can be changed using Register 0x571, Bit 7 to select /K/ characters. Data Sheet AD9691 ADC OVERRANGE AND FAST DETECT The operation of the upper threshold and lower threshold registers, along with the dwell time registers, is shown in Figure 56. In receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to clip. The standard overrange bit in the JESD204B outputs provides information on the state of the analog input that is of limited usefulness. Therefore, it is helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip actually occurs. In addition, because input signals can have significant slew rates, the latency of this function is of major concern. Highly pipelined converters can have significant latency. The AD9691 contains fast detect circuitry for individual channels to monitor the threshold and assert the FD_A and FD_B pins. The FD indicator is asserted if the input magnitude exceeds the value programmed in the fast detect upper threshold registers, located at Register 0x247 and Register 0x248. The selected threshold register is compared with the signal magnitude at the output of the ADC. The fast upper threshold detection has a latency of 28 clock cycles (maximum). The approximate upper threshold magnitude is defined by Upper Threshold Magnitude (dBFS) = 20log(Threshold Magnitude/213) ADC OVERRANGE The FD indicators are not cleared until the signal drops below the lower threshold for the programmed dwell time. The lower threshold is programmed in the fast detect lower threshold registers, located at Register 0x249 and Register 0x24A. The fast detect lower threshold register is a 13-bit register that is compared with the signal magnitude at the output of the ADC. This comparison is subject to the ADC pipeline latency, but is accurate in terms of converter resolution. The lower threshold magnitude is defined by The ADC overrange indicator is asserted when an overrange is detected on the input of the ADC. The overrange indicator can be embedded within the JESD204B link as a control bit (when CSB > 0). The latency of this overrange indicator matches the sample latency. The AD9691 also records any overrange condition in any of the four virtual converters. For more information on the virtual converters, see Figure 61. The overrange status of each virtual converter is registered as a sticky bit in Register 0x563. The contents of Register 0x563 can be cleared using Register 0x562, by toggling the bits corresponding to the virtual converter to the set and reset positions. Lower Threshold Magnitude (dBFS) = 20log(Threshold Magnitude/213) For example, to set an upper threshold of −6 dBFS, write 0xFFF to Register 0x247 and Register 0x248. To set a lower threshold of −10 dBFS, write 0xA1D to Register 0x249 and Register 0x24A. FAST THRESHOLD DETECTION (FD_A AND FD_B) The fast detect (FD) bit (enabled via the control bits in Register 0x559 and Register 0x55A) is immediately set whenever the absolute value of the input signal exceeds the programmable upper threshold level. The FD bit is cleared only when the absolute value of the input signal drops below the lower threshold level for greater than the programmable dwell time. This feature provides hysteresis and prevents the FD bit from excessively toggling. To program the dwell time from 1 to 65,535 sample clock cycles, place the desired value in the fast detect dwell time registers, located at Register 0x24B and Register 0x24C. See the Memory Map section (Register 0x040, and Register 0x245 to Register 0x24C in Table 35) for more details. UPPER THRESHOLD DWELL TIME TIMER RESET BY RISE ABOVE LOWER THRESHOLD DWELL TIME FD_A OR FD_B Figure 56. Threshold Settings for FD_A and FD_B Signals Rev. 0 | Page 23 of 72 TIMER COMPLETES BEFORE SIGNAL RISES ABOVE LOWER THRESHOLD 13092-057 MIDSCALE LOWER THRESHOLD AD9691 Data Sheet SIGNAL MONITOR The signal monitor block provides additional information about the signal being digitized by the ADC. The signal monitor computes the peak magnitude of the digitized signal. This information can be used to drive an AGC loop to optimize the range of the ADC in the presence of real-world signals. The results of the signal monitor block can be obtained either by reading back the internal values from the SPI port or by embedding the signal monitoring information into the JESD204B interface as special control bits. A global, 24-bit programmable period controls the duration of the measurement. Figure 57 shows the simplified block diagram of the signal monitor block. SIGNAL MONITOR PERIOD REGISTER (SMPR) REG 0x271, REG 0x272, REG 0x273 CLEAR FROM INPUT MAGNITUDE STORAGE REGISTER LOAD DOWN COUNTER IS COUNT = 1? LOAD LOAD SIGNAL MONITOR HOLDING REGISTER COMPARE A>B When the monitor period timer reaches a count of 1, the 13-bit peak level value is transferred to the signal monitor holding register, which can be read through the memory map or output through the SPORT over the JESD204B interface. The monitor period timer is reloaded with the value in the SMPR, and the countdown is restarted. In addition, the magnitude of the first input sample is updated in the magnitude storage register, and the comparison and update procedure continues. SPORT Over JESD204B TO SPORT OVER JESD204B AND MEMORY MAP 13092-058 FROM MEMORY MAP After enabling this mode, the value in the SMPR is loaded into a monitor period timer, which decrements at the decimated clock rate. The magnitude of the input signal is compared to the value in the internal magnitude storage register (not accessible to the user), and the greater of the two is updated as the current peak level. The initial value of the magnitude storage register is set to the current ADC input signal magnitude. This comparison continues until the monitor period timer reaches a count of 1. Figure 57. Signal Monitor Block The peak detector captures the largest signal within the observation period. The detector only observes the magnitude of the signal. The resolution of the peak detector is a 13-bit value, and the observation period is 24 bits and represents converter output samples. The peak magnitude can be derived by using the following equation: Peak Magnitude (dBFS) = 20log(Peak Detector Value/213) The magnitude of the input port signal is monitored over a programmable time period, which is determined by the signal monitor period register (SMPR). The peak detector function is enabled by setting Bit 1 of Register 0x270 in the signal monitor control register. The 24-bit SMPR must be programmed before activating this mode. The signal monitor data can also be serialized and sent over the JESD204B interface as control bits. These control bits must be deserialized from the samples to reconstruct the statistical data. This function is enabled by setting Bits[1:0] of Register 0x279 and Bit 1 of Register 0x27A. Figure 58 shows two different example configurations for the signal monitor control bit locations inside the JESD204B samples. A maximum of three control bits can be inserted into the JESD204B samples; however, only one control bit is required for the signal monitor. Control bits are inserted from MSB to LSB. If only one control bit is to be inserted (CS = 1), only the most significant control bit is used (see Example Configuration 1 and Example Configuration 2 in Figure 58). To select the SPORT over JESD204B option, program Register 0x559, Register 0x55A, and Register 0x58F. See Table 35 for more information on setting these bits. Figure 59 shows the 25-bit frame data that encapsulates the peak detector value. The frame data is transmitted MSB first with five 5-bit subframes. Each subframe contains a start bit that can be used by a receiver to validate the deserialized data. Figure 60 shows the SPORT over JESD204B signal monitor data with a monitor period timer set to 80 samples. Rev. 0 | Page 24 of 72 Data Sheet AD9691 16-BIT JESD204B SAMPLE SIZE (N' = 16) EXAMPLE CONFIGURATION 1 (N' = 16, N = 15, CS = 1) 1-BIT CONTROL BIT (CS = 1) 15-BIT CONVERTER RESOLUTION (N = 15) 15 S[14] X 14 13 S[13] X S[12] X 12 S[11] X 11 10 S[10] X 9 S[9] X 8 S[8] X 7 S[7] X 6 S[6] X 5 S[5] X 4 S[4] X S[3] X 3 S[2] X 2 S[1] X 1 0 S[0] X CTRL [BIT 2] X SERIALIZED SIGNAL MONITOR FRAME DATA 16-BIT JESD204B SAMPLE SIZE (N' = 16) 14-BIT CONVERTER RESOLUTION (N = 14) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S[13] X S[12] X S[11] X S[10] X S[9] X S[8] X S[7] X S[6] X S[5] X S[4] X S[3] X S[2] X S[1] X S[0] X CTRL [BIT 2] X TAIL X SERIALIZED SIGNAL MONITOR FRAME DATA Figure 58. Signal Monitor Control Bit Locations 5-BIT SUBFRAMES 5-BIT IDLE SUBFRAME (OPTIONAL) 25-BIT FRAME IDLE 1 IDLE 1 IDLE 1 IDLE 1 IDLE 1 5-BIT IDENTIFIER START 0 SUBFRAME ID[3] 0 ID[2] 0 ID[1] 0 ID[0] 1 5-BIT DATA MSB SUBFRAME START 0 P[12] P[11] P[10] P[9] 5-BIT DATA SUBFRAME START 0 P[8] P[7] P[6] P5] 5-BIT DATA SUBFRAME START 0 P[4] P[3] P[2] P1] 5-BIT DATA LSB SUBFRAME START 0 P[0] 0 0 0 P[] = PEAK MAGNITUDE VALUE Figure 59. SPORT over JESD204B Signal Monitor Frame Data Rev. 0 | Page 25 of 72 13092-060 EXAMPLE CONFIGURATION 2 (N' = 16, N = 14, CS = 1) 13092-059 1 CONTROL 1 TAIL BIT BIT (CS = 1) AD9691 Data Sheet SMPR = 80 SAMPLES (REG 0x271 = 0x50; REG 0x272 = 0x00; REG 0x273 = 0x00) 80-SAMPLE PERIOD PAYLOAD No. 3 25-BIT FRAME (N) IDENT. DATA MSB DATA DATA DATA LSB IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE 80-SAMPLE PERIOD PAYLOAD No. 3 25-BIT FRAME (N + 1) IDENT. DATA MSB DATA DATA DATA LSB IDLE IDLE IDLE IDLE IDLE 80-SAMPLE PERIOD IDENT. DATA MSB DATA DATA DATA LSB IDLE IDLE IDLE IDLE IDLE Figure 60. SPORT over JESD204B Signal Monitor Example with Period = 80 Samples Rev. 0 | Page 26 of 72 13092-061 PAYLOAD No. 3 25-BIT FRAME (N + 2) Data Sheet AD9691 DIGITAL DOWNCONVERTERS (DDCS) The AD9691 includes four digital downconverters (DDC 0 to DDC 3) that provide filtering and reduce the output data rate. This digital processing section includes a numerically controlled oscillator (NCO), a half-band decimating filter, a finite impulse response (FIR) filter, a gain stage, and a complex to real conversion stage. Each of these processing blocks have control lines that allow it to be independently enabled and disabled to provide the desired processing function. The digital downconverters can be configured to output either real data or complex output data. DDC I/Q INPUT SELECTION The AD9691 has two ADC channels and four DDC channels. Each DDC channel has two input ports that can be paired to support both real or complex inputs through the I/Q crossbar mux. For real signals, both DDC input ports must select the same ADC channel (for example, DDC Input Port I = ADC Channel A, and Input Port Q = ADC Channel A). For complex signals, each DDC input port must select different ADC channels (for example, DDC Input Port I = ADC Channel A, and Input Port Q = ADC Channel B). The inputs to each DDC are controlled by the DDC input selection registers (Register 0x311, Register 0x331, Register 0x351, and Register 0x371). See Table 35 for information on how to configure the DDCs. DDC I/Q OUTPUT SELECTION Each DDC channel has two output ports that can be paired to support both real or complex outputs. For real output signals, only the DDC Output Port I is used (the DDC Output Port Q is invalid). For complex I/Q output signals, both DDC Output Port I and DDC Output Port Q are used. The I/Q outputs to each DDC channel are controlled by the DDC complex to real enable bit (Bit 3) in the DDC control registers (Register 0x310, Register 0x330, Register 0x350, and Register 0x370). The Chip Q ignore bit (Bit 5) in the chip application mode register (Register 0x200) controls the chip output muxing of all the DDC channels. When all DDC channels use real outputs, this bit must be set high to ignore all DDC Q output ports. When any of the DDC channels are set to use complex I/Q outputs, the user must clear this bit to use both DDC Output Port I and DDC Output Port Q. For more information, refer to Memory Map Register Table section. DDC GENERAL DESCRIPTION The four DDC blocks extract a portion of the full digital spectrum captured by the ADC(s). They are intended for IF sampling or oversampled baseband radios requiring wide bandwidth input signals. Each DDC block contains the following signal processing stages: • • • • Frequency translation stage (optional) Filtering stage Gain stage (optional) Complex to real conversion stage (optional) Frequency Translation Stage (Optional) The frequency translation stage consists of a 12-bit complex NCO and quadrature mixers that can be used for frequency translation of both real or complex input signals. This stage shifts a portion of the available digital spectrum down to baseband. Filtering Stage After shifting down to baseband, the filtering stage decimates the frequency spectrum using a chain of up to four half-band low-pass filters for rate conversion. The decimation process lowers the output data rate, which in turn reduces the output interface rate. Gain Stage (Optional) Due to losses associated with mixing a real input signal down to baseband, the gain stange compensates by adding an additional 0 dB or 6 dB of gain. Complex to Real Conversion Stage (Optional) When real outputs are necessary, the complex to real conversion stage converts the complex outputs back to real by performing an fS/4 mixing operation plus a filter to remove the complex component of the signal. Figure 61 shows the detailed block diagram of the DDCs implemented in the AD9691. Rev. 0 | Page 27 of 72 AD9691 Data Sheet ADC SAMPLING AT fS HB1 FIR DCM = 2 COMPLEX TO REAL CONVERSION (OPTIONAL) Q CONVERTER 1 REAL/I CONVERTER 2 Q CONVERTER 3 SYSREF± COMPLEX TO REAL CONVERSION (OPTIONAL) REAL/Q Q ADC SAMPLING AT fS GAIN = 0dB OR 6dB NCO + MIXER (OPTIONAL) HB1 FIR DCM = 2 I HB2 FIR DCM = BYPASS OR 2 DDC 2 REAL/I REAL/I CONVERTER 4 OUTPUT INTERFACE COMPLEX TO REAL CONVERSION (OPTIONAL) GAIN = 0dB OR 6dB HB1 FIR DCM = 2 HB2 FIR DCM = BYPASS OR 2 REAL/Q Q HB3 FIR DCM = BYPASS OR 2 NCO + MIXER (OPTIONAL) HB3 FIR DCM = BYPASS OR 2 I/Q CROSSBAR MUX I HB4 FIR DCM = BYPASS OR 2 DDC 1 REAL/I REAL/I REAL/I CONVERTER 0 SYSREF± HB4 FIR DCM = BYPASS OR 2 REAL/I GAIN = 0dB OR 6dB REAL/Q Q HB2 FIR DCM = BYPASS OR 2 NCO + MIXER (OPTIONAL) HB3 FIR DCM = BYPASS OR 2 I HB4 FIR DCM = BYPASS OR 2 DDC 0 REAL/I Q CONVERTER 5 SYSREF± SYNCHRONIZATION CONTROL CIRCUITS SYSREF± COMPLEX TO REAL CONVERSION (OPTIONAL) REAL/I CONVERTER 6 Q CONVERTER 7 13092-062 SYSREF GAIN = 0dB OR 6dB REAL/Q Q HB1 FIR DCM = 2 NCO + MIXER (OPTIONAL) HB2 FIR DCM = BYPASS OR 2 I HB3 FIR DCM = BYPASS OR 2 REAL/I HB4 FIR DCM = BYPASS OR 2 DDC 3 Figure 61. DDC Detailed Block Diagram Figure 62 shows an example usage of one of the four DDC blocks with a real input signal and four half-band filters (HB4, HB3, HB2, and HB1). It shows both complex (decimate by 16) and real (decimate by 8) output options. the chip decimation ratio sample rate. Whenever the NCO frequency is set or changed, the DDC soft reset must be issued. If the DDC soft reset is not issued, the output may potentially show amplitude variations. When DDCs have different decimation ratios, the chip decimation ratio (Register 0x201) must be set to the lowest decimation ratio of all the DDC blocks. In this scenario, samples of higher decimation ratio DDCs are repeated to match Table 11, Table 12, Table 13, Table 14, and Table 15 show the DDC samples when the chip decimation ratio is set to 1, 2, 4, 8, or 16, respectively. Rev. 0 | Page 28 of 72 Data Sheet AD9691 ADC REAL INPUT—SAMPLED AT fS –fS/2 –fS/3 ADC SAMPLING AT fS REAL BANDWIDTH OF INTEREST IMAGE –fS/4 REAL BANDWIDTH OF INTEREST fS/32 –fS/32 DC –fS/16 fS/16 –fS/8 FREQUENCY TRANSLATION STAGE (OPTIONAL) DIGITAL MIXER + NCO FOR fS/3 TUNING, THE FREQUENCY TUNING WORD = ROUND ((fS/3)/fS × 4096) = +1365 (0x555) fS/8 fS/4 fS/3 fS/2 I NCO TUNES CENTER OF BANDWIDTH OF INTEREST TO BASEBAND cos(ωt) REAL 12-BIT NCO 90° 0° –sin(ωt) Q DIGITAL FILTER RESPONSE –fS/2 –fS/3 –fS/4 FILTERING STAGE 4 DIGITAL HALF-BAND FILTERS (HB4 + HB3 + HB2 + HB1) fS/32 –fS/32 DC –fS/16 fS/16 –fS/8 HB4 FIR I HALFBAND FILTER Q HALFBAND FILTER HB3 FIR 2 HALFBAND FILTER 2 HALFBAND FILTER HB4 FIR BANDWIDTH OF INTEREST IMAGE (–6dB LOSS DUE TO NCO + MIXER) BANDWIDTH OF INTEREST (–6dB LOSS DUE TO NCO + MIXER) fS/8 2 2 HALFBAND FILTER HB3 FIR fS/3 fS/2 HB1 FIR HB2 FIR HALFBAND FILTER fS/4 2 HALFBAND FILTER 2 HALFBAND FILTER 2 I HB1 FIR HB2 FIR 2 Q 6dB GAIN TO COMPENSATE FOR NCO + MIXER LOSS COMPLEX (I/Q) OUTPUTS GAIN STAGE (OPTIONAL) DIGITAL FILTER RESPONSE I GAIN STAGE (OPTIONAL) Q 0dB OR 6dB GAIN COMPLEX TO REAL CONVERSION STAGE (OPTIONAL) fS/4 MIXING + COMPLEX FILTER TO REMOVE Q fS/32 –fS/32 DC –fS/16 fS/16 –fS/8 I REAL (I) OUTPUTS +6dB +6dB fS/8 2 +6dB 2 +6dB I Q fS/32 –fS/32 DC –fS/16 fS/16 DOWNSAMPLE BY 2 I DECIMATE BY 8 Q DECIMATE BY 16 0dB OR 6dB GAIN Q COMPLEX REAL/I TO REAL –fS/8 fS/32 –fS/32 DC –fS/16 fS/16 fS/8 Figure 62. DDC Theory of Operation Example (Real Input—Decimate by 16) Rev. 0 | Page 29 of 72 13092-063 6dB GAIN TO COMPENSATE FOR NCO + MIXER LOSS AD9691 Data Sheet Table 11. DDC Samples, Chip Decimation Ratio = 1 HB1 FIR (DCM 1 = 1) N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19 N + 20 N + 21 N + 22 N + 23 N + 24 N + 25 N + 26 N + 27 N + 28 N + 29 N + 30 N + 31 1 Real (I) Output (Complex to Real Enabled) HB2 FIR + HB3 FIR + HB2 HB4 FIR + HB3 FIR + HB1 FIR FIR + HB1 FIR HB2 FIR + HB1 FIR (DCM1 = 2) (DCM1 = 4) (DCM1 = 8) N N N N+1 N+1 N+1 N N N N+1 N+1 N+1 N+2 N N N+3 N+1 N+1 N+2 N N N+3 N+1 N+1 N+4 N+2 N N+5 N+3 N+1 N+4 N+2 N N+5 N+3 N+1 N+6 N+2 N N+7 N+3 N+1 N+6 N+2 N N+7 N+3 N+1 N+8 N+4 N+2 N+9 N+5 N+3 N+8 N+4 N+2 N+9 N+5 N+3 N + 10 N+4 N+2 N + 11 N+5 N+3 N + 10 N+4 N+2 N + 11 N+5 N+3 N + 12 N+6 N+2 N + 13 N+7 N+3 N + 12 N+6 N+2 N + 13 N+7 N+3 N + 14 N+6 N+2 N + 15 N+7 N+3 N + 14 N+6 N+2 N + 15 N+7 N+3 Complex (I/Q) Outputs (Complex to Real Disabled) HB1 FIR (DCM1 = 2) N N+1 N N+1 N+2 N+3 N+2 N+3 N+4 N+5 N+4 N+5 N+6 N+7 N+6 N+7 N+8 N+9 N+8 N+9 N + 10 N + 11 N + 10 N + 11 N + 12 N + 13 N + 12 N + 13 N + 14 N + 15 N + 14 N + 15 DCM is decimation. Rev. 0 | Page 30 of 72 HB2 FIR + HB1 FIR (DCM1 = 4) N N+1 N N+1 N N+1 N N+1 N+2 N+3 N+2 N+3 N+2 N+3 N+2 N+3 N+4 N+5 N+4 N+5 N+4 N+5 N+4 N+5 N+6 N+7 N+6 N+7 N+6 N+7 N+6 N+7 HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 8) N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N+2 N+3 N+2 N+3 N+2 N+3 N+2 N+3 N+2 N+3 N+2 N+3 N+2 N+3 N+2 N+3 HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16) N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 Data Sheet AD9691 Table 12. DDC Samples, Chip Decimation Ratio = 2 Real (I) Output (Complex to Real Enabled) HB4 FIR + HB3 FIR + HB3 FIR + HB2 FIR + HB2 FIR + HB2 FIR + HB1 FIR HB1 FIR HB1 FIR (DCM 1 = 2) (DCM1 = 4) (DCM1 = 8) N N N N+1 N+1 N+1 N N N+2 N+1 N+1 N+3 N + 2 N N+4 N + 3 N+1 N+5 N+2 N N+6 N+3 N+1 N+7 N+4 N+2 N+8 N+5 N+3 N+9 N+4 N+2 N + 10 N+5 N+3 N + 11 N+6 N+2 N + 12 N+7 N+3 N + 13 N+6 N+2 N + 14 N+7 N+3 N + 15 1 Complex (I/Q) Outputs (Complex to Real Disabled) HB4 FIR + HB3 FIR + HB3 FIR + HB2 FIR + HB2 FIR + HB2 FIR + HB1 FIR HB1 FIR HB1 FIR HB1 FIR (DCM1 = 2) (DCM1 = 4) (DCM1 = 8) (DCM1 = 16) N N N N N+1 N+1 N+1 N+1 N N N N+2 N+1 N+1 N+1 N+3 N + 2 N N N+4 N + 3 N + 1 N+1 N+5 N+2 N N N+6 N+3 N+1 N+1 N+7 N+4 N+2 N N+8 N+5 N+3 N+1 N+9 N+4 N+2 N N + 10 N+5 N+3 N+1 N + 11 N+6 N+2 N N + 12 N+7 N+3 N+1 N + 13 N+6 N+2 N N + 14 N+7 N+3 N+1 N + 15 DCM is decimation. Table 13. DDC Samples, Chip Decimation Ratio = 4 Real (I) Output (Complex to Real Enabled) HB4 FIR + HB3 FIR + HB3 FIR + HB2 FIR + HB2 FIR + HB1 FIR HB1 FIR (DCM 1 = 4) (DCM1 = 8) N N N+1 N+1 N N+2 N+1 N+3 N+2 N+4 N+3 N+5 N+2 N+6 N+3 N+7 1 Complex (I/Q) Outputs (Complex to Real Disabled) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR HB3 FIR + HB2 FIR + HB2 FIR + HB1 FIR (DCM1 = 4) HB1 FIR (DCM1 = 8) (DCM1 = 16) N N N N+1 N+1 N+1 N N N+2 N+1 N+1 N+3 N+2 N N+4 N+3 N+1 N+5 N+2 N N+6 N+3 N+1 N+7 DCM is decimation. Table 14. DDC Samples, Chip Decimation Ratio = 8 Real (I) Output (Complex to Real Enabled) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM 1 = 8) N N+1 N+2 N+3 N+4 N+5 N+6 N+7 1 Complex (I/Q) Outputs (Complex to Real Disabled) HB3 FIR + HB2 FIR + HB1 FIR HB4 FIR + HB3 FIR + HB2 FIR + (DCM1 = 8) HB1 FIR (DCM1 = 16) N N N+1 N+1 N N+2 N+1 N+3 N+2 N+4 N+3 N+5 N+2 N+6 N+3 N+7 DCM is decimation. Rev. 0 | Page 31 of 72 AD9691 Data Sheet Table 15. DDC Samples, Chip Decimation Ratio = 16 Real (I) Output (Complex to Real Enabled) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM = 16) Not applicable Not applicable Not applicable Not applicable 1 Complex (I/Q) Outputs (Complex to Real Disabled) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM 1 = 16) N N+1 N+2 N+3 DCM is decimation. If the chip decimation ratio is set to decimate by 4, DDC 0 is set to use HB2 + HB1 filters (complex outputs, decimate by 4), and DDC 1 is set to use HB4 + HB3 + HB2 + HB1 filters (real outputs, decimate by 8). Then, DDC 1 repeats its output data two times for every one DDC 0 output. The resulting output samples are shown in Table 16. Table 16. DDC Output Samples when Chip DCM 1 = 4, DDC 0 DCM1 = 4 (Complex), and DDC 1 DCM1 = 8 (Real) DDC Input Samples N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 1 Output Port I I0 (N) DDC 0 Output Port Q Q0 (N) Output Port I I1 (N) DDC 1 Output Port Q Not applicable I0 (N + 1) Q0 (N + 1) I1 (N + 1) Not applicable I0 (N + 2) Q0 (N + 2) I1 (N) Not applicable I0 (N + 3) Q0 (N + 3) I1 (N + 1) Not applicable DCM is decimation. Rev. 0 | Page 32 of 72 Data Sheet AD9691 FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode Frequency translation is accomplished using a 12-bit complex NCO with a digital quadrature mixer. The frequency translation translates either a real or complex input signal from an IF to a baseband complex digital output (carrier frequency = 0 Hz). The NCO and the mixers are enabled. The NCO output frequency can be used to digitally tune the IF frequency. 0 Hz IF (ZIF) Mode The mixers are bypassed and the NCO is disabled. The frequency translation stage of each DDC can be controlled individually and supports four different IF modes using Bits[5:4] of the DDC control registers (Register 0x310, Register 0x330, Register 0x350, and Register 0x370). These IF modes are The mixers and NCO are enabled in a special downmixing by fS/4 mode to save power. Test Mode Variable IF mode 0 Hz IF, or zero IF (ZIF), mode fS/4 Hz IF mode Test mode The input samples are forced to 0.999 to positive full scale. The NCO is enabled. This test mode allows the NCOs to drive the decimation filters directly. Figure 63 and Figure 64 show examples of the frequency translation stage for both real and complex inputs. NCO FREQUENCY TUNING WORD (FTW) SELECTION 12-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096 I ADC + DIGITAL MIXER + NCO REAL INPUT—SAMPLED AT fS REAL ADC SAMPLING AT fS REAL 12-BIT NCO cos(ωt) 90° 0° COMPLEX –sin(ωt) Q BANDWIDTH OF INTEREST BANDWIDTH OF INTEREST IMAGE –fS/2 –fS/3 –fS/4 –fS/8 –fS/32 fS/32 DC –fS/16 fS/16 fS/8 fS/4 fS/3 fS/2 –6dB LOSS DUE TO NCO + MIXER 12-BIT NCO FTW = ROUND ((fS/3)/fS × 4096) = +1365 (0x555) POSITIVE FTW VALUES –fS/32 DC fS/32 12-BIT NCO FTW = ROUND ((fS/3)/fS × 4096) = –1365 (0xAAB) –fS/32 NEGATIVE FTW VALUES DC fS/32 Figure 63. DDC NCO Frequency Tuning Word Selection—Real Inputs Rev. 0 | Page 33 of 72 13092-064 • • • • fS/4 Hz IF Mode AD9691 Data Sheet NCO FREQUENCY TUNING WORD (FTW) SELECTION 12-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096 QUADRATURE ANALOG MIXER + 2 ADCs + QUADRATURE DIGITAL REAL MIXER + NCO COMPLEX INPUT—SAMPLED AT fS QUADRATURE MIXER ADC SAMPLING AT fS I + I I Q Q 90° PHASE 12-BIT NCO 90° 0° Q Q ADC SAMPLING AT fS Q Q I I – –sin(ωt) I I + COMPLEX Q + BANDWIDTH OF INTEREST IMAGE DUE TO ANALOG I/Q MISMATCH –fS/3 –fS/4 –fS/32 fS/32 –fS/16 fS/16 DC –fS/8 fS/8 fS/4 fS/3 fS/2 12-BIT NCO FTW = ROUND ((fS/3)/fS × 4096) = +1365 (0x555) POSITIVE FTW VALUES –fS/32 fS/32 13092-065 –fS/2 DC Figure 64. DDC NCO Frequency Tuning Word Selection—Complex Inputs DDC NCO PLUS MIXER LOSS AND SFDR Setting Up the NCO FTW and POW When mixing a real input signal down to baseband, 6 dB of loss is introduced in the signal due to filtering of the negative image. The NCO introduces an additional 0.05 dB of loss. The total loss of a real input signal mixed down to baseband is 6.05 dB. For this reason, it is recommended to compensate for this loss by enabling the additional 6 dB of gain in the gain stage of the DDC to recenter the dynamic range of the signal within the full scale of the output bits. The NCO frequency value is given by the 12-bit twos complement number entered in the NCO FTW. Frequencies between ±fS (+fS/2 excluded) are represented using the following frequency words: When mixing a complex input signal down to baseband, the maximum value that each I/Q sample can reach is 1.414 × full scale after it passes through the complex mixer. To avoid overrange of the I/Q samples and to keep the data bit-widths aligned with real mixing, introduce 3.06 dB of loss (0.707 × fullscale) in the mixer for complex signals. The NCO introduces an additional 0.05 dB of loss. The total loss of a complex input signal mixed down to baseband is −3.11 dB. The worst case spurious signal from the NCO is greater than 102 dBc SFDR for all output frequencies. NUMERICALLY CONTROLLED OSCILLATOR The AD9691 has a 12-bit NCO for each DDC that enables the frequency translation process. The NCO allows the input spectrum to be tuned to dc, where it can be effectively filtered by the subsequent filter blocks to prevent aliasing. The NCO can be set up by providing a frequency tuning word (FTW) and a phase offset word (POW). 0x800 represents a frequency of –fS/2. 0x000 represents dc (frequency is 0 Hz). 0x7FF represents a frequency of fS/2 – fS/212. Calculate the NCO frequency tuning word using the following equation: mod f C , f S NCO _ FTW round 2 12 fS where: NCO_FTW is a 12-bit twos complement number representing the NCO FTW. fC is the desired carrier frequency in Hz. fS is the AD9691 sampling frequency (clock rate) in Hz. mod( ) is a remainder function. For example, mod(110,100) = 10, and for negative numbers, mod(−32, +10) = –2. round( ) is a rounding function. For example, round(3.6) = 4, and for negative numbers, round(−3.4) = −3. Note that this equation applies to the aliasing of signals in the digital domain (that is, aliasing introduced when digitizing analog signals). Rev. 0 | Page 34 of 72 Data Sheet AD9691 For example, if the ADC sampling frequency (fS) is 1250 MSPS and the carrier frequency (fC) is 416.667 MHz, mod(416.667,1250 NCO _ FTW = round 212 = 1365 MHz 1250 This, in turn, converts to 0x555 in the 12-bit twos complement representation for NCO_FTW. Calculate the actual carrier frequency using the following equation: f C _ ACTUAL NCO _ FTW × f S = = 416.56 MHz 212 Use the following two methods to synchronize multiple PAWs within the chip: • • A 12-bit POW is available for each NCO to create a known phase relationship between multiple AD9691 chips or individual DDC channels inside one AD9691. The following procedure must be followed to update the FTW and/or POW registers to ensure proper operation of the NCO: 1. 2. 3. Write to the FTW registers for all the DDCs. Write to the POW registers for all the DDCs. Synchronize the NCOs either through the DDC soft reset bit accessible through the SPI, or through the assertion of the SYSREF± pin. Note that the NCOs must be synchronized either through the SPI or through the SYSREF± pin after all writes to the FTW or POW registers are complete. This synchronization is necessary to ensure the proper operation of the NCO. NCO Synchronization Each NCO contains a separate phase accumulator word (PAW) that determines the instantaneous phase of the NCO. The initial reset value of each PAW is determined by the POW described in the Setting Up the NCO FTW and POW section. The phase increment value of each PAW is determined by the FTW. Using the SPI. Use the DDC NCO soft reset bit in the DDC synchronization control register (Register 0x300, Bit 4) to reset all the PAWs in the chip. This is accomplished by toggling the DDC NCO soft reset bit. This method synchronizes DDC channels within the same AD9691 chip only. Using the SYSREF± pin. When the SYSREF± pin is enabled in the SYSREF± control registers (Register 0x120 and Register 0x121), and the DDC synchronization is enabled in Bits[1:0] in the DDC synchronization control register (Register 0x300), any subsequent SYSREF± event resets all the PAWs in the chip. This method synchronizes DDC channels within the same AD9691 chip, or DDC channels within separate AD9691 chips. Mixer The NCO is accompanied by a mixer, which operates similarly to an analog quadrature mixer. It performs the downconversion of input signals (real or complex) by using the NCO frequency as a local oscillator. For real input signals, this mixer performs a real mixer operation with two multipliers. For complex input signals, the mixer performs a complex mixer operation with four multipliers and two adders. The mixer adjusts its operation based on the input signal (real or complex) provided to each individual channel. The selection of real or complex inputs can be controlled individually for each DDC block by using Bit 7 of the DDC control registers (Register 0x310, Register 0x330, Register 0x350, and Register 0x370). Rev. 0 | Page 35 of 72 AD9691 Data Sheet FIR FILTERS GENERAL DESCRIPTION There are four sets of decimate by 2, low-pass, half-band, FIR filters (labeled HB1 FIR, HB2 FIR, HB3 FIR, and HB4 FIR in Figure 61) following the frequency translation stage. After the carrier of interest is tuned down to dc (carrier frequency = 0 Hz), these filters efficiently lower the sample rate while providing sufficient alias rejection from unwanted adjacent carriers around the bandwidth of interest. HB1 FIR is always enabled and cannot be bypassed. The HB2, HB3, and HB4 FIR filters are optional and can be bypassed for higher output sample rates. Table 17 shows the different bandwidth options by including different half-band filters. In all cases, the DDC filtering stage of the AD9691 provides less than −0.001 dB of pass-band ripple and greater than 100 dB of stop-band alias rejection. Table 18 shows the amount of stop-band alias rejection for multiple pass-band ripple/cutoff points. The decimation ratio of the filtering stage of each DDC can be controlled individually through Bits[1:0] of the DDC control registers (Register 0x310, Register 0x330, Register 0x350, and Register 0x370). Table 17. DDC Filter Characteristics ADC Sample Rate (MSPS) 1250 1 DDC Decimation Ratio 2 (HB1) 4 (HB1 + HB2) 8 (HB1 + HB2 + HB3) 16 (HB1 + HB2 + HB3 + HB4) Real Output Sample Rate (MSPS) 1250 625 312.5 156.25 Complex (I/Q) Output Sample Rate (MSPS) 625 (I) + 625 (Q) 312.5 (I) + 312.5 (Q) 156.25 (I) + 156.25 (Q) 78.125 (I) + 78.125 (Q) Alias Protected Bandwidth (MHz) 481.3 240.6 120.3 60.2 Ideal SNR Improvement 1 (dB) +1 +4 +7 +10 Pass-Band Ripple (dB) <−0.001 The ideal SNR improvement due to oversampling and filtering = 10log(bandwidth/(fS/2)). Table 18. DDC Filter Alias Rejection Alias Rejection (dB) >100 90 85 63.3 25 19.3 10.7 1 Pass-Band Ripple/ Cutoff Point (dB) <−0.001 <−0.001 <−0.001 <−0.006 −0.5 −1.0 −3.0 Alias Protected Bandwidth for Real (I) Outputs 1 <38.5% × fOUT <38.7% × fOUT <38.9% × fOUT <40% × fOUT 44.4% × fOUT 45.6% × fOUT 48% × fOUT fOUT = ADC input sample rate (fS) ÷ DDC decimation ratio. Rev. 0 | Page 36 of 72 Alias Protected Bandwidth for Complex (I/Q) Outputs1 <77% × fOUT <77.4% × fOUT <77.8% × fOUT <80% × fOUT 88.8% × fOUT 91.2% × fOUT 96% × fOUT Alias Rejection (dB) >100 Data Sheet AD9691 HALF-BAND FILTERS Table 20. HB3 Filter Coefficients The AD9691 offers four half-band filters to enable digital signal processing of the ADC converted data. These half-band filters are bypassable and can be individually selected. HB3 Coefficient Number C1, C11 C2, C10 C3, C9 C4, C8 C5, C7 C6 Table 19. HB4 Filter Coefficients HB4 Coefficient Number C1, C11 C2, C10 C3, C9 C4, C8 C5, C7 C6 Normalized Coefficient 0.006042 0 −0.049316 0 0.293273 0.500000 Decimal Coefficient (15-Bit) 99 0 −808 0 4805 8192 Decimal Coefficient (18-Bit) 859 0 −6661 0 38,570 65,536 0 –20 –40 –60 –80 –100 –120 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 NORMALIZED FREQUENCY (× π RAD/SAMPLE) 0 Figure 66. HB3 Filter Response HB2 Filter –20 MAGNITUDE (dB) 13092-067 The first decimate by 2, half-band, low-pass FIR filter (HB4) uses an 11-tap, symmetrical, fixed-coefficient filter implementation that is optimized for low power consumption. The HB4 filter is used only when complex outputs (decimate by 16) or real outputs (decimate by 8) are enabled; otherwise, the filter is bypassed. Table 19 and Figure 65 show the coefficients and response of the HB4 filter. MAGNITUDE (dB) HB4 Filter Normalized Coefficient 0.006554 0 −0.050819 0 0.294266 0.500000 The third decimate by 2, half-band, low-pass FIR filter (HB2) uses a 19-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The HB2 filter is only used when complex outputs (decimate by 4, 8, or 16) or real outputs (decimate by 2, 4, or 8) are enabled; otherwise, the filter is bypassed. –40 –60 –80 Table 21 and Figure 67 show the coefficients and response of the HB2 filter. –100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 NORMALIZED FREQUENCY (× π RAD/SAMPLE) 13092-066 –120 Figure 65. HB4 Filter Response HB3 Filter The second decimate by 2, half-band, low-pass, FIR filter (HB3) uses an 11-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The HB3 filter is only used when complex outputs (decimate by 8 or 16) or real outputs (decimate by 4 or 8) are enabled; otherwise, the filter is bypassed. Table 20 and Figure 66 show the coefficients and response of the HB3 filter. Table 21. HB2 Filter Coefficients HB2 Coefficient Number C1, C19 C2, C18 C3, C17 C4, C16 C5, C15 C6, C14 C7, C13 C8, C12 C9, C11 C10 Rev. 0 | Page 37 of 72 Normalized Coefficient 0.000614 0 −0.005066 0 0.022179 0 −0.073517 0 0.305786 0.500000 Decimal Coefficient (19-Bit) 161 0 −1328 0 5814 0 −19,272 0 80,160 131,072 AD9691 Data Sheet Table 22. HB1 Filter Coefficients 0 MAGNITUDE (dB) –20 –40 –60 –80 –100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 NORMALIZED FREQUENCY (× π RAD/SAMPLE) 13092-068 –120 Figure 67. HB2 Filter Response HB1 Filter The fourth and final decimate by 2, half-band, low-pass FIR filter (HB1) uses a 55-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The HB1 filter is always enabled and cannot be bypassed. Table 22 and Figure 68 show the coefficients and response of the HB1 filter. 0 –40 –60 –80 –100 –120 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 NORMALIZED FREQUENCY (× π RAD/SAMPLE) 13092-069 MAGNITUDE (dB) –20 HB1 Coefficient Number C1, C55 C2, C54 C3, C53 C4, C52 C5, C51 C6, C50 C7, C49 C8, C48 C9, C47 C10, C46 C11, C45 C12, C44 C13, C43 C14, C42 C15, C41 C16, C40 C17, C39 C18, C38 C19, C37 C20, C36 C21, C35 C22, C34 C23, C33 C24, C32 C25, C31 C26, C30 C27, C29 C28 Figure 68. HB1 Filter Response Rev. 0 | Page 38 of 72 Normalized Coefficient −0.000023 0 0.000097 0 −0.000288 0 0.000696 0 −0.0014725 0 0.002827 0 −0.005039 0 0.008491 0 −0.013717 0 0.021591 0 −0.033833 0 0.054806 0 −0.100557 0 0.316421 0.500000 Decimal Coefficient (21-Bit) −24 0 102 0 −302 0 730 0 −1544 0 2964 0 −5284 0 8903 0 −14,383 0 22,640 0 −35,476 0 57,468 0 −105,442 0 331,792 524,288 Data Sheet AD9691 DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION BLOCK Each DDC contains an independently controlled gain stage. The gain is selectable as either 0 dB or 6 dB. When mixing a real input signal down to baseband, it is recommended to enable the 6 dB of gain to recenter the dynamic range of the signal within the full scale of the output bits. Each DDC contains an independently controlled complex to real conversion block. The complex to real conversion block reuses the last filter (HB1 FIR) in the filtering stage, along with an fS/4 complex mixer to upconvert the signal. After upconverting the signal, the Q portion of the complex mixer is no longer needed and is dropped. When mixing a complex input signal down to baseband, the mixer has already recentered the dynamic range of the signal within the full scale of the output bits and no additional gain is necessary. However, the optional 6 dB gain compensates for low signal strengths. The downsample by 2 portion of the HB1 FIR filter is bypassed when using the complex to real conversion stage (see Figure 69). HB1 FIR Figure 69 shows a simplified block diagram of the complex to real conversion. GAIN STAGE COMPLEX TO REAL ENABLE LOW-PASS FILTER I 2 0dB OR 6dB I 0 I/REAL 1 COMPLEX TO REAL CONVERSION 0dB OR 6dB I cos(ωt) + LOW-PASS FILTER 2 Q 0dB OR 6dB Q 0° sin(ωt) – Q 13092-070 Q 0dB OR 6dB REAL 90° fS/4 HB1 FIR Figure 69. Complex to Real Conversion Block Rev. 0 | Page 39 of 72 AD9691 Data Sheet DDC EXAMPLE CONFIGURATIONS Table 23 describes the register settings for multiple DDC example configurations. Table 23. DDC Example Configurations Chip Application Layer One DDC Chip Decimation Ratio 2 DDC Input Type Complex DDC Output Type Complex Bandwidth Per DDC 1 38.5% × fS No. of Virtual Converters Required (M) 2 Two DDCs 4 Complex Complex 19.25% × fS 4 Two DDCs 4 Complex Real 9.63% × fS 2 Two DDCs 4 Real Real 9.63% × fS 2 Rev. 0 | Page 40 of 72 Register Settings 2 Register 0x200 = 0x01 (one DDC, I/Q selected) Register 0x201 = 0x01 (chip decimate by 2) Register 0x310 = 0x83 (complex mixer, 0 dB gain, variable IF, complex outputs, HB1 filter) Register 0x311 = 0x04 (DDC I input = ADC Channel A, DDC Q input = ADC Channel B) Register 0x314, Register 0x315, Register 0x320, Register 0x321 = FTW and POW set as required by application for DDC 0 Register 0x200 = 0x02 (two DDCs, I/Q selected) Register 0x201 = 0x02 (chip decimate by 4) Register 0x310, Register 0x330 = 0x80 (complex mixer, 0 dB gain, variable IF, complex outputs, HB2 + HB1 filters) Register 0x311, Register 0x331 = 0x04 (DDC I input = ADC Channel A, DDC Q input = ADC Channel B) Register 0x314, Register 0x315, Register 0x320, Register 0x321 = FTW and POW set as required by application for DDC 0 Register 0x334, Register 0x335, Register 0x340, Register 0x341 = FTW and POW set as required by application for DDC 1 Register 0x200 = 0x22 (two DDCs, I only selected) Register 0x201 = 0x02 (chip decimate by 4) Register 0x310, Register 0x330 = 0x89 (complex mixer, 0 dB gain, variable IF, real output, HB3 + HB2 + HB1 filters) Register 0x311, Register 0x331 = 0x04 (DDC I input = ADC Channel A, DDC Q input = ADC Channel B) Register 0x314, Register 0x315, Register 0x320, Register 0x321 = FTW and POW set as required by application for DDC 0 Register 0x334, Register 0x335, Register 0x340, Register 0x341 = FTW and POW set as required by application for DDC 1 Register 0x200 = 0x22 (two DDCs, I only selected) Register 0x201 = 0x02 (chip decimate by 4) Register 0x310, Register 0x330 = 0x49 (real mixer, 6 dB gain, variable IF, real output, HB3 + HB2 + HB1 filters) Register 0x311 = 0x00 (DDC 0 I input = ADC Channel A, DDC 0 Q input = ADC Channel A) Register 0x331 = 0x05 (DDC 1 I input = ADC Channel B, DDC 1 Q input = ADC Channel B) Register 0x314, Register 0x315, Register 0x320, Register 0x321 = FTW and POW set as required by application for DDC 0 Register 0x334, Register 0x335, Register 0x340, Register 0x341 = FTW and POW set as required by application for DDC 1 Data Sheet AD9691 Chip Application Layer Two DDCs Chip Decimation Ratio 4 DDC Input Type Real DDC Output Type Complex Bandwidth Per DDC 1 19.25% × fS No. of Virtual Converters Required (M) 4 Two DDCs 8 Real Real 4.81% × fS 2 Four DDCs 8 Real Complex 9.63% × fS 8 Rev. 0 | Page 41 of 72 Register Settings 2 Register 0x200 = 0x02 (two DDCs, I/Q selected) Register 0x201 = 0x02 (chip decimate by 4) Register 0x310, 0x330 = 0x40 (real mixer, 6 dB gain, variable IF, complex output, HB2 + HB1 filters) Register 0x311 = 0x00 (DDC 0 I input = ADC Channel A, DDC 0 Q input = ADC Channel A) Register 0x331 = 0x05 (DDC 1 I input = ADC Channel B, DDC 1 Q input = ADC Channel B) Register 0x314, Register 0x315, Register 0x320, Register 0x321 = FTW and POW set as required by application for DDC 0 Register 0x334, Register 0x335, Register 0x340, Register 0x341 = FTW and POW set as required by application for DDC 1 Register 0x200 = 0x22 (two DDCs, I only selected) Register 0x201 = 0x03 (chip decimate by 8) Register 0x310, Register 0x330 = 0x4A (real mixer, 6 dB gain, variable IF, real output, HB4 + HB3 + HB2 + HB1 filters) Register 0x311 = 0x00 (DDC 0 I input = ADC Channel A, DDC 0 Q input = ADC Channel A) Register 0x331 = 0x05 (DDC 1 I input = ADC Channel B, DDC 1 Q input = ADC Channel B) Register 0x314, Register 0x315, Register 0x320, Register 0x321 = FTW and POW set as required by application for DDC 0 Register 0x334, Register 0x335, Register 0x340, Register 0x341 = FTW and POW set as required by application for DDC 1 Register 0x200 = 0x03 (four DDCs, I/Q selected) Register 0x201 = 0x03 (chip decimate by 8) Register 0x310, Register 0x330, Register 0x350, Register 0x370 = 0x41 (real mixer, 6 dB gain, variable IF, complex output, HB3 + HB2 + HB1 filters) Register 0x311 = 0x00 (DDC 0 I input = ADC Channel A, DDC 0 Q input = ADC Channel A) Register 0x331 = 0x00 (DDC 1 I input = ADC Channel A, DDC 1 Q input = ADC Channel A) Register 0x351 = 0x05 (DDC 2 I input = ADC Channel B, DDC 2 Q input = ADC Channel B) Register 0x371 = 0x05 (DDC 3 I input = ADC Channel B, DDC 3 Q input = ADC Channel B) Register 0x314, Register 0x315, Register 0x320, Register 0x321 = FTW and POW set as required by application for DDC 0 Register 0x334, Register 0x335, Register 0x340, Register 0x341 = FTW and POW set as required by application for DDC 1 Register 0x354, Register 0x355, Register 0x360, Register 0x361 = FTW and POW set as required by application for DDC 2 Register 0x374, Register 0x375, Register 0x380, Register 0x381 = FTW and POW set as required by application for DDC 3 AD9691 Data Sheet Chip Application Layer Four DDCs Chip Decimation Ratio 8 DDC Input Type Real DDC Output Type Real Bandwidth Per DDC 1 4.81% × fS No. of Virtual Converters Required (M) 4 Four DDCs 16 Real Complex 4.81% × fS 8 1 2 Register Settings 2 Register 0x200 = 0x23 (four DDCs, I only selected) Register 0x201 = 0x03 (chip decimate by 8) Register 0x310, Register 0x330, Register 0x350, Register 0x370 = 0x4A (real mixer, 6 dB gain, variable IF, real output, HB4 + HB3 + HB2 + HB1 filters) Register 0x311 = 0x00 (DDC 0 I input = ADC Channel A, DDC 0 Q input = ADC Channel A) Register 0x331 = 0x00 (DDC 1 I input = ADC Channel A, DDC 1 Q input = ADC Channel A) Register 0x351 = 0x05 (DDC 2 I input = ADC Channel B, DDC 2 Q input = ADC Channel B) Register 0x371 = 0x05 (DDC 3 I input = ADC Channel B, DDC 3 Q input = ADC Channel B) Register 0x314, Register 0x315, Register 0x320, Register 0x321 = FTW and POW set as required by application for DDC 0 Register 0x334, Register 0x335, Register 0x340, Register 0x341 = FTW and POW set as required by application for DDC 1 Register 0x354, Register 0x355, Register 0x360, Register 0x361 = FTW and POW set as required by application for DDC 2 Register 0x374, Register 0x375, Register 0x380, Register 0x381 = FTW and POW set as required by application for DDC 3 Register 0x200 = 0x03 (four DDCs, I/Q selected) Register 0x201 = 0x04 (chip decimate by 16) Register 0x310, Register 0x330, Register 0x350, Register 0x370 = 0x42 (real mixer, 6 dB gain, variable IF, complex output, HB4 + HB3 + HB2 + HB1 filters) Register 0x311 = 0x00 (DDC 0 I input = ADC Channel A, DDC 0 Q input = ADC Channel A) Register 0x331 = 0x00 (DDC 1 I input = ADC Channel A, DDC 1 Q input = ADC Channel A) Register 0x351 = 0x05 (DDC 2 I input = ADC Channel B, DDC 2 Q input = ADC Channel B) Register 0x371 = 0x05 (DDC 3 I input = ADC Channel B, DDC 3 Q input = ADC Channel B) Register 0x314, Register 0x315, Register 0x320, Register 0x321 = FTW and POW set as required by application for DDC 0. Register 0x334, Register 0x335, Register 0x340, Register 0x341 = FTW and POW set as required by application for DDC 1 Register 0x354, Register 0x355, Register 0x360, Register 0x361 = FTW and POW set as required by application for DDC 2 Register 0x374, Register 0x375, Register 0x380, Register 0x381 = FTW and POW set as required by application for DDC 3 fS is the ADC sample rate. Bandwidths listed are <−0.001 dB of pass-band ripple and >100 dB of stop-band alias rejection. The NCOs must be synchronized either through the SPI or through the SYSREF± pin after all writes to the FTW or POW registers have completed. This is necessary to ensure the proper operation of the NCO. See the NCO Synchronization section for more information. Rev. 0 | Page 42 of 72 Data Sheet AD9691 DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE • The AD9691 digital outputs are designed to the JEDEC Standard JESD204B serial interface for data converters. JESD204B is a protocol to link the AD9691 to a digital processing device over a serial interface with lane rates of up to 10 Gbps. The benefits of the JESD204B interface over the LVDS interface include a reduction in required board area for data interface routing, and an ability to enable smaller packages for converter and logic devices. JESD204B OVERVIEW The JESD204B data transmit block assembles the parallel data from the ADC into frames and uses 8B/10B encoding as well as optional scrambling to form serial output data. Lane synchronization is supported through the use of special control characters during the initial establishment of the link. Additional control characters are embedded in the data stream to maintain synchronization thereafter. A JESD204B receiver is required to complete the serial link. For additional details on the JESD204B interface, refer to the JESD204B standard. The AD9691 JESD204B data transmit block maps up to two physical ADCs or up to eight virtual converters (when DDCs are enabled) over a link. A link can be configured to use one, two, or four JESD204B lanes. The JESD204B specification refers to a number of parameters to define the link, and these parameters must match between the JESD204B transmitter (the AD9691 output) and the JESD204B receiver (the logic device input). The JESD204B link is described according to the following parameters: • • • • • • • L is the number of lanes per converter device (lanes per link) (AD9691 value = 1, 2, or 4) M is the number of converters per converter device (virtual converters per link) (AD9691 value = 1, 2, 4, or 8) F is the octets per frame (AD9691 value = 1, 2, 4, 8, or 16) N΄ is the number of bits per sample (JESD204B word size) (AD9691 value = 8 or 16) N is the converter resolution (AD9691 value = 7 to 16) CS is the number of control bits per sample (AD9691 value = 0 to 3) K is the number of frames per multiframe (AD9691 value = 4, 8, 12, 16, 20, 24, 28, or 32) • • S is the samples transmitted per single converter per frame cycle (AD9691 value = set automatically based on L, M, F, and N΄) HD is the high density mode (AD9691 value = set automatically based on L, M, F, and N΄) CF is the number of control words per frame clock cycle per converter device (AD9691 value = 0) Figure 70 shows a simplified block diagram of the AD9691 JESD204B link. By default, the AD9691 is configured to use two converters and four lanes. Converter A data is output to SERDOUT0±, SERDOUT1±, SERDOUT2±, and SERDOUT3±, and Converter B data is output to SERDOUT4±, SERDOUT5±, SERDOUT6±, and SERDOUT7±. The AD9691 allows other configurations such as combining the outputs of both converters onto a single lane, or changing the mapping of the Converter A and Converter B digital output paths. These modes are set up via a quick configuration register in the SPI register map, along with additional customizable options. By default in the AD9691, the 14-bit converter word from each converter is broken into two octets (eight bits of data). Bit 13 (MSB) through Bit 6 are in the first octet. The second octet contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits can be configured as zeros or a pseudorandom number (PN) sequence. The tail bits can also be replaced with control bits indicating overrange, SYSREF±, signal monitor, or fast detect output. The two resulting octets can be scrambled. Scrambling is optional; however, it is recommended to avoid spectral peaks when transmitting similar digital data patterns. The scrambler uses a self synchronizing, polynomial-based algorithm defined by the equation 1 + x14 + x15. The descrambler in the receiver is a self synchronizing version of the scrambler polynomial. The two octets are then encoded with an 8B/10B encoder. The 8B/10B encoder takes eight bits of data (an octet) and encodes them into a 10-bit symbol. Figure 71 shows how the 14-bit data is taken from the ADC, the tail bits are added, the two octets are scrambled, and how the octets are encoded into two 10-bit symbols. Figure 71 illustrates the default data framing. Rev. 0 | Page 43 of 72 Data Sheet CONVERTER 0 CONVERTER A INPUT ADC A CONVERTER B INPUT LANE MUX AND MAPPING (SPI REG 0x5B0, REG 0x5B2, REG 0x5B3, REG 0x5B5, REG 0x5B6) JESD204B LINK CONTROL (L, M, F) (SPI REG 0x570) MUX/ FORMAT (SPI REG 0x561, REG 0x564) ADC B CONVERTER 1 SERDOUT0–, SERDOUT0+ SERDOUT1–, SERDOUT1+ SERDOUT2–, SERDOUT2+ SERDOUT3–, SERDOUT3+ SERDOUT4–, SERDOUT4+ SERDOUT5–, SERDOUT5+ SERDOUT6–, SERDOUT6+ SERDOUT7–, SERDOUT7+ SYSREF± SYNCINB± 13092-071 AD9691 Figure 70. Transmit Link Simplified Block Diagram Showing Full Bandwidth Mode (Register 0x200 = 0x00) JESD204B INTERFACE TEST PATTERN (REG 0x573, REG 0x551 TO REG 0x558) JESD204B LONG TRANSPORT TEST PATTERN REG 0x571[5] SERDOUT0± SERDOUT1± SERIALIZER MSB A13 A12 A11 A10 A9 A8 A7 LSB A6 A5 A4 A3 A2 A1 A0 C2 T MSB S7 S6 S5 S4 S3 S2 S1 LSB S0 S7 S6 S5 S4 S3 S2 S1 S0 8-BIT/10-BIT ENCODER a b a b c d e f g h i j i j a b SYMBOL0 i j SYMBOL1 a b c d e f g h i j 13092-072 TAIL BITS 0x571[6] SCRAMBLER 1 + x14 + x15 (OPTIONAL) OCTET 1 JESD204B SAMPLE CONSTRUCTION MSB A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 LSB A0 OCTET 1 OCTET 0 FRAME CONSTRUCTION OCTET 0 ADC TEST PATTERNS (RE0x550, REG 0x551 TO REG 0x558) ADC JESD204B DATA LINK LAYER TEST PATTERNS REG 0x574[2:0] C2 CONTROL BITS C1 C0 Figure 71. ADC Output Datapath Showing Data Framing TRANSPORT LAYER SAMPLE CONSTRUCTION FRAME CONSTRUCTION SCRAMBLER ALIGNMENT CHARACTER GENERATION PHYSICAL LAYER 8-BIT/10-BIT ENCODER CROSSBAR MUX SERIALIZER Tx OUTPUT 13092-073 PROCESSED SAMPLES FROM ADC DATA LINK LAYER SYSREF± SYNCINB± Figure 72. Data Flow T = N΄ – N – CS FUNCTIONAL OVERVIEW The block diagram in Figure 72 shows the flow of data through the JESD204B hardware from the sample input to the physical output. The processing can be divided into layers that are derived from the open-source initiative (OSI) model widely used to describe the abstraction layers of communications systems. These layers are the transport layer, the data link layer, and the physical layer, which includes the serializer and output driver). Transport Layer The transport layer handles packing the data (consisting of samples and optional control bits) into JESD204B frames that are mapped to 8-bit octets. These octets are sent to the data link layer. The transport layer mapping is controlled by rules derived from the link parameters. Tail bits are added to fill gaps where required. The following equation can be used to determine the number of tail bits within a sample (JESD204B word): Data Link Layer The data link layer manages the low level functions of passing data across the link. These functions include optionally scrambling the data, inserting control characters for multichip synchronization/lane alignment/monitoring, encoding 8-bit octets into 10-bit symbols, and remapping data using the crossbar mux. The data link layer is also responsible for sending the initial lane alignment sequence (ILAS), which contains the link configuration data used by the receiver to verify the settings in the transport layer. Physical Layer The physical layer consists of the high speed circuitry clocked at the serial clock rate. In this layer, parallel data is converted into one, two, or four lanes of high speed differential serial data. Rev. 0 | Page 44 of 72 Data Sheet AD9691 JESD204B LINK ESTABLISHMENT Initial Lane Alignment Sequence (ILAS) The AD9691 JESD204B transmitter (Tx) interface operates in Subclass 1 as defined in the JEDEC Standard JESD204B (July 2011 specification). The link establishment process is divided into the following steps: code group synchronization and SYNCINB±, initial lane alignment sequence, and user data and error correction. The ILAS phase follows the CGS phase and begins on the next LMFC boundary. The ILAS consists of four multiframes, with an /R/ character marking the beginning and an /A/ character marking the end. The ILAS begins by sending an /R/ character followed by 0 to 255 ramp data for one multiframe. On the second multiframe, the link configuration data is sent, starting with the third character. The second character is a /Q/ character to confirm that the link configuration data follows. All undefined data slots are filled with ramp data. The ILAS sequence is never scrambled. Code Group Synchronization (CGS) and SYNCINB± The CGS is the process by which the JESD204B receiver finds the boundaries between the 10-bit symbols in the stream of data. During the CGS phase, the JESD204B transmit block transmits the /K28.5/ characters. The receiver must locate the /K28.5/ characters in its input data stream using clock and data recovery (CDR) techniques. The receiver issues a synchronization request by asserting the SYNCINB± pin of the AD9691 low. The JESD204B Tx then begins sending /K/ characters. After the receiver is synchronized, it waits for the correct reception of at least four consecutive /K/ symbols. It then deasserts SYNCINB±. The AD9691 then transmits an ILAS on the following local multiframe clock (LMFC) boundary. For more information on the code group synchronization phase, refer to the JEDEC Standard JESD204B, July 2011, Section 5.3.3.1. The ILAS sequence construction is shown in Figure 73. The four multiframes include the following: • • • • Multiframe 1, which begins with an /R/ character (/K28.0/) and ends with an /A/ character (/K28.3/). Multiframe 2, which begins with an /R/ character followed by a /Q/ (/K28.4/) character, followed by link configuration parameters over 14 configuration octets (see Table 24) and ends with an /A/ character. Many of the parameter values are of the value – 1 notation. Multiframe 3, which begins with an /R/ character (/K28.0/) and ends with an /A/ character (/K28.3/). Multiframe 4, which begins with an /R/ character (/K28.0/) and ends with an /A/ character (/K28.3/). The SYNCINB± pin operation can also be controlled by the SPI. The SYNCINB± signal is a differential LVDS mode signal by default, but it can also be driven single-ended. For more information on configuring the SYNCINB± pin operation,see Register 0x572 in Table 35. K K R D D A R Q C C D D A R D D A R D D A D START OF ILAS START OF USER DATA START OF LINK CONFIGURATION DATA Figure 73. Initial Lane Alignment Sequence Rev. 0 | Page 45 of 72 13092-074 END OF MULTIFRAME AD9691 Data Sheet User Data and Error Detection After the initial lane alignment sequence is complete, the user data is sent. Normally, all characters within a frame are considered user data. However, to monitor the frame clock and multiframe clock synchronization, there is a mechanism for replacing characters with /F/ or /A/ alignment characters when the data meets certain conditions. These conditions are different for unscrambled and scrambled data. The scrambling operation is enabled by default, but it can be disabled using the SPI. For scrambled data, any 0xFC character at the end of a frame is replaced by an /F/ character, and any 0x7C character at the end of a multiframe is replaced with an /A/ character. The JESD204B receiver (Rx) checks for /F/ and /A/ characters in the received data stream and verifies that they only occur in the expected locations. If an unexpected /F/ or /A/ character is found, the receiver handles the situation by using dynamic realignment or asserting the SYNCINB± signal for more than four frames to initiate a resynchronization. For unscrambled data, when the final character of two subsequent frames is equal, the second character is replaced with an /F/ character if it is at the end of a frame, and an /A/ character if it is at the end of a multiframe. Insertion of alignment characters can be modified using the SPI. The frame alignment character insertion (FACI) is enabled by default. For more information on the link controls, see the Memory Map section, Register 0x571. 8B/10B Encoder The 8B/10B encoder converts 8-bit octets into 10-bit symbols and inserts control characters into the stream when needed. The control characters used in JESD204B are shown in Table 24. The 8B/10B encoding ensures that the signal is dc balanced by using the same number of ones and zeros across multiple symbols. The 8B/10B interface has options that can be controlled via the SPI. These operations include bypass and invert. These options are intended to be troubleshooting tools for the verification of the digital front end (DFE). See the Memory Map section, Register 0x572, Bits[2:1] for information on configuring the 8B/10B encoder. Table 24. AD9691 Control Characters Used in JESD204B Abbreviation /R/ /A/ /Q/ /K/ /F/ 1 Control Symbol /K28.0/ /K28.3/ /K28.4/ /K28.5/ /K28.7/ 8-Bit Value 000 11100 011 11100 100 11100 101 11100 111 11100 10-Bit Value, RD 1 = −1 001111 0100 001111 0011 001111 0010 001111 1010 001111 1000 RD means running disparity. Rev. 0 | Page 46 of 72 10-Bit Value, RD1 = +1 110000 1011 110000 1100 110000 1101 110000 0101 110000 0111 Description Start of multiframe Lane alignment Start of link configuration data Group synchronization Frame alignment Data Sheet AD9691 PHYSICAL LAYER (DRIVER) OUTPUTS 8000 Digital Outputs, Timing, and Controls 7000 6000 4000 HITS 3000 Place a 100 Ω differential termination resistor at each receiver, which results in a nominal 300 mV p-p swing at the receiver (see Figure 74). It is recommended to use ac coupling to connect the AD9691 serializer/deserializer (SERDES) outputs to the receiver. –3 –2 –1 1 0 2 3 4 Figure 76. Digital Outputs Histogram, External 100 Ω Terminations at 6 Gbps 1 RECEIVER 1–2 0.1µF 1–4 13092-075 OUTPUT SWING = 300mV p-p 1–6 Figure 74. AC-Coupled Digital Output Termination Example If there is no far end receiver termination, or if there is poor differential trace routing, timing errors may result. To avoid such timing errors, it is recommended that the trace length be less than six inches, and that the differential output traces be close together and at equal lengths. Figure 75 to Figure 77 show examples of the digital output data eye, time interval error (TIE) jitter histogram, and bathtub curve, respectively, for one AD9691 lane running at 6 Gbps. The format of the output data is twos complement by default. To change the output data format, see the Memory Map section (Register 0x561 in Table 35). 1–8 1–10 1–12 1–14 1–16 –0.5 –0.4 –0.3 –0.2 –0.1 0 UI 0.1 0.2 0.3 0.4 0.5 Figure 77. Digital Outputs Bathtub Curve, External 100 Ω Terminations at 6 Gbps De-Emphasis –300 De-emphasis enables the receiver eye diagram mask to be met in conditions where the interconnect insertion loss does not meet the JESD204B specification. Use the de-emphasis feature only when the receiver cannot recover the clock due to excessive insertion loss. Under normal conditions, it is disabled to conserve power. Additionally, enabling and setting too high a de-emphasis value on a short link may cause the receiver eye diagram to fail. Use the de-emphasis setting with caution because it may increase electromagnetic interference (EMI). See the Memory Map section (Register 0x5C1 to Register 0x5C5 in Table 35) for more details. –400 Phase-Locked Loop (PLL) 400 300 200 VOLTAGE (mV) 0 –4 TIME (ps) 100Ω DIFFERENTIAL TRACE PAIR 0.1µF 100Ω SERDOUTx– 1000 13092-078 SERDOUTx+ 2000 BER DRVDD 4000 13092-077 The AD9691 physical layer consists of drivers that are defined in the JEDEC Standard JESD204B (July 2011). The differential digital outputs are powered up by default. The drivers use a dynamic 100 Ω internal termination to reduce unwanted reflections. 100 0 –100 Tx EYE MASK –150 –100 –50 0 TIME (ps) 50 100 150 13092-076 –200 Figure 75. Digital Outputs Data Eye, External 100 Ω Terminations at 6 Gbps The PLL generates the serializer clock, which operates at the JESD204B lane rate. The JESD204B lane rate in Register 0x56E, Bit 4 must be set to correspond with the lane rate. Rev. 0 | Page 47 of 72 AD9691 Data Sheet CONFIGURING THE JESD204B LINK Use the following steps to configure the output: The AD9691 has one JESD204B link. The device offers an easy way to set up the JESD204B link through the quick configuration register (Register 0x570). The serial outputs (SERDOUT0± to SERDOUT3±) are considered to be part of one JESD204B link. The basic parameters that determine the link setup are 1. 2. 3. 4. 5. 6. • • • Number of lanes per link (L) Number of converters per link (M) Number of octets per frame (F) Power down the link. Select the quick configuration options. Configure the detailed options. Set the output lane mapping (optional). Set additional driver configuration options (optional). Power up the link. If the lane rate calculated is less than 6.25 Gbps, select the low lane rate option. This is done by programming a value of 0x10 to Register 0x56E. The maximum lane rate allowed by the JESD204B specification is 12.5 Gbps. The lane rate is related to the JESD204B parameters using the following equation: Table 25 and Table 26 show the JESD204B output configurations supported for both N΄ = 16 and N΄ = 8 for a given number of virtual converters. Take care to ensure that the serial lane rate for a given configuration is within the supported range of 3.125 Gbps to 12.5 Gbps. 10 M × N' × × f OUT 8 Lane Rate = L where fOUT = fADC_CLOCK ÷ Chip decimation ratio. Table 25. JESD204B Output Configurations for N' = 16 Number of Virtual Converters Supported (Same Value as M) 1 2 4 8 JESD204B Transport Layer Settings 2 JESD204B Quick Configuration (Register 0x570) 0x01 0x40 0x41 0x80 0x81 0xC0 0xC1 0x0A 0x49 0x88 0x89 0xC8 0xC9 0x13 0x52 0x91 0xD0 0xD1 0x1C 0x5B 0x9A 0xD9 JESD204B Serial Lane Rate 1 20 × fOUT 10 × fOUT 10 × fOUT 5 × fOUT 5 × fOUT 2.5 × fOUT 2.5 × fOUT 40 × fOUT 20 × fOUT 10 × fOUT 10 × fOUT 5 × fOUT 5 × fOUT 80 × fOUT 40 × fOUT 20 × fOUT 10 × fOUT 10 × fOUT 160 × fOUT 80 × fOUT 40 × fOUT 20 × fOUT L 1 2 2 4 4 8 8 1 2 4 4 8 8 1 2 4 8 8 1 2 4 8 M 1 1 1 1 1 1 1 2 2 2 2 2 2 4 4 4 4 4 8 8 8 8 F 2 1 2 1 2 1 2 4 2 1 2 1 2 8 4 2 1 2 16 8 4 2 S 1 1 2 2 4 4 8 1 1 1 2 2 4 1 1 1 1 2 1 1 1 1 HD 0 1 0 1 0 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 N 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 N' 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 CS 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 K3 Only valid K values that are divisible by 4 are supported fOUT = output sample rate = fADC_CLOCK ÷ chip decimation ratio. The JESD204B serial lane rate must be ≥3.125 Gbps and ≤12.5 Gbps; when the serial lane rate is ≤12.5 Gbps and ≥6.25 Gbps, the low lane rate mode must be disabled (set Bit 4 to 0x0 in Register 0x56E). When the serial lane rate is <6.25 Gbps and ≥3.125 Gbps, the low lane rate mode must be enabled (set Bit 4 to 0x1 in Register 0x56E). 2 The JESD204B transport layer descriptions are as described in the JESD204B Overview section. 3 For F = 1, K = 20, 24, 28, and 32. For F = 2, K = 12, 16, 20, 24, 28, and 32. For F = 4, K = 8, 12, 16, 20, 24, 28, and 32. For F = 8 and F = 16, K = 4, 8, 12, 16, 20, 24, 28, and 32. 1 Rev. 0 | Page 48 of 72 Data Sheet AD9691 Table 26. JESD204B Output Configurations for N'= 8 Number of Virtual Converters Supported (Same Value as M) 1 2 JESD204B Quick Configuration (Register 0x570) 0x00 0x01 0x40 0x41 0x42 0x80 0x81 0x09 0x48 0x49 0x88 0x89 0x8A JESD204B Transport Layer Settings 2 JESD204B Serial Lane Rate 1 10 × fOUT 10 × fOUT 5 × fOUT 5 × fOUT 5 × fOUT 2.5 × fOUT 2.5 × fOUT 20 × fOUT 10 × fOUT 10 × fOUT 5 × fOUT 5 × fOUT 5 × fOUT L 1 1 2 2 2 4 4 1 2 2 4 4 4 M 1 1 1 1 1 1 1 2 2 2 2 2 2 F 1 2 1 2 4 1 2 2 1 2 1 2 4 S 1 2 2 4 8 4 8 1 1 2 2 4 8 HD 0 0 0 0 0 0 0 0 0 0 0 0 0 N 7 to 8 7 to 8 7 to 8 7 to 8 7 to 8 7 to 8 7 to 8 7 to 8 7 to 8 7 to 8 7 to 8 7 to 8 7 to 8 N' 8 8 8 8 8 8 8 8 8 8 8 8 8 CS 0 to 1 0 to 1 0 to 1 0 to 1 0 to 1 0 to 1 0 to 1 0 to 1 0 to 1 0 to 1 0 to 1 0 to 1 0 to 1 K3 Only valid K values which are divisible by 4 are supported fOUT = output sample rate = fADC_CLOCK ÷ chip decimation ratio. The JESD204B serial lane rate must be ≥3125 Mbps and ≤12.5 Gbps; when the serial lane rate is ≤12.5 Gbps and ≥6.25 Gbps, the low lane rate mode must be disabled (set Bit 4 to 0x0 in Register 0x56E). When the serial lane rate is <6.25 Gbps and ≥3.125 Gbps, the low lane rate mode must be enabled (set Bit 4 to 0x1 in Register 0x56E). 2 The JESD204B transport layer descriptions are as described in the JESD204B Overview section. 3 For F = 1, K = 20, 24, 28, and 32. For F = 2, K = 12, 16, 20, 24, 28, and 32. For F = 4, K = 8, 12, 16, 20, 24, 28, and 32. For F = 8 and F = 16, K = 4, 8, 12, 16, 20, 24, 28, and 32. 1 CMOS See the Example 1: Full Bandwidth Mode section and the Example 2: ADC with DDC Option (Two ADCs Plus Two DDCs ) section for two examples describing which JESD204B transport layer settings are valid for a given chip mode. FAST DETECTION REAL/I Example 1: Full Bandwidth Mode The chip application mode is full bandwidth mode (see Figure 78), and includes the following: Two 14-bit converters at 1250 MSPS Full bandwidth application layer mode No decimation CMOS Figure 78. Full Bandwidth Mode Two virtual converters required (see Table 25) Output sample rate (fOUT) = 1250/1 = 1250 MSPS The JESD204B supported output configurations (see Table 25) include • • • • • • CONVERTER 1 JESD204B TRANSMIT INTERFACE FAST DETECTION The JESD204B output configuration includes the following: • • 14-BIT AT 1Gbps CONVERTER 0 L JESD204B LANES AT UP TO 12.5Gbps 13092-079 • • • REAL/Q 14-BIT AT 1Gbps N΄ = 16 bits N = 14 bits L = 8, M = 2, and F = 1, or L = 4, M = 2, and F = 1 (quick configuration = 0xC8 or 0x88) CS = 0 to 2 K = 32 Output serial lane rate = 6.25 Gbps per lane for L = 8; output serial lane rate = 12.5 Gbps per lane for L = 4; low lane rate mode disabled Example 2: ADC with DDC Option (Two ADCs Plus Two DDCs ) The chip application mode is two-DDC mode (see Figure 79), and includes the following: • • • • Two 14-bit converters at 1.25 GSPS Two-DDC application layer mode with complex outputs (I/Q) Chip decimation ratio = 2 DDC decimation ratio = 2 (see Table 35) The JESD204B output configuration includes the following: • • Rev. 0 | Page 49 of 72 Virtual converters required = 4 (see Table 25) Output sample rate (fOUT) = 1250/2 = 625 MSPS AD9691 Data Sheet The JESD204B supported output configurations include (see Table 25) N΄ = 16 bits N = 14 bits L = 4, M = 4, and F = 2 (quick configuration = 0x91) CS = 0 to 1 K = 32 Output serial lane rate = 10 Gbps per lane (L = 4) Low lane rate mode is disabled (0x56E = 0x00) REAL REAL SYSREF ADC A SAMPLING AT fS ADC B SAMPLING AT fS REAL/I I/Q CROSSBAR MUX REAL/Q DDC 0 I CONVERTER 0 Q CONVERTER 1 DDC 1 I CONVERTER 2 Q CONVERTER 3 L JESD204B LANES UP TO 12.5Gbps L JESD204B LANES AT UP TO 12.5Gbps 13092-080 • • • • • • • Example 2 shows the flexibility in the digital and lane configurations for the AD9691. The sample rate is 1.25 GSPS, but the outputs are all combined in either one or two lanes, depending on the input/output speed capability of the receiving device. SYNCHRONIZATION CONTROL CIRCUITS Figure 79. Two-ADC Plus Two-DDC Mode Rev. 0 | Page 50 of 72 Data Sheet AD9691 MULTICHIP SYNCHRONIZATION AD9691. The AD9691 supports several features that aid users in meeting the requirements for capturing a SYSREF± signal. The SYSREF± sample event can be defined as either a synchronous low to high transition, or synchronous high to low transition. Additionally, the AD9691 allows the SYSREF± signal to be sampled using either the rising edge or falling edge of the CLK± input. The AD9691 also can ignore a programmable number (up to 16) of SYSREF± events. The SYSREF± control options can be selected using Register 0x120 and Register 0x121. The AD9691 has a SYSREF± input that allows flexible options for synchronizing the internal blocks. The SYSREF± input is a source synchronous system reference signal that enables multichip synchronization. The input clock divider, DDCs, signal monitor block, and JESD204B link can be synchronized using the SYSREF± input. For the highest level of timing accuracy, SYSREF± must meet setup and hold requirements relative to the CLK± input. The flowchart in Figure 80 describes the internal mechanism by which multichip synchronization can be achieved in the START INCREMENT SYSREF± IGNORE COUNTER NO NO NO RESET SYSREF± IGNORE COUNTER SYSREF± ENABLED? (REG 0x120) NO YES SYSREF± ASSERTED? UPDATE SETUP/HOLD DETECTOR STATUS (0x128) YES SYSREF± IGNORE COUNTER EXPIRED? (REG 0x121) YES ALIGN CLOCK DIVIDER PHASE TO SYSREF INPUT CLOCK DIVIDER ALIGNMENT REQUIRED? YES YES NO SYNCHRONIZATION MODE? (REG 0x1FF) CLOCK DIVIDER AUTO ADJUST ENABLED? (REG 0x10D) NO TIMESTAMP MODE SYSREF± TIMESTAMP DELAY (REG 0x123) INCREMENT SYSREF± COUNTER (REG 0x12A) CLOCK DIVIDER > 1? (REG 0x10B) YES NO SYSREF± CONTROL BITS? (REG 0x559, REG 0x55A, REG 0x58F) YES SYSREF± INSERTED IN JESD204B CONTROL BITS NO RAMP TEST MODE ENABLED? (REG 0x550) NORMAL MODE YES SYSREF± RESETS RAMP TEST MODE GENERATOR BACK TO START NO YES ALIGN PHASE OF ALL INTERNAL CLOCKS (INCLUDING LMFC) TO SYSREF± SEND INVALID 8B/10B CHARACTERS (ALL 0s) SYNC~ ASSERTED NO SEND K28.5 CHARACTERS NORMAL JESD204B INITIALIZATION NO NO SIGNAL MONITOR ALIGNMENT ENABLED? (REG 0x26F) YES YES ALIGN SIGNAL MONITOR COUNTERS DDC NCO ALIGNMENT ENABLED? (REG 0x300) YES NO Figure 80. Multichip Synchronization Rev. 0 | Page 51 of 72 ALIGN DDC NCO PHASE ACCUMULATOR BACK TO START 13092-081 JESD204B LMFC ALIGNMENT REQUIRED? AD9691 Data Sheet SYSREF± SETUP/HOLD WINDOW MONITOR To assist in ensuring a valid SYSREF± signal capture, the AD9691 has a SYSREF± setup/hold window monitor. This feature allows the system designer to determine the location of the SYSREF± signals relative to the CLK± signals by reading back the amount of setup/hold margin on the interface through the memory map. Figure 81 and Figure 82 show the setup and REG 0x128[3:0] hold status values for different phases of SYSREF±. The setup detector returns the status of the SYSREF±signal before the CLK± edge and the hold detector returns the status of the SYSREF± signal after the CLK± edge. Register 0x128 stores the status of SYSREF± and alerts the user if the SYSREF± signal is captured by the ADC. –1 –2 –3 –4 –5 –6 –7 –8 7 6 5 4 3 2 1 0 CLK± INPUT SYSREF± INPUT VALID FLIP FLOP HOLD (MIN) FLIP FLOP HOLD (MIN) 13092-082 FLIP FLOP SETUP (MIN) Figure 81. SYSREF± Setup Detector REG 0x128[7:4] –1 –2 –3 –4 –5 –6 –7 –8 7 6 5 4 3 2 1 0 CLK± INPUT SYSREF± INPUT FLIP FLOP SETUP (MIN) FLIP FLOP HOLD (MIN) FLIP FLOP HOLD (MIN) Figure 82. SYSREF± Hold Detector Rev. 0 | Page 52 of 72 13092-083 VALID Data Sheet AD9691 Table 27 shows the description of the contents of Register 0x128 and how to interpret them. Table 27. SYSREF± Setup/Hold Monitor, Register 0x128 Register 0x128, Bits[7:4], Hold Status 0x0 0x0 to 0x8 0x8 0x8 0x9 to 0xF 0x0 Register 0x128, Bits[3:0], Setup Status 0x0 to 0x7 0x8 0x9 to 0xF 0x0 0x0 0x0 Description Possible setup error. The smaller this number, the smaller the setup margin. No setup or hold error (best hold margin). No setup or hold error (best setup and hold margin). No setup or hold error (best setup margin). Possible hold error. The larger this number, the smaller the hold margin. Possible setup or hold error. Rev. 0 | Page 53 of 72 AD9691 Data Sheet TEST MODES ADC TEST MODES The AD9691 has various test options that aid in the system level implementation. The AD9691 has ADC test modes that are available in Register 0x550. These test modes are described in Table 28. When an output test mode is enabled, the analog section of the ADC is disconnected from the digital back-end blocks and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting, and some are not. The PN generators from the PN sequence tests can be reset by setting Bit 4 or Bit 5 of Register 0x550. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. If the application mode has been set to select a DDC mode of operation, the test modes must be enabled for each DDC enabled. The test modes can be enabled via Bit 2 and Bit 0 of Register 0x327, Register 0x347, and Register 0x367, depending on which DDCs are selected. The I data uses the test patterns selected for Channel A, and the Q data uses the test patterns selected for Channel B. For DDC 3, only the I data uses the test patterns from Channel A. The Q data does not output test patterns. Bit 0 of Register 0x387 selects the Channel A test patterns for the I data. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. JESD204B BLOCK TEST MODES In addition to the ADC test modes, the AD9691 also has flexible test modes in the JESD204B block. These test modes are listed in Register 0x573 and Register 0x574. These test patterns can be inserted at various points along the output data path. These test insertion points are shown in Figure 71. Table 29 describes the various test modes available in the JESD204B block. For the AD9691, a transition from the test modes (Register 0x573 ≠ 0x00) to normal mode (Register 0x573 = 0x00) require a SPI soft reset. This is done by writing 0x81 to Register 0x00 (self cleared). Transport Layer Sample Test Mode The transport layer samples are implemented in the AD9691 as defined by Section 5.1.6.3 in the JEDEC JESD204B specification. These tests are enabled via Register 0x571, Bit 5. The test pattern is equivalent to the raw samples from the ADC. Interface Test Modes The interface test modes are described in Register 0x573, Bits[3:0]. These test modes are also explained in Table 29. The interface tests can be inserted at various points along the data. See Figure 71 for more information on the test insertion points. Register 0x573, Bits[5:4], selects where these tests are inserted. Table 30, Table 31, and Table 32 show examples of some of the test modes when inserted at the JESD204B sample input, physical layer (PHY) 10-bit input, and scrambler 8-bit input. UP in Table 30 to Table 32 represents the user pattern control bits from the memory map register table (see Table 35). Data Link Layer Test Modes The data link layer test modes are implemented in the AD9691 as defined by Section 5.3.3.8.2 in the JEDEC JESD204B specification. These tests are shown in Register 0x574, Bits[2:0]. Test patterns inserted at this point are useful for verifying the functionality of the data link layer. When the data link layer test modes are enabled, disable SYNCINB± by writing 0xC0 to Register 0x572. Table 28. ADC Test Modes Output Test Mode Bit Sequence 0000 0001 0010 0011 0100 1000 Pattern Name Off (default) Midscale short +Full-scale short −Full-scale short Alternating checkerboard PN sequence, long PN sequence, short One-/zero word toggle User input 1111 Ramp output 0101 0110 0111 Expression Not applicable 00 0000 0000 0000 01 1111 1111 1111 10 0000 0000 0000 10 1010 1010 1010 Default/Seed Value Not applicable Not applicable Not applicable Not applicable Not applicable Sample (N, N + 1, N + 2, …) Not applicable Not applicable Not applicable Not applicable 0x1555, 0x2AAA, 0x1555, 0x2AAA, 0x1555 x23 + x18 + 1 x 9 + x5 + 1 11 1111 1111 1111 0x3AFF 0x0092 Not applicable 0x3FD7, 0x0002, 0x26E0, 0x0A3D, 0x1CA6 0x125B, 0x3C9A, 0x2660, 0x0c65, 0x0697 0x0000, 0x3FFF, 0x0000, 0x3FFF, 0x0000 Register 0x551 to Register 0x558 Not applicable (x) % 214 Not applicable For repeat mode: User Pattern 1[15:2], User Pattern 2[15:2], User Pattern 3[15:2], User Pattern 4[15:2], User Pattern 1[15:2]… For single mode: User Pattern 1[15:2], User Pattern 2[15:2], User Pattern 3[15:2], User Pattern 4[15:2], 0x0000… (x) % 214, (x + 1) % 214, (x + 2) % 214, (x + 3) % 214 Rev. 0 | Page 54 of 72 Data Sheet AD9691 Table 29. JESD204B Interface Test Modes Output Test Mode Bit Sequence 0000 0001 0010 0011 0100 0101 0110 0111 1000 1110 1111 Pattern Name Off (default) Alternating checkerboard One-/zero-word toggle 31-bit PN sequence 23-bit PN sequence 15-bit PN sequence 9-bit PN sequence 7-bit PN sequence Ramp output Continuous/repeat user test Single user test Expression Not applicable 0x5555, 0xAAAA, 0x5555… 0x0000, 0xFFFF, 0x0000… x31 + x28 + 1 x23 + x18 + 1 x15 + x14 + 1 x9 + x5 + 1 x7 + x6 + 1 (x) % 216 Register 0x551 to Register 0x558 Register 0x551 to Register 0x558 Default Not applicable Not applicable Not applicable 0x0003AFFF 0x003AFF 0x03AF 0x092 0x07 Ramp size depends on test insertion point User Pattern 1 to User Pattern 4, then repeat User Pattern 1 to User Pattern 4, then zeros Table 30. JESD204B Sample Input for M = 2, S = 2, N΄ = 16 (Register 0x573, Bits[5:4] = 'b00) Frame No. 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 Converter No. 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Sample No. 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Alternating Checkerboard 0x5555 0x5555 0x5555 0x5555 0xAAAA 0xAAAA 0xAAAA 0xAAAA 0x5555 0x5555 0x5555 0x5555 0xAAAA 0xAAAA 0xAAAA 0xAAAA 0x5555 0x5555 0x5555 0x5555 One-/ZeroWord Toggle 0x0000 0x0000 0x0000 0x0000 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0x0000 0x0000 0x0000 0x0000 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0x0000 0x0000 0x0000 0x0000 Ramp (x) % 216 (x) % 216 (x) % 216 (x) % 216 (x + 1) % 216 (x + 1) % 216 (x + 1) % 216 (x + 1) % 216 (x + 2) % 216 (x + 2) % 216 (x + 2) % 216 (x + 2) % 216 (x + 3) % 216 (x + 3) % 216 (x + 3) % 216 (x + 3) % 216 (x + 4) % 216 (x + 4) % 216 (x + 4) % 216 (x + 4) % 216 PN9 0x496F 0x496F 0x496F 0x496F 0xC9A9 0xC9A9 0xC9A9 0xC9A9 0x980C 0x980C 0x980C 0x980C 0x651A 0x651A 0x651A 0x651A 0x5FD1 0x5FD1 0x5FD1 0x5FD1 User Repeat UP1[15:0] UP1[15:0] UP1[15:0] UP1[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP4[15:0] UP4[15:0] UP4[15:0] UP4[15:0] UP1[15:0] UP1[15:0] UP1[15:0] UP1[15:0] User Single UP1[15:0] UP1[15:0] UP1[15:0] UP1[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP4[15:0] UP4[15:0] UP4[15:0] UP4[15:0] 0x0000 0x0000 0x0000 0x0000 User Repeat UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] User Single UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] 0x000 0x000 0x000 0x000 0x000 0x000 0x000 0x000 PN23 0xFF5C 0xFF5C 0xFF5C 0xFF5C 0x0029 0x0029 0x0029 0x0029 0xB80A 0xB80A 0xB80A 0xB80A 0x3D72 0x3D72 0x3D72 0x3D72 0x9B26 0x9B26 0x9B26 0x9B26 Table 31. Physical Layer 10-Bit Input (Register 0x573, Bits[5:4] = 'b01) 10-Bit Symbol No. 0 1 2 3 4 5 6 7 8 9 10 11 Alternating Checkerboard 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA One-/Zero- Word Toggle 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF Ramp (x) % 210 (x + 1) % 210 (x + 2) % 210 (x + 3) % 210 (x + 4) % 210 (x + 5) % 210 (x + 6) % 210 (x + 7) % 210 (x + 8) % 210 (x + 9) % 210 (x + 10) % 210 (x + 11) % 210 Rev. 0 | Page 55 of 72 PN9 0x125 0x2FC 0x26A 0x198 0x031 0x251 0x297 0x3D1 0x18E 0x2CB 0x0F1 0x3DD PN23 0x3FD 0x1C0 0x00A 0x1B8 0x028 0x3D7 0x0A6 0x326 0x10F 0x3FD 0x31E 0x008 AD9691 Data Sheet Table 32. Scrambler 8-Bit Input (Register 0x573, Bits[5:4] = 'b10) 8-Bit Octet No. 0 1 2 3 4 5 6 7 8 9 10 11 Alternating Checkerboard 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA One-/Zero- Word Toggle 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF Ramp (x) % 28 (x + 1) % 28 (x + 2) % 28 (x + 3) % 28 (x + 4) % 28 (x + 5) % 28 (x + 6) % 28 (x + 7) % 28 (x + 8) % 28 (x + 9) % 28 (x + 10) % 28 (x + 11) % 28 Rev. 0 | Page 56 of 72 PN9 0x49 0x6F 0xC9 0xA9 0x98 0x0C 0x65 0x1A 0x5F 0xD1 0x63 0xAC PN23 0xFF 0x5C 0x00 0x29 0xB8 0x0A 0x3D 0x72 0x9B 0x26 0x43 0xFF User Repeat UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] User Single UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Data Sheet AD9691 SERIAL PORT INTERFACE The AD9691 SPI allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields. These fields are documented in the Memory Map section. For detailed operational information, see the Serial Control Interface Standard (Rev. 1.0). CONFIGURATION USING THE SPI Three pins define the SPI of this ADC: the SCLK pin, the SDIO pin, and the CSB pin (see Table 33). The SCLK (serial clock) pin synchronizes the read and write data presented from/to the ADC. The SDIO (serial data input/output) pin is a dual-purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB (chip select bar) pin is an active low control that enables or disables the read and write cycles. Table 33. Serial Port Interface Pins Pin SCLK SDIO CSB Function Serial clock. The serial shift clock input that synchronizes serial interface reads and writes. Serial data input/output. A dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip select bar. An active low control that gates the read and write cycles. The falling edge of CSB, in conjunction with the rising edge of SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 3 and Table 5. Other modes involving the CSB pin are available. The CSB pin can be held low indefinitely, which permanently enables the device; this is called streaming. The CSB pin can stall high between bytes to allow additional external timing. When CSB is tied high, SPI functions are placed in a high impedance mode. This mode turns on any SPI pin secondary functions. In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the SDIO pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB first mode or in LSB first mode. MSB first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the Serial Control Interface Standard (Rev. 1.0). HARDWARE INTERFACE The pins described in Table 33 compose the physical interface between the user programming device and the serial port of the AD9691. The SCLK pin and the CSB pin function as inputs when using the SPI. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. Do not activate the SPI port during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9691 to prevent these signals from transitioning at the converter inputs during critical sampling periods. SPI ACCESSIBLE FEATURES Table 34 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the Serial Control Interface Standard (Rev. 1.0). The AD9691 device specific features are described in the Memory Map section. All data is composed of 8-bit words. The first bit of each individual byte of serial data indicates whether a read or write command is issued. This allows the SDIO pin to change direction from an input to an output. Table 34. Features Accessible Using the SPI Feature Name Mode Clock DDC Test Input/Output Output Mode SERDES Output Setup Description Allows the user to set either power-down mode or standby mode. Allows the user to access the clock divider via the SPI. Allows the user to set up decimation filters for different applications. Allows the user to set test modes to have known data on output bits. Allows the user to set up outputs. Allows the user to vary SERDES settings such as swing and emphasis. Rev. 0 | Page 57 of 72 AD9691 Data Sheet MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Logic Levels Each row in the memory map register table has eight bit locations. The memory map is divided into four sections: the Analog Devices SPI registers (Register 0x000 to Register 0x00D), the ADC function registers (Register 0x015 to Register 0x27A), The DDC function registers (Register 0x300 to Register 0x387), and the digital outputs and test modes registers (Register 0x550 to Register 0x5C5). An explanation of logic level terminology follows: Table 35 (see the Memory Map section) documents the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x561, the output mode register, has a hexadecimal default value of 0x01. This means that Bit 0 = 1, and the remaining bits are 0s. This setting is the default output format value, which is twos complement. For more information on this function and others, see Table 35. Unassigned and Reserved Locations All address and bit locations that are not included in Table 35 are not currently supported for this device. Write unused bits of a valid address location with 0s unless the default value is set otherwise. Writing to these locations is required only when part of an address location is unassigned (for example, Address 0x561). If the entire address location is unassigned (for example, Address 0x013), do not write to this address location. Default Values After the AD9691 is reset, critical registers are loaded with default values. The default values for the registers are given in Table 35. • • • “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” X denotes a don’t care bit. Channel-Specific Registers Some channel setup functions, such as input termination (Register 0x016), can be programmed to a different value for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in Table 35 as local. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x008. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, set only Channel A or Channel B to read one of the two registers. If both bits are set during an SPI read cycle, the device returns the value for Channel A. Registers and bits designated as global in Table 35 affect the entire device and the channel features for which independent settings are not allowed between channels. The settings in Register 0x004 and Register 0x005 do not affect the global registers and bits. SPI Soft Reset After issuing a soft reset by programming 0x81 to Register 0x000, the AD9691 requires 5 ms to recover. When programming the AD9691 for application setup, ensure that an adequate delay is programmed into the firmware after asserting the soft reset and before starting the device setup. Rev. 0 | Page 58 of 72 Data Sheet AD9691 MEMORY MAP REGISTER TABLE All address locations that are not included in Table 35 are not currently supported for this device and must not be written. Table 35. Memory Map Registers Reg Addr Register Bit 7 (Hex) Name (MSB) Analog Devices SPI Registers INTERFACE_ Soft reset 0x000 CONFIG_A (self clearing) INTERFACE_ Single 0x001 CONFIG_B instruction Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 LSB first 0 = MSB 1 = LSB 0 Address ascensio n 0 0 0 Address ascension 0 0 Bit 1 Bit 0 (LSB) Default Notes DEVICE_ CONFIG (local) 0 0 0 0 0 CHIP_TYPE CHIP_ID (low byte) CHIP_ID (high 0x005 byte) 0x006 CHIP_GRADE 0x008 Device index 0x00A Scratch pad 0x00B SPI revision 0x00C Vendor ID (low byte) 0x00D Vendor ID (high byte) ADC Function Registers Analog input 0x015 (local) 0 1 0 1 0 0 0 1 0 Soft reset LSB first (self 0 = MSB clearing) 1 = LSB Datapath 0 0 soft reset (self clearing) 00 = normal operation 0 10 = standby 11 = power-down 011 = high speed ADC 0 0 1 0 0 0 0 0 0 0 0 0x00 Read only 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 X 0 0 0 0 X 0 0 0 1 X Channel B 0 0 1 X Channel A 0 1 0 0xAX 0x03 0x00 0x01 0x56 Read only 0 0 0 0 0 1 0 0 0x04 Read only 0 0 0 0 0 0 0 0x00 0 0 1 Input disable 0 = normal operation 1 = input disabled 1 0 0 0 0 0x30 0 Low frequency operation 0 = off 1 = on (default) 0 0 0 0x04 0 1.0 V reference select 0 = internal 1 = external 0x00 0x002 0x003 0x004 0x016 Input termination (local) 0x018 Input buffer current control (local) 0x935 Buffer Control 2 0 0x024 V_1P0 control 0 Analog input differential termination 0000 = 400 Ω (default) 0001 = 200 Ω 0010 = 100 Ω 0110 = 50 Ω 0000 = 1.0× buffer current 0001 = 1.5× buffer current 0010 = 2.0× buffer current 0011 = 2.5× buffer current (default) 0100 = 3.0× buffer current 0101 = 3.5× buffer current … 1111 = 8.5× buffer current 0 0 0 0 0 0 0 Rev. 0 | Page 59 of 72 0x00 0x03 0xD1 Read only Read only 0x00 0x00 0x03 Read only AD9691 Reg Addr (Hex) 0x028 Data Sheet Register Name Temperature diode (local) Bit 7 (MSB) 0 0x03F PDWN/ STBY pin control (local) 0x040 Chip pin control 0= 0 PDWN/ STBY enabled 1= disabled PDWN/STBY function 00 = power down 01 = standby 10 = disabled 0x10B Clock divider 0 0x10C Clock divider phase (local) 0x10D Clock divider and SYSREF± control 0x117 Clock delay control 0x118 Clock fine delay (local) 0x11C Clock status Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 0 0 0 0 Bit 1 0 0 Bit 0 (LSB) Diode selection 0 = no diode selected 1= temperature diode selected 0 Default 0x00 Notes Used in conjunction with Reg. 0x040 0x00 Used in conjunction with Reg. 0x040 0 0 0 0 0x00 Clock divider auto phase adjust 0= disabled 1= enabled 0 0 0 0 0 0 0 Fast Detect A (FD_A) 000 = Fast Detect A output 001 = JESD204B LMFC output 010 = JESD204B internal SYNC~ output 011 = temperature diode 111 = disabled 000 = divide by 1 001 = divide by 2 011 = divide by 4 111 = divide by 8 Independently controls Channel A and Channel B clock divider phase offset 0000 = 0 input clock cycles delayed 0001 = ½ input clock cycles delayed 0010 = 1 input clock cycles delayed 0011 = 1½ input clock cycles delayed 0100 = 2 input clock cycles delayed 0101 = 2½ input clock cycles delayed … 1111 = 7½ input clock cycles delayed Clock divider negative Clock divider positive skew window skew window 00 = no negative skew 00 = no positive skew 01 = 1 device clock of 01 = 1 device clock of negative skew positive skew 10 = 2 device clocks of 10 = 2 device clocks of negative skew positive skew 11 = 3 device clocks of 11 = 3 device clocks of negative skew positive skew Clock fine 0 0 0 delay adjust enable 0 = disabled 1 = enabled 0x3F 0 Fast Detect B (FD_B) 000 = Fast Detect B output 001 = JESD204B LMFC output 010 = JESD204B internal SYNC~ output 111 = disabled 0 0 0 Clock fine delay adjust, Bits[7:0], twos complement coded control to adjust the fine sample clock skew in 1.7 ps steps ≤ −88 = −151.7 ps skew −87 = −150 ps skew … 0 = 0 ps skew … ≥ +87 = +150 ps skew 0 = no input 0 0 0 0 0 0 clock detected 1 = input clock detected 0x00 0 Rev. 0 | Page 60 of 72 0x00 0x00 Clock divider must be >1 0x00 Enabling the clock fine delay adjust causes a datapath reset Used in conjunction with Reg. 0x117 Read only Data Sheet Reg Addr (Hex) 0x120 AD9691 Register Name SYSREF± Control 1 Bit 7 (MSB) 0 0x121 SYSREF± Control 2 0 0x123 SYSREF± timestamp delay control 0 0x128 SYSREF± Status 1 SYSREF± and clock divider status 0x129 0x12A 0x1FF SYSREF± counter Chip sync mode 0 Bit 6 SYSREF± flag reset 0= normal operation 1 = flags held in reset 0 0 Clock divider phase when SYSREF± was captured 0000 = in-phase 0001 = SYSREF± is ½ cycle delayed from clock 0010 = SYSREF± is 1 cycle delayed from clock 0011 = 1½ input clock cycles delayed 0100 = 2 input clock cycles delayed 0101 = 2½ input clock cycles delayed … 1111 = 7½ input clock cycles delayed SYSREF± counter, Bits[7:0] increments when a SYSREF± signal is captured 0 0 0 0 Chip Q ignore 0= normal (I/Q) 1= ignore (I only) 0 0 0 0 Chip decimation ratio Customer offset Fast detect (FD) control (local) 0 0 0 0 Bit 0 (LSB) 0 0 0 0x201 0x248 0 0 0 FD upper threshold LSB (local) FD upper threshold MSB (local) Bit 2 Bit 1 SYSREF± mode select 00 = disabled 01 = continuous 10 = N-shot 0 0 0x247 Bit 3 CLK± edge select 0 = rising 1= falling 0 Chip application mode 0x245 Bit 4 SYSREF± transition select 0 = low to high 1 = high to low SYSREF± N-shot ignore counter select 0000 = next SYSREF± only 0001 = ignore the first SYSREF± transitions 0010 = ignore the first two SYSREF± transitions … 1111 = ignore the first 16 SYSREF± transitions SYSREF± timestamp delay, Bits[6:0] 0x00 = no delay 0x01 = 1 clock delay … 0x7F = 127 clocks delay SYSREF± hold status, see Table 27 SYSREF± setup status, see Table 27 0x200 0x228 Bit 5 0 0 0 Synchronization mode 00 = normal 01 = timestamp Chip operating mode 00 = full bandwidth mode 01 = DDC 0 on 10 = DDC 0 and DDC 1 Chip decimation ratio select 000 = full sample rate (decimate = 1) 001 = decimate by 2 Offset adjust in LSBs from +127 to −128 (twos complement format) 0 0 0 0 Force value of FD_A/ FD_B pins if force pins is true, this value is output on FD pins Fast detect upper threshold, Bits[7:0] 0 Force FD_A/ FD_B pins 0= normal function 1 = force to value 0 Fast detect upper threshold, Bits[12:8] Rev. 0 | Page 61 of 72 Enable fast detect output Default 0x00 Notes 0x00 Mode select, Reg. 0x120, Bits[2:1], must be N-shot Ignored when Reg. 0x1FF = 0x00 0x00 Read only Read only Read only 0x00 0x00 0x00 0x00 0x00 0x00 0x00 AD9691 Reg Addr (Hex) 0x249 Data Sheet Register Name FD lower threshold LSB (local) FD lower threshold MSB (local) FD dwell time LSB (local) FD dwell time MSB (local) Signal monitor synchronizatio n control Bit 7 (MSB) Bit 6 Bit 5 0 0 0 0 0 0 0 0 0 0x270 Signal monitor control (local) 0 0 0 0 0 0 0x271 Signal Monitor Period Register 0 (local) Signal Monitor Period Register 1 (local) Signal Monitor Period Register 2 (local) Signal monitor result control (local) 0x24A 0x24B 0x24C 0x26F 0x272 0x273 0x274 0x275 0x276 Signal Monitor Result Register 0 (local) Signal Monitor Result Register 1 (local) 0x277 Signal Monitor Result Register 1 (local) 0x278 Signal monitor period counter result (local) 0x279 Signal monitor SPORT over JESD204B control (local) SPORT over JESD204B input selection (local) 0x27A 0 0 Bit 4 Bit 3 Bit 2 Fast detect lower threshold, Bits[7:0] Bit 1 Bit 0 (LSB) Fast detect lower threshold, Bits[12:8] 0 Fast detect dwell time, Bits[7:0] 0x00 Fast detect dwell time, Bits[15:8] 0x00 Synchronization mode 00 = disabled 01 = continuous 11 = one-shot 0 Peak detector 0= disabled 1= enabled 0x00 0x80 Signal monitor period, Bits[15:8] 0x00 Signal monitor period, Bits[23:16] 0x00 Read only Read only 0 Read only Period count result, Bits[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 Rev. 0 | Page 62 of 72 Read only 00 = reserved 11 = enable 0x00 0 0x00 Peak detector 0= disabled 1= enabled In decimated output clock cycles In decimated output clock cycles In decimated output clock cycles 0x01 Signal monitor result, Bits[15:8] Signal monitor result, Bits[19:16] See the Signal Monitor section 0x00 Signal monitor period, Bits[7:0] 0 0 Notes 0x00 0 0 0 Result Result selection update 0 = reserved 1 = update 1 = peak results (self detector clear) Signal monitor result, Bits[7:0] When Register 0x274, Bit 0 = 1, result Bits[19:7] = peak detector absolute value, Bits[12:0]; result Bits[6:0] = 0 0 Default 0x00 Updated based on Reg. 0x274, Bit 4 Updated based on Reg. 0x274, Bit 4 Updated based on Reg. 0x274, Bit 4 Updated based on Reg. 0x274, Bit 4 Data Sheet AD9691 Reg Addr Register Bit 7 (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 DDC Function Registers (See the Digital Downconverters (DDCs) Section) DDC sync DDC NCO 0x300 0 0 0 control soft reset 0 = normal operation 1 = reset IF (intermediate Gain 0x310 DDC 0 control Mixer frequency) mode select select 00 = variable IF mode 0 = 0 dB 0 = real (mixers and NCO gain mixer enabled) 1 = 6 dB 1= 01 = 0 Hz IF mode gain complex (mixer bypassed, NCO mixer disabled) 10 = fS/4 Hz IF mode (fS/4 downmixing mode) 11 = test mode (mixer inputs forced to +FS, NCO enabled) DDC 0 input 0x311 0 0 0 0 selection 0x314 0x315 0x320 0x321 0x327 DDC 0 frequency LSB DDC 0 frequency MSB DDC 0 phase LSB DDC 0 phase MSB DDC 0 output test mode selection Bit 2 0 0 Complex to real enable 0= disabled 1= enabled 0 Q input select 0 = Ch. A 1 = Ch. B DDC 0 NCO FTW, Bits[7:0], twos complement X X X 0 X Bit 1 Bit 0 (LSB) Synchronization mode (triggered by SYSREF±) 00 = disabled 01 = continuous 11 = one-shot Decimation rate select (complex to real disabled) 11 = decimate by 2 00 = decimate by 4 01 = decimate by 8 10 = decimate by 16 (complex to real enabled) 11 = decimate by 1 00 = decimate by 2 01 = decimate by 4 10 = decimate by 8 0 I input select 0 = Ch. A 1 = Ch. B DDC 0 NCO FTW, Bits[11:8], twos complement X X X X 0 0 0 0 IF (intermediate frequency) mode 00 = variable IF mode (mixers and NCO enabled) 01 = 0 Hz IF mode (mixer bypassed, NCO disabled) 10 = fS/4 Hz IF mode (fS/4 downmixing mode) 11 = test mode (mixer inputs forced to +FS, NCO enabled) 0 0 DDC 1 control Mixer select 0 = real mixer 1= complex mixer Gain select 0 = 0 dB gain 1 = 6 dB gain 0x331 DDC 1 input selection 0 0 0x334 DDC 1 frequency LSB DDC 1 frequency MSB X X X Q output test mode enable 0= disabled 1= enabled from Channel B 0 0 Q input select 0 = Ch. A 1 = Ch. B DDC 1 NCO FTW, Bits[7:0], twos complement 0 X Complex to real enable 0= disabled 1= enabled 0 0x00 0x00 0x00 I output test mode enable 0 = disabled 1 = enabled from Channel A 0x00 Decimation rate select (complex to real disabled) 11 = decimate by 2 00 = decimate by 4 01 = decimate by 8 10 = decimate by 16 (complex to real enabled) 11 = decimate by 1 00 = decimate by 2 01 = decimate by 4 10 = decimate by 8 0x00 I input select 0 = Ch. A 1 = Ch. B 0x00 DDC 1 NCO FTW, Bits[11:8], twos complement Rev. 0 | Page 63 of 72 0x00 0x00 DDC 0 NCO POW, Bits[11:8], twos complement 0 Default 0x00 DDC 0 NCO POW, Bits[7:0], twos complement 0x330 0x335 Bit 3 0x00 0x00 Notes AD9691 Reg Addr (Hex) 0x340 Data Sheet Register Name DDC 1 phase LSB DDC 1 phase MSB DDC 1 output test mode selection Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 DDC 1 NCO POW, Bits[7:0], twos complement X X X X 0 0 0 0 0x350 DDC 2 control Mixer select 0 = real mixer 1= complex mixer Gain select 0 = 0 dB gain 1 = 6 dB gain 0x351 DDC 2 input selection 0 0 IF (intermediate frequency) mode 00 = variable IF mode (mixers and NCO enabled) 01 = 0 Hz IF mode (mixer bypassed, NCO disabled) 10 = fS/4 Hz IF mode (fS/4 downmixing mode) 11 = test mode (mixer inputs forced to +FS, NCO enabled) 0 0 0x354 DDC 2 frequency LSB DDC 2 frequency MSB DDC 2 phase LSB DDC 2 phase MSB DDC 2 output test mode selection 0x341 0x347 0x355 0x360 0x361 0x367 X X X Bit 1 Bit 0 (LSB) DDC 1 NCO POW, Bits[11:8], twos complement 0x00 Q output test mode enable 0= disabled 1= enabled from Channel B 0 0 I output test mode enable 0 = disabled 1 = enabled from Channel A 0x00 Decimation rate select (complex to real disabled) 11 = decimate by 2 00 = decimate by 4 01 = decimate by 8 10 = decimate by 16 (complex to real enabled) 11 = decimate by 1 00 = decimate by 2 01 = decimate by 4 10 = decimate by 8 0x00 Q input select 0 = Ch. A 1 = Ch. B DDC 2 NCO FTW, Bits[7:0], twos complement 0 0x00 0 Complex to real enable 0= disabled 1= enabled 0 X I input select 0 = Ch. A 1 = Ch. B 0x00 DDC 2 NCO FTW, Bits[11:8], twos complement DDC 2 NCO POW, Bits[7:0], twos complement X X X X 0 0 0 0 IF (intermediate frequency) mode 00 = variable IF mode (mixers and NCO enabled) 01 = 0 Hz IF mode (mixer bypassed, NCO disabled) 10 = fS/4 Hz IF mode (fS/4 downmixing mode) 11 = test mode (mixer inputs forced to +FS, NCO enabled) 0 0 0x370 DDC 3 control Mixer select 0 = real mixer 1= complex mixer Gain select 0 = 0 dB gain 1 = 6 dB gain 0x371 DDC 3 input selection 0 0 Default 0x00 0x00 0x00 DDC 2 NCO POW, Bits[11:8], twos complement 0x00 Q output test mode enable 0= disabled 1= enabled from Channel B 0 0 I output test mode enable 0 = disabled 1 = enabled from Channel A 0x00 Decimation rate select (complex to real disabled) 11 = decimate by 2 00 = decimate by 4 01 = decimate by 8 10 = decimate by 16 (complex to real enabled) 11 = decimate by 1 00 = decimate by 2 01 = decimate by 4 10 = decimate by 8 0x00 Q input select 0 = Ch. A 1 = Ch. B 0 0x00 0 Complex to real enable 0= disabled 1= enabled 0 Rev. 0 | Page 64 of 72 I input select 0 = Ch. A 1 = Ch. B Notes Data Sheet Reg Addr (Hex) 0x374 0x375 0x380 0x381 0x387 Register Name DDC 3 frequency LSB DDC 3 frequency MSB DDC3 phase LSB DDC 3 phase MSB DDC 3 output test mode selection AD9691 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 DDC 3 NCO FTW, Bits[7:0], twos complement X X X X Bit 1 Bit 0 (LSB) DDC 3 NCO FTW, Bits[11:8], twos complement DDC 3 NCO POW, Bits[7:0], twos complement Default 0x00 0x00 0x00 X X X X 0 0 0 0 0 I output test mode enable 0 = disabled 1 = enabled from Channel A 0x00 0 Reset PN long gen 0 = long PN enable 1 = long PN reset Reset PN short gen 0 = short PN enable 1 = short PN reset 0x00 Digital Outputs and Test Modes User ADC test 0x550 pattern modes selection (local) 0= continuous repeat 1 = single pattern DDC 3 NCO POW, Bits[11:8], twos complement 0 0 0x00 0x551 User Pattern 1 LSB 0 0 0 0 Test mode selection 0000 = off, normal operation 0001 = midscale short 0010 = positive full scale 0011 = negative full scale 0100 = alternating checker board 0101 = PN sequence, long 0110 = PN sequence, short 0111 = 1/0 word toggle 1000 = the user pattern test mode (used with Register 0x550, Bit 7 and User Pattern 1 through User Pattern 4 registers), 1111 = ramp output 0 0 0 0 0x552 User Pattern 1 MSB 0 0 0 0 0 0 0 0 0x00 0x553 User Pattern 2 LSB 0 0 0 0 0 0 0 0 0x00 0x554 User Pattern 2 MSB 0 0 0 0 0 0 0 0 0x00 0x555 User Pattern 3 LSB 0 0 0 0 0 0 0 0 0x00 0x556 User Pattern 3 MSB 0 0 0 0 0 0 0 0 0x00 0x557 User Pattern 4 LSB 0 0 0 0 0 0 0 0 0x00 0x558 User Pattern 4 MSB 0 0 0 0 0 0 0 0 0x00 Rev. 0 | Page 65 of 72 Notes 0x00 Used with Reg. 0x550 and Reg. 0x573 Used with Reg. 0x550 and Reg. 0x573 Used with Reg. 0x550 and Reg. 0x573 Used with Reg. 0x550 and Reg. 0x573 Used with Reg. 0x550 and Reg. 0x573 Used with Reg. 0x550 and Reg. 0x573 Used with Reg. 0x550 and Reg. 0x573 Used with Reg. 0x550 and Reg. 0x573 AD9691 Reg Addr (Hex) 0x559 Data Sheet Register Name Output Mode Control 1 Bit 7 (MSB) 0 0x55A Output Mode Control 2 0x561 Bit 3 0 0 Bit 6 Bit 5 Bit 4 Converter control Bit 1 selection 000 = tie low (1’b0) 001 = overrange bit 010 = signal monitor bit 011 = fast detect (FD) bit 101 = SYSREF± Only used when CS (Register 0x58F) = 2 or 3 0 0 0 Output mode 0 0 0 0 0 0x562 Output overrange (OR) clear Virtual Converter 7 OR 0 = OR bit enabled 1 = OR bit cleared Virtual Converter 6 OR 0 = OR bit enabled 1 = OR bit cleared Virtual Converter 4 OR 0 = OR bit enabled 1 = OR bit cleared 0x563 Output OR status Virtual Converter 7 OR 0 = no OR 1 = OR occured Virtual Converter 3 OR 0 = OR bit enabled 1 = OR bit cleared Virtual Converter 3 OR 0 = no OR 1 = OR occured 0x564 Output channel select 0 Virtual Converter 6 OR 0 = no OR 1 = OR occured 0 Virtual Converter 5 OR 0 = OR bit enabled 1 = OR bit cleared Virtual Converter 5 OR 0 = no OR 1 = OR occured 0 0x56E JESD204B lane rate control 0 0 0 0x570 JESD204B quick configuration Virtual Converter 4 OR 0 = no OR 1 = OR occured 0 0 0 Bit 2 Bit 1 Bit 0 (LSB) Converter control Bit 0 selection 000 = tie low (1’b0) 001 = overrange bit 010 = signal monitor bit 011 = fast detect (FD) bit 101 = SYSREF± Only used when CS (Register 0x58F) = 3 Converter control Bit 2 selection 000 = tie low (1’b0) 001 = overrange bit 010 = signal monitor bit 011 = fast detect (FD) bit 101 = SYSREF± Used when CS (Register 0x58F) = 1, 2, or 3 Data format select Sample 00 = offset binary invert 01 = twos complement 0= normal 1= sample invert Virtual Virtual Virtual ConCon-verter Converter 0 OR 2 OR verter 1 0 = OR bit 0 = OR bit OR enabled enabled 0 = OR bit 1 = OR bit 1 = OR bit enabled cleared cleared 1 = OR bit cleared 0x01 0x00 Virtual Converter 1 OR 0 = no OR 1 = OR occured Virtual Converter 0 OR 0 = no OR 1 = OR occured 0x00 0 0 Converter channel swap 0 = normal channel ordering 1 = channel swap enabled 0 0x00 0 Notes 0x00 Virtual Con-verter 2 OR 0 = no OR 1 = OR occured 0 = serial 0 0 lane rate > 6.25 Gbps and ≤12.5 Gbps 1 = serial lane rate must be > 3.125 Gbps and ≤ 6.25 Gbps JESD204B quick configuration L = number of lanes = 2Register 0x570, Bits[7:6] M = number of converters = 2Register 0x570, Bits[5:3] F = number of octets/frame = 2 Register 0x570, Bits[2:0] Rev. 0 | Page 66 of 72 Default 0x00 Read only 0x10 0x88 See Table 25 and Table 26 Data Sheet Reg Addr (Hex) 0x571 AD9691 Register Name JESD204B Link Mode Control 1 Bit 7 (MSB) Standby mode 0 = all converter outputs 0 1 = CGS (/K28.5/) 0x572 JESD204B Link Mode Control 2 SYNCINB± pin control 00 = normal 10 = ignore SYNCINB± (force CGS) 11 = ignore SYNCINB± (force ILAS/user data) 0x573 JESD204B Link Mode Control 3 CHKSUM mode 00 = sum of all 8-bit link config registers 01 = sum of individual link config fields 10 = checksum set to zero 0x574 JESD204B Link Mode Control 4 0x578 JESD204B LMFC offset JESD204B DID config JESD204B BID config JESD204B LID Config 1 JESD204B LID Config 2 JESD204B LID Config 3 JESD204B LID Config 4 JESD204B LID Config 5 JESD204B LID Config 6 JESD204B LID Config 7 JESD204B LID Config 8 ILAS delay 0000 = transmit ILAS on first LMFC after SYNCINB± deasserted 0001 = transmit ILAS on second LMFC after SYNCINB± deasserted … 1111 = transmit ILAS on 16th LMFC after SYNCINB± deasserted 0 0 0 0x580 0x581 0x583 0x584 0x585 0x586 0x587 0x588 0x589 0x58A Bit 6 Tail bit (t) PN 0= disable 1= enable T = N΄ − N − CS Bit 5 Long transpor t layer test 0= disable 1= enable Bit 4 Lane synchronization 0 = disable FACI uses /K28.7/ 1 = enable FACI uses /K28.3/ and /K28.7/ SYNCINB± pin type 0= differential 1 = CMOS SYNCINB± pin invert 0= active low 1= active high Test injection point 00 = N΄ sample input 01 = 10-bit data at 8B/10B output (for PHY testing) 10 = 8-bit data at scrambler input Bit 3 Bit 2 ILAS sequence mode 00 = ILAS disabled 01 = ILAS enabled 11 = ILAS always on test mode 8B/10B bypass 0= normal 1 = bypass 0 Bit 1 FACI 0= enabled 1= disabled 8B/10B bit invert 0= normal 1 = invert the a to j symbols Bit 0 (LSB) Link control 0 = active 1 = power down Default 0x14 0 0x00 JESD204B test mode patterns 0000 = normal operation (test mode disabled) 0001 = alternating checker board 0010 = 1/0 word toggle 0011 = 31-bit PN sequence—x31 + x28 + 1 0100 = 23-bit PN sequence—x23 + x18 + 1 0101 = 15-bit PN sequence—x15 + x14 + 1 0110 = 9-bit PN sequence—x9 + x5 + 1 0111 = 7-bit PN sequence—x7 + x6 + 1 1000 = ramp output 1110 = continuous/repeat user test 1111 = single user test Link layer test mode 0 000 = normal operation (link layer test mode disabled) 001 = continuous sequence of /D21.5/ characters 100 = modified RPAT test sequence 101 = JSPAT test sequence 110 = JTSPAT test sequence LMFC phase offset value, Bits[4:0] JESD204B Tx device ID (DID) value, Bits[7:0] 0 JESD204B Tx bank ID (BID) value, Bits[3:0] 0x00 0x00 0x00 0x00 0 0 0 0 0 0 Lane 0 lane ID (LID) value, Bits[4:0] 0x00 0 0 0 Lane 1 LID value, Bits[4:0] 0x01 0 0 0 Lane 2 LID value, Bits[4:0] 0x02 0 0 0 Lane 3 LID value, Bits[4:0] 0x03 0 0 0 Lane 4 LID value, Bits[4:0] 0x04 0 0 0 Lane 5 LID value, Bits[4:0] 0x05 0 0 0 Lane 6 LID value, Bits[4:0] 0x06 0 0 0 Lane 7 LID value, Bits[4:0] 0x07 Rev. 0 | Page 67 of 72 0x00 Notes AD9691 Reg Addr (Hex) 0x58B Register Name JESD204B parameters SCR/L 0x58C JESD204B F config 0x58D JESD204B K config JESD204B M config 0x58E 0x58F JESD204B CS/N config 0x590 JESD204B N’ config 0x591 JESD204B S config JESD204B HD and CF configuration 0x592 0x5A0 0x5A1 0x5A2 0x5A3 0x5A4 0x5A5 0x5A6 0x5A7 0x5B0 JESD204B CHKSUM 0 JESD204B CHKSUM 1 JESD204B CHKSUM 2 JESD204B CHKSUM 3 JESD204B CHKSUM 4 JESD204B CHKSUM 5 JESD204B CHKSUM 6 JESD204B CHKSUM 7 JESD204B lane power-down Data Sheet Bit 7 (MSB) JESD204B scrambling (SCR) 0= disabled 1= enabled Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 Bit 1 Bit 0 (LSB) JESD204B lanes (L) 000 = 1 lane 001 = 2 lanes 011 = 4 lanes 111 = 7 lanes Read only, see Register 0x570 Number of octets per frame, F = Register 0x58C, Bits[7:0] + 1 Number of frames per multiframe, K = Register 0x58D, Bits[4:0] + 1 Only values where (F × K) mod 4 = 0 are supported Number of converters per link, Bits[7:0] 0x00 = link connected to one virtual converter (M = 1) 0x01 = link connected to two virtual converters (M = 2) 0x03 = link connected to four virtual converters (M = 4) 0x07 = link connected to eight virtual converters (M = 8) ADC converter resolution (N) Number of control bits 0 0x06 = 7-bit resolution (CS) per sample 0x07 = 8-bit resolution 00 = no control bits 0x08 = 9-bit resolution (CS = 0) 0x09 = 10-bit resolution 01 = 1 control bit (CS = 0x0A = 11-bit resolution 1); Control Bit 2 only 0x0B = 14-bit resolution (default) 10 = 2 control bits (CS = 0x0C = 13-bit resolution 2); Control Bit 2 and 0x0D = 14-bit resolution Control Bit 1 only 0x0E = 15-bit resolution 11 = 3 control bits (CS = 0x0F = 16-bit resolution 3); all control bits (2, 1, 0) ADC number of bits per sample (N’) Subclass support (Subclass 0x7 = 8 bits version) 0xF = 16 bits 000 = Subclass 0 (no deterministic latency) 001 = Subclass 1 Samples per converter frame cycle (S) 0 0 1 S value = Register 0x591, Bits[4:0] +1 Control words per frame clock cycle per link (CF) HD value 0 0 CF value = Register 0x592, Bits[4:0] 0= disabled 1= enabled CHKSUM value for SERDOUT0±, Bits[7:0] 0 SERDOUT7± 0 = on 1 = off 0 SERDOUT6± 0 = on 1 = off 0 SERDOUT5± 0 = on 1 = off Default 0x8X Notes 0x88 Read only, see Reg. 0x570 See Reg. 0x570 Read only 0x1F 0x0B 0x2F Read only 0x80 Read only 0xC3 Read only CHKSUM value for SERDOUT1±, Bits[7:0] 0xC4 Read only CHKSUM value for SERDOUT2±, Bits[7:0] 0xC5 Read only CHKSUM value for SERDOUT3±, Bits[7:0] 0xC6 Read only CHKSUM value for SERDOUT4±, Bits[7:0] 0xC7 Read only CHKSUM value for SERDOUT5±, Bits[7:0] 0xC8 Read only CHKSUM value for SERDOUT6±, Bits[7:0] 0xC9 Read only CHKSUM value for SERDOUT7±, Bits[7:0] 0xCA Read only SERDOUT4± 0 = on 1 = off SERDOUT3± 0 = on 1 = off Rev. 0 | Page 68 of 72 SERDOUT2± 0 = on 1 = off SERDOUT1± 0 = on 1 = off SERDOUT0± 0 = on 1 = off 0xAA Data Sheet Reg Addr (Hex) 0x5B2 AD9691 Register Name JESD204B lane SERDOUT0±/ SERDOUT1± assign Bit 7 (MSB) 0 0x5B3 JESD204B lane SERDOUT2±/ SERDOUT3± assign 0 0x5B5 JESD204B lane SERDOUT4±/ SERDOUT5± assign 0 0x5B6 JESD204B lane SERDOUT6±/ SERDOUT7± assign 0 0x5BF JESD204B serializer drive adjust 0 0x5C1 De-emphasis select SERDOUT7± 0= disable 1 = enable 0x5C2 De-emphasis setting for SERDOUT0±/ SERDOUT1± 0 Bit 6 Bit 5 Bit 4 SERDOUT1± lane assignment 000 = Logical Lane 0 001 = Logical Lane 1 010 = Logical Lane 2 011 = Logical Lane 3 100 = Logical Lane 4 101 = Logival Lane 5 110 = Logical Lane 6 111 = Logical Lane 7 SERDOUT3± lane assignment 000 = Logical Lane 0 001 = Logical Lane 1 010 = Logical Lane 2 011 = Logical Lane 3 100 = Logical Lane 4 101 = Logival Lane 5 110 = Logical Lane 6 111 = Logical Lane 7 SERDOUT5± lane assignment 000 = Logical Lane 0 001 = Logical Lane 1 010 = Logical Lane 2 011 = Logical Lane 3 100 = Logical Lane 4 101 = Logival Lane 5 110 = Logical Lane 6 111 = Logical Lane 7 SERDOUT7± lane assignment 000 = Logical Lane 0 001 = Logical Lane 1 010 = Logical Lane 2 011 = Logical Lane 3 100 = Logical Lane 4 101 = Logival Lane 5 110 = Logical Lane 6 111 = Logical Lane 7 0 0 0 SERDOUT6± 0= disable 1= enable 0 SERDOUT5± 0= disable 1= enable 0 SERDOUT4 ± 0 = disable 1 = enable 0 Bit 3 0 0 0 0 Bit 2 Bit 1 Bit 0 (LSB) SERDOUT0± lane assignment 000 = Logical Lane 0 001 = Logical Lane 1 010 = Logical Lane 2 011 = Logical Lane 3 100 = Logical Lane 4 101 = Logival Lane 5 110 = Logical Lane 6 111 = Logical Lane 7 SERDOUT2± lane assignment 000 = Logical Lane 0 001 = Logical Lane 1 010 = Logical Lane 2 011 = Logical Lane 3 100 = Logical Lane 4 101 = Logival Lane 5 110 = Logical Lane 6 111 = Logical Lane 7 SERDOUT4± lane assignment 000 = Logical Lane 0 001 = Logical Lane 1 010 = Logical Lane 2 011 = Logical Lane 3 100 = Logical Lane 4 101 = Logival Lane 5 110 = Logical Lane 6 111 = Logical Lane 7 SERDOUT6± lane assignment 000 = Logical Lane 0 001 = Logical Lane 1 010 = Logical Lane 2 011 = Logical Lane 3 100 = Logical Lane 4 101 = Logival Lane 5 110 = Logical Lane 6 111 = Logical Lane 7 Swing voltage 0000 = 237.5 mV 0001 = 250 mV 0010 = 262.5 mV 0011 = 275 mV 0100 = 287.5 mV 0101 = 300 mV (default) 0110 = 312.5 mV 0111 = 325 mV 1000 = 337.5 mV 1001 = 350 mV 1010 = 362.5 mV 1011 = 375 mV 1100 = 387.5 mV 1101 = 400 mV 1110 = 412.5 mV 1111 = 425 mV SERDOUT0± SERDSERD0 = disable OUT1± OUT2± 1 = enable 0= 0= disable disable 1 = enable 1 = enable SERDOUT3± 0= disable 1= enable SERDOUT0±/SERDOUT1± de-emphasis settings 0000 = 0 dB 0001 = 0.3 dB 0010 = 0.8 dB 0011 = 1.4 dB 0100 = 2.2 dB 0101 = 3.0 dB 0110 = 4.0 dB 0111 = 5.0 dB Rev. 0 | Page 69 of 72 Default 0x10 0x32 0x54 0x76 0x05 0x00 0x00 Notes AD9691 Reg Addr (Hex) 0x5C3 Data Sheet Register Name De-emphasis setting for SERDOUT2±/ SERDOUT3± Bit 7 (MSB) 0 Bit 6 0 Bit 5 0 Bit 4 0 0x5C4 De-emphasis setting for SERDOUT4±/ SERDOUT5± 0 0 0 0 0x5C5 De-emphasis setting for SERDOUT6±/ SERDOUT7± 0 0 0 0 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) SERDOUT2±/SERDOUT3± de-emphasis settings 0000 = 0 dB 0001 = 0.3 dB 0010 = 0.8 dB 0011 = 1.4 dB 0100 = 2.2 dB 0101 = 3.0 dB 0110 = 4.0 dB 0111 = 5.0 dB SERDOUT4±/SERDOUT5± de-emphasis settings 0000 = 0 dB 0001 = 0.3 dB 0010 = 0.8 dB 0011 = 1.4 dB 0100 = 2.2 dB 0101 = 3.0 dB 0110 = 4.0 dB 0111 = 5.0 dB SERDOUT6±/SERDOUT7± de-emphasis settings 0000 = 0 dB 0001 = 0.3 dB 0010 = 0.8 dB 0011 = 1.4 dB 0100 = 2.2 dB 0101 = 3.0 dB 0110 = 4.0 dB 0111 = 5.0 dB Rev. 0 | Page 70 of 72 Default 0x00 0x00 0x00 Notes Data Sheet AD9691 APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS The AD9691 must be powered by the following seven supplies: AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, and SPIVDD = 1.8 V. For applications requiring an optimal high power efficiency and low noise performance, it is recommended that the ADP2164 and ADP2370 switching regulators be used to convert the 3.3 V, 5.0 V, or 12 V input rails to an intermediate rail (1.8 V and 3.8 V). These intermediate rails are then postregulated by very low noise, low dropout (LDO) regulators (ADP1741, ADP1740, and ADP125). Figure 83 shows the recommended power supply scheme for AD9691. ADP1741 2.5V: AVDD2 ADP125 1.8V: SPIVDD ADP1741 1.25V: AVDD1 LDO LDO ADP2164 BUCK REGULATOR 1.8V LDO ADP125 LDO 1.25V: DVDD ADP1740 1.25V: DRVDD LDO 5V/12V INPUT ADP2370 BUCK REGULATOR 3.8V 1.25V: AVDD1_SR ADP1741 LDO ADP125 LDO To maximize the coverage and adhesion between the ADC and PCB, partition the continuous copper plane by overlaying a silkscreen on the PCB into several uniform sections. This provides several tie points between the ADC and PCB during the reflow process, whereas using one continuous plane with no partitions only guarantees one tie point. See Figure 84 for a recommended PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). 13092-084 3.3V INPUT The copper plane must have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias must be solder filled or plugged. The number of vias and the fill determine the resultant θJA measured on the board. This is shown in Table 7. 3.3V: AVDD3 It is not necessary to split all of these power domains in all cases. The recommended solution shown in Figure 83 provides the lowest noise, highest efficiency power delivery system for the AD9691. If only one 1.25 V supply is available, route to AVDD1 first and then tap it off and isolate it with a ferrite bead or a filter choke, preceded by decoupling capacitors for AVDD1_SR, SPIVDD, DVDD, and DRVDD, in that order. The user can employ several different decoupling capacitors to cover both high and low frequencies. These must be located close to the point of entry at the PCB level and close to the devices, with minimal trace lengths. EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS It is required that the exposed pad on the underside of the ADC be connected to ground to achieve the best electrical and thermal performance of the AD9691. Connect an exposed continuous copper plane on the PCB to the AD9691 exposed pad, Pin 0. 13092-085 Figure 83. High Efficiency, Low Noise Power Solution for the AD9691 Figure 84. Recommended PCB Layout of Exposed Pad for the AD9691 AVDD1_SR (PIN 78) AND AGND (PIN 77 AND PIN 81) AVDD1_SR (Pin 78) and AGND (Pin 77 and Pin 81) can be used to provide a separate power supply node to the SYSREF± circuits of AD9691. If running in Subclass 1, the AD9691 can support periodic one-shot or gapped signals. To minimize the coupling of this supply into the AVDD1 supply node, adequate supply bypassing is needed. Rev. 0 | Page 71 of 72 AD9691 Data Sheet OUTLINE DIMENSIONS 12.10 12.00 SQ 11.90 0.60 MAX 0.30 0.23 0.18 0.60 MAX 88 67 66 1 PIN 1 INDICATOR PIN 1 INDICATOR 11.85 11.75 SQ 11.65 0.50 BSC 0.50 0.40 0.30 TOP VIEW 12° MAX 22 23 45 44 BOTTOM VIEW 10.50 REF 0.70 0.65 0.60 0.05 MAX 0.01 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-VRRD EXCEPT FOR MINIMUM THICKNESS AND LEAD COUNT. 07-02-2012-B *0.90 0.85 0.75 8.35 8.20 SQ 8.05 EXPOSED PAD Figure 85. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 12 mm × 12 mm Body, Very Thin Quad (CP-88-4) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD9691BCPZ-1250 AD9691BCPZRL7-1250 AD9691-1250EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board for AD9691-1250 Z = RoHS Compliant Part. ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13092-0-7/15(0) Rev. 0 | Page 72 of 72 Package Option CP-88-4 CP-88-4