ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com 16-Bit, Six-Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER Check for Samples: ADS8555 FEATURES DESCRIPTION • • The ADS8555 contains six low-power, 16-bit, successive approximation register (SAR)-based analog-to-digital converters (ADCs) with true bipolar inputs. Each channel contains a sample-and-hold circuit that allows simultaneous high-speed multi-channel signal acquisition. 1 2 • • • • • • • • Six SAR ADCs Grouped in Three Pairs Maximum Data Rate Per Channel with Internal Clock and Reference: 630kSPS (Parallel) or 450kSPS (Serial) Maximum Data Rate Per Channel with External Clock and Reference: 800kSPS (Parallel) or 500kSPS (Serial) Pin-Selectable or Programmable Input Voltage Ranges: Up to ±12V Excellent AC Performance: 91.5dB SNR, –94dB THD Programmable and Buffered Internal Reference: 0.5V to 2.5V and 0.5V to 3.0V Comprehensive Power-Down Modes: Deep Power-Down (Standby Mode) Auto-Nap Power-Down Selectable Parallel or Serial Interface Operating Temperature Range: –40°C to +125°C LQFP-64 Package APPLICATIONS • • • • • Power Quality Measurement Protection Relays Multi-Axis Motor Control Programmable Logic Controllers Industrial Data Acquisition The ADS8555 supports data rates of up to 630kSPS in parallel interface mode or up to 450kSPS if the serial interface is used. The bus width of the parallel interface can be set to eight or 16 bits. In serial mode, up to three output channels can be activated. The ADS8555 is specified over the extended industrial temperature range of –40°C to +125°C and is available in an LQFP-64 package. HVDD HVSS AVDD BVDD Clock Generator CH_A0 AGND SAR ADC CONVST_A Control Logic REFC_A CH_A1 AGND SAR ADC CH_B0 AGND BUSY/INT RANGE/XCLK HW/SW REFEN/WR STBY RESET SAR ADC CONVST_B Config Register REFC_B CH_B1 AGND SAR ADC CH_C0 AGND SAR ADC CONVST_C CS/FS RD DB[15:0] WORD/BYTE PAR/SER I/O REFC_C CH_C1 AGND SAR ADC String DAC REF_IO AGND 2.5V/3V REF BGND 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. © 2010–2011, Texas Instruments Incorporated ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. ADS8555 UNIT Supply voltage, HVDD to AGND –0.3 to +18 V Supply voltage, HVSS to AGND –18 to +0.3 V Supply voltage, AVDD to AGND –0.3 to +6 V Supply voltage, BVDD to BGND –0.3 to +6 V Analog input voltage HVSS – 0.3 to HVDD + 0.3 V Reference input voltage with respect to AGND AGND – 0.3 to AVDD + 0.3 V Digital input voltage with respect to BGND BGND – 0.3 to BVDD + 0.3 V Ground voltage difference AGND to BGND ±0.3 V –10 to +10 mA +150 °C Human body model (HBM) JEDEC standard 22, test method A114-C.01, all pins ±2000 V Charged device model (CDM) JEDEC standard 22, test method C101, all pins ±500 V Input current to all pins except supply Maximum virtual junction temperature, TJ ESD ratings (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. THERMAL INFORMATION ADS8555 THERMAL METRIC (1) PM UNITS 64 PINS θJA Junction-to-ambient thermal resistance θJCtop Junction-to-case (top) thermal resistance 16 θJB Junction-to-board thermal resistance N/A ψJT Junction-to-top characterization parameter N/A ψJB Junction-to-board characterization parameter N/A θJCbot Junction-to-case (bottom) thermal resistance N/A (1) 48 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A. 2 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS MIN TYP MAX 4.5 5 5.5 V Low-voltage levels 2.7 3.0 3.6 V 5V logic levels 4.5 5 5.5 V Supply voltage, AVDD to AGND Supply voltage, BVDD to BGND Input supply voltage, HVDD to AGND Input supply voltage, HVSS to AGND Input range = ±2 × VREF 2 × VREF 16.5 V Input range = ±4 × VREF 4 × VREF 16.5 V Input range = ±2 × VREF –16.5 –2 × VREF V Input range = ±4 × VREF –16.5 –4 × VREF V 3.0 V V Reference input voltage (VREF) 0.5 Analog inputs (also see the Analog Inputs section) UNIT 2.5 Input range = ±2 × VREF –2 × VREF 2 × VREF Input range = ±4 × VREF –4 × VREF 4 × VREF V –40 +125 °C Operating ambient temperature range, TA ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range of –40°C to +125°C, AVDD = 4.5V to 5.5V, BVDD = 2.7V to 5.5V, HVDD = 10V to 15V, HVSS = –15V to –10V, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted. ADS8555 PARAMETER CONDITIONS MIN TYP (1) MAX UNIT DC ACCURACY Resolution 16 No missing codes Integral linearity error Differential linearity error Bits 16 INL DNL At TA = –40°C to +85°C –3 At TA = –40°C to +125°C –4 At TA = –40°C to +85°C –1 At TA = –40°C to +125°C –1 –4.0 Offset error Bits ±1.5 3 LSB ±1.5 4 LSB ±0.75 1.5 LSB ±0.75 2 LSB ±0.8 4.0 ±3.5 Offset error drift –0.75 ±0.25 mV μV/°C Gain error Referenced to voltage at REFIO Gain error drift Referenced to voltage at REFIO ±6 ppm/°C PSRR At output code FFFFh, related to AVDD 60 dB Power-supply rejection ratio 0.75 %FSR SAMPLING DYNAMICS Acquisition time tACQ Conversion time per ADC tCONV Internal conversion clock period tCCLK Throughput rate fDATA 280 ns 1.26 μs 18.5 tCCLK 68.0 ns Parallel interface, internal clock and reference 630 kSPS Serial interface, internal clock and reference 450 kSPS AC ACCURACY Signal-to-noise ratio Signal-to-noise ratio + distortion Total harmonic distortion (2) Spurious-free dynamic range SNR SINAD THD SFDR Channel-to-channel isolation –3dB small-signal bandwidth (1) (2) At fIN = 10kHz, TA = –40°C to +85°C 90 91.5 dB At fIN = 10kHz, TA = –40°C to +125°C 89 91.5 dB At fIN = 10kHz, TA = –40°C to +85°C 87 89.5 dB 86.5 89.5 At fIN = 10kHz, TA = –40°C to +125°C dB At fIN = 10kHz, TA = –40°C to +85°C –94 –90 At fIN = 10kHz, TA = –40°C to +125°C –94 –89.5 At fIN = 10kHz, TA = –40°C to +85°C dB 90 95 dB 89.5 95 dB 100 dB Input Range = ±4 × VREF 48 MHz Input Range = ±2 × VREF 24 MHz At fIN = 10kHz, TA = –40°C to +125°C At fIN = 10kHz All values are at TA = +25°C. Calculated on the first nine harmonics of the input frequency. 3 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over recommended operating free-air temperature range of –40°C to +125°C, AVDD = 4.5V to 5.5V, BVDD = 2.7V to 5.5V, HVDD = 10V to 15V, HVSS = –15V to –10V, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted. ADS8555 PARAMETER CONDITIONS MIN TYP (1) MAX UNIT ANALOG INPUT Bipolar full-scale range CHXX Input capacitance Input leakage current RANGE pin/RANGE bit = 0 –4 × VREF 4 × VREF RANGE pin/RANGE bit = 1 –2 × VREF 2 × VREF Input range = ±4 × VREF 10 Input range = ±2 × VREF 20 Aperture delay matching pF ±1 Common CONVST for all channels Aperture jitter V pF No ongoing conversion Aperture delay V μA 5 ns 250 ps 50 ps EXTERNAL CLOCK INPUT (XCLK) fXCLK An external reference must be used for fXCLK > fCCLK External clock frequency External clock duty cycle 1 18 45 20 MHz 55 % REFERENCE VOLTAGE OUTPUT (REFOUT) Reference voltage Reference voltage drift Power-supply rejection ratio Output current VREF 2.5V operation, REFDAC = 0x3FF 2.485 2.5 2.515 V 2.5V operation, REFDAC = 0x3FF at +25°C 2.496 2.5 2.504 V 3.0V operation, REFDAC = 0x3FF 2.985 3.0 3.015 V 3.0V operation, REFDAC = 0x3FF at +25°C 2.995 3.0 3.005 ±10 dVREF/dT PSRR 73 dB –2 IREFOUT DC current V ppm/°C 2 mA Short-circuit current (3) IREFSC 50 mA Turn-on settling time tREFON 10 ms μF External load capacitance Tuning range At CREF_x pins 4.7 10 At REFIO pins 100 470 REFDAC Internal reference output voltage range REFDAC resolution nF 0.2 × VREF VREF 10 V Bits DNLDAC –1 ±0.1 1 LSB REFDAC integral nonlinearity INLDAC –2 ±0.1 2 LSB REFDAC offset error VOSDAC VREF = 0.5V (DAC = 0x0CC) –4 ±0.65 4 LSB 2.5 3.025 REFDAC differential nonlinearity REFERENCE VOLTAGE INPUT (REFIN) Reference input voltage VREFIN 0.5 Input resistance 100 Input capacitance V MΩ 5 pF Reference input current 1 μA SERIAL CLOCK INPUT (SCLK) Serial clock input frequency fSCLK 0.1 36 MHz Serial clock period tSCLK 0.0278 10 μs 40 60 % V Serial clock duty cycle DIGITAL INPUTS (4) Logic family CMOS with Schmitt-Trigger High-level input voltage 0.7 × BVDD BVDD + 0.3 Low-level input voltage BGND – 0.3 0.3 × BVDD V –50 +50 nA Input current VI = BVDD to BGND Input capacitance (3) (4) 5 pF Reference output current is not limited internally. Specified by design. 4 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over recommended operating free-air temperature range of –40°C to +125°C, AVDD = 4.5V to 5.5V, BVDD = 2.7V to 5.5V, HVDD = 10V to 15V, HVSS = –15V to –10V, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted. ADS8555 PARAMETER DIGITAL OUTPUTS CONDITIONS MIN TYP (1) MAX UNIT BVDD – 0.6 BVDD V BGND BGND + 0.4 V –50 50 nA (5) Logic family CMOS High-level output voltage IOH = 100μA Low-level output voltage IOH = –100μA High-impedance-state output current Output capacitance 5 Load capacitance pF 30 pF POWER-SUPPLY REQUIREMENTS Analog supply voltage AVDD 4.5 5.0 5.5 V Buffer I/O supply voltage BVDD 2.7 3.0 5.5 V Input positive supply voltage HVDD 5.0 10.0 16.5 V Input negative supply voltage HVSS –16.5 –10.0 –5.0 V 30.0 36.0 mA 14.0 16.5 mA 4.0 6.0 mA Power-down mode 0.1 50.0 μA fDATA = maximum 0.9 2.0 mA 0.5 1.5 mA 0.1 10.0 μA Power-down mode 0.1 10.0 μA fDATA = maximum 3.0 3.5 mA 1.6 2.0 mA 0.2 0.3 μA Power-down mode 0.1 10.0 μA fDATA = maximum 3.6 4.0 mA 1.8 2.2 mA 0.2 0.25 μA fDATA = maximum Analog supply current (6) Buffer I/O supply current (7) Input positive supply current (8) Input negative supply current (9) fDATA = 250kSPS (auto-NAP mode) IAVDD Auto-NAP mode, no ongoing conversion, internal conversion clock fDATA = 250kSPS (auto-NAP mode) IBVDD Auto-NAP mode, no ongoing conversion, internal conversion clock fDATA = 250kSPS (auto-NAP mode) IHVDD Auto-NAP mode, no ongoing conversion, internal conversion clock fDATA = 250kSPS (auto-NAP mode) IHVSS Auto-NAP mode, no ongoing conversion, internal conversion clock 0.1 10.0 μA fDATA = maximum 251.7 298.5 mW fDATA = 250kSPS (auto-NAP mode) 122.5 150.0 mW 26.0 38.3 mW 3.8 580.0 μW Power-down mode Power dissipation (10) Auto-NAP mode, no ongoing conversion, internal conversion clock Power-down mode (5) (6) (7) (8) (9) (10) Specified by design. At AVDD = 5V. At BVDD = 3V, parallel mode, load capacitance = 6pF/pin. At HVDD = 15V. At HVSS = –15V. At AVDD = 5V, BVDD = 3V, HVDD = 15V, and HVSS = –15V. 5 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com EQUIVALENT INPUT CIRCUITS Input range: ±2VREF Input range: ±4VREF RSER = 200W RSW = 130W RSER = 200W CH_XX RSW = 130W CH_XX CS = 20pF CS = 10pF VDC CPAR = 5pF VDC CPAR = 5pF CS = 20pF CS = 10pF AGND AGND RSER = 200W RSW = 130W RSER = 200W RSW = 130W PIN CONFIGURATION DB15 REFEN/WR HW/SW PAR/SER AVDD AGND REFC_C AGND REFC_B AGND REFC_A AGND AGND REFIO AVDD AGND PM PACKAGE LQFP-64 (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DB14/REFBUFEN 1 48 CH_C1 DB13/SDI 2 47 AVDD DB12 3 46 AVDD DB11 4 45 CH_C0 DB10/SDO_C 5 44 AGND DB9/SDO_B 6 43 AGND DB8/SDO_A 7 42 CH_B1 BGND 8 41 AVDD BVDD 9 40 AVDD DB7/HBEN/DCEN 10 39 CH_B0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RESET WORD/BYTE HVSS HVDD AGND 33 CH_A0 RANGE/XCLK DB1/SEL_B 16 AVDD 34 AVDD AGND DB2/SEL_C 15 STBY 35 AVDD CONVST_A DB3/DCIN_C 14 CONVST_B 36 CH_A1 CONVST_C DB4/DCIN_B 13 RD 37 AGND CS/FS DB5/DCIN_A 12 BUSY/INT 38 AGND DB0/SEL_A DB6/SCLK 11 6 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com PIN DESCRIPTIONS DESCRIPTION NAME DB14/REFBUFEN PIN # 1 TYPE (1) DIO/DI PARALLEL INTERFACE (PAR/SER = 0) Data bit 14 input/output SERIAL INTERFACE (PAR/SER = 1) Hardware mode (HW/SW = 0): Reference buffers enable input. When low, all reference buffers are enabled (mandatory if internal reference is used). When high, all reference buffers are disabled. Software mode (HW/SW = 1):Connect to BGND or BVDD. The reference buffers are controlled by bit C24 (REFBUF) in control register (CR). Hardware mode (HW/SW = 0): Connect to BGND DB13/SDI 2 DIO/DI Data bit 13 input/output DB12 3 DIO Data bit 12 input/output Connect to BGND DB11 4 DIO Data bit 11 input/output Connect to BGND DB10/SDO_C 5 DIO/DO Data bit 10 input/output When SEL_C = 1, data output for channel C When SEL_C = 0, this pin should be tied to BGND DB9/SDO_B 6 DIO/DO Data bit 9 input/output When SEL_B = 1, data output for channel B When SEL_B = 0, this pin should be tied to BGND When SEL_C = 0, data from channel C1 are also available on this output Data bit 8 input/output Data output for channel A When SEL_C = 0, data from channel C0 are also available on this output When SEL_C = 0 and SEL_B = 0, SDO_A acts as the single data output for all channels Software mode (HW/SW = 1): Serial data input DB8/SDO_A 7 DIO/DO BGND 8 P Buffer I/O ground, connect to digital ground plane BVDD 9 P Buffer I/O supply, connect to digital supply (2.7V to 5.5V). Decouple with a 1μF ceramic capacitor or a combination of 100nF and 10μF ceramic capacitors to BGND. Word mode (WORD/BYTE = 0): Data bit 7 input/output DB7/HBEN/DCEN 10 DIO/DI/DI DB6/SCLK 11 DIO/DI DB5/DCIN_A 12 DIO/DI DB4/DCIN_B DB3/DCIN_C DB2/SEL_C DB1/SEL_B (1) 13 14 15 16 DIO/DI DIO/DI DIO/DI DIO/DI Byte mode (WORD/BYTE = 1): High byte enable input. When high, the high byte is output first on DB[15:8]. When low, the low byte is output first on DB[15:8]. Word mode (WORD/BYTE = 0): Data bit 6 input/output Byte mode (WORD/BYTE = 1): Connect to BGND or BVDD Word mode (WORD/BYTE = 0): Data bit 5 input/output Byte mode (WORD/BYTE = 1): Connect to BGND or BVDD Word mode (WORD/BYTE = 0): Data bit 4 input/output Byte mode (WORD/BYTE = 1): Connect to BGND or BVDD Word mode (WORD/BYTE = 0): Data bit 3 input/output Byte mode (WORD/BYTE = 1): Connect to BGND or BVDD Word mode (WORD/BYTE = 0): Data bit 2 input/output Byte mode (WORD/BYTE = 1): Connect to BGND or BVDD Word mode (WORD/BYTE = 0): Data bit 1 input/output Byte mode (WORD/BYTE = 1): Connect to BGND or BVDD Daisy-chain enable input. When high, DB[5:3] serve as daisy-chain inputs DCIN[A:C]. If daisy-chain mode is not used, connect to BGND. Serial interface clock input (36MHz max) When DCEN = 1, daisy-chain data input for channel A When DCEN = 0, connect to BGND When SEL_B = 1 and DCEN = 1, daisy-chain data input for channel B When DCEN = 0, connect to BGND When SEL_C = 1 and DCEN = 1, daisy-chain data input for channel C When DCEN = 0, connect to BGND Select SDO_C input. When high, SDO_C is active. When low, SDO_C is disabled. Select SDO_B input. When high, SDO_B is active. When low, SDO_B is disabled. AI = analog input; AIO = analog input/output; DI = digital input; DO = digital output; DIO = digital input/output; and P = power supply. 7 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com PIN DESCRIPTIONS (continued) DESCRIPTION NAME DB0/SEL_A PIN # 17 TYPE (1) DIO/DI BUSY/INT 18 DO CS/FS 19 DI/DI RD 20 DI CONVST_C CONVST_B 21 22 DI DI PARALLEL INTERFACE (PAR/SER = 0) Word mode (WORD/BYTE = 0): Data bit 0 (LSB) input/output Byte mode (WORD/BYTE = 1): Connect to BGND or BVDD SERIAL INTERFACE (PAR/SER = 1) Select SDO_A input. When high, SDO_A is active. When low, SDO_A is disabled. Should always be high. When CR bit C21 = 0 (BUSY/INT), converter busy status output. Transitions high when a conversion has been started and remains high during the entire process. Transitions low when the conversion data of all six channels are latched to the output register and remains low thereafter. In sequential mode (SEQ = 1 in the CR), the BUSY output transitions high when a conversion has been started and goes low for a single conversion clock cycle (tCCLK) whenever a channel pair conversion is completed. When bit C21 = 1 (BUSY/INT in CR), interrupt output. This bit transitions high after a conversion has been completed and goes low with the first read data access. The polarity of BUSY/INT output can be changed using bit C20 (BUSY L/H) in the control register. Chip select input. When low, the parallel interface is enabled. When high, the interface is disabled. Frame synchronization. The falling edge of FS controls the frame transfer. Read data input. When low, the parallel data output is enabled. When high, the data output is disabled. Connect to BGND Hardware mode (HW/SW = 0): Conversion start of channel pair C. The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_C[1:0]. Software mode (HW/SW = 1): Conversion start of channel pair C in sequential mode (CR bit C23 = 1) only; connect to BGND or BVDD otherwise Hardware mode (HW/SW = 0): Conversion start of channel pair B. The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_B[1:0]. Software mode (HW/SW = 1): Conversion start of channel pair B in sequential mode (CR bit C23 = 1) only; connect to BGND or BVDD otherwise Hardware mode (HW/SW = 0): Conversion start of channel pair A. The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_A[1:0]. CONVST_A 23 DI STBY 24 DI Standby mode input. When low, the entire device is powered down (including the internal clock and reference). When high, the device operates in normal mode. AGND 25, 32, 37, 38, 43, 44, 49, 52, 53, 55, 57, 59 P Analog ground, connect to analog ground plane Pin 25 may have a dedicated ground if the difference between its potential and AGND is always kept within ±300mV. AVDD 26, 34, 35, 40, 41, 46, 47, 50, 60 P Analog power supply (4.5V to 5.5V). Decouple each pin with a 100nF ceramic capacitor to AGND. Use an additional 10μF capacitor to AGND close to the device but without compromising the placement of the smaller capacitor. Pin 26 may have a dedicated power supply if the difference between its potential and AVDD is always kept within ±300mV. RANGE/XCLK 27 DI/DIO RESET 28 DI Reset input, active high. Aborts any ongoing conversions. Resets the internal control register to 0x000003FF. The RESET pulse should be at least 50ns long. Software mode (HW/SW = 1): Conversion start of all selected channels except in sequential mode (CR bit C23 = 1): Conversion start of channel pair A only Hardware mode (HW/SW = 0): Input voltage range select input. When low, the analog input range is ±4VREF. When high, the analog input range is ±2VREF. Software mode (HW/SW = 1): External conversion clock input, if CR bit C11 (CLKSEL) is set high or internal conversion clock output, if CR bit C10 (CLKOUT_EN) is set high. If not used, connect to BVDD or BGND. WORD/BYTE 29 DI Output mode selection input. When low, data are transferred in word mode using DB[15:0]. When high, data are transferred in byte Connect to BGND mode using DB[15:8] with the byte order controlled by HBEN pin while two accesses are required for a complete 16-bit transfer. HVSS 30 P Negative supply voltage for the analog inputs (–16.5V to –5V). Decouple with a 100nF ceramic capacitor to AGND placed next to the device and a 10μF capacitor to AGND close to the device but without compromising the placement of the smaller capacitor. HVDD 31 P Positive supply voltage for the analog inputs (5V to 16.5V). Decouple with a 100nF ceramic capacitor to AGND placed next to the device and a 10μF capacitor to AGND close to the device but without compromising the placement of the smaller capacitor. CH_A0 33 AI Analog input of channel A0. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C26 (RANGE_A) in software mode. CH_A1 36 AI Analog input of channel A1. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C26 (RANGE_A) in software mode. 8 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com PIN DESCRIPTIONS (continued) DESCRIPTION NAME PIN # TYPE (1) PARALLEL INTERFACE (PAR/SER = 0) SERIAL INTERFACE (PAR/SER = 1) CH_B0 39 AI Analog input of channel B0. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C27 (RANGE_B) in software mode. CH_B1 42 AI Analog input of channel B1. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C27 (RANGE_B) in software mode. CH_C0 45 AI Analog input of channel C0. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C28 (RANGE_C) in software mode. CH_C1 48 AI Analog input of channel C1. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C28 (RANGE_C) in software mode. REFIO 51 AIO Reference voltage input/output (0.5V to 3.025V). The internal reference is enabled via REFEN/WR pin in hardware mode or CR bit C25 (REFEN) in software mode. The output value is controlled by the internal DAC (CR bits C[9:0]). Connect a 470nF ceramic decoupling capacitor between this pin and pin 52. REFC_A 54 AI Decoupling capacitor for reference of channels A. Connect a 10μF ceramic decoupling capacitor between this pin and pin 53. REFC_B 56 AI Decoupling capacitor for reference of channels B. Connect a 10μF ceramic decoupling capacitor between this pin and pin 55. REFC_C 58 AI Decoupling capacitor for reference of channels C. Connect a 10μF ceramic decoupling capacitor between this pin and pin 57. PAR/SER 61 DI Interface mode selection input. When low, the parallel interface is selected. When high, the serial interface is enabled. HW/SW 62 DI Mode selection input. When low, the hardware mode is selected and part works according to the settings of external pins. When high, the software mode is selected in which the device is configured by writing into the control register. REFEN/WR DB15 63 64 DI DIO Hardware mode (HW/SW = 0): Internal reference enable input. When high, the internal reference is enabled (the reference buffers are to be enabled). When low, the internal reference is disabled and an external reference is applied at REFIO. Hardware mode (HW/SW = 0): Internal reference enable input. When high, the internal reference is enabled (the reference buffers are to be enabled). When low, the internal reference is disabled and an external reference should be applied at REFIO. Software mode (HW/SW = 1): Write input. The parallel data input is enabled, when CS and WR are low. The internal reference is enabled by the CR bit C25 (REFEN). Software mode (HW/SW = 1): Connect to BGND or BVDD. The internal reference is enabled by CR bit C25 (REFEN). Data bit 15 (MSB) input/output Connect to BGND 9 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com TIMING CHARACTERISTICS XCLK (C11 = 1) tS3 tS3 t1 CONVST_x tACQ tCONV tD1 BUSY (C20 = C21 = 0) t3 t2 FS tSCLK 32 1 SCLK tD3 tD4 tD2 ADS8556 SDO_x CH_x0 MSB tH2 CH_x1 D3 tS1 SDI or DCIN_x Don’t Care D31 D3 CH_x1 D2 tH1 CH_x1 D1 CH_x1 LSB D2 D1 D0 Don’t Care Figure 1. Serial Operation Timing Diagram (All Three SDOs Active) SERIAL INTERFACE TIMING REQUIREMENTS (1) Over recommended operating free-air temperature range at –40°C to +125°C, AVDD = 5V, and BVDD = 2.7V to 5.5V, unless otherwise noted. ADS8555 PARAMETER MIN MAX Acquisition time tCONV Conversion time t1 CONVST_x low time t2 BUSY low to FS low time t3 Bus access finished to next conversion start time tD1 CONVST_x high to BUSY high delay 5 20 ns tD2 FS low to SDO_x active delay 5 12 ns tD3 SCLK rising edge to new data valid delay 15 ns tD4 FS high to SDO_x 3-state delay 10 ns tH1 Input data to SCLK falling edge hold time 5 ns tH2 Output data to SCLK rising edge hold time 5 ns tS1 Input data to SCLK falling edge setup time 3 ns tS3 CONVST_x high to XCLK falling or rising edge setup time 6 tSCLK Serial clock period (1) 280 UNIT tACQ ns 1.26 µs 20 ns 0 ns 40 0.0278 ns ns 10 μs All input signals are specified with tR = tF = 1.5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2. 10 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com t1 CONVST_A CONVST_B CONVST_C tCONV tACQ tD1 BUSY (C20 = C21 = 0) t3 t2 CS t4 t6 t5 t7 RD tD5 CH A0 DB[15:0] CH A1 CH B0 CH B1 tH3 CH C0 CH C1 Figure 2. Parallel Read Access Timing Diagram PARALLEL INTERFACE TIMING REQUIREMENTS (Read Access) (1) Over recommended operating free-air temperature range at –40°C to +125°C, AVDD = 5V, and BVDD = 2.7V to 5.5V, unless otherwise noted. ADS8555 PARAMETER MIN tACQ Acquisition time tCONV Conversion time t1 CONVST_x low time t2 BUSY low to CS low time t3 Bus access finished to next conversion start time (2) t4 t5 t6 MAX UNIT 1.26 µs 280 ns 20 ns 0 ns 40 ns CS low to RD low time 0 ns RD high to CS high time 0 ns RD pulse width 30 ns t7 Minimum time between two read accesses 10 tD1 CONVST_x high to BUSY high delay tD5 RD falling edge to output data valid delay tH3 Output data to RD rising edge hold time (1) (2) 5 ns 20 ns 20 ns 5 ns All input signals are specified with tR = tF = 1.5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2. Refer to CS signal or RD, whichever occurs first. 11 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com CS t9 t10 t11 t8 WR tS2 tH4 C [31:16] DB[15:0] C [15:0] Don’t Care Word Mode (WORD/BYTE = 0) C [31:24] C [23:16] C [15:8] C [7:0] Byte Mode (WORD/BYTE = 1) Figure 3. Parallel Write Access Timing Diagram PARALLEL INTERFACE TIMING REQUIREMENTS (Write Access) (1) Over recommended operating free-air temperature range at –40°C to +125°C, AVDD = 5V, and BVDD = 2.7V to 5.5V, unless otherwise noted. ADS8555 PARAMETER t8 CS low to WR low time t9 MIN MAX UNIT 0 ns WR low pulse width 15 ns t10 WR high pulse width 10 ns t11 WR high to CS high time 0 ns tS2 Output data to WR rising edge setup time 5 ns tH4 Data output to WR rising edge hold time 5 ns (1) All input signals are specified with tR = tF = 1.5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2. 12 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com TYPICAL CHARACTERISTICS At +25°C, over entire supply voltage range, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted. INL vs CODE (±10VIN Range) 3.0 3.0 AVDD = BVDD = 5V HVSS = -15V HVDD = 15V fDATA = Max Internal Reference 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.0 0 1.5 8190 16380 24570 32760 40950 49140 57330 65520 8190 16380 24570 32760 40950 49140 57330 65520 Code Figure 4. Figure 5. DNL vs CODE (±10VIN Range) DNL vs CODE (±5VIN Range) 1.5 AVDD = BVDD = 5V HVSS = -15V HVDD = 15V fDATA = Max Internal Reference 1.0 0 Code Differential Nonlinearity (LSB) Differential Nonlinearity (LSB) AVDD = BVDD = 5V HVSS = -15V HVDD = 15V fDATA = Max Internal Reference 2.5 Integral Nonlinearity (LSB) 2.5 Integral Nonlinearity (LSB) INL vs CODE (±5VIN Range) 0.5 0 -0.5 -1.0 AVDD = BVDD = 5V HVSS = -15V HVDD = 15V fDATA = Max Internal Reference 1.0 0.5 0 -0.5 -1.0 0 8190 16380 24570 32760 40950 49140 57330 65520 0 8190 16380 24570 32760 40950 49140 57330 65520 Code Code Figure 6. Figure 7. OFFSET ERROR vs TEMPERATURE GAIN ERROR vs TEMPERATURE 4 0.75 3 0.50 Gain Error (%) Offset Error (mV) 2 1 0 -1 0.25 0 -0.25 -2 -0.50 -3 -0.75 -4 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 Temperature (°C) 5 20 35 50 65 80 95 110 125 Temperature (°C) Figure 8. Figure 9. 13 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At +25°C, over entire supply voltage range, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted. PSRR vs AVDD NOISE FREQUENCY CONVERSION TIME vs TEMPERATURE 1.40 CSUPPLY = 100nF on AVDD 1.35 -40 Conversion Time (ms) Power-Supply Rejection Ratio (dB) -30 -50 -60 -70 1.30 1.25 1.20 1.15 1.10 1.05 1.00 -80 0.95 -90 0.90 0 20 40 60 80 100 120 140 160 180 200 -40 -25 -10 5 AVDD Noise Frequency (kHz) 20 Figure 10. 4500 4000 3500 3000 AVDD = BVDD = 5V HVSS = -15V HVDD = 15V 8192 Samples Range = +4 ´ VREF Internal Reference T = +25°C 1500 1000 88 86 84 82 80 AVDD = BVDD = 5V HVSS = -15V, HVDD = 15V fSIGNAL = 10kHz, fDATA = Max Range = ±4 ´ VREF Internal Reference 78 76 74 70 -3 -2 0 -1 1 2 -40 -25 -10 5 Code 35 50 65 80 95 110 125 Figure 13. SINAD vs TEMPERATURE THD vs TEMPERATURE 94 -86 AVDD = BVDD = 5V, HVSS = -15V, HVDD = 15V fSIGNAL = 10kHz, fDATA = Max, Range = ±4 ´ VREF Internal Reference 92 Total Harmonic Distortion (dB) Signal-to-Noise Ratio and Distortion (dB) 20 Temperature (°C) Figure 12. 90 88 86 84 82 80 72 110 125 90 72 500 74 95 92 2000 76 80 SNR vs TEMPERATURE 2500 78 65 94 Signal-to-Noise Ratio (dB) Number of Occurrences 5000 50 Figure 11. CODE HISTOGRAM (8192 Hits) 5500 35 Temperature (°C) AVDD = BVDD = 5V HVSS = -15V, HVDD = 15V fSIGNAL = 10kHz, fDATA = Max Range = ±4 ´ VREF Internal Reference -88 -90 -92 -94 -96 -98 70 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 Temperature (°C) 5 20 35 50 65 80 95 110 125 Temperature (°C) Figure 14. Figure 15. 14 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At +25°C, over entire supply voltage range, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted. FREQUENCY SPECTRUM (2048-Point FFT, fIN = 10kHz, ±10VIN Range) SFDR vs TEMPERATURE 0 AVDD = BVDD = 5V HVSS = -15V HVDD = 15V fSAMPLE = 500kSPS fSIGNAL = 10kHz Range = ±4 ´ VREF Internal Reference T = +25°C -20 98 -40 96 Amplitude (dB) Spurious-Free Dynamic Range (dB) 100 94 92 AVDD = BVDD = 5V HVSS = -15V, HVDD = 15V fSIGNAL = 10kHz, fDATA = Max Range = ±4 ´ VREF Internal Reference 90 88 5 20 35 50 65 80 95 -80 -100 -120 -140 -160 -180 86 -40 -25 -10 -60 0 110 125 25 50 75 Temperature (°C) Figure 16. Figure 17. FREQUENCY SPECTRUM (2048-Point FFT, fIN = 10kHz, ±5VIN Range) CHANNEL-TO-CHANNEL ISOLATION vs INPUT NOISE FREQUENCY 0 -60 -80 250 AVDD = BVDD = 5V HVSS = -15V HVDD = 15V fDATA = Max Range = ±2 ´ VREF Internal Reference 115 110 Isolation (dB) -40 Amplitude (dB) 120 AVDD = BVDD = 5V HVSS = -15V, HVDD = 15V fSAMPLE = 500kSPS fSIGNAL = 10kHz Range = ±2 ´ VREF Internal Reference T = +25°C -20 -100 -120 105 100 95 90 -140 85 -160 80 -180 0 25 50 75 100 125 150 175 200 225 0 250 30 60 90 120 150 180 210 240 270 300 Noise Frequency (kHz) Frequency (kHz) Figure 18. Figure 19. INTERNAL REFERENCE VOLTAGE vs ANALOG SUPPLY VOLTAGE (2.5V Mode) INTERNAL REFERENCE VOLTAGE vs TEMPERATURE (2.5V Mode) 2.504 2.504 2.503 2.503 2.502 2.502 2.501 VREF (V) VREF (V) 100 125 150 175 200 225 Frequency (kHz) VREF 2.500 2.501 2.500 2.499 2.499 2.498 2.498 2.497 2.497 2.496 2.496 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) AVDD (V) Figure 20. Figure 21. 15 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At +25°C, over entire supply voltage range, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted. INTERNAL REFERENCE VOLTAGE vs TEMPERATURE (3.0V Mode) ANALOG SUPPLY CURRENT vs TEMPERATURE 3.005 3.004 3.003 IAVDD (mA) VREF (V) 3.002 3.001 3.000 2.999 2.998 2.997 2.996 2.995 -40 -25 -10 5 20 35 50 65 80 95 110 125 36 34 32 30 28 26 24 22 20 18 16 14 12 10 fDATA = Max AVDD = 5V Internal Reference fDATA = 250kSPS (A-NAP) -40 -25 -10 5 20 Temperature (°C) Figure 22. IBVDD (mA) IAVDD (mA) AVDD = 5V Internal Reference A-NAP Mode BVDD = 5V 1.4 1.2 fDATA = Max 1.0 0.8 0.6 fDATA = 250kSPS (A-NAP) 0.4 0.2 45 90 135 180 225 270 315 360 405 450 495 540 585 630 -40 -25 -10 5 20 50 65 80 95 110 125 Figure 25. INPUT SUPPLY CURRENT vs TEMPERATURE INPUT SUPPLY CURRENT vs INPUT SUPPLY VOLTAGE 4.5 IHVSS (fDATA = Max) 4.0 IHVDD (fDATA = Max) HVSS = -15V HVDD = 15V Range = ±4 ´ VREF Internal Reference 2.50 2.25 IHVSS (250kSPS A-NAP) 1.75 IHVDD (250kSPS A-NAP) Input Supply Current (mA) Input Supply Current (mA) 35 Temperature (°C) Figure 24. 2.75 1.50 110 125 1.6 3.50 2.00 95 1.8 4.00 3.00 80 Normal Operation Sample Rate (kSPS) 3.25 65 BUFFER I/O SUPPLY CURRENT vs TEMPERATURE 2.0 0 3.75 50 Figure 23. ANALOG SUPPLY CURRENT vs DATA RATE 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 35 Temperature (°C) IHVSS (fDATA = Max) 3.5 3.0 IHVDD (fDATA = Max) 2.5 2.0 1.5 1.0 IHVSS (250kSPS A-NAP) 0.5 1.25 IHVDD (250kSPS A-NAP) 0 1.00 -40 -25 -10 5 20 35 50 65 80 95 110 125 5 6 7 8 9 10 11 12 13 14 15 HVDD, |HVSS| (V) Temperature (°C) Figure 26. Figure 27. 16 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At +25°C, over entire supply voltage range, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted. INPUT SUPPLY CURRENT vs DATA RATE 3.6 IHVSS 3.3 3.0 IHVSS (A-NAP) IHVxx (mA) 2.7 2.4 2.1 IHVDD (A-NAP) 1.8 1.5 IHVDD 1.2 0.9 HVSS = -15V HVDD = 15V Range = ±4 ´ VREF 0.6 0.3 0 0 90 180 270 360 450 540 630 Data Rate (kSPS) Figure 28. 17 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com GENERAL DESCRIPTION The ADS8555 includes six 16-bit analog-to-digital converters (ADCs) that operate based on the successive approximation register (SAR) principle. The architecture is designed on the charge redistribution principle, which inherently includes a sample-and-hold function. The six analog inputs are grouped into three channel pairs. These channel pairs can be sampled and converted simultaneously, preserving the relative phase information of the signals of each pair. Separate conversion start signals allow simultaneous sampling on each channel pair, on four channels or on all six channels. These devices accept single-ended, bipolar analog input signals in the selectable ranges of ±4VREF or ±2VREF with an absolute value of up to ±12V; see the Analog Inputs section. The devices offer an internal 2.5V/3V reference source followed by a 10-bit digital-to-analog converter (DAC) that allows the reference voltage VREF to be adjusted in 2.44mV or 2.93mV steps, respectively. The ADS8555 also offers a selectable parallel or serial interface that can be used in hardware or software mode; see the Device Configuration section for details. ANALOG This section addresses the analog input circuit, the ADCs and control signals, and the reference design of the device. Analog Inputs The inputs and the converters are of the single-ended, bipolar type. The absolute voltage range can be selected using the RANGE pin (in hardware mode) or RANGE_x bits (in software mode) in the control register (CR, see Table 3) to either ±4VREF or ±2VREF. With the reference set to 2.5V (CR bit C18 = 0), the input voltage range can be ±10V or ±5V. With the reference source set to 3V (CR bit C18 = 1), an input voltage range of ±12V or ±6V can be configured. The logic state of the RANGE pin is latched with the falling edge of BUSY (if CR bit C20 = 0). The input current on the analog inputs depends on the actual sample rate, input voltage, and signal source impedance. Essentially, the current into the analog inputs charges the internal capacitor array only during the sampling period (tACQ). The source of the analog input voltage must be able to charge the input capacitance of 10pF in ±4VREF mode or 20pF in ±2VREF to a 12-, 14-, 16-bit accuracy level within the acquisition time of 280ns at maximum data rate; see the Equivalent Input Circuit. During the conversion period, there is no further input current flow and the input impedance is greater than 1MΩ. To ensure a defined start condition, the sampling capacitors of the ADS8555 are pre-charged to a fixed internal voltage, before switching into sampling mode. To maintain the linearity of the converter, the inputs should always remain within the specified range of HVSS – 0.2V to HVDD + 0.2V. The minimum –3dB bandwidth of the driving operational amplifier can be calculated using Equation 1: ln(2) ´ (n + 1) f-3dB = 2p ´ tACQ Where: n = 16 (n is the resolution of the device) (1) With a minimum acquisition time of tACQ = 280ns, the required minimum bandwidth of the driving amplifier is 6.7MHz. The required bandwidth can be lower if the application allows a longer acquisition time. A gain error occurs if a given application does not fulfill the bandwidth requirement shown in Equation 1. A driving operational amplifier may not be required, if the impedance of the signal source (RSOURCE) fulfills the requirement of Equation 2: tACQ RSOURCE < - (RSER + RSW) CS ln(2) ´ (n + 1) Where: n = 16 (n is the resolution of the ADC). CS = 10pF is the sample capacitor value for VIN = ±4 × VREF mode. RSER = 200Ω is the input resistor value. and RSW = 130Ω is the switch resistance value. (2) With tACQ = 280ns, the maximum source impedance should be less than 2.0kΩ in VIN = ±4VREF mode or less than 0.9kΩ in VIN = ±2VREF mode. The source impedance can be higher if the application allows longer acquisition time. Analog-to-Digital Converter (ADC) The devices include six ADCs that operate with either an internal or an external conversion clock. The conversion time is 1.26μs with the internal conversion clock. When an external clock and reference are used, the minimum conversion time is 925ns. 18 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Conversion Clock CONVST_x The device uses either an internally-generated or an external (XCLK) conversion clock signal (in software mode only). In default mode, the device generates an internal clock. When the CLKSEL bit is set high (bit C11 in the CR), an external conversion clock of up to 20MHz (max) can be applied on pin 27. In both cases, 18.5 clock cycles are required for a complete conversion including the pre-charging of the sample capacitors. The external clock can remain low between conversions. The analog inputs of each channel pair (CH_x0/1) are held with the rising edge of the corresponding CONVST_x signal. Only in software mode (except sequential mode), CONVST_A is used for all six ADCs. The conversion automatically starts with the next edge of the conversion clock. The conversion clock duty cycle should be 50%. However, the ADS8555 functions properly with a duty cycle between 45% and 55%. A conversion start must not be issued during an ongoing conversion on the same channel pair. It is allowed to initiate conversions on the other input pairs, however (see the Sequential Mode section for more details). If a parallel interface is used, the behavior of the output port depends on which CONVST_x signals have been issued. Figure 29 shows examples of different scenarios. BUSY (C20 = C21 = 0) CS CONVST_A CONVST_C CONVST_B RD DB[15:0] CH A0 CH A1 CH C0 CH C1 CH A0 CH A1 CH C0 CH B0 CH B1 CH B0 CH B1 CH B0 CH B1 CH B0 CONVST_B CONVST_A CONVST_B RD DB[15:0] NOTE: Boxed areas indicate the minimum required frame to acquire all data. Figure 29. Data Output versus CONVST_x 19 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 BUSY/INT The BUSY signal indicates if a conversion is in progress. It goes high with a rising edge of any CONVST_x signal and goes low when the output data of the last channel pair are available in the respective output register. The readout of the data can be initiated immediately after the falling edge of BUSY. In sequential mode, the BUSY signal goes low only for one clock cycle. See the Sequential Mode section for more details. The INT output goes high upon completion of a conversion process and remains high after first read data access. The polarity of the BUSY/INT signal can be changed using CR bit C20. Reference The ADS8555 provides an internal, low-drift 2.5V reference source. To increase the input voltage range, the reference voltage can be switched to 3V mode using the VREF bit (bit C18 in the CR). The reference feeds a 10-bit string-DAC controlled by bits C[9:0] in the control register. The buffered DAC output is connected to the REFIO pin. In this way, the voltage at this pin is programmable in 2.44mV (2.92mV in 3V mode) steps and adjustable to the application needs without additional external components. The actual output voltage can be calculated using Equation 3: Range ´ (Code + 1) VREF = 1024 Where: Range = the chosen maximum reference voltage output range (2.5V or 3V). Code = the decimal value of the DAC register content. (3) www.ti.com Table 1 lists some examples of internal reference DAC settings with a reference range set to 2.5V. However, to ensure proper performance, the DAC output voltage should not be programmed below 0.5V. The buffered output of the DAC should be decoupled with a 100nF capacitor (minimum); for best performance, a 470nF capacitor is recommended. If the internal reference is placed into power-down (default), an external reference voltage can drive the REFIO pin. The voltage at the REFIO pin is buffered with three internal amplifiers, one for each ADC pair. The output of each buffer needs to be decoupled with a 10μF capacitor between pin pairs 53 and 54, 55 and 56, and 57 and 58. The 10μF capacitors are available as ceramic 0805-SMD components and in X5R quality. The internal reference buffers can be powered down to decrease the power dissipation of the device. In this case, external reference drivers can be connected to REFC_A, REFC_B, and REFC_C pins. With 10μF decoupling capacitors, the minimum required bandwidth can be calculated using Equation 4: ln(2) f-3dB = 2p ´ tCONV (4) With the minimum tCONV of 1.26μs, the external reference buffers require a minimum bandwidth of 88kHz. Table 1. DAC Setting Examples (2.5V Operation) VREF OUT (V) DECIMAL CODE BINARY CODE HEXADECIMAL CODE 0.500 204 00 1100 1100 CC 1.25 511 01 1111 1111 1FF 2.500 1023 11 1111 1111 3FF 20 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 www.ti.com SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 DIGITAL SDO_B, and SDO_C depending on the selections made using the SEL_x pins. Starting with the most significant bit (MSB), the output data are changed at the rising edge of SCLK, so that the host processor can read it at the following falling edge. This section describes the digital control and the timing of the device in detail. Device Configuration Depending on the desired mode of operation, the ADS8555 can be configured using the external pins and/or the control register (see Table 3), as shown in Table 2. Parallel Interface To use the device with the parallel interface, the PAR/SER pin should be held low. The maximum achievable data throughput rate using the internal clock is 630kSPS in this case. Access to the ADS8555 is controlled as illustrated in Figure 2 and Figure 3. The device can either operate with a 16-bit (WORD/BYTE pin set low) or an 8-bit (WORD/BYTE pin set high) parallel interface. If 8-bit operation is used, the HBEN pin selects if the low-byte (DB7 low) or the high-byte (DB7 high) is available on the data output DB[15:8] first. Serial Interface The serial interface mode is selected by setting the PAR/SER pin high. In this case, each data transfer starts with the falling edge of the frame synchronization input (FS). The conversion results are presented on the serial data output pins SDO_A, Serial data input SDI are latched at the falling edge of SCLK. The serial interface can be used with one, two, or three output ports. These ports are enabled with pins SEL_A, SEL_B, and SEL_C. If all three serial data output ports (SDO_A, SDO_B, and SDO_C) are selected, the data can be read with either two 16-bit data transfers or with one 32-bit data transfer. The data of channels CH_x0 are available first, followed by data from channels CH_x1. The maximum achievable data throughput rate is 450kSPS in this case. If the application allows a data transfer using two ports only, SDO_A and SDO_B outputs are used. The device outputs data from channel CH_A0 followed by CH_A1 and CH_C0 on SDO_A, while data from channel CH_B0 followed by CH_B1 and CH_C1 occurs on SDO_B. In this case, a data transfer of three consecutive 16-bit words or one continuous 48-bit word is supported. The maximum achievable data throughput rate is 375kSPS. The output SDO_A is selected if only one serial data port is used in the application. The data are available in the following order: CH_A0, CH_A1, CH_B0, CH_B1, CH_C0, and, finally CH_C1. Data can be read using six 16-bit transfers, three 32-bit transfers, or a single 96-bit transfer. The maximum achievable data throughput rate is 250kSPS in this case. Figure 1 (the serial operation timing diagram) and Figure 30 show all possible scenarios in more detail. Table 2. ADS8555 Configuration Settings INTERFACE MODE HARDWARE MODE (HW/SW = 0) CONVERSION START CONTROLLED BY SEPARATE CONVST_x PINS SOFTWARE MODE (HW/SW = 1) CONVERSION START CONTROLLED BY CONVST_A PIN ONLY, EXCEPT IN SEQUENTIAL MODE Parallel (PAR/SER = 0) Configuration using pins, optionally, control bits C[22:18], C[15:13], and C[9:0] Configuration using control register bits C[31:0] only; status of pins 27 (only if used as RANGE input) and 63 is disregarded Serial (PAR/SER = 1) Configuration using control register bits C[31:0] only; status of pins 1, 27 (only if used as RANGE input), and Configuration using pins, optionally, control bits C[22:18], 63 is disregarded; each access requires a control register C[15:13], and C[9:0]; bits C[31:24] are disregarded update via SDI (see the Serial Interface section for details) 21 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com CONVST_A CONVST_B CONVST_C BUSY (C20 = C21 = 0) 48 SCLKs SEL_A = SEL_B = 1, SEL_C = 0 FS SDO_A CHA0 CHA1 CHC0 SDO_B CHB0 CHB1 CHC1 SEL_A = 1, SEL_B = SEL_C = 0 96 SCLKs FS SDO_A CHA0 CHA1 CHB0 CHB1 CHC0 CHC1 Figure 30. Serial Interface: Data Output with One or Two Active SDOs Hardware Mode With the HW/SW input (pin 62) set low, the device functions are controlled via the pins and, optionally, control register bits C[22:18], C[15:13], and C[9:0]. It is possible to generally use the part in hardware mode but to switch it into software mode to initialize or adjust the control register settings (for example, the internal reference DAC) and back to hardware mode thereafter. Software Mode When the HW/SW input is set high, the device operates in software mode with functionality set only by the control register bits (corresponding pin settings are ignored). If parallel interface is used, an update of all control register settings is performed by issuing two 16-bit write accesses on pins DB[15:0] in word mode or four 8-bit accesses on pins DB[15:8] in byte mode (to avoid losing data, the entire sequence must be finished before starting a new conversion). CS should be held low during the two or four write accesses to completely update the configuration register. It is also possible to update only the upper eight bits (C[31:24]) using a single write access and pins DB[15:8] in both word and byte modes. In word mode, the first write access updates only the upper eight bits and stores the lower eight bits (C[23:16]) for an update that takes place with the second write access along with C[15:0]. If the serial interface is used, input data containing control register contents are required with each read access to the device in this mode (combined read/write access). For initialization purposes, all 32 bits of the register should be set (bit C16 must be set to '1' during that access to allow the update of the entire register content). To minimize switching noise on the interface, an update of the first eight bits (C[31:24]) with the remaining bits held low can be performed thereafter. Figure 31 illustrates the different control register update options. Control Register (CR); Default Value = 0x000003FF The control register settings can only be changed in software mode and are not affected when switching to hardware mode thereafter. The register values are independent from input pin settings. Changes are active with the rising edge of WR in parallel interface mode or with the 32nd falling SCLK edge of the access in which the register content has been updated in serial mode. Optionally, the register can also be partially updated by writing only the upper eight bits (C[31:24]). The CR content is defined in Table 3. 22 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com RESET (or Power-Up) BUSY (C20 = C21 = 0) PAR/SER = 1 FS C[31:0] Initialization Data SDI Continuous Update Continuous Update C [31:24] C [31:24] PAR/SER = 0; WORD/BYTE = 0 CS WR Initialization Data DB[15:0] C [31:16] Update C [15:0] C [31:24] C [15:0] PAR/SER = 0; WORD/BYTE = 1 WR Initialization Data DB[15:8] C [31:24] C [23:16] C [15:8] Update C [7:0] C [31:24] C [23:16] Figure 31. Control Register Update Options 23 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Table 3. Control Register (CR) Map ACTIVE IN HARDWARE MODE BIT NAME DESCRIPTION C31 CH_C 0 = Channel pair C disabled for next conversion (default) 1 = Channel pair C enabled No C30 CH_B 0 = Channel pair B disabled for next conversion (default) 1 = Channel pair B enabled No C29 CH_A 0 = Channel pair A disabled for next conversion (default) 1 = Channel pair A enabled No C28 RANGE_C 0 = Input voltage range selection for channel pair C: 4VREF (default) 1 = Input voltage range selection for channel pair C: 2VREF No C27 RANGE_B 0 = Input voltage range selection for channel pair B: 4VREF (default) 1 = Input voltage range selection for channel pair B: 2VREF No C26 RANGE_A 0 = Input voltage range selection for channel pair A: 4VREF (default) 1 = Input voltage range selection for channel pair A: 2VREF No C25 REFEN 0 = Internal reference source disabled (default) 1 = Internal reference source enabled No C24 REFBUF 0 = Internal reference buffers enabled (default) 1 = Internal reference buffers disabled No C23 SEQ 0 = Sequential convert start mode disabled (default) 1 = Sequential convert start mode enabled (bit 11 must be '1' in this case) No C22 A-NAP 0 = Normal operation (default) 1 = Auto-NAP feature enabled Yes C21 BUSY/INT 0 = BUSY/INT pin in normal mode (BUSY) (default) 1 = BUSY/INT pin in interrupt mode (INT) Yes C20 BUSY L/H 0 = BUSY/INT active high (default) 1 = BUSY/INT active low Yes C19 Don’t use This bit is always set to '0' — 0 = Internal reference voltage: 2.5V (default) 1 = Internal reference voltage: 3V Yes C18 VREF C17 READ_EN 0 = Normal operation (conversion results available on SDO_x) (default) 1 = Control register contents output on SDO_x with next access Yes C16 C23:0_EN 0 = Control register bits C[31:24] update only (serial mode only) (default) 1 = Entire control register update enabled (serial mode only) Yes C15 PD_C 0 = Normal operation (default) 1 = Power-down for channel pair C enabled (bit 31 must be '0' in this case) Yes C14 PD_B 0 = Normal operation (default) 1 = Power-down for channel pair B enabled (bit 30 must be '0' in this case) Yes C13 PD_A 0 = Normal operation (default) 1 = Power-down for channel pair A enabled (bit 29 must be '0' in this case) Yes C12 Don't use This bit is always '0' — C11 CLKSEL 0 = Normal operation with internal conversion clock (mandatory in hardware mode) (default) 1 = External conversion clock (applied through pin 27) used No C10 CLKOUT_EN 0 = Normal operation (default) 1 = Internal conversion clock available at pin 27 No C9 REFDAC[9] Bit 9 (MSB) of reference DAC value; default = 1 Yes C8 REFDAC[8] Bit 8 of reference DAC value; default = 1 Yes C7 REFDAC[7] Bit 7 of reference DAC value; default = 1 Yes C6 REFDAC[6] Bit 6 of reference DAC value; default = 1 Yes C5 REFDAC[5] Bit 5 of reference DAC value; default = 1 Yes C4 REFDAC[4] Bit 4 of reference DAC value; default = 1 Yes C3 REFDAC[3] Bit 3 of reference DAC value; default = 1 Yes C2 REFDAC[2] Bit 2 of reference DAC value; default = 1 Yes C1 REFDAC[1] Bit 1 of reference DAC value; default = 1 Yes C0 REFDAC[0] Bit 0 (LSB) of reference DAC value; default = 1 Yes 24 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com XCLK CONVST_A (1) EOC CHBx EOC CHCx (1) CONVST_B CONVST_C tCCLK BUSY (C20 = 0) CS Sequential Mode (in Software Mode with External Conversion clock Only) The three channel pairs of the ADS8555 can be run in sequential mode, with the corresponding CONVST_x signals interleaved, when an external clock is used. To activate the device in sequential mode, CR bits C11 (CLKSEL) and C23 (SEQ) must be asserted. In this case, the BUSY output indicates a finished conversion by going low (when C20 = 0) or high (when C20 = 1) for only a single conversion clock cycle in case of ongoing conversions of any other channel pairs. Figure 32 shows the behavior of the BUSY output in this mode. Each conversion start (1) The serial interface of the ADS8555 supports a daisy-chain feature that allows cascading of multiple devices to minimize the board space requirements and simplify routing of the data and control lines. In this case, pins DB5/DCIN_A, DB4/DCIN_B, and DB3/DCIN_C are used as serial data inputs for channels A, B, and C, respectively. Figure 33 shows an example of a daisy-chain connection of three devices sharing a common CONVST line to allow simultaneous sampling of 18 analog channels along with the corresponding timing diagram. To activate the daisy-chain mode, the DCEN pin must be pulled high. As a result of the time specifications tS1, tH1, and tD3, the maximum SCLK frequency that may be used in daisy-chain mode is 27.78MHz (assuming 50% duty cycle). should be initiated during the high phase of the external clock, as shown in Figure 32. The minimum time required between two CONVST_x pulses in the time required to read the conversion result of a channel (pair). EOC CHAx Daisy-Chain Mode (in Serial Mode Only) RD CH A0 D[15:0] CH A1 CH B0 CH B1 CH C0 CH C1 (1) EOC = end of conversion (internal signal). Figure 32. Sequential Mode Timing Output Data Format The data output format of the ADS8555 is binary twos complement, as shown in Table 4. Table 4. Output Data Format DESCRIPTION INPUT VOLTAGE VALUE BINARY CODE (HEXADECIMAL CODE) Positive full-scale +4VREF or +2VREF 0111 1111 1111 1111 (7FFF) Midscale + 0.5LSB VREF/(2 × resolution) 0000 0000 0000 0000 (0000) Midscale – 0.5LSB –VREF/(2 × resolution) 1111 1111 1111 1111 (FFFF) Negative full-scale –4VREF or –2VREF 1000 0000 0000 0000 (8000) 25 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com CONVST FS SCLK ADS8555 #1 ADS8555 #2 ADS8555 #3 CONVST_A CONVST_A CONVST_A FS SCLK FS SCLK FS SCLK DCIN_A DCIN_B DCIN_C SDO_A SDO_B SDO_C DCEN = ‘0’ SDO_A SDO_B SDO_C DCIN_A DCIN_B DCIN_C DCEN = ‘1’ SDO_A SDO_B SDO_C To Processing Unit DCEN = ‘1’ CONVST BUSY (C20 = C21 = 0) FS SDO_x #3 Don’t Care 16-Bit Data CHx0 ADS8555 #3 16-Bit Data CHx1 ADS8555 #3 16-Bit Data CHx0 ADS8555 #2 16-Bit Data CHx1 ADS8555 #2 16-Bit Data CHx0 ADS8555 #1 16-Bit Data CHx1 ADS8555 #1 Figure 33. Example of Daisy-Chaining Three ADS8555s Reset and Power-Down Modes AVDD (V) The device supports two reset mechanisms: a power-on reset (POR) and a pin-controlled reset (RESET) that can be issued using pin 28. Both the POR and RESET act as a master reset that causes any ongoing conversion to be interrupted, the control register content to be set to the default value, and all channels to be switched into sample mode. When the device is powered up, the POR sets the device in default mode when AVDD reaches 1.5V. When the device is powered down, the POR circuit requires AVDD to remain below 125mV at least 350ms to ensure proper discharging of internal capacitors and to ensure correct behavior of the device when powered up again. If the AVDD drops below 400mV but remains above 125mV (see the undefined zone in Figure 34), the internal POR capacitor does not discharge fully and the device requires a pin-controlled reset to perform correctly after the recovery of AVDD. 5.500 Specified Supply Voltage Range 5.000 4.500 4.000 3.000 2.000 POR Trigger Level 1.500 1.000 0.400 0.125 Undefined Zone 0 0.350 t (s) Figure 34. POR: Relevant Voltage Levels 26 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com The entire device, except the digital interface, can be powered down by pulling the STBY pin low (pin 24). As the digital interface section remains active, data can be retrieved while in stand-by mode. To power the part on again, the STBY pin must be brought high. The device is ready to start a new conversion after 10ms required to activate and settle the internal circuitry. This user-controlled approach can be used in applications that require lower data throughput rates and lowest power dissipation. The content of CR is not changed during standby mode. It is not required to perform a pin-controlled reset after returning to normal operation. The auto-NAP power-down mode is enabled by asserting the A-NAP bit (C22) in the control register. If the auto-NAP mode is enabled, the ADS8555 automatically reduces the current requirement to 6mA after finishing a conversion; thus, the end of conversion actually activates the power-down mode. Triggering a new conversion by applying a positive CONVST_x edge puts the device back into normal operation, starts the acquisition of the analog input, and automatically starts a new conversion six conversion clock cycles later. Therefore, a complete conversion cycle takes 24.5 conversion clock cycles; thus, the maximum throughput rate in auto-NAP power-down mode is reduced to a maximum of 380kSPS in serial mode, and 500kSPS in parallel mode. The internal reference remains active during the auto-NAP mode. Table 5 compares the analog current requirements of the device in the different modes. While the standby mode impacts the entire device, each device channel pair can also be individually switched off by setting control register bits C[15:13] (PD_x). When reactivated, the relevant channel pair requires 10ms to fully settle before starting a new conversion. The internal reference remains active, except all channels are powered down at the same time. Table 5. Maximum Analog Current (IAVDD) Demand of the ADS8555 ENABLED BY ACTIVATED BY NORMAL OPERATION TO POWERDOWN DELAY Normal operation 12mA/channel pair (maximum data rate) Power on CONVST_x — — — — Power off Auto-NAP 6mA A-NAP = 1 (CR bit) Each end of conversion At falling edge of BUSY CONVST_x Immediate 6 × tCCLK A-NAP = 0 (CR bit) Power-down of channel pair x 16μA (channel pair x) HW/SW = 1 PD_x = 1 (CR bit) Immediate PD_x = 0 (CR bit) Immediate after completing register update 10ms HW/SW = 0 Stand-by 50μA Power on STBY = 0 Immediate STBY = 1 Immediate 10ms Power off OPERATIONAL MODE ANALOG CURRENT (IAVDD) RESUMED BY POWER-UP TO NORMAL OPERATION DELAY POWER-UP TO NEXT CONVERSION START TIME DISABLED BY 27 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 GROUNDING All GND pins should be connected to a clean ground reference. This connection should be kept as short as possible to minimize the inductance of this path. It is recommended to use vias connecting the pads directly to the ground plane. In designs without ground planes, the ground trace should be kept as wide as possible. Avoid connections that are too close to the grounding point of a microcontroller or digital signal processor. Depending on the circuit density on the board, placement of the analog and digital components, and the related current loops, a single solid ground plane for the entire printed circuit board (PCB) or a dedicated analog ground area may be used. In case of a separated analog ground area, ensure a low-impedance connection between the analog and digital ground of the ADC by placing a bridge underneath (or next) to the ADC. Otherwise, even short undershoots on the digital interface lower than –300mV lead to the conduction of ESD diodes causing current flow through the substrate and degrading the analog performance. During PCB layout, care should be taken to avoid any return currents crossing sensitive analog areas or signals. SUPPLY The ADS8555 requires four separate supplies: the analog supply for the ADC (AVDD), the buffer I/O supply for the digital interface (BVDD), and the high-voltage supplies driving the analog input circuitry (HVDD and HVSS). Generally, there are no specific requirements with regard to the power sequencing of the device. However, when HVDD is supplied before AVDD, the internal ESD structure conducts, increasing IHVDD beyond the specified value. www.ti.com The AVDD supply provides power to the internal circuitry of the ADC. It can be set in the range of 4.5V to 5.5V. Because the supply current of the device is typically 30mA, it is not possible to use a passive filter between the digital board supply of the application and the AVDD pin. A linear regulator is recommended to generate the analog supply voltage. Each AVDD pin should be decoupled to AGND with a 100nF capacitor. In addition, a single 10μF capacitor should be placed close to the device but without compromising the placement of the smaller capacitor. Optionally, each supply pin can be decoupled using a 1μF ceramic capacitor without the requirement for a 10μF capacitor. The BVDD supply is only used to drive the digital I/O buffers and can be set in the range of 2.7V to 5.5V. This range allows the device to interface with most state-of-the-art processors and controllers. To limit the noise energy from the external digital circuitry to the device, BVDD should be filtered. A 10Ω resistor can be placed between the external digital circuitry and the device, because the current drawn is typically below 2mA (depending on the external loads). A bypass ceramic capacitor of 1μF (or alternatively, a pair of 100nF and 10μF capacitors) should be placed between the BVDD pin and pin 8. The high-voltage supplies (HVSS and HVDD) are connected to the analog inputs. Noise and glitches on these supplies directly couple into the input signals. Place a 100nF ceramic decoupling capacitor, located as close to the device as possible, between each of pins 30, 31, and AGND. An additional 10μF capacitor is used that should be placed close to the device but without compromising the placement of the smaller capacitor. Figure 35 shows a layout recommendation for the ADS8555 along with the proper decoupling and reference capacitor placement and connections. 28 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com ADS8555 Top View To AVDD To AVDD AVDD Source To DUT 10 mF AVDD 51 0.1mF AGND 54 0.47mF AGND 56 10mF AGND 58 10mF AGND 61 AGND 62 10mF 1 48 2 AVDD 3 AVDD 4 45 5 AGND 6 AGND 7 42 BGND AVDD BVDD AVDD 10 39 14 AVDD 15 AVDD 16 33 17 18 19 20 21 22 23 24 0.1mF LEGEND To AVDD 27 28 29 0.1 mF To AVDD 0.1 mF 0.1 mF To AVDD 0.1 mF 0.1 mF To AVDD 0.1 mF AGND 36 HVDD AGND 13 HVSS AGND AVDD 11 12 AGND 1 mF To BVDD 63 AVDD 64 AGND 0.1mF 0.1mF 0.1mF 10mF 10mF To HVSS/HVDD TOP layer; copper pour and traces Lower layer; AGND area Lower layer; BGND area Via (1) All 0.1μF, 0.47μF, and 1μF capacitors should be placed as close to the ADS8555 as possible. (2) All 10μF capacitors should be close to the device but without compromising the placement of the smaller capacitors. Figure 35. Layout Recommendation 29 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com APPLICATION INFORMATION The minimum configuration of the ADS8555 in parallel mode is shown in Figure 36. In this case, the BUSY signal is not used while the SW generates the required signals in a timely manner. TI’s OPA2211 is used as an input driver, supporting bandwidth that allows running the device at the maximum data rate. R1 AGND The actual values of the resistors and capacitors depend on the bandwidth and performance requirements of the application. For highest data rate, it is recommended to use a filter capacitor value of 1nF and a series resistor of 22Ω to fulfill the settling requirements to an accuracy level of 16 bits within the acquisition time of 280ns. R2 HVDD ADS8555 RF CH_A0 Input #1 CF OPA2211 CF RF Input #2 BVDD AGND STBY CH_A1 RANGE REFEN/WR HVSS R1 R2 REFC_A 10mF AGND R1 AGND CONVST_A 10mF R2 CONVST_B REFC_B AGND CONVST_C HVDD RESET RD CH_B0 Input #3 CF OPA2211 DB[15:0] AGND CF RF Input #4 Host Controller CS RF CH_B1 HVSS R1 R2 REFIO 0.47mF AGND R1 AGND R2 10mF REFC_C AGND HVDD ADS8555 AVDD RF CH_C0 Input #5 CF OPA2211 HW/SW AVDD PAR/SER AVDD WORD/BYTE AGND RF Input #6 AVDD AVDD BVDD BVDD AGND BGND CF AGND CH_C1 1mF BGND AGND BGND AGND AGND HVSS R1 AGND R2 HVSS AGND AGND 0.1mF AGND 10mF 0.1mF 0.1mF 0.1mF 0.1mF 0.1mF 0.1mF 0.1mF AGND HVSS AGND AGND AGND AGND AVDD AVDD 0.1mF 10mF 0.1mF 10mF AGND HVDD AVDD HVSS AVDD AVDD AVDD Figure 36. Minimum Configuration in Parallel Interface Mode 30 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 ADS8555 SBAS531B – DECEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (January 2011) to Revision B Page • Changed description of pin 18 in Pin Descriptions table ...................................................................................................... 8 • Added clarification of INT in BUSY/INT section .................................................................................................................. 20 • Changed bit C20 in Table 3 ................................................................................................................................................ 24 • Updated Table 5 ................................................................................................................................................................. 27 Changes from Original (December 2010) to Revision A Page • Changed description of CONVST_C, CONVST_B, and CONVST_A pins in Pin Descriptions table ................................... 8 • Changed description of CONVST_x section ....................................................................................................................... 19 • Changed first paragraph of BUSY/INT section ................................................................................................................... 20 31 © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8555 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) ADS8555SPM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 8555 ADS8555SPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ADS 8555 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 5-Mar-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS8555SPMR Package Package Pins Type Drawing LQFP PM 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 13.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 2.1 16.0 24.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 5-Mar-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8555SPMR LQFP PM 64 1000 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. 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