TYPICAL APPLICATION CIRCUITS
Input voltage range: 3.3 V to 20 V
Maximum output current: 500 mA
Low noise: 15 µV rms for fixed output versions
PSRR performance of 60 dB at 10 kHz, VOUT = 3.3 V
Reverse current protection
Low dropout voltage: 350 mV at 500 mA
Initial accuracy: ±0.8%
Accuracy over line, load, and temperature: −2% to +1%
Low quiescent current: 900 μA at VIN = 10 V, IOUT = 500 mA
Low shutdown current: <50 µA at VIN = 12 V, stable with small
1 µF ceramic output capacitor
3 fixed output voltage options: 1.8, 3.3 V and 5 V
Adjustable output from 1.22 V to 19 V
Programmable soft start for inrush current control
Foldback current-limit and thermal overload protection
User programmable precision UVLO/enable
Power-good indicator
8-lead LFCSP and 8-lead SOIC packages
VIN = 8V
CIN +
1µF
VIN
VOUT
SENSE
ON
OFF
100kΩ
VOUT = 5V
+ COUT
1µF
100kΩ
EN/
UVLO
PG
PG
100kΩ
GND SS
11641-001
FEATURES
CSS
Figure 1. ADP7105 with Fixed Output Voltage, 5 V
VIN = 8V
CIN +
1µF
VIN
VOUT
40.2kΩ
ADJ
ON
OFF
VOUT = 5V
+ COUT
1µF
13kΩ
100kΩ
100kΩ
EN/
UVLO
100kΩ
PG
PG
GND SS
CSS
11641-002
Data Sheet
20 V, 500 mA, Low Noise LDO Regulator
with Soft Start
ADP7105
Figure 2. ADP7105 with Adjustable Output Voltage, 5 V
APPLICATIONS
Regulation of noise sensitive applications: ADC and DAC
circuits, precision amplifiers, high frequency oscillators,
clocks, and PLLs
Communications and infrastructure
Medical and healthcare
Industrial and instrumentation
GENERAL DESCRIPTION
The ADP7105 is a CMOS, low dropout (LDO)linear regulator
that operates from 3.3 V to 20 V and provides up to 500 mA of
output current. This high input voltage LDO is ideal for regulation of high performance analog and mixed-signal circuits
operating from 1.22 V to 19 V rails. Using an advanced proprietary architecture, the ADP7105 provides high power supply
rejection and low noise, and achieves excellent line and load
transient response with only a small 1 µF ceramic output
capacitor.
The ADP7105 is available in three fixed output voltage options
and an adjustable version that allows output voltages ranging
from 1.22 V to 19 V via an external feedback divider. The
ADP7105 allows an external soft start capacitor to be connected
to program the startup.
Rev. 0
Note that throughout this data sheet, the sense function
(SENSE) of the SENSE/ADJ pin applies to fixed output voltage
models only, whereas the adjust input function (ADJ) applies to
adjustable output voltage models only. For example, Figure 1
shows the sense function, and Figure 2 shows the adjust input
function.
The ADP7105 output noise voltage is 15 μV rms and is independent of the output voltage. A digital power-good output
allows power system monitors to check the health of the output
voltage. A user programmable precision undervoltage lockout
function facilitates sequencing of multiple power supplies.
The ADP7105 is available in 8-lead, 3 mm × 3 mm LFCSP
and 8-lead SOIC packages. The LFCSP offers a very compact
solution and provides excellent thermal performance for
applications that require up to 500 mA of output current in a
small, low profile footprint.
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Technical Support
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ADP7105
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 17
Applications ....................................................................................... 1
Applications Information .............................................................. 18
Typical Application Circuits............................................................ 1
Capacitor Selection .................................................................... 18
General Description ......................................................................... 1
Programmable Undervoltage Lockout (UVLO) .................... 19
Revision History ............................................................................... 2
Soft Start Function ..................................................................... 19
Specifications..................................................................................... 3
Power-Good Feature .................................................................. 20
Input and Output Capacitor, Recommended Specifications .. 4
Noise Reduction of the Adjustable ADP7105 ........................ 20
Absolute Maximum Ratings ............................................................ 5
Current-Limit and Thermal Overload Protection ................. 21
Thermal Data ................................................................................ 5
Thermal Considerations............................................................ 21
Thermal Resistance ...................................................................... 5
Printed Circuit Board Layout Considerations ............................ 24
ESD Caution .................................................................................. 5
Outline Dimensions ....................................................................... 25
Pin Configurations and Function Descriptions ........................... 6
Ordering Guide .......................................................................... 26
Typical Performance Characteristics ............................................. 7
REVISION HISTORY
7/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
Data Sheet
ADP7105
SPECIFICATIONS
VIN = (VOUT + 1 V) or 3.3 V (whichever is greater), EN = VIN, IOUT = 10 mA, CIN = COUT = 1 µF, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
INPUT VOLTAGE RANGE
OPERATING SUPPLY CURRENT
Symbol
VIN
IGND
SHUTDOWN CURRENT
IGND-SD
INPUT REVERSE CURRENT
IREV-INPUT
OUTPUT VOLTAGE ACCURACY
Fixed Output Voltage Accuracy
Adjustable Output Voltage
Accuracy
VOUT
VADJ
LINE REGULATION
LOAD REGULATION 1
∆VOUT/∆VIN
∆VOUT/∆IOUT
ADJ INPUT BIAS CURRENT 2
ADJI-BIAS
SENSE INPUT BIAS CURRENT2
SENSEI-BIAS
DROPOUT VOLTAGE 3
VDROPOUT
START-UP TIME 4
tSTART-UP
CURRENT-LIMIT THRESHOLD 5
PG OUTPUT LOGIC LEVEL
PG Output Logic High
PG Output Logic Low
PG OUTPUT THRESHOLD
Output Voltage Falling
Output Voltage Rising
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
ILIMIT
PGHIGH
PGLOW
Test Conditions/Comments
IOUT = 100 µA, VIN = 10 V
IOUT = 100 µA, VIN = 10 V, TJ = −40°C to +125°C
IOUT = 10 mA, VIN = 10 V
IOUT = 10 mA, VIN = 10 V, TJ = −40°C to +125°C
IOUT = 300 mA, VIN = 10 V
IOUT = 300 mA, VIN = 10 V, TJ = −40°C to +125°C
IOUT = 500 mA, VIN = 10 V
IOUT = 500 mA, VIN = 10 V, TJ = −40°C to +125°C
EN = GND, VIN = 12 V
EN = GND, VIN = 12 V, TJ = −40°C to +125°C
EN = GND, VIN = 0 V, VOUT = 20 V
EN = GND, VIN = 0 V, VOUT = 20 V, TJ = −40°C to
+125°C
+0.8
+1
%
%
1.23
V
1.232
V
+0.015
10
%/V
%/A
%/A
nA
1
μA
1050
750
1400
900
40
1600
50
75
0.3
1.196
1.21
1.22
−0.015
0.2
0.75
20
1000
mV
mV
mV
mV
mV
mV
mV
mV
µs
ms
mA
0.4
V
V
40
100
175
200
325
350
550
625
Rev. 0 | Page 3 of 28
5
Unit
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
900
1 mA < IOUT < 500 mA, VIN = (VOUT + 1 V) to 20 V,
TJ = −40°C to +125°C
VIN = (VOUT + 1 V) to 20 V, TJ = −40°C to +125°C
1 mA < IOUT < 500 mA
1 mA < IOUT < 500 mA, TJ = −40°C to +125°C
1 mA < IOUT < 500 mA, VIN = (VOUT + 1 V) to 20 V,
ADJ connected to VOUT
1 mA < IOUT < 500 mA, VIN = (VOUT + 1 V) to 20 V,
SENSE connected to VOUT, VOUT = 1.5 V
IOUT = 10 mA
IOUT = 10 mA, TJ = −40°C to +125°C
IOUT = 150 mA
IOUT = 150 mA, TJ = −40°C to +125°C
IOUT = 300 mA
IOUT = 300 mA, TJ = −40°C to +125°C
IOUT = 500 mA
IOUT = 500 mA, TJ = −40°C to +125°C
CSS = 0 nF, IOUT = 10 mA
CSS = 10 nF, IOUT = 10 mA
TJ rising
Max
20
450
−0.8
−2
IOH < 1 µA
IOL < 2 mA
Typ
400
IOUT = 10 mA
1 mA < IOUT < 500 mA, VIN = (VOUT + 1 V) to 20 V,
TJ = −40°C to +125°C
IOUT = 10 mA
PGFALL
PGRISE
TSSD
TSSD-HYS
Min
3.3
625
11.5
775
1.0
−9.2
−6.5
%
%
150
15
°C
°C
ADP7105
Data Sheet
Parameter
SOFT START SOURCE CURRENT
PROGRAMMABLE EN/UVLO
UVLO Threshold Rising
UVLO Threshold Falling
Symbol
SSI-SOURCE
Test Conditions/Comments
SS = GND
Min
Typ
1
Max
Unit
µA
UVLORISE
UVLOFALL
1.18
1.23
1.13
1.28
V
V
UVLO Hysteresis Current
Enable Pull-Down Current
Start Threshold
Shutdown Threshold
Hysteresis
OUTPUT NOISE
UVLOHYS
IEN-IN
VSTART
VSHUTDOWN
3.3 V ≤ VIN ≤ 20 V, TJ = −40°C to +125°C
3.3 V ≤ VIN ≤ 20 V, TJ = −40°C to +125°C, 10 kΩ in
series with the enable input pin
VEN > 1.25 V, TJ = −40°C to +125°C
EN = VIN
TJ = −40°C to +125°C
TJ = −40°C to +125°C
7.5
9.8
500
12
250
15
15
15
15
18
µA
nA
V
V
mV
µV rms
µV rms
µV rms
µV rms
µV rms
30
µV rms
65
µV rms
50
50
60
60
50
60
60
60
80
80
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
POWER SUPPLY REJECTION RATIO
OUTNOISE
PSRR
3.2
2.45
10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.8 V
10 Hz to 100 kHz, VIN = 6.3 V, VOUT = 3.3 V
10 Hz to 100 kHz, VIN = 8 V, VOUT = 5 V
10 Hz to 100 kHz, VIN = 12 V, VOUT = 9 V
10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.5 V,
adjustable mode
10 Hz to 100 kHz, VIN = 12 V, VOUT = 5 V, adjustable
mode
10 Hz to 100 kHz, VIN = 20 V, VOUT = 15 V,
adjustable mode
100 kHz, VIN = 4.3 V, VOUT = 3.3 V
100 kHz, VIN = 6 V, VOUT = 5 V
10 kHz, VIN = 4.3 V, VOUT = 3.3 V
10 kHz, VIN = 6 V, VOUT = 5 V
100 kHz, VIN = 3.3 V, VOUT = 1.8 V, adjustable mode
100 kHz, VIN = 6 V, VOUT = 5 V, adjustable mode
100 kHz, VIN = 16 V, VOUT = 15 V, adjustable mode
10 kHz, VIN = 3.3 V, VOUT = 1.8 V, adjustable mode
10 kHz, VIN = 6 V, VOUT = 5 V, adjustable mode
10 kHz, VIN = 16 V, VOUT = 15 V, adjustable mode
Based on an endpoint calculation using 1 mA and 500 mA loads. See Figure 6 for typical load regulation performance for loads less than 1 mA.
The adjust input function (ADJ) of the SENSE/ADJ pin applies to adjustable output voltage models only; whereas the sense function (SENSE) applies to fixed output
voltage models only.
3
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This specification applies only for
output voltages greater than 3.0 V.
4
Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value.
5
Current-limit threshold is defined as the current at which the output voltage falls to 90% of the specified typical value. For example, the current limit for a 5.0 V output
voltage is defined as the current that causes the output voltage to fall to 90% of 5.0 V, or 4.5 V.
1
2
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 2.
Parameter
Minimum Input and Output Capacitance 1
Capacitor ESR
1
Symbol
CMIN
RESR
Test Conditions/Comments
TA = −40°C to +125°C
TA = −40°C to +125°C
Min
0.7
0.001
Typ
Max
0.2
Unit
µF
Ω
Ensure that the minimum input and output capacitance is greater than 0.7 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with any LDO regulator.
Rev. 0 | Page 4 of 28
Data Sheet
ADP7105
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
VOUT to GND
EN/UVLO to GND
PG to GND
SENSE/ADJ to GND
SS to GND
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
−0.3 V to +22 V
−0.3 V to +20 V
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to VOUT
−0.3 V to +3.6 V
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP7105 can be damaged when the junction
temperature (TJ) limit is exceeded. Monitoring ambient
temperature does not guarantee that TJ is within the specified
temperature limits. In applications with high power dissipation
and poor printed circuit board (PCB) thermal resistance, the
maximum ambient temperature may need to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (TJ) of
the device is dependent on the ambient temperature (TA), the
power dissipation of the device (PD), and the junction-to-ambient
thermal resistance of the package (θJA).
Maximum junction temperature (TJ) is calculated from the
ambient temperature (TA) and power dissipation (PD) using the
formula
board design is required. The value of θJA may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θJA are based on a 4-layer, 4 in. × 3 in. circuit
board. See JEDEC JESD51-7 and JESD51-9 for detailed
information on the board construction. For additional
information, see the AN-772 Application Note, A Design and
Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP), available at www.analog.com.
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. The package ΨJB is based on modeling and
calculation using a 4-layer board. JEDEC JESD51-12, Guidelines
for Reporting and Using Electronic Package Thermal Information,
states that thermal characterization parameters are not the same
as thermal resistances. ΨJB measures the component power
flowing through multiple thermal paths rather than through a
single path as in thermal resistance, θJB. Therefore, ΨJB thermal
paths include convection from the top of the package as well as
radiation from the package, factors that make ΨJB more useful
in real-world applications. Maximum junction temperature (TJ)
is calculated from the board temperature (TB) and power
dissipation (PD) using the formula
TJ = TB + (PD × ΨJB)
See JESD51-8 and JESD51-12 for more detailed information
about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
θJC is a parameter for surface-mount packages with top
mounted heat sinks. θJC is presented here for reference only.
Table 4. Thermal Resistance
Package Type
8-Lead LFCSP
8-Lead SOIC
ESD CAUTION
TJ = TA + (PD × θJA)
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
Rev. 0 | Page 5 of 28
θJA
40.1
48.5
θJC
27.1
58.4
ΨJB
17.2
31.3
Unit
°C/W
°C/W
ADP7105
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
8 VIN
GND 3
TOP VIEW
(Not to Scale)
SS 4
VOUT 1
7 PG
6 GND
5 EN/UVLO
NOTES
1. IT IS HIGHLY RECOMMENDED THAT THE
EXPOSED PAD ON THE BOTTOM OF THE
PACKAGE BE CONNECTED TO THE GROUND
PLANE ON THE BOARD.
8
ADP7105
VIN
PG
TOP VIEW
GND 3 (Not to Scale) 6 GND
5 EN/UVLO
SS 4
SENSE/ADJ 2
7
NOTES
1. IT IS HIGHLY RECOMMENDED THAT THE
EXPOSED PAD ON THE BOTTOM OF THE
PACKAGE BE CONNECTED TO THE GROUND
PLANE ON THE BOARD.
11641-003
ADP7105
Figure 3. Pin Configuration, LFCSP Package
11641-004
VOUT 1
SENSE/ADJ 2
Figure 4. Pin Configuration, Narrow-Body SOIC Package
Table 5. Pin Function Descriptions
Pin No.
1
2
Mnemonic
VOUT
SENSE/ADJ
3
4
5
GND
SS
EN/UVLO
6
7
GND
PG
8
VIN
EPAD
Description
Regulated Output Voltage. Bypass VOUT to GND with a 1 µF or greater capacitor.
Sense (SENSE). SENSE measures the actual output voltage at the load and feeds it to the error
amplifier. Connect SENSE as close as possible to the load to minimize the effect of IR drop
between the regulator output and the load. This function applies to fixed voltage models only.
Adjust Input (ADJ). An external resistor divider sets the output voltage. This function applies to
adjustable voltage models only.
Ground.
Soft Start. A capacitor connected to this pin determines the soft start time.
Enable Input (EN). Drive EN high to turn on the regulator; drive EN low to turn off the regulator.
For automatic startup, connect EN to VIN.
Programmable Undervoltage Lockout (UVLO). When the programmable UVLO function is used,
the upper and lower thresholds are determined by the programming resistors.
Ground.
Power Good. This open-drain output requires an external pull-up resistor to VIN or VOUT. If the
part is in shutdown mode, current-limit mode, or thermal shutdown, or if VOUT falls below 90%
of the nominal output voltage, PG immediately transitions low. If the power-good function is
not used, the pin can be left open or connected to ground.
Regulator Input Supply. Bypass VIN to GND with a 1 µF or greater capacitor.
Exposed Pad. The exposed pad on the bottom of the package enhances thermal performance
and is electrically connected to GND inside the package. It is highly recommended that the
exposed pad be connected to the ground plane on the board.
Rev. 0 | Page 6 of 28
Data Sheet
ADP7105
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 7.5 V, VOUT = 5 V, IOUT = 10 mA, CIN = COUT = 1 µF, TA = 25°C, unless otherwise noted.
3.35
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
LOAD = 500mA
1000
GROUND CURRENT (µA)
3.33
3.31
3.29
3.27
800
600
400
200
–40
–5
25
85
0
11641-005
3.25
125
TJ (°C)
–40
–5
25
85
11641-008
VOUT (V)
1200
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
LOAD = 500mA
125
TJ (°C)
Figure 8. Ground Current vs. Junction Temperature, VOUT = 3.3 V
Figure 5. Output Voltage vs. Junction Temperature, VOUT = 3.3 V
800
3.35
700
GROUND CURRENT (µA)
VOUT (V)
3.33
3.31
3.29
600
500
400
300
200
3.27
1
10
100
1000
ILOAD (mA)
0
0.1
11641-006
3.25
0.1
1000
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
LOAD = 500mA
GROUND CURRENT (µA)
1000
3.29
3.27
800
600
400
4
6
8
10
12
14
16
18
VIN (V)
20
0
4
6
8
10
12
14
16
18
VIN (V)
Figure 7. Output Voltage vs. Input Voltage, VOUT = 3.3 V
Figure 10. Ground Current vs. Input Voltage, VOUT = 3.3 V
Rev. 0 | Page 7 of 28
20
11641-010
200
11641-007
VOUT (V)
1200
3.31
3.25
100
Figure 9. Ground Current vs. Load Current, VOUT = 3.3 V
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
LOAD = 500mA
3.33
10
ILOAD (mA)
Figure 6. Output Voltage vs. Load Current, VOUT = 3.3 V
3.35
1
11641-009
100
ADP7105
120
1200
GROUND CURRENT (µA)
140
SHUTDOWN CURRENT (µA)
1400
3.3V
4.0V
6.0V
8.0V
12.0V
20.0V
100
80
60
40
1000
800
600
400
200
20
–25
0
25
50
75
100
0
3.1
11641-011
0
–50
125
TEMPERATURE (°C)
3.3
3.4
3.5
3.6
3.7
Figure 14. Ground Current vs. Input Voltage (in Dropout), VOUT = 3.3 V
5.05
VOUT = 3.3V
TA = 25°C
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
LOAD = 500mA
5.04
300
5.03
250
5.02
200
VOUT (V)
DROPOUT VOLTAGE (mV)
3.2
VIN (V)
Figure 11. Shutdown Current vs. Temperature at Various Input Voltages
350
LOAD = 5mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 300mA
LOAD = 500mA
11641-014
160
Data Sheet
150
5.01
5.00
4.99
4.98
100
4.97
50
1
10
100
1000
ILOAD (mA)
4.95
11641-012
0
–40°C
–5°C
25°C
85°C
125°C
TJ (°C)
11641-015
4.96
Figure 15. Output Voltage vs. Junction Temperature, VOUT = 5 V
Figure 12. Dropout Voltage vs. Load Current, VOUT = 3.3 V
5.05
3.4
5.04
3.3
5.03
VOUT (V)
5.02
3.1
3.0
5.00
4.98
LOAD = 5mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 300mA
LOAD = 500mA
2.8
3.2
3.3
3.4
VIN (V)
3.5
3.6
3.7
4.97
4.96
4.95
0.1
1
10
100
ILOAD (mA)
Figure 16. Output Voltage vs. Load Current, VOUT = 5 V
Figure 13. Output Voltage vs. Input Voltage (in Dropout), VOUT = 3.3 V
Rev. 0 | Page 8 of 28
1000
11641-016
2.9
2.7
3.1
5.01
4.99
11641-013
VOUT (V)
3.2
Data Sheet
5.05
ADP7105
300
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
LOAD = 500mA
5.03
5.02
VOUT (V)
VOUT = 5V
TA = 25°C
250
DROPOUT VOLTAGE (mV)
5.04
5.01
5.00
4.99
4.98
200
150
100
4.97
50
6
8
10
12
14
16
18
20
VIN (V)
0
11641-017
1
1000
Figure 20. Dropout Voltage vs. Load Current, VOUT = 5 V
1000
5.05
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
900
800
5.00
4.95
4.90
600
4.85
VOUT (V)
700
500
400
4.80
4.75
4.70
200
4.65
100
4.60
–40
–5
25
85
4.55
4.8
11641-118
0
125
TJ (°C)
LOAD = 5mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 300mA
LOAD = 500mA
4.9
5.0
5.1
5.2
5.3
5.4
VIN (V)
11641-019
300
Figure 21. Output Voltage vs. Input Voltage (in Dropout), VOUT = 5 V
700
2500
600
2000
GROUND CURRENT (µA)
Figure 18. Ground Current vs. Junction Temperature, VOUT = 5 V
500
400
300
200
1500
1000
500
0
100
0
0.1
1
10
100
ILOAD (mA)
1000
11641-119
GROUND CURRENT (µA)
100
ILOAD (mA)
Figure 17. Output Voltage vs. Input Voltage, VOUT = 5 V
GROUND CURRENT (µA)
10
–500
4.80
LOAD = 5mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 300mA
LOAD = 500mA
4.90
5.00
5.10
5.20
5.30
5.40
VIN (V)
Figure 22. Ground Current vs. Input Voltage (in Dropout), VOUT = 5 V
Figure 19. Ground Current vs. Load Current, VOUT = 5 V
Rev. 0 | Page 9 of 28
11641-020
4.95
11641-018
4.96
ADP7105
1.85
900
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
LOAD = 500mA
800
700
GROUND CURRENT (µA)
1.83
VOUT (V)
Data Sheet
1.81
1.79
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
600
500
400
300
200
1.77
–40
–5
25
85
0
11641-021
1.75
125
TJ (°C)
–40
25
–5
85
11641-126
100
125
TJ (°C)
Figure 23. Output Voltage vs. Junction Temperature, VOUT = 1.8 V
Figure 26. Ground Current vs. Junction Temperature, VOUT = 1.8 V
1.85
700
600
GROUND CURRENT (µA)
VOUT (V)
1.83
1.81
1.79
500
400
300
200
1.77
1
10
100
1000
ILOAD (mA)
0
11641-022
1.75
0.1
0.1
1000
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
LOAD = 500mA
GROUND CURRENT (µA)
1000
1.79
1.77
800
600
400
2
4
6
8
10
12
14
16
18
VIN (V)
20
0
2
4
6
8
10
12
14
16
18
VIN (V)
Figure 28. Ground Current vs. Input Voltage, VOUT = 1.8 V
Figure 25. Output Voltage vs. Input Voltage, VOUT = 1.8 V
Rev. 0 | Page 10 of 28
20
11641-024
200
11641-023
VOUT (V)
1200
1.81
1.75
100
Figure 27. Ground Current vs. Load Current, VOUT = 1.8 V
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
LOAD = 500mA
1.83
10
ILOAD (mA)
Figure 24. Output Voltage vs. Load Current, VOUT = 1.8 V
1.85
1
11641-127
100
Data Sheet
5.07
5.06
2.0
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
LOAD = 500mA
REVERSE INPUT CURRENT (µA)
5.08
ADP7105
VOUT (V)
5.05
5.04
5.03
5.02
5.01
5.00
3.3V
4V
5V
6V
8V
10V
12V
15V
18V
20V
1.5
1.0
0.5
4.98
–5
25
85
0
–40
11641-025
–40
125
TJ (°C)
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
Figure 29. Output Voltage vs. Junction Temperature, VOUT = 5 V, Adjustable
11641-054
4.99
Figure 32. Reverse Input Current vs. Temperature, VIN = 0 V, Different
Voltages on VOUT
5.08
5.07
5.06
VOUT (V)
5.05
EN
1
5.04
5.03
VOUT
2
5.02
5.01
5.00
IIN
4.99
1
10
100
1000
ILOAD (mA)
5.08
0
5.07
–10
5.06
–20
5.05
–30
5.04
–40
5.03
5.02
M2.00ms
A CH1
T
5.95ms
3.00V
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
–50
–60
–70
5.01
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 300mA
LOAD = 500mA
6
8
10
–90
12
14
16
18
20
VIN (V)
Figure 31. Output Voltage vs. Input Voltage, VOUT = 5 V, Adjustable
–100
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
11641-028
4.99
–80
11641-027
5.00
4.98
CH2 2.00V
Figure 33. Start-Up Time, VEN and VIN = 6 V, CIN and COUT = 1 µF, CSS = 10 nF,
IOUT = 10 mA, VOUT = 5 V
PSRR (dB)
VOUT (V)
Figure 30. Output Voltage vs. Load Current, VOUT = 5 V, Adjustable
CH1 2.00V
CH3 20mA
11641-133
4.98
0.1
11641-026
3
Figure 34. Power Supply Rejection Ratio vs. Frequency, VOUT = 1.8 V, VIN = 3.3 V
Rev. 0 | Page 11 of 28
ADP7105
–20
–30
–40
–40
–50
–60
–80
–80
–90
–90
–100
10
–100
10
1k
10k
100k
1M
10M
Figure 35. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V, VIN = 4.8 V
0
–10
–20
0
–10
–20
–30
–40
–40
PSRR (dB)
–30
–60
–80
–80
–90
–90
–100
10
–100
10
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 36. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V, VIN = 4.3 V
0
–10
–20
0
–20
–30
–40
–40
PSRR (dB)
–30
–70
–80
–90
–90
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 37. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V, VIN = 3.8 V
1k
10k
100k
1M
10M
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
–100
11641-031
1k
100
–60
–80
100
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
–50
–70
–100
10
10M
Figure 39. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 6 V
–10
–60
1M
FREQUENCY (Hz)
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
–50
100k
–60
–70
1k
10k
–50
–70
100
1k
Figure 38. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 6.5 V
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
–50
100
FREQUENCY (Hz)
11641-030
PSRR (dB)
–60
–70
FREQUENCY (Hz)
PSRR (dB)
–50
–70
100
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
11641-032
PSRR (dB)
–30
11641-029
PSRR (dB)
–20
–10
11641-033
–10
0
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
11641-034
0
Data Sheet
Figure 40. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 5.5 V
Rev. 0 | Page 12 of 28
Data Sheet
–20
–30
–40
–40
PSRR (dB)
–30
–50
–60
–70
–80
–80
–90
–90
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
–100
11641-035
10
Figure 41. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 5.3 V
10
0
0
–10
–20
–20
–30
–30
–40
–40
–60
–70
–90
–100
10
–20
10M
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
–50
–60
100
1k
10k
100k
1M
10M
–100
0
0.50
0.75
1.00
0
–20
–40
–40
PSRR (dB)
–30
–60
–50
–60
–70
–70
–80
–80
–90
–90
1k
10k
100k
FREQUENCY (Hz)
1M
10M
–100
11641-037
–100
Figure 43. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 6 V,
Adjustable
1.50
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
–10
–50
1.25
Figure 45. Power Supply Rejection Ratio vs. Headroom Voltage, 100 Hz,
VOUT = 5 V
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
100
0.25
HEADROOM VOLTAGE (V)
–30
10
1M
–90
Figure 42. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 5.2 V
0
100k
–80
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
FREQUENCY (Hz)
–10
10k
–70
11641-036
–80
1k
Figure 44. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 6 V,
Adjustable with Noise Reduction Circuit
–10
–50
100
FREQUENCY (Hz)
PSRR (dB)
PSRR (dB)
–60
–70
–100
PSRR (dB)
–50
11641-038
–20
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
–10
11641-039
–10
PSRR (dB)
0
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
0
0.25
0.50
0.75
1.00
HEADROOM VOLTAGE (V)
1.25
1.50
11641-040
0
ADP7105
Figure 46. Power Supply Rejection Ratio vs. Headroom Voltage, 1 kHz,
VOUT = 5 V
Rev. 0 | Page 13 of 28
ADP7105
Data Sheet
0
10
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
–10
–20
NOISE (µV/√Hz)
–30
PSRR (dB)
–40
–50
–60
–70
3.3V
5V
5VADJ
5VADJ NR
1
0.1
–80
0.25
0.50
0.75
1.00
1.25
1.50
HEADROOM VOLTAGE (V)
0.01
10
11641-041
0
–20
10k
100k
Figure 50. Output Noise Spectral Density, ILOAD = 10 mA, COUT = 1 μF
LOAD = 500mA
LOAD = 300mA
LOAD = 100mA
LOAD = 10mA
LOAD = 1mA
–10
1k
FREQUENCY (Hz)
Figure 47. Power Supply Rejection Ratio vs. Headroom Voltage, 10 kHz,
VOUT = 5 V
0
100
11641-044
–90
–100
LOAD CURRENT
1
–30
PSRR (dB)
–40
–50
–60
OUTPUT VOLTAGE
2
–70
–80
0
0.25
0.50
0.75
1.00
1.25
1.50
HEADROOM VOLTAGE (V)
Figure 48. Power Supply Rejection Ratio vs. Headroom Voltage, 100 kHz,
VOUT = 5 V
CH1 500mA Ω
B
W
CH2 50mV
B
W
M 20µs
T 10%
A CH1
270mA
11641-045
–100
11641-042
–90
Figure 51. Load Transient Response, CIN = COUT = 1 μF, ILOAD = 1 mA to
500 mA, VOUT = 1.8 V, VIN = 5 V
30
LOAD CURRENT
25
15
OUTPUT VOLTAGE
2
3.3V
1.8V
5V
5VADJ
5VADJ NR
5
0
0.00001
0.0001
0.001
0.01
0.1
1
ILOAD (A)
Figure 49. Output Noise vs. Load Current and Output Voltage,
COUT = 1 μF
CH1 500mA Ω
B
W
CH2 50mV
B
W
M 20µs
T 10.2%
A CH1
280mA
11641-046
10
11641-043
NOISE (µV rms)
1
20
Figure 52. Load Transient Response, CIN = COUT = 1 μF, ILOAD = 1 mA to
500 mA, VOUT = 3.3 V, VIN = 5 V
Rev. 0 | Page 14 of 28
Data Sheet
ADP7105
INPUT VOLTAGE
LOAD CURRENT
1
OUTPUT VOLTAGE
2
B
W
B
CH2 50mV
W
M 20µs
T 10.2%
A CH1
300mA
1
11641-047
CH1 500mA Ω
CH1 1V
B
W
CH2 10mV
B
W
M 4µs
T 9.8%
A CH4
1.56V
11641-050
OUTPUT VOLTAGE
2
Figure 53. Load Transient Response, CIN = COUT = 1 μF, ILOAD = 1 mA to
500 mA, VOUT = 5 V, VIN = 7 V
Figure 56. Line Transient Response, CIN = COUT = 1 μF, ILOAD = 500 mA,
VOUT = 5 V
INPUT VOLTAGE
INPUT VOLTAGE
OUTPUT VOLTAGE
2
OUTPUT VOLTAGE
2
B
W
CH2 10mV
B
W
M 4µs
T 9.8%
A CH4
1.56V
11641-048
CH1 1V
CH1 1V
B
W
CH2 10mV
B
W
M 4µs
T 9.8%
A CH4
1.56V
11641-051
1
1
Figure 54. Line Transient Response, CIN = COUT = 1 μF, ILOAD = 500 mA,
VOUT = 1.8 V
Figure 57. Line Transient Response, CIN = COUT = 1 μF, ILOAD = 1 mA,
VOUT = 1.8 V
INPUT VOLTAGE
INPUT VOLTAGE
OUTPUT VOLTAGE
2
OUTPUT VOLTAGE
2
B
W
CH2 10mV
B
W
M 4µs
T 9.8%
A CH4
1.56V
11641-049
CH1 1V
CH1 1V
Figure 55. Line Transient Response, CIN = COUT = 1 μF, ILOAD = 500 mA,
VOUT = 3.3 V
B
W
CH2 10mV
B
W
M 4µs
T 9.8%
A CH4
1.56V
11641-052
1
1
Figure 58. Line Transient Response, CIN = COUT = 1 μF, ILOAD = 1 mA,
VOUT = 3.3 V
Rev. 0 | Page 15 of 28
ADP7105
Data Sheet
INPUT VOLTAGE
1
CH1 1V
B
W
CH2 10mV
B
W
M 4µs
T 9.8%
A CH4
1.56V
11641-053
OUTPUT VOLTAGE
2
Figure 59. Line Transient Response, CIN = COUT = 1 μF, ILOAD = 1 mA,
VOUT = 5 V
Rev. 0 | Page 16 of 28
Data Sheet
ADP7105
THEORY OF OPERATION
The ADP7105 is a low quiescent current, LDO linear regulator
that operates from 3.3 V to 20 V and provides up to 500 mA of
output current. The ADP7105 draws a low 900 µA of quiescent
current (typical) at full load, making it ideal for battery-operated
portable equipment. Typical shutdown current consumption is
40 μA at room temperature.
Optimized for use with small 1 µF ceramic capacitors, the
ADP7105 provides excellent transient performance.
VOUT = 1.22 V(1 + R1/R2)
VOUT
VREG
GND
SHORT-CIRCUIT,
THERMAL
PROTECT
PGOOD
VIN = 8V
PG
SHUTDOWN
EN/
UVLO
CIN +
1µF
VIN
VOUT
R1
40.2kΩ
ADJ
R1
ON
SENSE
9.8µA
The ADP7105 is available in three fixed output voltage options,
1.8 V, 3.3 V, and 5 V, and in an adjustable version with an output
voltage that can be set from 1.22 V to 19 V by an external
voltage divider. The output voltage can be set according to the
following equation:
OFF
R2
R3
100kΩ
R4
100kΩ
EN/
UVLO
R2
13kΩ
11641-055
GND
1.22V
REFERENCE
Figure 60. Fixed Output Voltage Internal Block Diagram
VIN
VREG
9.8µA
EN/
UVLO
SHORT-CIRCUIT,
THERMAL
PROTECT
SHUTDOWN
PGOOD
PG
R2
ADJ
11641-056
SS
1.22V
REFERENCE
RPG
100kΩ
CSS
Figure 62. Typical Adjustable Output Voltage Application Schematic
Ensure that the value of R2 is less than 200 kΩ to minimize
errors in the output voltage caused by the ADJ input current.
For example, when R1 and R2 each equal 200 kΩ, the output
voltage is 2.46 V. The output voltage error introduced by the
ADJ input current is 2 mV or 0.08%, assuming a typical ADJ
input current of 10 nA at 25°C.
VOUT
GND
SS
VOUT = 5V
PG
PG
SS
+ COUT
1µF
11641-075
VIN
device is pulled higher, allowing less current to pass and
decreasing the output voltage.
Figure 61. Adjustable Output Voltage Internal Block Diagram
Internally, the ADP7105 consists of a reference, an error
amplifier, a feedback voltage divider, and a PMOS pass
transistor. Output current is delivered via the PMOS pass
device, which is controlled by the error amplifier. The error
amplifier compares the reference voltage with the feedback
voltage from the output and amplifies the difference. If the
feedback voltage is lower than the reference voltage, the gate
of the PMOS device is pulled lower, allowing more current to
pass and increasing the output voltage. If the feedback voltage
is higher than the reference voltage, the gate of the PMOS
The ADP7105 uses the EN/UVLO pin to enable and disable
the VOUT pin under normal operating conditions. When
EN/UVLO is high, VOUT turns on; when EN/UVLO is low,
VOUT turns off. For automatic startup, EN/UVLO can be tied
to VIN.
The ADP7105 incorporates reverse current protection circuitry
that prevents current flow backwards through the pass element
when the output voltage is greater than the input voltage. A
comparator senses the difference between the input and output
voltages. When the difference between the input voltage and
output voltage exceeds 55 mV, the body of the PFET is switched
to VOUT and turned off or opened. In other words, the gate is
connected to VOUT.
Rev. 0 | Page 17 of 28
ADP7105
Data Sheet
APPLICATIONS INFORMATION
Output Capacitor
The ADP7105 is designed for operation with small, space-saving
ceramic capacitors but functions with most commonly used
capacitors as long as care is taken with regard to the effective series
resistance (ESR) value. The ESR of the output capacitor affects the
stability of the LDO control loop. A minimum of 1 µF capacitance
with an ESR of 1 Ω or less is recommended to ensure the stability
of the ADP7105. Transient response to changes in load current is
also affected by output capacitance. Using a larger value of output
capacitance improves the transient response of the ADP7105 to
large changes in load current. Figure 63 shows the transient
responses for an output capacitance value of 1 µF.
LOAD CURRENT
Figure 64 shows the capacitance vs. voltage bias characteristic of
an 0402, 1 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is ~±15% over the −40°C to +85°C temperature
range and is not a function of package or voltage rating.
1.2
1.0
CAPACITANCE (µF)
CAPACITOR SELECTION
1
0.8
0.6
0.4
0
0
2
4
6
8
10
VOLTAGE (V)
OUTPUT VOLTAGE
2
11641-058
0.2
Figure 64. Capacitance vs. Voltage Bias Characteristic
CH1 500mA Ω
CH2 50mV
M 20µs
T 10%
A CH1
270mA
11641-057
Use Equation 1 to determine the worst-case capacitance,
accounting for capacitor variation over temperature,
component tolerance, and voltage.
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)
Figure 63. Output Transient Response, VOUT = 1.8 V, COUT = 1 µF
Input Bypass Capacitor
(1)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
Connecting a 1 µF capacitor from VIN to GND reduces the
circuit sensitivity to PCB layout, especially when long input
traces or high source impedance is encountered. If greater than
1 µF of output capacitance is required, increase the input
capacitor to match it.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
CBIAS is 0.94 μF at 1.8 V, as shown in Figure 64.
Input and Output Capacitor Properties
Substituting these values in Equation 1 yields
Any good quality ceramic capacitors can be used with the
ADP7105, as long as they meet the minimum capacitance and
maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior
over temperature and applied voltage. Capacitors must have a
dielectric adequate to ensure the minimum capacitance over
the necessary temperature range and dc bias conditions. X5R
or X7R dielectrics with a voltage rating of 6.3 V to 25 V are
recommended. Y5V and Z5U dielectrics are not recommended,
due to their poor temperature and dc bias characteristics.
CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO regulator
overtemperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP7105, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
Rev. 0 | Page 18 of 28
Data Sheet
ADP7105
PROGRAMMABLE UNDERVOLTAGE LOCKOUT
(UVLO)
The ADP7105 uses the EN/UVLO pin to enable and disable the
VOUT pin under normal operating conditions. As shown in
Figure 65, when a rising voltage on EN/UVLO crosses the upper
threshold, VOUT turns on. When a falling voltage on EN/UVLO
crosses the lower threshold, VOUT turns off. The hysteresis of
the EN/UVLO threshold is determined by the Thevenin
equivalent resistance in series with the EN/UVLO pin.
2.0
1.8
1.6
SOFT START FUNCTION
For applications that require a controlled startup, the ADP7105
provides a programmable soft start function. Programmable
soft start is useful for reducing inrush current upon startup and
for providing voltage sequencing. To implement soft start, connect
a small ceramic capacitor from SS to GND. Upon startup, a
1 µA current source charges this capacitor. The ADP7105
start-up output voltage is limited by the voltage at SS, providing
a smooth ramp-up to the nominal output voltage. The soft start
time is calculated by
tSS = VREF × (CSS/ISS)
1.2
VOUT, EN/UVLO RISE
VOUT, EN/UVLO FALL
1.0
where:
tSS is the soft start delay.
VREF is the 1.22 V reference voltage.
CSS is the soft start capacitance between SS and GND.
ISS is the current sourced from SS (1 µA).
0.8
0.6
0.4
0
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
11641-060
0.2
EN/UVLO (V)
When the ADP7105 is disabled (by driving EN low), the soft
start capacitor is discharged to GND through an internal 5 kΩ
resistor.
Figure 65. Typical VOUT Response to EN/UVLO Pin Operation
7
R2 = 1.23 V × R1/(VIN − 1.23 V)
R2
100kΩ
10nF
3
2
VIN
VOUT
SENSE
+C
OUT
1µF
VOUT = 5V
100kΩ
EN/
UVLO
PG
PG
GND SS
0
5
10
Figure 67. Typical Start-Up Behavior
CSS
11641-059
OFF
R1
100kΩ
6.8nF
2.7nF
TIME (ms)
Hysteresis can also be achieved by connecting a resistor in series
with the EN/UVLO pin. For the example shown in Figure 66,
the enable threshold is 2.46 V with a hysteresis of 1 V.
ON
0nF
4
0
where:
VHYS is the desired EN/UVLO hysteresis level.
VIN is the desired turn-on voltage.
CIN +
1µF
EN
5
1
R1 = VHYS/10 μA
VIN = 8V
6
OUTPUT VOLTAGE (V)
The upper and lower thresholds are user programmable and can
be set using two resistors. When the EN/UVLO pin voltage is
below 1.23 V, the LDO is disabled. When the EN/UVLO pin
voltage transitions above 1.23 V, the LDO is enabled and 10 µA
hysteresis current is sourced out of the pin, raising the voltage
and thus providing threshold hysteresis. Typically, two external
resistors program the minimum operational voltage for the
LDO. The resistance values, R1 and R2, can be determined from
the following:
Figure 66. Typical EN/UVLO Pin Voltage Divider
Rev. 0 | Page 19 of 28
15
11641-061
VOUT (V)
1.4
Figure 65 shows the typical hysteresis of the EN/UVLO pin.
This prevents on/off oscillations that can occur due to noise
on the EN/UVLO pin as it passes through the threshold points.
ADP7105
Data Sheet
The ADP7105 provides a power-good pin (PG) to indicate
the status of the output. This open-drain output requires an
external pull-up resistor to VIN or VOUT. If the part is in
shutdown mode, current-limit mode, or thermal shutdown, or
if VOUT falls below 90% of the nominal output voltage, the
power-good pin (PG) immediately transitions low. During soft
start, the rising threshold of the power-good signal is 93.5% of
the nominal output voltage.
The open-drain output is held low when the ADP7105 has sufficient input voltage to turn on the internal PG transistor. The PG
transistor is terminated via a pull-up resistor to VOUT or VIN.
Power-good accuracy is 93.5% of the nominal regulator output
voltage when this voltage is rising, with a 90.8% trip point when
this voltage is falling. Regulator input voltage brownouts or
glitches trigger power no good signals if VOUT falls below 90.8%
of the nominal output voltage.
A normal power-down causes the power-good signal to go low
when VOUT falls below 90.8%.
Figure 68 and Figure 69 show the typical power-good rising and
falling thresholds over temperature.
6
5
–40°C
–5°C
+25°C
+85°C
+125°C
NOISE REDUCTION OF THE ADJUSTABLE
ADP7105
The ultralow output noise of the fixed output ADP7105 is
achieved by keeping the LDO error amplifier in unity gain
and setting the reference voltage equal to the output voltage.
This architecture does not apply to the adjustable output voltage
LDO regulator. The adjustable output ADP7105 uses the more
conventional architecture where the reference voltage is fixed
and the error amplifier gain is a function of the output voltage.
The disadvantage of the conventional LDO architecture is that
the output voltage noise is proportional to the output voltage.
The adjustable LDO circuit can be modified slightly to reduce
the output voltage noise to levels close to that of the fixed output
ADP7105. The circuit shown in Figure 70 adds two additional
components to the output voltage setting resistor divider. CNR
and RNR are added in parallel with RFB1 to reduce the ac gain of
the error amplifier. RNR is chosen to be equal to RFB2. This limits
the ac gain of the error amplifier to approximately 6 dB. The
actual gain is the parallel combination of RNR and RFB1 divided
by RFB2. This ensures that the error amplifier always operates at
greater than unity gain.
CNR is chosen by setting the reactance of CNR equal to RFB1 − RNR
at a frequency between 50 Hz and 100 Hz. This capacitor value sets
the frequency so that the ac gain of the error amplifier is 3 dB
less than its dc gain.
VIN = 8V
PG (V)
4
CIN +
1µF
VIN
VOUT
RFB1
40.2kΩ
ADJ
3
OFF
R3
ON 100kΩ
R4
100kΩ
2
RFB2
13kΩ
EN/
UVLO
VOUT = 5V
+ COUT
1µF
+ CNR
100nF
RNR
13kΩ
RPG
100kΩ
PG
PG
GND
0
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
VOUT (V)
11641-062
1
Figure 68. Typical Power-Good Threshold vs. Output Voltage and
Temperature, VOUT Rising
6
CSS
Figure 70. Noise Reduction Modification to Adjustable LDO Regulator
The noise of the adjustable LDO regulator can be found by
using the following formula, assuming the noise of a fixed
output LDO is approximately 15 μV:
–40°C
–5°C
+25°C
+85°C
+125°C
1
/ 13 kΩ
15 μV × 1 +
1/13 kΩ + 1 / 40.2 kΩ
4
Based on the component values shown in Figure 70, the
ADP7105 has the following characteristics:
3
•
•
•
•
•
2
1
0
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
VOUT (V)
11641-063
PG (V)
5
SS
11641-064
POWER-GOOD FEATURE
•
Figure 69. Typical Power-Good Threshold vs. Output Voltage and
Temperature, VOUT Falling
Rev. 0 | Page 20 of 28
DC gain of 4.09 (12.2 dB)
3 dB roll-off frequency of 59 Hz
High frequency ac gain of 1.76 (4.89 dB)
Noise reduction factor of 1.33 (2.59 dB)
RMS noise of the ADP7105 adjustable LDO without noise
reduction of 27.8 µV rms
RMS noise of the ADP7105 adjustable LDO with noise
reduction (assuming 15 µV rms for fixed voltage option)
of 19.95 µV rms
Data Sheet
ADP7105
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP7105 is protected against damage due to excessive
power dissipation by current and thermal overload protection
circuits. The ADP7105 is designed to limit the current when the
output load reaches 775 mA (typical). When the output load
exceeds 775 mA, the output voltage is reduced to maintain a
constant current limit. As the output voltage drops, the current
is folded back to approximately 50 mA to minimize heat
generation inside the LDO regulator.
Thermal overload protection is included, which limits the
junction temperature to a maximum of 150°C (typical). Under
extreme conditions (that is, high ambient temperature and/or
high power dissipation) when the junction temperature starts to
rise above 150°C, the output is turned off, reducing the output
current to zero. When the junction temperature falls below
135°C, the output is turned on again, and output current is
restored to its operating value.
Consider the case where a hard short from VOUT to ground
occurs. At first, the ADP7105 limits the current so that only
775 mA is conducted into the short. If self heating of the
junction is great enough to cause its temperature to rise above
150°C, thermal shutdown is activated, turning off the output and
reducing the output current to zero. As the junction temperature
cools and falls below 135°C, the output turns on and conducts
775 mA into the short, again causing the junction temperature
to rise above 150°C. This thermal oscillation between 135°C
and 150°C causes a current oscillation between 775 mA and
0 mA that continues as long as the short remains at the output.
Current-limit and thermal limit protections are intended to
protect the device against accidental overload conditions. For
reliable operation, device power dissipation must be externally
limited so that the junction temperature does not exceed 125°C.
THERMAL CONSIDERATIONS
In applications with a low input-to-output voltage differential,
the ADP7105 does not dissipate much heat. However, in
applications with high ambient temperature and/or high input
voltage, the heat dissipated in the package may become
significant enough that it causes the junction temperature of the
die to exceed the maximum junction temperature of 125°C.
When the junction temperature exceeds 150°C, the regulator
enters thermal shutdown. It recovers only after the junction
temperature decreases below 135°C to prevent any permanent
damage. Therefore, thermal analysis for the chosen application
is very important to guarantee reliable performance over all
conditions. The junction temperature of the die is the sum of
the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown
in Equation 2.
To guarantee reliable operation, the junction temperature of the
ADP7105 must not exceed 125°C. To ensure that the junction
temperature stays below this maximum value, the user must be
aware of the parameters that contribute to junction temperature
changes. These parameters include ambient temperature, power
dissipation in the power device, and thermal resistances between
the junction and ambient air (θJA). The θJA value is dependent on
the package assembly compounds that are used and the amount of
copper used to solder the package GND pins to the PCB.
Table 6 shows typical θJA values for the 8-lead SOIC and 8-lead
LFCSP packages for various PCB copper sizes. Table 7 shows
the typical ΨJB values for the 8-lead SOIC and 8-lead LFCSP
with PCB area.
Table 6. Typical θJA Values
Copper Size (mm2)
251
100
500
1000
6400
1
LFCSP
165.1
125.8
68.1
56.4
42.1
θJA (°C/W)
SOIC
167.8
111
65.9
56.1
45.8
Device soldered to minimum size pin traces.
Table 7. Typical ΨJB Values with PCB Area
Model
8-Lead LFCSP1
8-Lead SOIC
1
ΨJB (°C/W)
15.1
31.3
Note that the ΨJB value for the LFCSP package accounts for PCB area, which
is being used as a heat sink via the exposed pad, whereas the value in Table 4 is
per the JEDEC standard.
The junction temperature of the ADP7105 is calculated from
the following equation:
TJ = TA + (PD × θJA)
(2)
where:
TA is the ambient temperature.
θJA is the junction-to-ambient thermal resistance.
PD is the power dissipation in the die, given by
PD = [(VIN − VOUT) × ILOAD] + (VIN × IGND)
(3)
where:
VIN and VOUT are the input and output voltages, respectively.
ILOAD is the load current.
IGND is the ground current.
Power dissipation due to ground current is quite small and can
be ignored. Therefore, the junction temperature equation
simplifies to the following:
TJ = TA + {[(VIN − VOUT) × ILOAD] × θJA}
(4)
As shown in Equation 4, for a given ambient temperature, inputto-output voltage differential, and continuous load current, a
minimum copper size requirement for the PCB exists to ensure
that the junction temperature does not rise above 125°C. Figure 71
to Figure 76 show junction temperature calculations for
different ambient temperatures, power dissipation, and areas of
PCB copper.
Rev. 0 | Page 21 of 28
Data Sheet
145
135
135
125
125
115
105
95
85
75
65
55
6400mm 2
500mm 2
25mm 2
TJ MAX
45
35
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
TOTAL POWER DISSIPATION (W)
85
75
65
55
6400mm 2
500mm 2
25mm 2
TJ MAX
45
35
25
0
0.2
0.4
0.6
140
130
130
JUNCTION TEMPERATURE (°C)
140
120
110
100
90
80
70
6400mm 2
500mm 2
25mm 2
TJ MAX
60
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
70
50
6400mm 2
500mm 2
25mm 2
TJ MAX
0
0.2
0.4
JUNCTION TEMPERATURE (°C)
105
95
85
6400mm 2
500mm 2
25mm 2
TJ MAX
75
0.7
TOTAL POWER DISSIPATION (W)
0.6
0.8
1.0
1.2
1.4
1.6
1.8
TOTAL POWER DISSIPATION (W)
0.8
0.9
125
115
105
95
85
6400mm 2
500mm 2
25mm 2
TJ MAX
75
1.0
11641-067
JUNCTION TEMPERATURE (°C)
115
0.6
2.4
Figure 75. SOIC, TA = 50°C
125
0.5
2.2
80
135
0.4
2.0
90
135
0.3
1.8
100
145
0.2
1.6
110
145
0.1
1.4
120
Figure 72. LFCSP, TA = 50°C
0
1.2
60
TOTAL POWER DISSIPATION (W)
65
1.0
Figure 74. SOIC, TA = 25°C
11641-066
JUNCTION TEMPERATURE (°C)
Figure 71. LFCSP, TA = 25°C
50
0.8
TOTAL POWER DISSIPATION (W)
11641-069
0
95
Figure 73. LFCSP, TA = 85°C
65
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
TOTAL POWER DISSIPATION (W)
Figure 76. SOIC, TA = 85°C
Rev. 0 | Page 22 of 28
0.8
0.9
1.0
11641-070
25
115
105
11641-068
JUNCTION TEMPERATURE (°C)
145
11641-065
JUNCTION TEMPERATURE (°C)
ADP7105
Data Sheet
ADP7105
(5)
100
80
60
40
140
20
120
0
TB = 25°C
TB = 50°C
TB = 65°C
TB = 85°C
TJ MAX
0
0.5
1.0
1.5
2.0
Figure 78. SOIC
80
60
40
TB = 25°C
TB = 50°C
TB = 65°C
TB = 85°C
TJ MAX
20
0
2.5
TOTAL POWER DISSIPATION (W)
100
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
TOTAL POWER DISSIPATION (W)
11641-071
JUNCTION TEMPERATURE (TJ)
The typical value of ΨJB is 15.1°C/W for the 8-lead LFCSP package
and 31.3°C/W for the 8-lead SOIC package (see Table 7).
120
Figure 77. LFCSP
Rev. 0 | Page 23 of 28
3.0
3.5
11641-072
TJ = TB + (PD × ΨJB)
140
JUNCTION TEMPERATURE (TJ)
In the case where the board temperature is known, use the ΨJB
thermal characterization parameter to estimate the junction
temperature rise (see Figure 77 and Figure 78). Maximum
junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the following
formula:
ADP7105
Data Sheet
PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS
Heat dissipation from the package can be improved by increasing
the amount of copper attached to the pins of the ADP7105.
However, as shown in Table 6, a point of diminishing returns
is eventually reached, beyond which an increase in the copper
size does not yield significant heat dissipation benefits.
11641-074
Place the input capacitor as close as possible to the VIN and
GND pins. Place the output capacitor as close as possible to the
VOUT and GND pins. Use of 0805 or 0603 size capacitors and
resistors achieves the smallest possible footprint solution on
boards where space is limited.
11641-073
Figure 80. Example SOIC PCB Layout
Figure 79. Example LFCSP PCB Layout
Rev. 0 | Page 24 of 28
Data Sheet
ADP7105
OUTLINE DIMENSIONS
2.48
2.38
2.23
3.10
3.00 SQ
2.90
8
5
EXPOSED
PAD
INDEX
AREA
4
TOP VIEW
SEATING
PLANE
0.30
0.25
0.18
0.20 MIN
PIN 1
INDICATOR
(R 0.2)
1
BOTTOM VIEW
0.80 MAX
0.55 NOM
0.80
0.75
0.70
1.74
1.64
1.49
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
0.50 BSC
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
02-05-2013-B
0.50
0.40
0.30
COMPLIANT TO JEDEC STANDARDS MO-229-WEED-4
Figure 81. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-5)
Dimensions shown in millimeters
5.00
4.90
4.80
3.098
0.356
5
1
4
6.20
6.00
5.80
4.00
3.90
3.80
2.41
0.457
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
BOTTOM VIEW
1.27 BSC
3.81 REF
TOP VIEW
1.65
1.25
1.75
1.35
SEATING
PLANE
0.51
0.31
0.50
0.25
0.10 MAX
0.05 NOM
COPLANARITY
0.10
8°
0°
45°
0.25
0.17
1.04 REF
1.27
0.40
COMPLIANT TO JEDEC STANDARDS MS-012-A A
Figure 82. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
Narrow Body
(RD-8-2)
Dimensions shown in millimeters
Rev. 0 | Page 25 of 28
06-03-2011-B
8
ADP7105
Data Sheet
ORDERING GUIDE
Model 1
ADP7105ACPZ-1.8-R7
ADP7105ACPZ-3.3-R7
ADP7105ACPZ-5.0-R7
ADP7105ACPZ-R2
ADP7105ACPZ-R7
ADP7105ARDZ-1.8
ADP7105ARDZ-1.8-R7
ADP7105ARDZ-3.3
ADP7105ARDZ-3.3-R7
ADP7105ARDZ-5.0
ADP7105ARDZ-5.0-R7
ADP7105ARDZ
ADP7105ARDZ-R7
1
Temperature
Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Output
Voltage (V)
1.8
3.3
5
Adjustable
Adjustable
1.8
1.8
3.3
3.3
5
5
Adjustable
Adjustable
Z = RoHS Compliant Part.
Rev. 0 | Page 26 of 28
Package
Description
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
Package
Option
CP-8-5
CP-8-5
CP-8-5
CP-8-5
CP-8-5
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
Branding
LNS
LNT
LNU
LNV
LNV
Data Sheet
ADP7105
NOTES
Rev. 0 | Page 27 of 28
ADP7105
Data Sheet
NOTES
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11641-0-7/13(0)
Rev. 0 | Page 28 of 28