TI1 BUF08630 Programmable gamma-voltage generator and high slew rate vcom Datasheet

BU
BUF08630
F08
832
www.ti.com
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
Programmable Gamma-Voltage Generator and High Slew Rate VCOM
with Integrated Two-Bank Memory plus 1/2 AVDD Topology
Check for Samples: BUF08630
FEATURES
DESCRIPTION
•
•
•
•
•
•
The BUF08630 offers eight programmable gamma
channels and one programmable VCOM channel.
1
2
•
•
•
•
•
•
10-Bit Resolution
8-Channel P-Gamma
1-Channel P-VCOM
High Slew Rate VCOM: 45 V/μs
16x Rewritable Nonvolatile Memory
Two Independent Pin-Selectable Memory
Banks
Rail-to-Rail Output:
– 300 mV Min Swing-to-Rail (10 mA)
– > 300 mA Max IOUT
Low Supply Current
Supply Voltage: 9 V to 20 V
Digital Supply: 2 V to 5.5 V
Two-Wire Interface:
– Supports 400 kHz and 3.4 MHz
1/2 AVDD Capability
APPLICATIONS
•
TFT-LCD Reference Drivers
BKSEL
VSD
VCOM-FB
VCOM-VS
VCOM-OUT
VCOM
DAC
All gamma and VCOM channels offer a rail-to-rail
output that typically swings to within 150 mV of either
supply rail with a 10-mA load. All channels are
programmed using a two-wire interface that supports
standard operations up to 400 kHz, and high-speed
data transfers up to 3.4 MHz.
The BUF08630 is manufactured using Texas
Instruments’ proprietary, state-of-the-art, high-voltage
CMOS process. This process offers very dense logic
and high supply voltage operation of up to 20V. The
BUF08630 is available in a 20-pin QFN package, and
is specified from –40°C to +95°C.
RELATED PRODUCTS
FEATURES
PRODUCT
22-channel gamma correction buffer
BUF22821
16-channel gamma correction buffer
BUF16821
12-channel gamma correction buffer
BUF12800
OUT1
18-/20-channel programmable buffer, 10-Bit, VCOM
BUF20800
OUT2
18-/20-Channel programmable buffer with memory
BUF20820
OUT3
Programmable VCOM driver
BUF01900
22-V supply, traditional gamma buffers
BUF11705
High-resolution, fully-programmable LCD bias IC for TV
TPS65168
VCOM-GND
DAC Resistors
16X Nonvolatile Memory BANK1
The BUF08630 has two separate memory banks,
allowing simultaneous storage of two different gamma
curves to facilitate switching between gamma curves.
VS
1
OUT4
VSH
OUT5
DAC Resistors
16X Nonvolatile Memory BANK0
The final gamma and VCOM values can be stored in
the on-chip, nonvolatile memory. To allow for
programming errors or liquid crystal display (LCD)
panel rework, the BUF08630 supports up to 16 write
operations to the on-chip memory.
OUT6
OUT7
OUT8
SDA
SCL
2k ´ 16 OTP
Memory
Control (IF and Memory)
A0
DGND
GND
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2012, Texas Instruments Incorporated
BUF08630
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
(1)
PRODUCT
PACKAGE
PACKAGE DESIGNATOR
PACKAGE MARKING
BUF08630
VQFN-20
RGW
BUF08630
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
Supply voltage
BUF08630
UNIT
VS
+22
V
VSH
GND + 4.0 < VSH < VS – 4.0
V
VSD
+6
V
–0.5 to +6
V
Digital input pins, SCL, SDA, AO, BKSEL: voltage
Digital input pins, SCL, SDA, AO, BKSEL: current
±10
mA
Output pins, OUT1 through OUT4 (2)
(V–) – 0.5 to (VSH) + 0.5
V
Output pins, OUT5 through OUT8 (2)
(VSH) – 0.5 to (V+) + 0.5
V
(V–) – 0.5 to (V+) + 0.5
V
VCOM
(2)
Output short-circuit (3)
Continuous
Ambient operating temperature
–40 to +95
°C
Ambient storage temperature
–65 to +150
°C
Junction temperature, TJ
ESD ratings
+125
°C
Human body model (HBM)
4
kV
Charged device model (CDM)
1
kV
200
V
Machine model (MM)
(1)
(2)
(3)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
See the Output Protection section.
Short-circuit to ground, one amplifier per package. Exposed thermal die is soldered to the printed circuit board (PCB) using thermal vias.
Refer to Texas Instruments' application report SLAU271, QFN/SON PCB Attachment.
THERMAL INFORMATION
BUF08630
THERMAL METRIC (1)
RGW
UNITS
20 PINS
θJA
Junction-to-ambient thermal resistance
42.4
θJC(top)
Junction-to-case(top) thermal resistance
34.4
θJB
Junction-to-board thermal resistance
10.4
ψJT
Junction-to-top characterization parameter
8.2
ψJB
Junction-to-board characterization parameter
42.4
θJC(bottom)
Junction-to-case(bottom) thermal resistance
2.1
(1)
2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
BUF08630
www.ti.com
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TA = –40°C to +95°C.
At TA = +25°C, VS = +18 V, VSH = 9.0 V, VSD = +2 V, and CL = 200 pF, unless otherwise noted.
BUF08630
PARAMETER
CONDITIONS
MIN
TYP
17.7
17.85
MAX
UNIT
ANALOG GAMMA BUFFER CHANNELS
Reset value
Code = 512
OUT1, 4 output swing: high
Code = 1023, sourcing 10 mA
OUT1, 4 output swing: low
Code = 512, sinking 10 mA
OUT2, 3 output swing: high
Code = 1023, sourcing 10 mA
OUT2, 3 output swing: low
Code = 512, sinking 10 mA
OUT5, 8 output swing: high
Code = 511, sourcing 10 mA
OUT5, 8 output swing: low
Code = 0, sinking 10 mA
OUT6, 7 output swing: high
Code = 511, sourcing 10 mA
OUT6, 7 output swing: low
Code = 0, sinking 10 mA
VCOM output swing: high (1)
Code = 960, sourcing 400 mA
VCOM output swing: low (1)
VSH + 0.07
17.5
VSH – 0.3
3.8
Note
(4)
V
0.5
V
V
5
V
V
45
(3)
V/μs
30
mA
Code = 512
±25
Code = 768, VSH = 9 V, VS = 18 V
±20
Code = 768
±25
Code = 256, VSH = 9 V, VS = 18 V
±20
Code = 256
±25
μV/°C
INL
0.3
LSB
DNL
0.3
vs Temperature
Output accuracy, OUT5 to OUT8
vs Temperature
Load regulation
V
±20
Output accuracy, OUT1 to OUT4
Differential nonlinearity (4)
V
0.3
Code = 512
vs Temperature
Integral nonlinearity (4)
V
6
RLOAD = 60 Ω, CLOAD = 100 pF
Continuous output current
V
VSH + 0.5
15.3
Code = 0, sinking 400 mA
VCOM slew rate (2)
V
VSH – 0.15
0.05
13
V
VSH + 0.3
VSH – 0.15
0.05
VSH – 0.5
V
17.85
VSH + 0.07
Code = 0, sinking 400 mA
vs Temperature
Output accuracy, VCOM
9
REG
±50
mV
μV/°C
±50
mV
μV/°C
±50
mV
LSB
OUT1 to OUT4 code = 768, IOUT = +5-mA to –5-mA step
0.5
1.5
mV/mA
OUT5 to OUT8 code = 256, IOUT = +5-mA to –5-mA step
0.5
1.5
mV/mA
16
Cycles
OTP MEMORY
Number of OTP write cycles
Memory retention
100
Years
ANALOG POWER SUPPLY
Operating range
Total analog supply current
9
IS
OUT1 to OUT4 set code = 768,
OUT5 to OUT8 set code = 256, no load
6.9
Over temperature
20
V
11
mA
11
mA
DIGITAL
Logic 1 input voltage
Logic 0 input voltage
Logic 0 output voltage
VIH
0.7 × VSD
VIL
0.3 × VSD
VOL
ISINK = 3-mA
Input leakage
Clock frequency
V
fCLK
V
0.15
0.4
V
±0.01
±10
μA
Standard/Fast mode
400
kHz
High-Speed mode
3.4
MHz
DIGITAL POWER SUPPLY
Specified range
Digital supply current (3)
DVDD
DIDD
2.0
Outputs at reset values, no load, two-wire bus inactive
Over temperature
(1)
(2)
(3)
(4)
5.5
V
115
180
μA
115
180
μA
The BUF08630 VCOM DAC limits can be programmed. These default limits apply if the device is not programmed. See the
Programmable Vcom Limits section.
See Figure 19, Large-Signal Step Response, VCOM.
Observe maximum power dissipation.
The VCOM output voltage is limited to codes 0 to 960 because of the common-mode input range of the VCOM amplifier. This limitation is
for VCOM only; it does not affect DAC OUT1 to 8.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
3
BUF08630
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Boldface limits apply over the specified temperature range, TA = –40°C to +95°C.
At TA = +25°C, VS = +18 V, VSH = 9.0 V, VSD = +2 V, and CL = 200 pF, unless otherwise noted.
BUF08630
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
TEMPERATURE RANGE
Specified range
–40
+95
°C
Storage range
–65
+150
°C
PIN CONFIGURATION
SCL
OUT8
OUT7
VSH
NC
19
18
17
16
9
10
5
OUT1
4
BKSEL
GND
VCOM-OUT
8
3
VS
VSD
Exposed
thermal pad
is connected
to GND.
7
2
VCOM-VS
A0
6
1
VCOM-FB
SDA
20
RGW PACKAGE
VQFN-20
(TOP VIEW)
15
OUT6
14
OUT5
13
OUT4
12
OUT3
11
OUT2
PIN DESCRIPTIONS
4
PIN NAME
PIN NO.
A0
2
A0 address pin for two-wire address; connect to either logic 1 or logic 0. See Table 1.
DESCRIPTION
BKSEL
9
Selects memory bank 0 or 1; connect to either logic 1 to select bank 1 or logic 0 to select bank 0.
GND
4
Ground
NC
16
No Connect
OUT1
10
DAC output 1
OUT2
11
DAC output 2
OUT3
12
DAC output 3
OUT4
13
DAC output 4
OUT5
14
DAC output 5
OUT6
15
DAC output 6
OUT7
18
DAC output 7
OUT8
19
DAC output 8
SCL
20
Serial clock input; connect to pull-up resistor.
SDA
1
Serial data I/O; open-drain, connect to pull-up resistor.
VCOM-AVDD
7
VCOM supply
VCOM-FB
6
VCOM feedback
VCOM-OUT
5
VCOM output
VS
8
VS connected to analog supply.
VSD
3
Digital supply; connect to logic supply.
VSH
17
VSH connected to 1/2 analog supply.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
BUF08630
www.ti.com
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = +18 V, VSH = +9 V, and VSD = +2 V, unless otherwise noted.
VOUT vs IOUT
(OUT5 to OUT8)
18
9
17
8
16
7
Output Voltage (V)
Output Voltage (V)
VOUT vs IOUT
(OUT1 to OUT4)
15
14
13
+125°C
+95°C
+25°C
−40°C
12
6
5
4
11
2
10
1
9
0
50
100
Output Current (mA)
150
0
200
+125°C
0
50
100
Output Current (mA)
Figure 1.
25
16
20
14
15
150
200
Average VOS Shown in Green
10
12
VOS (mV)
Output Voltage (V)
−40°C
VOS (VCOM) vs TEMPERATURE
18
10
+125°C
+95°C
+25°C
−40°C
8
6
5
0
−5
−10
4
−15
2
−20
0
100
200
Output Current (mA)
300
−25
−50
400
−25
0
Figure 3.
IQ (Analog) vs TEMPERATURE
75
100
125
100
125
IQ (Digital) vs TEMPERATURE
Digital Supply Current (µA)
140
7
6
5
4
−50
25
50
Temperature (°C)
Figure 4.
8
Analog Supply Current (mA)
+25°C
Figure 2.
VOUT vs IOUT
(VCOM)
0
+95°C
3
−25
0
25
50
Temperature (°C)
75
100
125
130
120
110
100
−50
Figure 5.
−25
0
25
50
Temperature (°C)
75
Figure 6.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
5
BUF08630
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = +18 V, VSH = +9 V, and VSD = +2 V, unless otherwise noted.
INTEGRAL LINEARITY ERROR
(VCOM)
DIFFERENTIAL LINEARITY ERROR
(VCOM)
0.25
0.2
0.2
0.15
0.15
0.1
DNL (LSB)
INL (LSB)
0.1
0.05
0
−0.05
0.05
0
−0.05
−0.1
−0.1
−0.15
−0.15
−0.2
−0.25
0
128
256
384
512
Code
640
768
896
−0.2
1023
512
Code
640
768
INTEGRAL LINEARITY ERROR
(OUT1 to OUT4)
DIFFERENTIAL LINEARITY ERROR
(OUT1 to OUT4)
896
1023
0.1
0.05
0
−0.05
0.05
0
−0.05
−0.1
−0.1
−0.15
−0.15
−0.2
512
DNL1
DNL2
DNL3
DNL4
0.15
DNL (LSB)
INL (LSB)
384
0.2
0.1
640
768
Code
896
−0.2
512
1023
640
768
Code
896
Figure 9.
Figure 10.
INTEGRAL LINEARITY ERROR
(OUT5 to OUT8)
DIFFERENTIAL LINEARITY ERROR
(OUT5 to OUT8)
0.2
1023
0.2
INL5
INL6
INL7
INL8
0.15
0.1
0.1
0.05
0
−0.05
0.05
0
−0.05
−0.1
−0.1
−0.15
−0.15
0
DNL5
DNL6
DNL7
DNL8
0.15
DNL (LSB)
INL (LSB)
256
Figure 8.
INL1
INL2
INL3
INL4
0.15
128
256
Code
384
511
−0.2
0
Figure 11.
6
128
Figure 7.
0.2
−0.2
0
128
256
Code
384
511
Figure 12.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
BUF08630
www.ti.com
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = +18 V, VSH = +9 V, and VSD = +2 V, unless otherwise noted.
ANALOG HISTOGRAM
DIGITAL HISTOGRAM
3000
10000
9000
8000
7000
Population
Population
2000
1000
6000
5000
4000
3000
2000
1000
0
5
5.4
5.8
6.2 6.6
7
7.4 7.8 8.2
Analog Supply Current (mA)
8.6
0
9
100 104 108 112 116 120 124 128 132 136 140
Digial Supply Current (µA)
Figure 13.
Figure 14.
BKSEL SWITCHING TIME DELAY
(OUT1 to OUT4)
BKSEL SWITCHING TIME DELAY
(OUT5 to OUT8)
19
11
Typical Lower Channel
17
9
15
7
Typical Upper Channel
Voltage (V)
Voltage (V)
13
11
9
7
BKSEL
5
3
5
BKSEL
3
1
1
−1
0
10
20
−1
30
Time (µs)
20
Time (µs)
Figure 15.
Figure 16.
LARGE-SIGNAL STEP RESPONSE
(OUT1 to OUT4)
LARGE-SIGNAL STEP RESPONSE
(OUT5 to OUT8)
20
30
40
8
Output Voltage (V)
Output Voltage (V)
10
10
18
16
14
12
6
4
2
10
8
0
0
2
4
6
Time (µs)
8
10
12
0
0
Figure 17.
2
4
6
8
10
Time (µs)
12
14
16
18
Figure 18.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
7
BUF08630
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = +18 V, VSH = +9 V, and VSD = +2 V, unless otherwise noted.
LARGE-SIGNAL STEP RESPONSE
(VCOM)
Output Voltage (V)
15
10
5
0
0
2
4
6
8
10
Time (µs)
12
14
16
Figure 19.
8
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
BUF08630
www.ti.com
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
APPLICATION INFORMATION
The BUF08630 programmable voltage reference
allows fast and easy adjustment of eight
programmable gamma reference outputs and a VCOM
output, each with 10-bit resolution. The BUF08630 is
programmed through a high-speed, two-wire
interface. The final gamma and VCOM values can be
stored in the onboard, nonvolatile memory. To allow
for programming errors or liquid crystal display (LCD)
panel rework, the BUF08630 supports up to 16 write
operations to the onboard memory. The BUF08630
has two separate memory banks, allowing
simultaneous storage of two different gamma curves
to facilitate dynamic switching between gamma
curves.
The BUF08630 can be powered using an analog
supply voltage from 9 V to 20 V, and a digital supply
from 2 V to 5.5 V. The digital supply must be applied
before the analog supply to avoid excessive current
and power consumption, or possibly even damage to
the device if left connected only to the analog supply
for extended periods of time. In addtion, analog
supply voltage VS should be turned on before VSH.
It is recommended that the TPS65168 be used
together with the BUF08630 for best performance, as
shown in Figure 24. Note that the TPS65168 provides
the power sequence previously described and
required by the BUF08630.
Figure 20 shows the proper power-up sequence
when two supplies are used (that is, VS and VCOM-VS
are connected together).Figure 21 shows the proper
power-up sequence when three supplies are used
(that is, VSH, VS, and VCOM-VS are separate supplies).
16
12
10
8
6
4
Power-Up Sequence
If VCOM-VS is brought up
after VS, damage will occur
to the analog switches for
VCOM.
0
2
4
Time (ms)
6
8
Figure 20. Startup Requirement with Two
Supplies
16
Digital Supply
VCOM−VS
VS
VSH
14
12
Supply Voltage (V)
CAUTION
VS and VCOM−VS May
Come Up Together
2
0
When applying power to the BUF08630, the digital
supply must be powered up first. The analog supply
for the VCOM amplifier (VCOM-VS), and the analog
supply (VS) should be brought up at least 1.2 ms later
so that the programmed values in the nonvolatile
memory can be written to the DAC registers. The
analog supply voltage (VCOM-VS) must always preceed
VS, or the two supply pins should be tied together so
that they turn on and off simultaneously. The supply
voltage VSH must always follow VS.
Digital Supply
VS
VSH
14
Supply Voltage (V)
GENERAL DESCRIPTION
10
8
6
4
VS and VCOM−VS May
Come Up Together
2
0
0
2
4
Time (ms)
6
8
Figure 21. Startup Requirement with Three
Supplies
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
9
BUF08630
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
www.ti.com
Power-Down Sequence
16
Digital Supply
VS
VSH
0
Supply Voltage (V)
12
0
2
4
Time (ms)
6
8
Figure 23. Shutdown Requirement with Three
Supplies
8
4
VCOM−VS is connected to VS
0
2
4
Time (ms)
6
8
Figure 22. Shutdown Requirement with Two
Supplies
10
8
4
16
0
Digital Supply
VCOM−VS
VS
VSH
12
Supply Voltage (V)
When removing power from the BUF08630, the
reverse sequence from that described in the PowerUp Sequence must be used. Figure 22 shows the
sequence that must be followed when VCOM-VS is
connected to VS. Figure 23 shows the sequence that
must be followed when VCOM-VS is not connected to
VS.
A separate supply pin is provided for VCOM-VS so that
separate supplies can be used for the gamma buffers
and VCOM. The gamma buffers could be powered with
a clean supply to prevent noise coupling into the
gamma channels. The VCOM amplifier can then be
supplied by a power source with more current
capability, but with higher noise.
It is highly recommended that a Schottky diode be
placed between VS and VSH, as shown in Figure 37.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
BUF08630
www.ti.com
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
L1
10µH
D1
SL22
C1~2
2*10µF/
25V
C4~7
4*10µF/
25V
SWI
SW
SW
C3
10µF/
25V
R1
33kW
C8
1nF
VDD
16.5V / 800mA
SWO
VIN
8.6V to 14.7V
Boost Converter
(VDD)
+
Isolation Switch
COMP
C9
100nF
SS
PGND
VI/O
PGND
R3
2.2kW
R2
2.2kW
AVIN
C10
1µF
DAC
+
I C controller
Internal
Supply
VL
2
AGND
SDA
VCOM-VS
I 2C
SCL
VS
A0
HVDD
8V / ±300mA
L2
PVINB3
C11
10µF/
25V
SWB3
Synchronous Buck Converter 3
(HVDD)
6.8µH
D1(6)
VSH
C12
10µF/
25V
OUT3
10mF
OUT8
PGND3
0.1mF
0.1mF
10mF
Timing
Controller
OUT1
EN
OUT6
A0
OUT5
BUF08630(1)
L4
S WB2
RST
Reset
(RST)
VL
R6
120kW
R5
47kW
Synchronous
Buck Converter 2
(VCORE )
R1(2)
OUT3
VCOM-OUT
OUT2
2.2µH
C19
10µF/
6V
OUT2
R2(3)
OUT6
OUT5
OUT4
Source
Drivers
LCD
Panel
OUT3
OUT2
OUT1
R3(3)
R4(4)
PGND2
NTC 47kW
OUT4
VCOM-GND
VCOM-FB
R4
10kW
RST
VCORE
1.0V / 600mA
NC
SDA
VSD
VI/O
VSH
VSD
OUT7
C15~18
4*10µF/
6V
OUT1
Buck Converter 1
(VI/O )
10µH
D2
SL22
BKSEL
SWB1
VS
SWB1
PVINB1
SCL
PVINB1
VCOM-VS
C13~14
2*10µF/
25V
OUT8
OUT7
VI/O
3.3V / 400mA
L3
R5(5)
SWB1
TCOMP
VDD
D3, D4
BAT54S
SW
VGH
26V / 100mA
C20
1µF/
50V
Q1
MMBT2907ALT1
C22
220nF
R8
100kW
Positive
Charge Pump
Controller
(VGH )
+
C21
100nF/
25V CTRLP
VGH
Temperature
C26
100nF
Q2
MMBT2222A
Negative
Charge Pump
Controller
(VGL )
CTRLN
D5, D6
BAT54S
C25
100nF/ R11
25V 4.42kW
VGL
-5V / 100mA
0.1mF
0.1mF
10mF
10mF
C23
4.7µF/
10V
R9
FBN 100kW
R12
1.8kW
C24
100nF
VI/O
Figure 24. Typical Application Circuit using the TPS65168
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
11
BUF08630
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
www.ti.com
Table 1. Quick Reference of BUF08630 Addresses
TWO-WIRE BUS OVERVIEW
The BUF08630 communicates over an industrystandard, two-wire interface to receive data in slave
mode. This model uses a two-wire, open-drain
interface that supports multiple devices on a single
bus. Bus lines are driven to a logic low level only. The
device that initiates the communication is called a
master, and the devices controlled by the master are
slaves. The master generates the serial clock on the
clock signal line (SCL), controls the bus access, and
generates the START and STOP conditions.
To address a specific device, the master initiates a
START condition by pulling the data signal line (SDA)
from a high to a low logic level while SCL is high. All
slaves on the bus shift in the slave address byte on
the rising edge of SCL, with the last bit indicating
whether a read or write operation is intended. During
the ninth clock pulse, the slave being addressed
responds to the master by generating an
Acknowledge and pulling SDA low.
Data transfer is then initiated and eight bits of data
are sent, followed by an Acknowledge bit. During
data transfer, SDA must remain stable while SCL is
high. Any change in SDA while SCL is high is
interpreted as a START or STOP condition.
Once all data have been transferred, the master
generates a STOP condition, indicated by pulling
SDA from low to high while SCL is high. The
BUF08630 can act only as a slave device; therefore,
it never drives SCL. SCL is an input only for the
BUF08630.
ADDRESSING THE BUF08630
The address of the BUF08630 is 111010x, where x is
the state of the A0 pin. When the A0 pin is low, the
device acknowledges on address 74h (1110100). If
the A0 pin is high, the device acknowledges on
address 75h (1110101). Table 1 shows the A0 pin
settings and BUF08630 address options.
DEVICE/COMPONENT
BUF08630 ADDRESS
ADDRESS
A0 pin is low
(device acknowledges on address 74h)
1110100
A0 pin is high
(device acknowledges on address 75h)
1110101
DATA RATES
The two-wire bus operates in one of three speed
modes:
• Standard: allows clock frequency up to 100 kHz;
• Fast: allows clock frequency up to 400 kHz; and
• High-speed mode (also called Hs mode): allows
clock frequency up to 3.4 MHz.
The BUF08630 is fully compatible with all three
modes. No special action is required to use the
device in Standard or Fast modes, but High-speed
mode must be activated. To activate High-speed
mode, send a special address byte of 00001 xxx, with
SCL ≤ 400 kHz, following the START condition;
where xxx are bits unique to the Hs-capable master,
which can be any value. This byte is called the Hs
master code. Table 2 provides a reference for the
High-speed mode command code. (Note that this
configuration is different from normal address
bytes—the low bit does not indicate read/write
status.) The BUF08630 responds to the High-speed
command regardless of the value of these last three
bits. The BUF08630 does not acknowledge this byte;
the
communication
protocol
prohibits
acknowledgment of the Hs master code. Upon
receiving a master code, the BUF08630 switches on
its Hs mode filters, and communicates at up to 3.4
MHz. Additional high-speed transfers may be initiated
without resending the Hs mode byte by generating a
repeat START without a STOP. The BUF08630
switches out of Hs mode with the next STOP
condition.
Other valid addresses are possible through a simple
mask change. Contact your TI representative for
information.
Table 2. Quick Reference of Command Codes
12
COMMAND
CODE
General-Call Reset
Address byte of 00h followed by a data byte of 06h.
High-Speed Mode
00001xxx, with SCL ≤ 400 kHz; where xxx are bits unique to the Hs-capable master. This
byte is called the Hs master code.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
BUF08630
www.ti.com
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
GENERAL-CALL RESET AND POWER-UP
UPDATING THE DAC OUTPUT VOLTAGES
The BUF08630 responds to a General-Call Reset,
which is an address byte of 00h (0000 0000) followed
by a data byte of 06h (0000 0110). The BUF08630
acknowledges both bytes. Table 2 provides a
reference for the General-Call Reset command code.
Upon receiving a General-Call Reset, the BUF08630
performs a full internal reset, as though it had been
powered off and then on. It always acknowledges the
General-Call address byte of 00h (0000 0000), but
does not acknowledge any General-Call data bytes
other than 06h (0000 0110).
Because the BUF08630 features a double-buffered
register structure, updating the digital-to-analog
converter (DAC) and/or the VCOM register is not the
same as updating the DAC and/or VCOM output
voltage. There are two methods for updating the
DAC/VCOM output voltages.
When the BUF08630 powers up, it automatically
performs a reset. As part of the reset, the BUF08630
is configured for all outputs to change to the last
programmed nonvolatile memory values, or
1000000000 if the nonvolatile memory values have
not been programmed.
Upon power-up or general-call reset, the DAC
registers for channels 1 though 8 are set to 200
(default) that corresponds to mid-scale output for a
10-bit DAC. The high and low limit registers are set to
3FF and 000 respectively. Therefore, the limits are
transparent if not programmed. Reset typically
requires approximately 1ms.
Method 1: Method 1 is used when it is desirable to
have the DAC/VCOM output voltage change
immediately after writing to a DAC register. For each
write transaction, the master sets data bit 15 to a '1'.
The DAC/VCOM output voltage update occurs after
receiving the 16th data bit for the currently-written
register.
Method 2: Method 2 is used when it is desirable to
have all DAC/VCOM output voltages change at the
same time. First, the master writes to the desired
DAC/VCOM channels with data bit 15 a '0'. Then,
when writing the last desired DAC/VCOM channel, the
master sets data bit 15 to a '1'. All DAC/VCOM
channels are updated at the same time after
receiving the 16th data bit.
NONVOLATILE MEMORY
BKSEL Pin
OUTPUT VOLTAGE
Buffer output values are determined by the analog
supply voltage (VS) and the decimal value of the
binary input code used to program that buffer. The
value is calculated using Equation 1:
Code
VOUT = VS ´
1024
Where Code = 0 to 1023.
(1)
The BUF08630 outputs are capable of a full-scale
voltage output change in typically 5 μs; no
intermediate steps are required.
The BUF08630 has 16x rewrite capability of the
nonvolatile memory. Additionally, the BUF08630 has
the ability to store two distinct gamma curves in two
different nonvolatile memory banks, each of which
has 16x rewrite capability. One of the two available
banks is selected using the external input pin,
BKSEL. When this pin is low, BANK0 is selected;
when this pin is high, BANK1 is selected.
When the BKSEL pin changes state, the BUF08630
loads values from the DAC registers to the DAC
outputs for the newly chosen bank. At power-up, the
state of the BKSEL pin determines which memory
bank is selected.
The two-wire master also has the ability to update
(acquire) the DAC registers with the last programmed
nonvolatile memory values using software control.
The bank to be acquired depends on the state of
BKSEL.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
13
BUF08630
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
www.ti.com
General Acquire Command
5. Send a STOP condition on the bus.
A general acquire command is used to update all
registers and DAC/VCOM outputs to the last
programmed values stored in nonvolatile memory. A
single-channel acquire command updates only the
register and DAC/VCOM output of the DAC/VCOM
corresponding to the DAC/VCOM address used in the
single-channel acquire command.
Approximately 36μs (±4 μs) after issuing this
command, the specified DAC/VCOM register and
DAC/VCOM output voltage change to the appropriate
memory value.
These are the steps of the sequence to initiate a
general channel acquire:
1. Be sure BKSEL is in its desired state and has
been stable for at least 1ms.
2. Send a START condition on the bus.
3. Send the appropriate device address (based on
A0) and the read/write bit = low. The BUF08630
acknowledges this byte.
4. Send a DAC/VCOM pointer address byte. Set bit
D7 = 1 and D6 = 0. Bits D5-D0 are any valid
DAC/VCOM address. Although the BUF08630
acknowledges 000000 through 010111, it stores
and returns data only from these addresses:
– 000000 through 000111
– 010010
It returns 0000 for reads from 001000 through
010001, and 010011 through 010111. See
Table 4 for valid DAC/VCOM addresses.
5. Send a STOP condition on the bus.
Approximately 750μs (±80 μs) after issuing this
command, all DAC/VCOM registers and DAC/VCOM
output voltages change to the respective, appropriate
nonvolatile memory values.
Single-Channel Acquire Command
MaxBank
The BUF08630 can provide the user with the number
of times the nonvolatile memory of a particular
DAC/VCOM channel nonvolatile memory has been
written to for the current memory bank. This
information is provided by reading the register at
pointer address 111111.
There are two ways to update the MaxBank register:
1. After initiating a single acquire command, the
BUF08630 updates the MaxBank register with a
code corresponding to how many times that
particular channel memory has been written to.
2. Following a general acquire command, the
BUF08630 updates the MaxBank register with a
code corresponding to the maximum number of
times the most used channel (OUT1-8 and
VCOMs) has been written to.
MaxBank is a read-only register and is only updated
by performing a general- or single-channel acquire.
Table 3 shows the relationship between the number
of times the nonvolatile memory has been
programmed and the corresponding state of the
MaxBank Register.
Table 3. MaxBank Details
NUMBER OF TIMES WRITTEN TO
RETURNS CODE
0
0000
1
0000
2
0001
3
0010
4
0011
5
0100
6
0101
7
0110
8
0111
9
1000
10
1001
11
1010
12
1011
13
1100
14
1101
15
1110
16
1111
These are the steps to initiate a single-channel
acquire:
1. Be sure BKSEL is in its desired state and has
been stable for at least 1ms.
2. Send a START condition on the bus.
3. Send the device address (based on A0) and
read/write
bit
=
low.
The
BUF08630
acknowledges this byte.
4. Send a DAC/VCOM pointer address byte using the
DAC/VCOM address corresponding to the output
and register to update with the OTP memory
value. Set bit D7 = 0 and D6 = 1. Bits D5-D0 are
the DAC/VCOM address. Although the BUF08630
acknowledges 000000 through 010111, it stores
and returns data only from these addresses:
– 000000 through 000111
– 010010
It returns 0000 reads from 001000 through
010001, and 010011 through 010111. See
Table 4 for valid DAC/VCOM addresses.
14
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
BUF08630
www.ti.com
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
Parity Error Correction
The BUF08630 provides single-bit parity error
correction for data stored in the nonvolatile memory
to provide increased reliability of the nonvolatile
memory. If a single bit of nonvolatile memory for a
channel fails, the BUF08630 corrects for it and
updates the appropriate DAC with the intended value
when its memory is acquired.
If more than one bit of nonvolatile memory for a
channel fails, the BUF08630 does not correct for it,
and updates the appropriate DAC/VCOM with the
default value of 1000000000.
DIE_ID AND DIE_REV REGISTERS
The user can verify the presence of the BUF08630 in
the system by reading from address 111101. The
BUF08630 returns 0010000110110110 when read at
this address.
The user can also determine the die revision of the
BUF08630 by reading from register 111100.
BUF08630 returns 0000000000000000 when a RevA
die is present. RevB would be designated by
0000000000000001 and so on.
READ/WRITE OPERATIONS
Read and write operations can be done for a single
DAC/VCOM or for multiple DAC/VCOMs. Writing to a
DAC/VCOM register differs from writing to the
nonvolatile memory. Bits D15–D14 of the most
significant byte of data determines if data are written
to the DAC/VCOM register or the nonvolatile memory.
Read/Write: DAC/VCOM Register (volatile memory)
The BUF08630 is able to read from a single
DAC/VCOM, or multiple DAC/VCOMs, or write to the
register of a single DAC/VCOM or multiple DAC/VCOMs
in a single communication transaction. DAC pointer
addresses begin with 000000 (which corresponds to
OUT1) through 000111 (which corresponds to
OUT8). The VCOM address is 010010.
Write commands are performed by setting the
read/write bit low. Setting the read/write bit high
performs a read transaction.
Writing: DAC/VCOM Register (Volatile Memory)
To write to a single DAC/VCOM register:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = low.
The BUF08630 acknowledges this byte.
3. Send a DAC/VCOM pointer address byte. Set bit
D7 = 0 and D6 = 0. Bits D5–D0 are the
DAC/VCOM address. Although the BUF08630
acknowledges 000000 through 010111, it stores
and returns data only from these addresses:
– 000000 through 000111
– 010010
It returns 0000 for reads from 001000 through
010001, and 010011 through 010111. See
Table 4 for valid DAC/VCOM addresses.
4. Send two bytes of data for the specified register.
Begin by sending the most significant byte first
(bits D15–D8, of which only bits D9 and D8 are
used, and bits D15–D14 must not be 01),
followed by the least significant byte (bits
D7–D0). The register is updated after receiving
the second byte.
5. Send a STOP or START condition on the bus.
The BUF08630 acknowledges each data byte. If the
master terminates communication early by sending a
STOP or START condition on the bus, the specified
register is not updated. Updating the DAC/VCOM
register is not the same as updating the DAC/VCOM
output voltage; see the Updating the DAC Output
Voltages section.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
15
BUF08630
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
www.ti.com
The process of updating multiple DAC/VCOM registers
begins the same as when updating a single register.
However, instead of sending a STOP condition after
writing the addressed register, the master continues
to send data for the next register. The BUF08630
automatically and sequentially steps through
subsequent registers as additional data are sent. The
process continues until all desired registers have
been updated or a STOP or START condition is sent.
The BUF08630 acknowledges each byte. To
terminate communication, send a STOP or START
condition on the bus. Only DAC registers that have
received both bytes of data are updated.
To write to multiple DAC/VCOM registers:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = low.
The BUF08630 acknowledges this byte.
3. Send either the OUT1 pointer address byte to
start at the first DAC, or send the pointer address
byte for whichever DAC/VCOM is the first in the
sequence of DAC/VCOMs to be updated. The
BUF08630 begins with this DAC/VCOM and steps
through subsequent DAC/VCOMs in sequential
order.
4. Send the bytes of data; begin by sending the
most significant byte (bits D15–D8, of which only
bits D9 and D8 have meaning, and bits D15–D14
must not be 01), followed by the least significant
byte (bits D7–D0). The first two bytes are for the
DAC/VCOM addressed in the previous step. The
DAC/VCOM register is automatically updated after
receiving the second byte. The next two bytes are
for the following DAC/VCOM. That DAC/VCOM
register is updated after receiving the fourth byte.
This process continues until the registers of all
following DAC/VCOMs have been updated. The
BUF08630 accepts data for eight DACS, VCOM
voltage, gain set, VCOM high limit, and VCOM low
limit. Note that between these addresses, there
are some unused addresses that must be
skipped. For more details, see Table 4. The write
disable bit cannot be accessed using this
method. It must be written to using the write to a
single DAC register procedure.
5. Send a STOP or START condition on the bus.
To read a single DAC/VCOM/OTHER register:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = low.
The BUF08630 acknowledges this byte.
3. Send the DAC/VCOM/OTHER pointer address
byte. Set bit D7 = 0 and D6 = 0; bits D5–D0 are
the DAC/VCOM/OTHER address. NOTE: The
BUF08630 stores and returns data only from
these addresses:
– 000000 through 000111
– 010010
– 111100 through 111111
It returns 0000 for reads from 001000 through
010001, and 010011 through 010111. See
Table 4 for valid DAC/VCOM/OTHER addresses.
4. Send a START or STOP/START condition.
5. Send the correct device address and read/write
bit = high. The BUF08630 acknowledges this
byte.
6. Receive two bytes of data. They are for the
specified register. The most significant byte (bits
D15–D8) is received first; next is the least
significant byte (bits D7–D0). In the case of
DAC/VCOM channels, bits D15–D10 have no
meaning.
7. Acknowledge after receiving the first byte.
8. Send a STOP or START condition on the bus or
do not acknowledge the second byte to end the
read transaction.
16
Reading: DAC/VCOM/OTHER Register (Volatile
Memory)
Reading a register returns the data stored in that
DAC/VCOM/OTHER register.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
BUF08630
www.ti.com
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
Communication may be terminated by sending a
premature STOP or START condition on the bus, or
by not acknowledging.
To read multiple registers:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = low.
The BUF08630 acknowledges this byte.
3. Send either the OUT1 pointer address byte to
start at the first DAC, or send the pointer address
byte for whichever register is the first in the
sequence of DAC/VCOMs to be read. The
BUF08630 begins with this DAC/VCOM and steps
through subsequent DAC/VCOMs in sequential
order.
4. Send a START or STOP/START condition on the
bus.
5. Send the correct device address and read/write
bit = high. The BUF08630 acknowledges this
byte.
6. Receive two bytes of data. They are for the
specified DAC/VCOM. The first received byte is the
most significant byte (bits D15–D8; only bits D9
and D8 have meaning), next is the least
significant byte (bits D7–D0).
7. Acknowledge after receiving each byte of data.
8. When all desired DACs have been read, send a
STOP or START condition on the bus.
Communication may be terminated by sending a
premature STOP or START condition on the bus, or
by not sending the acknowledge bit. The reading of
registers DieID, DieRev, and MaxBank is not
supported in this mode of operation (these values
must be read using the single register read method).
Write: Nonvolatile Memory for the DAC Register
The BUF08630 is able to write to the nonvolatile
memory of a single DAC/VCOM in a single
communication transaction. In contrast to the
BUF20820, writing to multiple nonvolatile memory
words in a single transaction is not supported. Valid
DAC/VCOM pointer addresses begin with 000000
(which corresponds to OUT1) through 000111 (which
corresponds to OUT8). The VCOM address is 010010.
When programming the nonvolatile memory, the
analog supply voltage must be between 9 V and 20
V. Write commands are performed by setting the
read/write bit low.
To write to a single nonvolatile register:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = low.
The BUF08630 acknowledges this byte. Although
the BUF08630 acknowledges 000000 through
010111, it stores and returns data only from
these addresses:
– 000000 through 000111
– 010010
It returns 0000 for reads from 001000 through
010001, and 010011 through 010111. See
Table 4 for DAC/VCOM addresses.
3. Send a DAC/VCOM pointer address byte. Set bit
D7 = 0 and D6 = 0. Bits D5–D0 are the
DAC/VCOM address.
4. Send two bytes of data for the nonvolatile register
of the specified DAC/VCOM. Begin by sending the
most significant byte first (bits D15–D8, of which
only bits D9 and D8 are data bits, and bits
D15–D14 must be 01), followed by the least
significant byte (bits D7–D0). The register is
updated after receiving the second byte.
5. Send a STOP condition on the bus.
The BUF08630 acknowledges each data byte. If the
master terminates communication early by sending a
STOP or START condition on the bus, the specified
nonvolatile register is not updated. Writing a
nonvolatile register also updates the DAC/VCOM
register and output voltage.
The DAC/VCOM register and DAC/VCOM output voltage
are updated immediately, while the programming of
the nonvolatile memory takes up to 250μs. Once a
nonvolatile register write command has been issued,
no communication with the BUF08630 should take
place for at least 250 μs. Writing or reading over the
serial interface while the nonvolatile memory is being
written jeopardizes the integrity of the data being
stored.
Read: Nonvolatile Memory for the DAC Register
To read the data present in nonvolatile register for a
particular DAC/VCOM channel, the master must first
issue a general acquire command, or a single acquire
command with the appropriate DAC/VCOM channel
chosen. This action updates both the DAC/VCOM
register(s) and DAC/VCOM output voltage(s). The
master may then read from the appropriate
DAC/VCOM register as described earlier.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
17
BUF08630
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
www.ti.com
PROGRAMMABLE VCOM LIMITS
The BUF08630 uses double-buffered registers. The
input of data is stored in the first layer. The input may
be latched to the DAC output, depending upon
application. The DACs update only when the second
layer of latches are enabled.
VCOM channel. Because the input of data is stored in
the first layer of latches, the VCOM output is limited
according to the following rule in either sequence:
1. If the VCOM OTP write is enabled, then the VCOM
input is always stored in the OTP. Limit
comparison happens only before the DAC output.
2. If the VCOM input is higher than the high limit, then
the high limit is latched to the DAC output.
Reading of the DAC register returns the high
limit.
3. If the VCOM input is lower than the low limit, then
the low limit is latched to the DAC output.
Reading of the DAC register returns the low limit.
4. If the VCOM input is in between the high and low
limit, then the programmed value is latched to
DAC output. Reading of the DAC register returns
the programmed value.
5. If the high limit is lower than the low limit, then
the BUF08630 ignores the limits and latches the
programmed value to the DAC output. Reading of
the DAC register returns the programmed value.
The high and low limits can be programmed to any
desired value to limit the VCOM output. The limit can
be programmed before or after programming the
There are two banks of OTP associated with each of
the two limit registers. OTP operations on these two
addresses are valid, just like OTP for DAC registers.
The BUF08630 VCOM output has a programmable
high limit and low limit. The implementation and
interface of these limits are the same as with the
DAC registers. These registers are written to and
read back through the two-wire bus. Addresses for
limiters are 1E and 1F for the high limit and low limit,
respectively. See Table 4 for register pointer
addresses.
Upon power-up or general-call reset, the DAC
registers for VCOM are set to 200 (default) that
corresponds to mid-scale output for a 10-bit DAC.
The high and low limit registers are set to 3FF and
000 respectively. Therefore, the limits are transparent
if not programmed. Reset typically requires
approximately 1ms.
18
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
BUF08630
www.ti.com
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
Table 4. Register Pointer Addresses
COMMENT
Add control MSBs M1 and M0 (see
Table 5)
These special addresses are only
valid in this exact format
POINTER ADDRESS
REGISTER FUNCTION
READ/WRITE PERMISSION
000000
Channel 1 address
R/W
000001
Channel 2 address
R/W
000010
Channel 3 address
R/W
000011
Channel 4 address
R/W
000100
Channel 5 address
R/W
000101
Channel 6 address
R/W
000110
Channel 7 address
R/W
000111
Channel 8 address
R/W
001000
Reserved
R/W
001001
Reserved
R/W
001010
Reserved
R/W
001011
Reserved
R/W
001100
Reserved
R/W
001101
Reserved
R/W
001110
Reserved
R/W
001111
Reserved
R/W
010000
Reserved
R/W
010001
Reserved
R/W
010010
VCOM address
R/W
010011
Reserved
R/W
010100
Reserved
R/W
010101
Reserved
R/W
010110
Reserved
R/W
010111
Reserved
R/W
011000
Reserved
R/W
011001
Reserved
R/W
011010
Reserved
R/W
011011
Reserved
R/W
011100
Gain set
R/W
011101
Reserved
R/W
011110
VCOM high limit
R/W
011111
VCOM low limit
R/W
100000
Reserved
R/W
00111100
Die revision
Read only
00111101
Die ID
Read only
00111111
MaxBank
Read only
00111110
Memory raw data
Read only
Table 5. Control Bits M1 and M0
M0
M1
0
0
Write to DAC register if Write command is received. Read DAC Register if Read command is received.
OPERATION
0
1
Single acquire nonvolatile memory pointed to by the current register address.
1
0
General acquire nonvolatile memory for all DAC registers.
1
1
Not allowed.
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
19
BUF08630
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
www.ti.com
ADJUSTABLE GAIN VCOM
configuration; and an external user-defined, gainselect configuration, as shown in Table 7. The
internal configuration uses the topology depicted in
Figure 25 to achieve the different gain selections that
are selected by setting internal switches 1 through 8.
The VCOM channel has eight internal, adjustable
gain configurations that are selectable through the
I2C bus, as shown in Table 6. The selectable gains
include buffer gains of 1, 2, 3, 4, 5, and 6; a buffer
Table 6. VCOM Gain Set Register Description
REGISTER
ADDRESS
REGISTER
NAME
REGISTER
DESCRIPTION
NUMBER OF
BITS
VOLATILE
MEMORY WRITE
TIMES
POWER-ON
RESET VALUE
NONVOLATILE
MEMORY WRITE
TIMES
1Ch
VcomGain
Set VCOM gain
8
Unlimited
1 (1)
16
(1)
Power-on reset requires 1.2ms.
Table 7. VCOM Gain Set Register (Address = 1Ch)
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
GAIN
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
+1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
–1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
–2
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
–3
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
–4
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
–5
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
–6
0
Set by
external
resistor
1
0
0
0
0
0
0
0
1
RF
RE
RD
RC
0
0
0
0
0
0
Feedback
RG
2
1
3
4
5
RB
6
RA
7
8
VCOM
Feedback
DAC
Figure 25. Feedback Configuration Topology
20
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
BUF08630
www.ti.com
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
Table 8 lists the approximate values (±15%) of the
internal resistors in the feedback configuration
depicted in Figure 25, for a total resistive value of
approximately 13 kΩ (±15%).
For switch positions 2, 3, 4, 5, 6, and 7, the buffer is
configured in an internal inverting gain, as shown in
Figure 26.
Feedback
Table 8. Feedback Resistor Values
RESISTOR
TYPICAL VALUE(1)
(Ω)
RA
6502.5
RB
2165
RC
1083
RD
651.25
R2 int
R1 int
VCOM
VCOM
RE
432.5
RF
310.625
RG
1858.75
Figure 26. Configuration for Switch Positions
2, 3, 4, 5, 6, 7
(1) All values are ±15%.
Table 9. Gain Select Resistor Ratio (±15%)
GAIN
VALUE OF R2 BASED ON SWITCH POSITIONS
VALUE OF R1 BASED ON SWITCH POSITIONS
G=1
6502 Ω
6501 Ω
G=2
8667 Ω
4336 Ω
G=3
9750 Ω
3253 Ω
G=4
10401 Ω
2601 Ω
G=5
10834 Ω
2169 Ω
G=6
11144 Ω
1858 Ω
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
21
BUF08630
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
www.ti.com
Table 10 shows the theoretical gain values of the
inverting configuration using the internal resistors,
±15%.
Feedback
IC
RA
Table 10. Gain Equation
GAIN
RATIO
TYPICAL VALUE
G=1
–R2/R1
–1.00021
G=2
–R2/R1
–1.9989
G=3
–R2/R1
–2.99727
G=4
–R2/R1
–3.99779
G=5
–R2/R1
–4.99418
G=6
–R2/R1
–5.9959
VCOM
DAC
Figure 27. Configuration for Switch Position 8
A buffer configuration is achieved using switch
position 8 as indicated in Figure 27
R1 ext
Feedback
R
An external user-selectable gain configuration is
achieved using switch position 1, as indicated in
Figure 28. By using a single external gain resistor
value and the internal values of the resistor string, a
wide range of selectable gains can be achieved using
the internal switch configuration.
Table 11 shows the possible gains that can be
achieved with a single 1-kΩ external resistor for each
of the internal switch selections.
VCOM
VCOM
Figure 28. Configuration for Switch Position 1
Table 11. Possible Gains Using a 1-kΩ External Resistor
22
EXTERNAL RESISTANCE
INTERNAL RESISTANCE
GAIN
SWITCH POSITION
R1 ext = 1000 Ω
R = 13003.63 Ω
–13.0036
1
R1 ext + RINT = 2858.75 Ω
R = 11144.88 Ω
–3.89851
2
R1 ext + RINT = 3169.375 Ω
R = 10834.25 Ω
–3.41842
3
R1 ext + RINT = 3601.875 Ω
R = 10401.75 Ω
–2.88787
4
R1 ext + RINT = 4253.125 Ω
R = 9750.5 Ω
–2.29255
5
R1 ext + RINT = 5336.125 Ω
R = 8667.5 Ω
–1.62431
6
R1 ext + RINT = 7501.125 Ω
R = 6502.5 Ω
–0.86687
7
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
Figure 29. Write DAC Register Timing
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
A6
A6
A6
SDA_In
Device_Out
Start
A3
A5
A5
A4
A4
A5
A5
A4
A4
A3
A3
Device Address
A2
A2
A5
A5
A4
A4
A3
A3
Device Address
A2
A2
A3
A3
A1
A1
A1
A1
Device Address
Read multiple DAC registers. P4-P0 specify DAC address.
A6
Start
SDA_In
SCL
A4
A3
A2
A2
A1
A1
A2
A0
A0
A0
A0
A2
A1
W
W
Write
W
W
Write
A1
Ackn
Ackn
Ackn
W
D7
W
D7
D7
D7
Read operation.
Ackn
Ackn
Ackn
W
W
Write
Read operation.
A0
A0
A0
A0
Write
D7
D7
D7
D7
D5
D5
D6
D6
D6
D5
D5
D5
D5
P4
P4
P3
P3
P2
P2
P4
D6
D6
D5
D5
P4
P4
P3
P3
P2
P2
P1
P1
P1
P1
P4
Start DAC address pointer. D7-D5 must be 000.
D6
P4
P4
P3
P3
P2
P2
P0
P0
P0
P0
P3
P3
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
P2
P2
P1
P1
P1
P1
Start
Start
DAC address pointer. D7-D5 must be 000.
D6
D6
DAC address pointer. D7-D5 must be 000.
DAC address pointer. D7-D5 must be 000.
Ackn
Ackn
Ackn
Write Operation
Ackn
Ackn
Ackn
Write Operation
D14
D14
D15
D14
D14
A3
A3
A4
A3
A3
Device Address
A4
D14
D14
D15
D13
D13
D11
D11
D10
D10
D13
D13
D12
D12
D11
D11
D10
D10
DAC (pointer) MSbyte. D14 must be 0.
Device Address
A4
D12
D12
D9
D9
D8
D8
Ackn
Ackn
D7
D7
D9
D9
D8
D8
Ackn
Ackn
Ackn
D7
D7
A2
A2
A2
A2
A1
A1
A1
A1
A0
A0
A0
A0
D12
D12
D11
D11
D9
D9
D10
D10
R
D8
D8
R
R
Read
R
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
D15
D15
D7
D7
D15
D11
D11
D10
D10
D9
D9
D6
D6
D6
D6
D8
D8
D13
D12
D12
D11
D11
D10
D10
D14
D6
D6
D14
D13
D12
D12
D11
D11
D10
D5
D5
D4
D4
D3
D3
D2
D2
D10
Final address pointer LSbyte.
D13
D4
D4
D3
D3
DAC LSbyte
D9
D9
Ackn
Ackn
Ackn
D5
D5
D9
D1
D1
D9
D0
D3
D3
D6
D6
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
D7
D7
D0
D8
D8
D8
D8
D4
D4
DAC (pointer) LSbyte
D5
D5
DAC (pointer) MSbyte. D15-D10 have no meaning.
D14
D13
DAC MSbyte. D15-D10 have no meaning.
D14
D12
D13
D15
D12
D13
Ackn
Ackn
D14
D15
Read
D14
D15
Final address pointer MSbyte. D14 must be 0.
If D15 = 1, all DACs are updated when the current DAC register is updated.
D15
A4
D13
D13
Ackn
If D15 = 1, all DACs are updated when the current DAC register is updated.
D15
D15
DAC MSbyte. D14 must be 0.
Final address pointer MSbyte. D15-D10 have no meaning.
A5
A5
A5
A5
Ackn
Ackn
Ackn
Ackn
Ackn
D15
A6
A6
A6
A6
P0
P0
P0
P0
Ackn
D1
D1
D0
D0
Ackn
Ackn
D2
D1
D1
D0
D0
Ackn
Ackn
D7
Stop
D7
D5
D5
D6
D6
D5
D5
D4
D4
D2
D2
D4
D4
D3
D3
DAC LSbyte.
D3
D3
Final address pointer LSbyte
is updated at this moment.
Stop
D2
D2
D1
D1
D15
D15
D0
D0
D1
D1
D14
D14
D0
D0
Stop
Stop
No Ackn
No Ackn
Ackn
Ackn
Ackn
D13
D13
DAC (pointer + 1) MSbyte. D14 must be 0.
The entire DAC register D9-D0
D2
Ackn
is updated at this moment.
The entire DAC register D9-D0
D2
D2
Ackn
www.ti.com
Device_Out
SCL
A5
A4
Read single DAC register. P4-P0 specify DAC address.
A6
A6
SDA_In
Start
Device_Out
SCL
A6
Device_Out
A5
Device Address
Write multiple DAC registers. P4-P0 specify DAC address.
A6
SDA_In
SCL
Start
Write single DAC register. P4-P0 specify DAC address.
BUF08630
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
Figure 30. Read Register Timing
Submit Documentation Feedback
23
24
A6
A6
SDA_In
Device_Out
SCL
Start
A5
A5
A4
A4
A3
A3
Device Address
Figure 31. Write Nonvolatile Register Timing
Submit Documentation Feedback
Product Folder Links: BUF08630
A1
A0
W
W
Ackn
Ackn
D6
D6
D5
D5
P4
P4
P3
P3
P2
P2
A5
A5
A4
A4
A3
A3
Device address.
A2
A2
A1
A1
P1
A0
A0
P1
A6
A6
SDA_In
Device_Out
Start
A5
A5
A4
A4
A3
A3
Device address.
A2
A2
A1
A1
A0
A0
P0
P0
W
W
Write
W
W
Write
Single channel acquire command. P4-P0 must specify and valid DAC address.
A6
Start
Device_Out
SCL
D7
D7
DAC address pointer. D7-D0 must be 000.
General acquire command. P4-P0 must specify and valid DAC address.
A0
Ackn
Write operation.
A6
SCL
A1
Write
SDA_In
A2
A2
Write single OTP register. P4-P0 specify DAC address.
D15
D15
D7
D7
Ackn
Ackn
Ackn
D7
D7
Write Operation
Ackn
Ackn
Ackn
Write Operation
Ackn
Ackn
Ackn
D14
D14
D12
D12
D11
D11
D10
D10
D9
D9
D5
D5
P4
P4
P3
P3
P2
P2
D6
D6
D5
D5
P4
P4
P3
P3
P2
P2
DAC address pointer. D7-D5 must be 010.
D6
D6
DAC address pointer. D7-D5 must be 100.
D13
D13
DAC MSbyte. D15-D14 must be 01.
D8
D8
P1
P1
P1
P1
Ackn
Ackn
Ackn
P0
P0
P0
P0
D7
D6
D6
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
D7
D5
Stop
Stop
D5
D4
D4
D2
D2
D1
D1
D0
D0
Ackn
Ackn
Ackn
Stop
The OTP memory update begins at this time and
requires up to 250ms to complete.
D3
D3
DAC LSbyte.
BUF08630
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
www.ti.com
Figure 32. Acquire Operation Timing
Copyright © 2010–2012, Texas Instruments Incorporated
Figure 33. General-Call Reset Timing
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
Start
High-Speed Command
Address Byte = 00h
Address Byte = 00001xxx (HS Master Code)
Ackn
Ackn
Device enters high-speed mode at ACK clock pulse.
Device exits high-speed mode with stop condition.
No Ackn
Device begins reset at arrow and is in reset until ACK clock pulse.
Then the device acquires memory, etc., as it does at power-up.
Address Byte = 06h
www.ti.com
SDA
SCL
SDA
SCL
Start
General-Call Reset Command
BUF08630
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
Figure 34. High-Speed Mode Timing
Submit Documentation Feedback
25
BUF08630
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
www.ti.com
END-USER SELECTED GAMMA CONTROL
Because the BUF08630 has two banks of nonvolatile
memory, it is well-suited for providing two levels of
gamma control by using the BKSEL pin, as shown in
Figure 35. When the state of the BKSEL pin changes,
the BUF08630 updates all nine programmable buffer
outputs simultaneously after 10 μs, typical.
To update all nine programmable output voltages
simultaneously via hardware, toggle the BKSEL pin to
switch between Gamma Curve 0 (stored in Bank0)
and Gamma Curve 1 (stored in Bank1).
All DAC/VCOM registers and output voltages are
updated simultaneously after approximately 10 μs,
typical.
remain unchanged—the display is unaffected. At the
beginning or the end of a picture frame, the
DAC/VCOM outputs (and therefore, the gamma
voltages) can be quickly updated by writing a '1' in bit
15 of any DAC/VCOM register. For details on the
operation of the double register input structure, see
the Updating the DAC Output Voltages section.
To update all nine programmable output voltages
simultaneously via software, perform the following
actions:
STEP 1: Write to registers 1–9 with bit 15 always '0'.
STEP 2: Write any DAC/VCOM register a second time
with identical data. Make sure that bit 15 is set to '1'.
All DAC/VCOM channels are updated simultaneously
after receiving the last bit of data.
5V
OUTPUT PROTECTION
BUF08630
BKSEL
OUT1
Change in
Output Voltages
BANK0
BANK1
Switch
OUT8
The BUF08630 output stages can safely source and
sink the current levels indicated in Figure 1 and
Figure 2. However, there are other modes where
precautions must be taken to prevent to the output
stages from being damaged by excessive current
flow. The outputs (OUT1 through OUT8, and VCOM)
include ESD protection diodes, as shown in
Figure 36. Normally, these diodes do not conduct and
are passive during typical device operation. However,
unusual operating conditions can occur where the
diodes may conduct, potentially subjecting them to
high, even damaging current levels. These conditions
are most likely to occur when a voltage applied to an
output exceeds (VS) + 0.5 V, or drops below GND –
0.5 V.
Two-Wire
Figure 35. Gamma Control
DYNAMIC GAMMA CONTROL
Dynamic gamma control is a technique used to
improve the picture quality in LCD television
applications. This technique typically requires
switching gamma curves between frames. Using the
BKSEL pin to switch between two gamma curves
does not often provide good results because of the
750 μs required to transfer the data from the
nonvolatile memory to the DAC register. However,
dynamic gamma control can still be accomplished by
storing two gamma curves in an external EEPROM
and writing directly to the DAC register (volatile).
One common scenario where this condition can occur
is when the output pin is connected to a sufficiently
large capacitor, and the BUF08630 power-supply
source (VS) is suddenly removed. Removing the
power-supply source allows the capacitor to
discharge through the current-steering diodes. The
energy released during the high current flow period
causes the power dissipation limits of the diode to be
exceeded. Protection against the high current flow
may be provided by placing a Schottky diode as
shown in Figure 36. This diode must be capable of
discharging the capacitor without allowing more than
0.5V to develop across the internal ESD current
sterring diodes.
The double register input structure saves
programming time by allowing updated DAC values to
be pre-stored into the first register bank. Storage of
this data can occur while a picture is still being
displayed. Because the data are only stored into the
first register bank, the DAC/VCOM output values
26
Submit Documentation Feedback
CAUTION
Do not connect large
capacitors to the output of
the gamma buffers without
connecting
a
Schottky
diode.
Otherwise,
the
device will be damaged.
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
BUF08630
www.ti.com
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
APPLICATION INFORMATION
VS
Figure 37 shows a typical application circuit.
ESD Current
Steering
Diodes
BUF08630
GENERAL POWERPAD DESIGN
CONSIDERATIONS
Schottkey
Diode
The BUF08630 is available in a thermally-enhanced
PowerPAD package. The exposed thermal die must
be soldered to the PCB using thermal vias. Refer to
Texas Instruments' application report SLAU271,
QFN/SON PCB Attachment.
OUTX
or
VCOM
External Capacitor
(not recommended)
Figure 36. Output Pins ESD Protection CurrentSteering Diodes
VCOM-VS
VS
D1(6)
VSH
10mF
OUT8
10mF
NC
A0
OUT5
BUF08630(1)
VSD
OUT4
OUT3
VCOM-OUT
OUT2
R2(3)
BKSEL
VCOM-GND
VCOM-FB
R1(2)
VSH
OUT6
OUT6
OUT5
OUT4
Source
Drivers
LCD
Panel
OUT3
OUT2
OUT1
Timing
Controller
SDA
VS
0.1mF
VCOM-VS
0.1mF
OUT7
SCL
VSD
OUT8
OUT7
OUT1
R3(3)
R4(4)
R5(5)
0.1mF
0.1mF
10mF
10mF
(1)
Exposed thermal pad must be connected to GND.
(2)
R1 should be chosen for best stability.
(3)
R2 and R3 are not needed if internal gain is used.
(4)
R4 must not exceed 10 Ω.
(5)
R5 must never be used. VCOM can provide up to 400mA. A 10-Ω resistor would cause a 4V drop to the device.
(6)
D1 should be used if there is any possibility of VSH exceeding VS.
Figure 37. Typical Application Circuit
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
27
BUF08630
SBOS515A – OCTOBER 2010 – REVISED AUGUST 2012
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (October 2010) to Revision A
Page
•
Changed data sheet associated to BUF08630 device from 1-page (SBOS535) to this full PDF ......................................... 1
•
Updated step 4 in the To write to multiple DAC/VCOM registers subsection ....................................................................... 16
•
Updated Table 4 ................................................................................................................................................................. 19
•
Changed Figure 29 ............................................................................................................................................................. 23
•
Changed Figure 30 ............................................................................................................................................................. 23
28
Submit Documentation Feedback
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: BUF08630
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
BUF08630RGWR
ACTIVE
VQFN
RGW
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 95
BUF
08630
BUF08630RGWT
ACTIVE
VQFN
RGW
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 95
BUF
08630
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Aug-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BUF08630RGWR
VQFN
RGW
20
3000
330.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
BUF08630RGWT
VQFN
RGW
20
250
180.0
12.4
5.3
5.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Aug-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BUF08630RGWR
VQFN
RGW
20
3000
367.0
367.0
35.0
BUF08630RGWT
VQFN
RGW
20
250
210.0
185.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2014, Texas Instruments Incorporated