IRF AUIRFN8458TR Advanced process technology Datasheet

AUTOMOTIVE GRADE
Features
 Advanced Process Technology
 Dual N-Channel MOSFET
 Ultra Low On-Resistance
 175°C Operating Temperature
 Fast Switching
 Repetitive Avalanche Allowed up to Tjmax
 Lead-Free, RoHS Compliant
 Automotive Qualified *
AUIRFN8458
VDSS
RDS(on) typ.
max
40V
8.0m
10m
ID
43A
(@TC (Bottom) = 25°C
Description
Specifically designed for Automotive applications, this
HEXFET® Power MOSFET utilizes the latest processing
techniques to achieve extremely low on-resistance per
silicon area. Additional features of this design are a 175°C
junction operating temperature, fast switching speed and
improved repetitive avalanche rating. These features
combine to make this product an extremely efficient and
reliable device for use in Automotive and wide variety of
other applications.
DUAL PQFN 5X6 mm
G
D
S
Gate
Drain
Source
Applications
 12V Automotive Systems
 Low Power Brushed Motor
 Braking
Base Part Number
Package Type
AUIRFN8458
Dual PQFN 5mm x 6mm
Standard Pack
Form
Quantity
Tape and Reel
4000
Orderable Part Number
AUIRFN8458TR
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only; and
functional operation of the device at these or any other condition beyond those indicated in the specifications is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. The thermal resistance and power dissipation ratings are measured under
board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless otherwise specified.
ID @ TC (Bottom) = 25°C
ID @ TC (Bottom) = 100°C
IDM
Parameter
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current 
Max.
43
30
180
PD @TC (Bottom) = 25°C
Power Dissipation
VGS
EAS
EAS (Tested)
IAR
EAR
TJ
TSTG
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy (Thermally Limited) 
Single Pulse Avalanche Energy 
Avalanche Current 
Repetitive Avalanche Energy 
Operating Junction and
Storage Temperature Range
Units
A
34
W
0.23
± 20
35
37
See Fig. 14, 15, 22a, 22b
W/°C
V
mJ
-55 to + 175
A
°C
HEXFET® is a registered trademark of International Rectifier.
*Qualification standards can be found at http://www.irf.com/
1
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AUIRFN8458
Thermal Resistance
Symbol
RJC (Bottom)
Junction-to-Case 
Parameter
Typ.
–––
Max.
4.4
RJC (Top)
Junction-to-Case 
–––
50
RJA
Junction-to-Ambient 
–––
105
RJA (<10s)
Junction-to-Ambient 
–––
82
Static Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max.
V(BR)DSS
Drain-to-Source Breakdown Voltage
40
–––
–––
–––
37
–––
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient
–––
8.0
10
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
Gate Threshold Voltage
2.2
–––
3.9
gfs
Forward Transconductance
56
–––
–––
RG
Internal Gate Resistance
–––
1.9
–––
–––
–––
1.0
Drain-to-Source Leakage Current
IDSS
–––
–––
150
IGSS
Gate-to-Source Forward Leakage
–––
–––
100
Gate-to-Source Reverse Leakage
–––
––– -100
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max.
Qg
Total Gate Charge
–––
22
33
Qgs
Gate-to-Source Charge
–––
6.3
–––
Qgd
Gate-to-Drain ("Miller") Charge
–––
7.6
–––
Qsync
Total Gate Charge Sync. (Qg - Qgd)
––– 14.4 –––
td(on)
Turn-On Delay Time
–––
9.7
–––
tr
Rise Time
–––
71
–––
td(off)
Turn-Off Delay Time
–––
11
–––
Fall Time
–––
19
–––
tf
Ciss
Input Capacitance
––– 1060 –––
Coss
Output Capacitance
–––
170
–––
Crss
Reverse Transfer Capacitance
–––
100
–––
Coss eff. (ER) Effective Output Capacitance (Energy Related)
–––
210
–––
Coss eff. (TR) Effective Output Capacitance (Time Related)
–––
250
–––
Diode Characteristics
Symbol
Parameter
Min. Typ. Max.
Continuous Source Current
–––
–––
43
IS
(Body Diode)
Pulsed Source Current
–––
–––
180
ISM
(Body Diode) 
VSD
Diode Forward Voltage
–––
–––
1.3
dv/dt
Peak Diode Recovery
–––
8.2
–––
–––
18
–––
trr
Reverse Recovery Time
–––
19
–––
–––
9.6
–––
Qrr
Reverse Recovery Charge
–––
11
–––
IRRM
Reverse Recovery Current
––– 0.89 –––
2
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Units
V
mV/°C
m
V
S

µA
nA
Units
nC
ns
pF
Units
°C/W
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1.0mA
VGS = 10V, ID = 26A
VDS = VGS, ID = 25µA
VDS = 10V, ID = 26A
VDS = 40V, VGS = 0V
VDS = 40V, VGS = 0V, TJ = 125°C
VGS = 20V
VGS = -20V
Conditions
ID = 26A
VDS = 20V
VGS = 10V
ID = 26A, VDS =0V, VGS = 10V
VDD = 26V
ID = 26A
RG = 2.7
VGS = 10V 
VGS = 0V
VDS = 25V
ƒ = 1.0 MHz
VGS = 0V, VDS = 0V to 32V 
VGS = 0V, VDS = 0V to 32V 
Units
Conditions
MOSFET symbol
A
showing the
integral reverse
A
p-n junction diode.
V TJ = 25°C, IS = 26A, VGS = 0V 
V/ns TJ = 175°C, IS= 26A, VDS = 40V
TJ = 25°C
ns
VR = 34V,
TJ = 125°C
I
F = 26A
TJ = 25°C
nC
di/dt = 100A/µs
TJ = 125°C
A TJ = 25°C
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AUIRFN8458
1000
1000
100
BOTTOM
10
4.8V
1
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.15V
4.8V
100
BOTTOM
10
4.8V
60µs PULSE WIDTH
60µs PULSE WIDTH
Tj = 25°C
Tj = 175°C
1
0.1
0.1
1
10
0.1
100
V DS, Drain-to-Source Voltage (V)
10
100
Fig. 2 Typical Output Characteristics
1000
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
1
V DS, Drain-to-Source Voltage (V)
Fig. 1 Typical Output Characteristics
100
T J = 175°C
10
T J = 25°C
VDS = 10V
60µs PULSE WIDTH
1.0
ID = 43A
VGS = 10V
1.8
1.6
1.4
1.2
1.0
0.8
0.6
3
4
5
6
7
8
9
10
11
12
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
Fig. 4 Normalized On-Resistance vs. Temperature
Fig. 3 Typical Transfer Characteristics
100000
14.0
VGS = 0V,
f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
ID= 26A
V GS, Gate-to-Source Voltage (V)
Crss = C gd
Coss = Cds + Cgd
10000
C, Capacitance (pF)
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.15V
4.8V
Ciss
1000
Coss
Crss
100
10
12.0
V DS= 32V
V DS= 20V
10.0
V DS= 8.0V
8.0
6.0
4.0
2.0
0.0
1
10
100
0
5
10
15
20
25
30
V DS, Drain-to-Source Voltage (V)
QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
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AUIRFN8458
1000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
100
100
T J = 175°C
10
T J = 25°C
100µsec
1msec
10
OPERATION
IN THIS
AREA
LIMITED BY
RDS(on)
0.1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.1
VSD, Source-to-Drain Voltage (V)
Fig. 7 Typical Source-to-Drain Diode
Forward Voltage
ID, Drain Current (A)
40
30
20
10
0
25
50
75
100
125
1
150
175
Fig 8. Maximum Safe Operating Area
50
Id = 1.0mA
48
46
44
42
40
-60 -40 -20 0 20 40 60 80 100120140160180
TC , Case Temperature (°C)
T J , Temperature ( °C )
Fig 9. Maximum Drain Current vs. Case Temperature
0.14
0.12
Energy (µJ)
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
0
5
10
15
20
25
30
35
40
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
Fig 10. Drain-to-Source Breakdown Voltage
RDS(on), Drain-to -Source On Resistance ( m)
0.16
-5
10
VDS, Drain-to-Source Voltage (V)
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
50
DC
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
1.0
10msec
1
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120
Vgs = 5.5V
Vgs = 6.0V
Vgs = 7.0V
Vgs = 8.0V
Vgs = 10V
100
80
60
40
20
0
0
20
40
60
80
100 120 140 160
ID, Drain Current (A)
Fig 12. Typical On-Resistance vs. Drain Current
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AUIRFN8458
Thermal Response ( Z thJC ) °C/W
10
D = 0.50
1
0.20
0.10
0.05
0.02
0.01
0.1
0.01
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Avalanche Current (A)
100
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 150°C and
Tstart =25°C (Single Pulse)
10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming  j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs. Pulse Width
EAR , Avalanche Energy (mJ)
40
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 26A
30
20
10
0
25
50
75
100
125
150
175
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as Tjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
Starting T J , Junction Temperature (°C)
Fig 15. Maximum Avalanche Energy vs. Temperature
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PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC
Iav = 2T/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
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25
5.0
ID = 26A
VGS(th) , Gate threshold Voltage (V)
RDS(on), Drain-to -Source On Resistance (m )
AUIRFN8458
20
TJ = 125°C
15
10
TJ = 25°C
5
4
6
8
10
12
14
16
18
4.5
4.0
3.5
3.0
ID
ID
ID
ID
2.5
2.0
= 25µA
= 250µA
= 1.0mA
= 1.0A
1.5
1.0
20
-75 -50 -25
Fig 17. Threshold Voltage vs. Temperature
Fig 16. Typical On-Resistance vs. Gate Voltage
4.0
50
IF = 17A
V R = 64V
QRR (nC)
IRRM (A)
40
TJ = 25°C
TJ = 125°C
2.0
1.0
IF = 17A
V R = 64V
TJ = 25°C
TJ = 125°C
30
20
10
0.0
0
100
200
300
400
500
600
100
200
diF /dt (A/µs)
400
500
600
Fig. 19 - Typical Stored Charge vs. dif/dt
4
60
IF = 26A
V R = 64V
TJ = 25°C
TJ = 125°C
QRR (nC)
IRRM (A)
300
diF /dt (A/µs)
Fig. 18 - Typical Recovery Current vs. dif/dt
3
25 50 75 100 125 150 175
T J , Temperature ( °C )
V GS, Gate -to -Source Voltage (V)
3.0
0
2
50
IF = 26A
V R = 64V
40
TJ = 25°C
TJ = 125°C
30
20
1
10
0
0
100
200
300
400
500
600
diF /dt (A/µs)
Fig. 20 - Typical Recovery Current vs. dif/dt
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100
200
300
400
500
600
diF /dt (A/µs)
Fig. 21 - Typical Stored Charge vs. dif/dt
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AUIRFN8458
Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
Fig 22a. Unclamped Inductive Test Circuit
Fig 23a. Switching Time Test Circuit
Fig 22b. Unclamped Inductive Waveforms
Fig 23b. Switching Time Waveforms
VDD
Fig 24a. Gate Charge Test Circuit
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Fig 24b. Gate Charge Waveform
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AUIRFN8458
Dual PQFN 5x6 Package Details
For more information on board mounting, including footprint and stencil recommendation, please refer to application
note AN-1136: http://www.irf.com/technical-info/appnotes/an-1136.pdf
For more information on package inspection techniques, please refer to application note AN-1154:
http://www.irf.com/technical-info/appnotes/an-1154.pdf
Dual PQFN 5x6 Part Marking
INTERNATIONAL
RECTIFIER LOGO
DATE CODE
ASSEMBLY
SITE CODE
(Per SCOP 200-002)
PIN 1
IDENTIFIER
XXXX
XYWWX
XXXXX
PART NUMBER
(“4 or 5 digits”)
MARKING CODE
(Per Marking Spec)
LOT CODE
(Eng Mode - Min last 4 digits of EATI#)
(Prod Mode - 4 digits of SPN code)
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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Qualification Information†
Automotive
(per AEC-Q101)
Qualification Level
Moisture Sensitivity Level
Human Body Model
ESD
Comments: This part number(s) passed Automotive qualification. IR’s Industrial and Consumer qualification level is granted by extension of the higher Automotive level.
Dual PQFN 5mm x 6mm
MSL1
Class H1A (+/- 500V)
††
AEC-Q101-001
Charged Device Model
Class C5 (+/- 1000V)††
AEC-Q101-005
RoHS Compliant
Yes
† Qualification standards can be found at International Rectifier’s web site: http//www.irf.com/
†† Highest passing voltage.
Notes:
 Repetitive rating; pulse width limited by max. junction temperature.
 Limited by TJmax, starting TJ = 25°C, L =110µH, RG = 50, IAS = 50A, VGS = 10V.
ISD  50A, di/dt  650A/µs, VDD  V(BR)DSS, TJ  175°C.
 Pulse width  400µs; duty cycle 2%.
 Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
 Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS.
 When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques
refer to application note #AN-994: http://www.irf.com/technical-info/appnotes/an-994.pdf
 R is measured at TJ of approximately 90°C.
 This value determined from sample failure population, starting TJ = 25°C, L= 110µH, RG = 50, IAS = 50A, VGS =10V.
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IMPORTANT NOTICE
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the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services
at any time and to discontinue any product or services without notice. Part numbers designated with the “AU” prefix follow
automotive industry and / or customer specific requirements with regards to product discontinuance and process change
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IR warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with IR’s
standard warranty. Testing and other quality control techniques are used to the extent IR deems necessary to support this
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For technical support, please contact IR’s Technical Assistance Center
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WORLD HEADQUARTERS:
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Tel: (310) 252-7105
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