SILABS CY28353OC-2 Differential clock buffer/driver Datasheet

CY28353-2
Differential Clock Buffer/Driver
Features
Description
• Phase-locked loop (PLL) clock distribution for double
data rate synchronous DRAM applications
This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD
operation and differential data input and output levels.
• Distributes one differential clock input to six differential
outputs
This device is a zero delay buffer that distributes a differential
clock input pair (CLKINT, CLKINC) to six differential pairs of
clock outputs (CLKT[0:5], CLKC[0:5]) and one differential pair
feedback clock outputs (FBOUTT, FBOUTC). The clock
outputs are controlled by the input clocks (CLKINT, CLKINC)
and the feedback clocks (FBINT, FBINC).
• External feedback pins (FBINT, FBINC) are used to
synchronize the outputs to the clock input
• Conforms to the DDRI specification
• Spread Aware for electromagnetic interference (EMI)
reduction
• 28-pin SSOP package
The two-line serial bus can set each output clock pair
(CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AVDD is
grounded, the PLL is turned off and bypassed for test
purposes.
The PLL in this device uses the input clocks (CLKINT,
CLKINC) and the feedback clocks (FBINT, FBINC) to provide
high-performance, low-skew, low–jitter output differential
clocks.
Block Diagram
Pin Configuration
10
CLKT0
CLKC0
CLKT1
CLKC1
SDATA
Serial
Interface
Logic
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKINT
CLKINC
FBINC
FBINT
AVDD
PLL
CLKT5
CLKC5
FBOUTT
FBOUTC
CLKC1
GND
SCLK
CLKINT
CLKINC
AVDD
AGND
VDD
CLKT2
CLKC2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CY28353-2
SCLK
CLKC0
CLKT0
VDD
CLKT1
GND
CLKC5
CLKT5
CLKC4
CLKT4
VDD
SDATA
FBINC
FBINT
FBOUTT
FBOUTC
CLKT3
CLKC3
GND
28 pin SSOP
.......................... Document #: 38-07372 Rev. *B Page 1 of 9
400 West Cesar Chavez, Austin, TX 78701
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www.silabs.com
CY28353-2
Pin Description
[1]
Pin Number
Pin Name
I/O
Pin Description
Electrical Characteristics
8
CLKINT
I
Complementary Clock Input.
9
CLKINC
I
Complementary Clock Input.
LV Differential Input
21
FBINC
I
Feedback Clock Input. Connect to
FBOUTC for accessing the PLL.
20
FBINT
I
Feedback Clock Input. Connect to
FBOUTT for accessing the PLL.
Differential Input
2,4,13,17,24,26
CLKT(0:5)
O
Clock Outputs.
1,5,14,16,25,27
CLKC(0:5)
O
Clock Outputs.
Differential Outputs
19
FBOUTT
O
Feedback Clock Output. Connect to Differential Output
FBINT for normal operation. A bypass
delay capacitor at this output will control
Input Reference/Output Clocks phase
relationships.
18
FBOUTC
O
Feedback Clock Output. Connect to
FBINC for normal operation. A bypass
delay capacitor at this output will control
Input Reference/Output Clocks phase
relationships.
7
SCLK
22
SDATA
I, PU Serial Clock Input. Clocks data at
SDATA into the internal register.
I/O,
PU
Data Input for the two-line serial
bus
Serial Data Input. Input data is clocked Data Input and Output for the
to the internal register to enable/disable two-line serial bus
individual outputs. This provides flexibility in power management.
3,12,23
VDD
2.5V Power Supply for Logic.
2.5V Nominal
10
AVDD
2.5V Power Supply for PLL.
2.5V Nominal
6,15,28
GND
Ground.
11
AGND
Analog Ground for PLL.
Function Table
Inputs
VDDA
Outputs
CLKT(0:5)[2]
CLKC(0:5)[2]
H
L
L
H
H
L
L
H
< 20 MHz
Hi-Z
CLKINT
CLKINC
GND
L
GND
H
2.5V
L
2.5V
H
2.5V
< 20 MHz
PLL
FBOUTT
FBOUTC
H
L
H
BYPASSED/OFF
L
H
L
BYPASSED/OFF
H
L
H
On
L
H
L
On
Hi-Z
Hi-Z
Hi-Z
Off
Notes:
1. A bypass capacitor (0.1 F) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
2. Each output pair can be three-stated via the two-line serial interface.
..........................Document #: 38-07372 Rev. *B Page 2 of 9
CY28353-2
Zero Delay Buffer
Serial Data Interface
When used as a zero delay buffer the CY28353-2 will likely be
in a nested clock tree application. For these applications the
CY28353-2 offers a differential clock input pair as a PLL
reference. The CY28353-2 then can lock onto the reference
and translate with near zero delay to low skew outputs. For
normal operation, the external feedback input, FBINT, is
connected to the feedback output, FBOUTT. By connecting
the feedback output to the feedback input the propagation
delay through the device is eliminated. The PLL works to align
the output edge with the input reference edge thus producing
a near zero delay. The reference frequency affects the static
phase offset of the PLL and thus the relative delay between
the inputs and outputs.
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
When VDDA is strapped low, the PLL is turned off and
bypassed for test purposes.
Power Management
The individual output enable/disable control of the CY28353-2
allows the user to implement unique power management
schemes into the design. Outputs are tri-stated when disabled
through the two-line interface as individual bits are set low in
Byte0 and Byte1 registers. The feedback output pair
(FBOUTT, FBOUTC) cannot be disabled via two line serial
bus. The enabling and disabling of individual outputs is done
in such a manner as to eliminate the possibility of partial “runt”
clocks.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block r\ead operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 1. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
Description
Start
Slave address – 7 bits
Write
Block Read Protocol
Bit
1
8:2
9
Description
Start
Slave address – 7 bits
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code – 8 Bits
18:11
Command Code – 8 Bits
19
Acknowledge from slave
19
Acknowledge from slave
Byte Count – 8 bits
(Skip this step if I2C_EN bit set)
20
Repeat start
27:20
28
36:29
37
45:38
46
Acknowledge from slave
27:21
Slave address – 7 bits
Data byte 1 – 8 bits
28
Read = 1
Acknowledge from slave
29
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
....
Data Byte /Slave Acknowledges
....
Data Byte N –8 bits
....
Acknowledge from slave
....
Stop
..........................Document #: 38-07372 Rev. *B Page 3 of 9
37:30
38
46:39
47
55:48
56
Byte Count from slave – 8 bits
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
Acknowledge
CY28353-2
Table 2. Block Read and Block Write Protocol (continued)
Block Write Protocol
Bit
Block Read Protocol
Description
Bit
Description
....
Data bytes from slave / Acknowledge
....
Data Byte N from slave – 8 bits
....
NOT Acknowledge
...
Stop
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
Byte Read Protocol
Description
Bit
Start
1
Slave address – 7 bits
8:2
Description
Start
Slave address – 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code – 8 bits
18:11
Command Code – 8 bits
Acknowledge from slave
19
Acknowledge from slave
Data byte – 8 bits
20
Repeated start
19
27:20
28
Acknowledge from slave
29
Stop
27:21
28
Slave address – 7 bits
Read
29
Acknowledge from slave
37:30
Data from slave – 8 bits
38
NOT Acknowledge
39
Stop
Byte0: Output Register (1 = Enable, 0 = Disable)
Bit
@Pup
Pin#
7
1
2, 1
Description
6
1
4, 5
5
1
–
Reserved
4
1
–
Reserved
3
1
13, 14
2
1
26, 27
1
1
–
0
1
24, 25
CLKT0, CLKC0
CLKT1, CLKC1
CLKT2, CLKC2
CLKT5, CLKC5
Reserved
CLKT4, CLKC4
Byte1: Output Register (1 = Enable, 0 = Disable)
Bit
@Pup
Pin#
7
1
–
6
1
17, 16
5
0
–
Reserved
4
0
–
Reserved
3
0
–
Reserved
2
0
–
Reserved
1
0
–
Reserved
0
0
–
Reserved
..........................Document #: 38-07372 Rev. *B Page 4 of 9
Description
Reserved
CLKT3, CLKC3
CY28353-2
Byte2: Test Register 3
Bit
@Pup
Pin#
7
1
–
0 = PLL leakage test, 1 = disable test
6
1
–
Reserved
5
1
–
Reserved
4
1
–
Reserved
3
1
–
Reserved
2
1
–
Reserved
1
1
–
Reserved
0
1
–
Reserved
Maximum Ratings[3]
Description
Storage Temperature: ................................. –65°C to +150°C
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, VIN and VOUT should be constrained to
the range:
Operating Temperature:.................................... 0°C to +85°C
VSS < (VIN or VOUT) < VDD.
Maximum Power Supply: ................................................ 3.5V
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
Input Voltage Relative to VSS:...............................VSS – 0.3V
Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V
DC Parameters VDDA = VDDQ = 2.5V + 5%, TA = 0C to +70C[4]
Parameter
Description
Condition
Min.
VIL
Input Low Voltage
VIH
Input High Voltage
VID
Differential Input
Voltage[5]
CLKINT, FBINT
0.35
VIX
Differential Input
Crossing Voltage[6]
CLKINT, FBINT
(VDDQ/2) – 0.2
IIN
Input Current
VIN = 0V or VIN = VDDQ,
CLKINT, FBINT
Typ.
SDATA, SCLK
Max.
1.0
2.2
Unit
V
V
VDDQ/2
–10
VDDQ + 0.6
V
(VDDQ/2) + 0.2
V
10
A
IOL
Output Low Current
VDDQ = 2.375V, VOUT = 1.2V
26
35
mA
IOH
Output High Current
VDDQ = 2.375V, VOUT=1V
–18
–32
mA
VOL
Output Low Voltage
VDDQ = 2.375V, IOL = 12 mA
VOH
Output High Voltage
VDDQ = 2.375V, IOH = –12 mA
VOUT
Output Voltage Swing[7]
Output Crossing
Voltage[8]
IOZ
High-impedance Output VO = GND or VO = VDDQ
Current
IDSTAT
Dynamic Supply
Current[9]
(VDDQ/2) – 0.2
All VDDQ and VDDI, FO = 170
MHz
VDDQ – 0.4
V
(VDDQ/2) + 0.2
V
10
µA
300
mA
1
mA
9
12
mA
4
6
pF
VDDQ/2
–10
235
Static Supply Current
IDD
PLL Supply Current
Cin
Input Pin Capacitance
VDDA only
..........................Document #: 38-07372 Rev. *B Page 5 of 9
V
V
1.1
VOC
IDDQ
0.6
1.7
CY28353-2
AC Parameters VDD = VDDQ = 2.5V ± 5%, TA = 0°C to +70°C [10,11]
Parameter
Description
fCLK
Operating Clock Frequency
tDC
Input Clock Duty Cycle
tlock
Maximum PLL lock Time
Tr / Tf
tpZL, tpZH
tpLZ, tpHZ
tCCJ
tjit(h-per)
Condition
Min.
AVDD, VDD = 2.5V ± 0.2V
60
40
Output Clocks Slew Rate
20% to 80% of VOD
1
Output Enable Time[12](all outputs)
Output Disable
Time[12] (all
jitter[14]
Max.
Unit
170
MHz
60
%
100
s
2.5
V/ns
3
outputs)
Cycle to Cycle Jitter
Half-period
Typ.
ns
3
f > 66 MHz
–100
f > 66 MHz
–100
ns
100
ps
100
ps
tPLH
Low-to-High Propagation Delay,
CLKINT to CLKT[0:5]
1.5
3.5
6
ns
tPHL
High-to-Low Propagation Delay,
CLKINT to CLKT[0:5]
1.5
3.5
6
ns
100
ps
–150
150
ps
–50
50
ps
tSKEW
Any Output to Any Output Skew[13]
Error[13]
tPHASE
Phase
tPHASEJ
Phase Error Jitter
f > 66MHz
Notes:
3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply srquencing is NOT required.
4. Unused inputs must be held HIGH or LOW to prevent them from floating.
5. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level and VCP is the complementary input level.
6. Differential cross-point input voltage is expected to track VDDQ and is the voltage at which the differential signals must be crossing.
7. For load conditions see Figure 7.
8. The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120 resistor. See Figure 7.
9. All outputs switching loaded with 16 pF in 60 environment. See Figure 7.
10. Parameters are guaranteed by design and characterization. Not 100% tested in production.
11. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz with a down
spread of –0.5%.
12. Refers to transition of non-inverting output.
..........................Document #: 38-07372 Rev. *B Page 6 of 9
CY28353-2
Differential Parameter Measurement Information
CLKINT
CLKINC
FBINT
FBINC
t()n+1
t()n
t()n =
 n1=N
t()n
(N is large number of samples)
Figure 1. Static Phase Offset
CLKINT
CLKINC
FBINT
FBINC
td()
t()
td()
td()
Figure 2. Dynamic Phase Offset
CLKT[0:5], FBOUTT
CLKC[0:5], FBOUTC
CLKT[0:5], FBOUTT
CLKC[0:5], FBOUTC
tsk(o)
Figure 3. Output Skew
Notes:
13. All differential input and output terminals are terminated with 120/16 pF, as shown in Figure 7.
14. Period Jitter and Half-period Jitter specifications are separate specifications that must be met independently of each other.
..........................Document #: 38-07372 Rev. *B Page 7 of 9
t( )
td()
CY28353-2
CLKT[0:5], FBOUTT
CLKC[0:5], FBOUTC
tc(n)
CLKT[0:5], FBOUTT
CLKC[0:5], FBOUTC
1
f(o)
tjit(hper) = tc(n) - 1
fo
Figure 4. Period Jitter
CLKT[0:5], FBOUTT
CLKC[0:5], FBOUTC
t(hper_N+1)
t(hper_n)
1
f(o)
tjit(hper) = thper(n) - 1
2x fo
Figure 5. Half-Period Jitter
CLKT[0:5], FBOUTT
CLKC[0:5], FBOUTC
t c(n)
t c(n)
tjit(cc) = tc(n)-tc(n+1)
Figure 6. Cycle-to-Cycle Jitter
T PCB
M e a s u re m e n t P o in t
CLKT
16 pF
C L K IN
   
   
C LKC
T PCB
M e a s u re m e n t P o in t
16 pF
   
F B IN T
FBOUTT
FBOUTC
F B IN C
Figure 7. Differential Signal Using Direct Termination Resistor
..........................Document #: 38-07372 Rev. *B Page 8 of 9
CY28353-2
Ordering Information
Part Number
CY28353OC-2
CY28353OC-2T
Package Type
Product Flow
28-pin SSOP
Commercial, 0° to 70°C
28-pin SSOP–Tape and Reel
Commercial, 0° to 70°C
Lead Free
CY28353OXC-2
CY28353OXC-2T
28-pin SSOP
Commercial, 0° to 70°C
28-pin SSOP–Tape and Reel
Commercial, 0° to 70°C
Package Drawing and Dimensions
28-Lead (5.3 mm) Shrunk Small Outline Package O28
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use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or
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..........................Document #: 38-07372 Rev. *B Page 9 of 9