DISCRETE SEMICONDUCTORS DATA SHEET BF1211; BF1211R; BF1211WR N-channel dual-gate MOS-FETs Product specification 2003 Dec 16 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR FEATURES PINNING • Short channel transistor with high forward transfer admittance to input capacitance ratio PIN • Low noise gain controlled amplifier • Excellent low frequency noise performance • Partly internal self-biasing circuit to ensure good cross-modulation performance during AGC and good DC stabilization. DESCRIPTION 1 source 2 drain 3 gate 2 4 gate 1 handbook, 2 columns 4 3 APPLICATIONS • Gain controlled low noise VHF and UHF amplifiers for 5 V digital and analog television tuner applications. 1 2 Top view DESCRIPTION BF1211 marking code: LFp Enhancement type N-channel field-effect transistor with source and substrate interconnected. Integrated diodes between gates and source protect against excessive input voltage surges. The BF1211, BF1211R and BF1211WR are encapsulated in the SOT143B, SOT143R and SOT343R plastic packages respectively. handbook, 2 columns 3 Fig.1 4 2 MSB014 Simplified outline (SOT143B). handbook, halfpage 3 4 2 1 1 Top view Top view MSB035 BF1211R marking code: LHp BF1211WR marking code: MK Fig.2 Fig.3 Simplified outline (SOT143R). MSB842 Simplified outline (SOT343R). QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDS drain-source voltage − − 6 V ID drain current − − 30 mA Ptot total power dissipation − − 180 mW yfs forward transfer admittance 25 30 40 mS Cig1-ss input capacitance at gate 1 − 2.1 2.6 pF Crss reverse transfer capacitance f = 1 MHz − 15 30 fF F noise figure f = 400 MHz − 0.9 1.6 dB Xmod cross-modulation input level for k = 1% at 40 dB AGC 100 105 − dBµV Tj junction temperature − − 150 °C 2003 Dec 16 2 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION BF1211 − plastic surface mounted package; 4 leads SOT143B BF1211R − plastic surface mounted package; reverse pinning; 4 leads SOT143R BF1211WR − plastic surface mounted package; reverse pinning; 4 leads SOT343R LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS drain-source voltage − 6 ID drain current (DC) − 30 mA IG1 gate 1 current − ±10 mA IG2 gate 2 current − ±10 mA Ptot total power dissipation V BF1211; BF1211R Ts ≤ 116 °C; note 1 − 180 mW BF1211WR Ts ≤ 122 °C; note 1 − 180 mW Tstg storage temperature −65 +150 °C Tj junction temperature − 150 °C Note 1. Ts is the temperature of the soldering point of the source lead. THERMAL CHARACTERISTICS SYMBOL Rth(j-s) 2003 Dec 16 PARAMETER VALUE UNIT BF1211; BF1211R 185 K/W BF1211WR 155 K/W thermal resistance from junction to soldering point 3 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR MDB828 250 handbook, halfpage Ptot (mW) 200 (2) 150 (1) 100 50 0 0 50 100 150 Ts (°C) 200 (1) BF1211WR. (2) BF1211; BF1211R. Fig.4 Power derating curve. STATIC CHARACTERISTICS Tj = 25 °C unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VG1-S = VG2-S = 0 V; ID = 10 µA 6 − V V(BR)G1-SS gate 1-source breakdown voltage VG2-S = VDS = 0 V; IG1-S = 10 mA 6 10 V V(BR)G2-SS gate 2-source breakdown voltage VG1-S = VDS = 0 V; IG2-S = 10 mA 6 10 V V(F)S-G1 forward source-gate 1 voltage VG2-S = VDS = 0 V; IS-G1 = 10 mA 0.5 1.5 V V(F)S-G2 forward source-gate 2 voltage VG1-S = VDS = 0 V; IS-G2 = 10 mA 0.5 1.5 V VG1-S(th) gate 1-source threshold voltage VG2-S = 4 V; VDS = 5 V; ID = 100 µA 0.3 1 V VG2-S(th) gate 2-source threshold voltage VG1-S = 5 V; VDS = 5 V; ID = 100 µA 0.35 1 V IDSX drain-source current VG2-S = 4 V; VDS = 5 V; RG1 = 75 kΩ; note 1 11 19 mA IG1-S gate 1 cut-off current VG2-S = VDS = 0 V; VG1-S = 5 V − 50 nA IG2-S gate 2 cut-off current VG1-S = VDS = 0 V; VG2-S = 4 V − 20 nA V(BR)DSS drain-source breakdown voltage Note 1. RG1 connects G1 to VGG = 5 V. 2003 Dec 16 4 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR DYNAMIC CHARACTERISTICS Common source; Tamb = 25 °C; VG2-S = 4 V; VDS = 5 V; ID = 15 mA; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT yfs forward transfer admittance pulsed; Tj = 25 °C 25 30 40 mS Cig1-ss input capacitance at gate 1 f = 1 MHz − 2.1 2.6 pF Cig2-ss input capacitance at gate 2 f = 1 MHz − 1.1 − pF Coss output capacitance f = 1 MHz − 0.9 − pF Crss reverse transfer capacitance f = 1 MHz − 15 30 fF F noise figure f = 11 MHz; GS = 20 mS; BS = 0 − 3.5 − dB f = 400 MHz; YS = YS (opt) − 0.9 1.6 dB f = 800 MHz; YS = YS (opt) − 1.3 2 dB f = 200 MHz; GS = 2 mS; BS = BS (opt); GL = 0.5 mS; BL = BL (opt) − 34 − dB f = 400 MHz; GS = 2 mS; BS = BS (opt); GL = 1 mS; BL = BL (opt) − 29 − dB f = 800 MHz; GS = 3.3 mS; BS = BS (opt); GL = 1 mS; BL = BL (opt) − 24 − dB at 0 dB AGC 90 − − dBµV at 10 dB AGC − 92 − dBµV at 40 dB AGC 100 105 − dBµV Gtr Xmod power gain cross-modulation input level for k = 1%; fw = 50 MHz; funw = 60 MHz; note 1 Note 1. Measured in test circuit Fig.21. 2003 Dec 16 5 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR MDB829 25 ID (1) (2) (3) (4) (mA) 20 MDB830 24 handbook, halfpage handbook, halfpage (1) ID (mA) (2) (5) (3) 16 15 (4) (6) (5) 10 (6) 8 (7) 5 (7) (8) 0 0 0.5 1 0 2.5 2 VG1-S (V) 1.5 0 VDS = 5 V; Tj = 25 °C. 4 VDS (V) 6 VG2-S = 4 V; Tj = 25 °C. (4) VG2-S = 2.5 V. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V. (1) VG2-S = 4 V. (2) VG2-S = 3.5 V. (3) VG2-S = 3 V. 2 (7) VG2-S = 1 V. (1) VG1-S = 1.5 V. Fig.5 Transfer characteristics; typical values. MDB832 40 handbook, halfpage (1) (2) (3) IG1 (µA) (7) VG1-S = 0.9 V. (8) VG1-S = 0.8 V. Fig.6 Output characteristics; typical values. MDB831 100 handbook, halfpage (4) VG1-S = 1.2 V. (5) VG1-S = 1.1 V. (6) VG1-S = 1 V. (2) VG1-S = 1.4 V. (3) VG1-S = 1.3 V. 80 (4) yfs (mS) (1) 30 (2) (3) 60 20 (5) 40 (6) (5) (4) 10 (6) 20 (7) 0 0 0 0.5 1 1.5 0 2 6 12 18 VG1-S (V) VDS = 5 V; Tj = 25 °C. (1) VG2-S = 4 V. (2) VG2-S = 3.5 V. (3) VG2-S = 3 V. Fig.7 VDS = 5 V; Tj = 25 °C. (4) VG2-S = 2.5 V. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V. (7) VG2-S = 1 V. (1) VG2-S = 4 V. (2) VG2-S = 3.5 V. Gate 1 current as a function of gate 1 voltage; typical values. 2003 Dec 16 24 30 ID (mA) Fig.8 6 (3) VG2-S = 3 V. (4) VG2-S = 2.5 V. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V. Forward transfer admittance as a function of drain current; typical values. Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR MDB833 20 MDB834 16 handbook, halfpage handbook, halfpage ID (mA) 16 ID (mA) 12 12 8 8 4 4 0 0 10 0 20 30 40 0 50 IG1(µA) 1 2 3 4 5 VGG (V) VDS = 5 V; VG2-S = 4 V. Tj = 25 °C. VDS = 5 V; VG2-S = 4 V; Tj = 25 °C. RG1 = 75 kΩ (connected to VGG); see Fig.21. Fig.9 Fig.10 Drain current as a function of gate 1 supply voltage (VGG); typical values. Drain current as a function of gate 1 current; typical values. MDB835 20 MDB836 20 handbook, halfpage handbook, halfpage ID (1) (mA) 16 ID (mA) (2) (3) (4) (5) (1) 16 (2) (3) (6) 12 (4) 12 (7) (5) 8 8 4 4 0 0 0 2 4 6 VGG = VDS (V) 0 2 4 VG2-S (V) 6 VG2-S = 4 V; Tj = 25 °C; RG1 connected to VGG; see Fig.21. VDS = 5 V; Tj = 25 °C; RG1 = 75 kΩ (connected to VGG); see Fig.21. (1) RG1 = 47 kΩ. (2) RG1 = 56 kΩ. (3) RG1 = 68 kΩ. (1) VGG = 5 V. (2) VGG = 4.5 V. (3) VGG = 4 V. (4) RG1 = 75 kΩ. (5) RG1 = 82 kΩ. (6) RG1 = 100 kΩ. (7) RG1 = 120 kΩ. Fig.11 Drain current as a function of gate 1 (VGG) and drain supply voltage; typical values. 2003 Dec 16 (4) VGG = 3.5 V. (5) VGG = 3 V. Fig.12 Drain current as a function of gate 2 voltage; typical values. 7 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR MDB837 50 MDB838 0 gain halfpage handbook, handbook, halfpage IG1 (µA) reduction (dB) −10 (1) 40 (2) −20 (3) 30 (4) −30 (5) 20 −40 10 −50 −60 0 0 2 4 VG2-S (V) 6 (3) VGG = 4 V. (4) VGG = 3.5 V. 1 2 4 VDS = 5 V; VGG = 5 V; RG1 = 75 kΩ (connected to VGG); see Fig.21; f = 50 MHz; Tamb = 25 °C. (5) VGG = 3 V. Fig.13 Gate 1 current as a function of gate 2 voltage; typical values. Fig.14 Typical gain reduction as a function of AGC voltage. MDB839 120 3 VAGC (V) VDS = 5 V; Tj = 25 °C; RG1 = 75 kΩ (connected to VGG); see Fig.21. (1) VGG = 5 V. (2) VGG = 4.5 V. 0 MDB840 20 handbook, halfpage handbook, halfpage ID (mA) Vunw (dBµV) 16 110 12 100 8 90 4 80 0 10 20 30 40 0 50 0 gain reduction (dB) 10 20 30 40 50 gain reduction (dB) VDS = 5 V; VGG = 5 V; RG1 = 75 kΩ (connected to VGG); see Fig.21; f = 50 MHz; funw = 60 MHz; Tamb = 25 °C. VDS = 5 V; VGG = 5 V; RG1 = 75 kΩ (connected to VGG); see Fig.21; f = 50 MHz; Tamb = 25 °C. Fig.15 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values. Fig.16 Drain current as a function of gain reduction; typical values. 2003 Dec 16 8 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR MDB841 102 handbook, halfpage MDB842 103 handbook, halfpage −103 |yrs| (µS) yis (mS) ϕrs (deg) ϕrs 102 10 −102 bis 1 |yrs| 10 −10 gis 10−1 10 102 f (MHz) 1 10 103 102 103 f (MHz) −1 VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 °C. VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 °C. Fig.17 Input admittance as a function of frequency; typical values. Fig.18 Reverse transfer admittance and phase as a function of frequency; typical values. MDB843 102 handbook, halfpage −102 |yfs| (mS) ϕfs (deg) yos (mS) |yfs| bos 1 −10 10 ϕfs 1 10 MDB844 10 handbook, halfpage 102 f (MHz) gos 10−1 103 −1 10−2 10 102 f (MHz) VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 °C. VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 °C. Fig.19 Forward transfer admittance and phase as functions of frequency; typical values. Fig.20 Output admittance as a function of frequency; typical values. 2003 Dec 16 9 103 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR VAGC handbook, full pagewidth R1 10 kΩ C1 4.7 nF C3 4.7 nF RGEN 50 Ω R2 50 Ω RL 50 Ω L1 C2 ≈ 2.2 µH DUT C4 4.7 nF RG1 4.7 nF VGG VI VDS MGS315 Fig.21 Cross-modulation test set-up. Table 1 f (MHz) Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 15 mA; Tamb = 25 °C s21 s11 s12 s22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) 50 0.987 −3.86 2.928 175.8 0.0005 89.3 0.993 −1.58 100 0.985 −7.73 2.921 171.6 0.0010 86.9 0.993 −3.14 200 0.979 −15.25 2.807 163.2 0.0015 91.1 0.993 −6.31 300 0.965 −22.84 2.846 155.0 0.0028 77.4 0.988 −9.41 400 0.949 −30.15 2.784 146.7 0.0034 74.0 0.985 −12.48 500 0.929 −30.25 2.704 138.9 0.0037 71.4 0.981 −15.54 600 0.904 −44.24 2.639 130.9 0.0040 69.6 0.976 −18.59 700 0.876 −51.16 2.558 123.0 0.0039 69.0 0.971 −21.65 800 0.846 −58.16 2.486 115.1 0.0037 70.0 0.965 −24.27 900 0.816 −65.15 2.402 107.2 0.0032 74.5 0.960 −27.79 1000 0.791 −72.22 2.315 99.9 0.0028 87.1 0.956 −30.94 Table 2 Noise data: VDS = 5 V; VG2-S = 4 V; ID = 15 mA; Tamb = 25 °C Γopt f (MHz) Fmin (dB) (ratio) (deg) Rn (Ω) 400 0.9 0.693 16.75 29.85 800 1.3 0.707 37.33 29.90 2003 Dec 16 10 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR PACKAGE OUTLINES Plastic surface mounted package; 4 leads SOT143B D B E A X y HE v M A e bp w M B 4 3 Q A A1 c 1 2 Lp b1 e1 detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp b1 c D E e e1 HE Lp Q v w y mm 1.1 0.9 0.1 0.48 0.38 0.88 0.78 0.15 0.09 3.0 2.8 1.4 1.2 1.9 1.7 2.5 2.1 0.45 0.15 0.55 0.45 0.2 0.1 0.1 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 97-02-28 SOT143B 2003 Dec 16 EUROPEAN PROJECTION 11 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR Plastic surface mounted package; reverse pinning; 4 leads D SOT143R B E A X y HE v M A e bp w M B 3 4 Q A A1 c 2 1 Lp b1 e1 detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp b1 c D E e e1 HE Lp Q v w y mm 1.1 0.9 0.1 0.48 0.38 0.88 0.78 0.15 0.09 3.0 2.8 1.4 1.2 1.9 1.7 2.5 2.1 0.55 0.25 0.45 0.25 0.2 0.1 0.1 OUTLINE VERSION SOT143R 2003 Dec 16 REFERENCES IEC JEDEC EIAJ SC-61B 12 EUROPEAN PROJECTION ISSUE DATE 97-03-10 99-09-13 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR Plastic surface mounted package; reverse pinning; 4 leads D SOT343R E B A X HE y v M A e 3 4 Q A A1 c 2 w M B 1 bp Lp b1 e1 detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp b1 c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.4 0.3 0.7 0.5 0.25 0.10 2.2 1.8 1.35 1.15 1.3 1.15 2.2 2.0 0.45 0.15 0.23 0.13 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 97-05-21 SOT343R 2003 Dec 16 EUROPEAN PROJECTION 13 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2003 Dec 16 14 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA75 © Koninklijke Philips Electronics N.V. 2003 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R77/01/pp15 Date of release: 2003 Dec 16 Document order number: 9397 750 12003