Octal LNA/VGA/AAF/ADC and Crosspoint Switch AD9271 Each channel features a variable gain range of 30 dB, a fully differential signal path, an active input preamplifier termination, a maximum gain of up to 40 dB, and an ADC with a conversion rate of up to 50 MSPS. The channel is optimized for dynamic performance and low power in applications where a small package size is critical. LO-C LI-C LG-C LOSW-D LO-D LI-D LG-D LOSW-E LO-E LI-E LG-E LOSW-F LO-F LI-F LG-F LOSW-G LO-G LI-G LG-G LNA VGA AAF LNA VGA AAF LNA VGA AAF LNA VGA AAF LNA VGA AAF LOSW-H LO-H LI-H LG-H LNA VGA AAF SERIAL LVDS DOUTB+ DOUTB– 12-BIT ADC SERIAL LVDS DOUTC+ DOUTC– 12-BIT ADC SERIAL LVDS DOUTD+ DOUTD– 12-BIT ADC SERIAL LVDS DOUTE+ DOUTE– 12-BIT ADC SERIAL LVDS DOUTF+ DOUTF– 12-BIT ADC SERIAL LVDS DOUTG+ DOUTG– 12-BIT ADC SERIAL LVDS DOUTH+ DOUTH– REFERENCE SENSE VREF REFB REFT RBIAS SWITCH ARRAY DATA RATE MULTIPLIER LOSW-C 12-BIT ADC CLK+ CLK– AAF DOUTA+ DOUTA– SDIO VGA SERIAL LVDS SERIAL PORT INTERFACE LNA 12-BIT ADC CSB SCLK AAF LOSW-B LO-B LI-B LG-B DRVDD PDWN STBY VGA FCO+ FCO– DCO+ DCO– 06304-001 The AD9271 is designed for low cost, low power, small size, and ease of use. It contains eight channels of a variable gain amplifier (VGA) with low noise preamplifier (LNA); an antialiasing filter (AAF); and a 12-bit, 10 MSPS to 50 MSPS analog-to-digital converter (ADC). LNA GAIN– GENERAL DESCRIPTION AD9271 GAIN+ Medical imaging/ultrasound Automotive radar LOSW-A LO-A LI-A LG-A CWVDD APPLICATIONS FUNCTIONAL BLOCK DIAGRAM CWD[5:0]+/– 8 channels of LNA, VGA, AAF, and ADC Low noise preamplifier (LNA) Input-referred noise = 1.1 nV/√Hz @ 5 MHz typical, gain = 18 dB SPI-programmable gain = 14 dB/15.6 dB/18 dB Single-ended input; VIN maximum = 400 mV p-p/ 333 mV p-p/250 mV p-p Dual-mode active input impedance matching Bandwidth (BW) > 70 MHz Full-scale (FS) output = 2 V p-p differential Variable gain amplifier (VGA) Gain range = −6 dB to +24 dB Linear-in-dB gain control Antialiasing filter (AAF) 3rd-order Butterworth cutoff Programmable from 8 MHz to 18 MHz Analog-to-digital converter (ADC) 12 bits at 10 MSPS to 50 MSPS SNR = 70 dB SFDR = 80 dB Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link) Data and frame clock outputs Includes crosspoint switch to support continuous wave (CW) Doppler Low power, 150 mW per channel at 12 bits/40 MSPS (TGC) 90 mW per channel in CW Doppler Single 1.8 V supply (3.3 V supply for CW Doppler output bias) Flexible power-down modes Overload recovery in <10 ns Fast recovery from low power standby mode, <2 μs 100-lead TQFP AVDD FEATURES Figure 1. The LNA has a single-ended-to-differential gain that is selectable through the SPI. The LNA input noise is typically 1.2 nV/√Hz, and the combined input-referred noise of the entire channel is 1.4 nV/√Hz at maximum gain. Assuming a 15 MHz noise bandwidth (NBW) and a 15.6 dB LNA gain, the input SNR is roughly 86 dB. In CW Doppler mode, the LNA output drives a transconductance amp that is switched through an 8 × 6 differential crosspoint switch. The switch is programmable through the SPI. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved. AD9271* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS DESIGN RESOURCES View a parametric search of comparable parts. • AD9271 Material Declaration • PCN-PDN Information DOCUMENTATION • Quality And Reliability Application Notes • Symbols and Footprints • AN-1142: Techniques for High Speed ADC PCB Layout • AN-586: LVDS Outputs for High Speed A/D Converters DISCUSSIONS • AN-812: MicroController-Based Serial Port Interface (SPI) Boot Circuit View all AD9271 EngineerZone Discussions. • AN-877: Interfacing to High Speed ADCs via SPI SAMPLE AND BUY • AN-878: High Speed ADC SPI Control Software Visit the product page to see pricing options. Data Sheet • AD9271: Octal LNA/VGA/AAF/ADC and Crosspoint Switch Data Sheet TECHNICAL SUPPORT Submit a technical question or find your regional support number. TOOLS AND SIMULATIONS • Visual Analog DOCUMENT FEEDBACK Submit feedback for this data sheet. REFERENCE MATERIALS Informational • Integrated Analog Front End (AFE) Contains Eight Ultrasound Receive Channels in a Single IC Press • Industry’s First Octal Ultrasound Receiver with Digital I/Q Demodulator and Decimation Filter Reduces Processor Overhead in Ultrasound Systems Technical Articles • MS-2210: Designing Power Supplies for High Speed ADC • Semiconductors: The Heart of Next-Generation Medical Devices This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified. AD9271 TABLE OF CONTENTS Features .............................................................................................. 1 TGC Operation ........................................................................... 25 Applications ....................................................................................... 1 ADC ............................................................................................. 27 General Description ......................................................................... 1 Clock Input Considerations ...................................................... 28 Functional Block Diagram .............................................................. 1 Serial Port Interface (SPI) .............................................................. 35 Revision History ............................................................................... 2 Hardware Interface..................................................................... 35 Product Highlights ........................................................................... 3 Memory Map .................................................................................. 37 Specifications..................................................................................... 4 Reading the Memory Map Table .............................................. 37 AC Specifications.......................................................................... 4 Reserved Locations .................................................................... 37 Digital Specifications ................................................................... 7 Default Values ............................................................................. 37 Switching Specifications .............................................................. 8 Logic Levels ................................................................................. 37 ADC Timing Diagrams ............................................................... 9 Applications Information .............................................................. 41 Absolute Maximum Ratings.......................................................... 10 Design Guidelines ...................................................................... 41 Thermal Impedance ................................................................... 10 Evaluation Board ............................................................................ 42 ESD Caution ................................................................................ 10 Power Supplies ............................................................................ 42 Pin Configuration and Function Descriptions ........................... 11 Input Signals................................................................................ 42 Equivalent Circuits ......................................................................... 14 Output Signals ............................................................................ 42 Typical Performance Characteristics ........................................... 16 Default Operation and Jumper Selection Settings ................. 43 Theory of Operation ...................................................................... 20 Quick Start Procedure ............................................................... 44 Ultrasound................................................................................... 20 Schematics and Artwork ........................................................... 45 Channel Overview...................................................................... 21 Outline Dimensions ....................................................................... 58 Input Overdrive .......................................................................... 23 Ordering Guide .......................................................................... 58 CW Doppler Operation ............................................................. 24 REVISION HISTORY 5/09—Rev. A to Rev. B Changes to Figure 27 ...................................................................... 17 Changes to Figure 40 and Figure 41 ............................................. 21 Changes to Ordering Guide .......................................................... 58 12/07—Rev. 0 to Rev. A Change to AC Specifications Text .................................................. 4 Added Input Noise Current ............................................................ 4 Added Noise Figure .......................................................................... 4 Changes to Signal-to-Noise Ratio Units ........................................ 4 Changes to Harmonic Distortion Units ........................................ 5 Added Endnote 3 .............................................................................. 6 Changes to Table 6 .......................................................................... 11 Inserted Figure 19 and Figure 21 .................................................. 16 Changes to Figure 20 ...................................................................... 16 Changes to Theory of Operation Section .................................... 20 Changes to Figure 40 and Figure 41 ............................................. 21 Change to Active Impedance Matching Section ........................ 22 Changes to LNA Noise Section .................................................... 22 Changes to Figure 43...................................................................... 22 Change to Input Overload Protection Section ........................... 23 Changes to TGC Operation Section ............................................ 25 Changes to Gain Control Section ................................................. 26 Changes to Figure 52...................................................................... 26 Change to Table 11 ......................................................................... 33 Changes to Serial Interface Port (SPI) Section ........................... 35 Changes to Hardware Interface Section ...................................... 35 Changes to Reading the Memory Map Table Section ............... 37 Added Applications Information and Design Guidelines Sections ...................................................... 41 Change to Input Signals Section................................................... 42 Changes to Figure 73...................................................................... 42 Changes to Table 16 ....................................................................... 55 6/07—Revision 0: Initial Version Rev. B | Page 2 of 60 AD9271 The AD9271 requires a LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. Fabricated in an advanced CMOS process, the AD9271 is available in a 16 mm × 16 mm, RoHS compliant, 100-lead TQFP. It is specified over the industrial temperature range of −40°C to +85°C. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO±) for capturing data on the output and a frame clock (FCO±) trigger for signaling a new output byte are provided. PRODUCT HIGHLIGHTS Powering down individual channels is supported to increase battery life for portable applications. There is also a standby mode option that allows quick power-up for power cycling. In CW Doppler operation, the VGA, AAF, and ADC are powered down. The power of the TGC path scales with selectable speed grades. 2. 3. The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudorandom patterns, and custom user-defined test patterns entered via the serial port interface. 1. 4. 5. 6. Rev. B | Page 3 of 60 Small Footprint. Eight channels are contained in a small, space-saving package. Full TGC path, ADC, and crosspoint switch contained within a 100-lead, 16 mm × 16 mm TQFP. Low Power of 150 mW per Channel at 40 MSPS. Integrated Crosspoint Switch. This switch allows numerous multichannel configuration options to enable the CW Doppler mode. Ease of Use. A data clock output (DCO±) operates up to 300 MHz and supports double data rate (DDR) operation. User Flexibility. Serial port interface (SPI) control offers a wide range of flexible features to meet specific system requirements. Integrated Third-Order Antialiasing Filter. This filter is placed between the TGC path and the ADC and is programmable from 8 MHz to 18 MHz. AD9271 SPECIFICATIONS AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 1.0 V internal ADC reference, fIN = 5 MHz, RS = 50 Ω, LNA gain = 15.6 dB (6), AAF LPF cutoff = 1/3 × fS, HPF cutoff = 700 kHz, full temperature, unless otherwise noted. Table 1. Parameter 1 LNA CHARACTERISTICS Gain = 5/6/8 Input Voltage Range, Gain = 5/6/8 Input Common Mode Input Resistance Input Capacitance −3 dB Bandwidth Input Noise Current, Gain = 5/6/8 Input Noise Voltage, Gain = 5/6/8 1 dB Input Compression Point, Gain = 5/6/8 Noise Figure Active Termination Match Unterminated FULL-CHANNEL (TGC) CHARACTERISTICS AAF High-Pass Cutoff AAF Low-Pass Cutoff Bandwidth Tolerance Group Delay Variation Input-Referred Noise Voltage Correlated Noise Ratio Output Offset Signal-to-Noise Ratio (SNR) fIN = 5 MHz at −7 dBFS fIN = 5 MHz at −1 dBFS Conditions Min Single-ended input to differential output Single-ended input to single-ended output LNA output limited to 2 V p-p differential output AD9271-25 Typ Max Min AD9271-40 Typ Max Min AD9271-50 Typ Max Unit 14/15.6/18 14/15.6/18 14/15.6/18 dB 8/9.6/12 8/9.6/12 8/9.6/12 dB 400/333/250 400/333/250 400/333/250 mV p-p SE 2 1.4 1.4 1.4 V RFB = 200 Ω RFB = 400 Ω RFB = ∞ LI-x 50 100 15 15 40 1.1 50 100 15 15 60 1.1 50 100 15 15 70 1.1 Ω Ω kΩ pF MHz pA/√Hz RS = 0 Ω, RFB = ∞ 1.4/1.4/1.3 1.3/1.2/1.1 1.3/1.2/1.1 nV/√Hz VGAIN = 0 V 770/650/495 770/650/495 770/650/495 mV p-p RS = 50 Ω, RFB = 200 Ω 6.7 6.7 6.7 dB RFB = ∞ 4.9 4.4 4.2 dB −3 dB −3 dB, programmable DC/350/700 1/3 × fSAMPLE (8 to 18) ±15 ±2 DC/350/700 1/3 × fSAMPLE (8 to 18) ±15 ±2 DC/350/700 1/3 × fSAMPLE (8 to 18) ±15 ±2 kHz MHz 1.7/1.6/1.5 1.6/1.4/1.3 1.6/1.4/1.2 nV/√Hz −30 −30 −30 dB f = 1 to 18 MHz, gain = 0 V to 1 V LNA gain = 5/6/8, RFB = ∞ No signal, correlated/ uncorrelated AAF high pass = 700 kHz −50 +50 −35 +35 −35 % ns +35 LSB VGAIN = 0 V 65.8 64.4 63.7 dBFS VGAIN = 1 V 62 59.7 59 dBFS Rev. B | Page 4 of 60 AD9271 Parameter 1 Harmonic Distortion Second Harmonic fIN = 5 MHz at −7 dBFS Second Harmonic fIN = 5 MHz at −1 dBFS Third Harmonic fIN = 5 MHz at −7 dBFS Third Harmonic fIN = 5 MHz at −1 dBFS Two-Tone IMD3 (2 × F1 − F2) Distortion fIN1 = 5.0 MHz at −7 dBFS, fIN2 = 6.0 MHz at −7 dBFS Channel-to-Channel Crosstalk Channel-to-Channel Crosstalk (Overrange Condition) 3 Overload Recovery GAIN ACCURACY Gain Law Conformance Error Linear Gain Error Channel-to-Channel Matching GAIN CONTROL INTERFACE Normal Operating Range Gain Range Scale Factor Response Time CW DOPPLER MODE Transconductance Common Mode Input-Referred Noise Voltage Output DC Bias Maximum Output Swing Conditions Min AD9271-25 Typ Max Min AD9271-40 Typ Max Min AD9271-50 Typ Max Unit VGAIN = 0 V −73 −71 −71 dBFS VGAIN = 1 V −80 −72 −68 dBFS VGAIN = 0 V −81 −77 −74 dBFS VGAIN = 1 V −65 −63 −66 dBFS VGAIN = 1 V −54.6 −63.4 −68.5 dBc −70 −70 −70 dB −70 −70 −70 dB 5 5 5 Degrees +0.8 +0.8 +0.8 dB Full TGC path, fIN = 1 MHz to 10 MHz, gain = 0 V to 1 V 25°C 0 < VGAIN < 0.1 V 0.1 V < VGAIN < 0.9 V 0.9 V < VGAIN < 1 V VGAIN = 0.5 V, normalized for ideal AAF loss 0.1 V < VGAIN < 0.9 V −1.2 +1.2 −1.3 +1.3 −1.3 0.2 0 V to 1 V, normalized for ideal AAF loss 30 dB change +1.2 −1.2 −1.2 1 +1.3 0 +1.2 −1.2 −1.3 0.2 0 LNA gain = 5/6/8 CW Doppler output pins LNA gain = 5/6/8, RS = 0 Ω, RFB = ∞ Per channel Per channel −1.2 −1.2 +1.3 0.2 1 0 dB dB dB dB 1 V 10 to 40 10 to 40 10 to 40 dB 31.6 350 31.6 350 31.6 350 dB/V ns 10/12/16 10/12/16 1.5 3.6 1.5 10/12/16 3.6 1.5 3.6 mA/V V 1.8 /1.7/1.5 1.7 /1.5/1.4 1.7 /1.5/1.3 nV/√Hz 2.4 ±2 2.4 ±2 2.4 ±2 mA mA p-p Rev. B | Page 5 of 60 AD9271 Parameter 1 POWER SUPPLY AVDD DRVDD CWVDD IAVDD IDRVDD Total Power Dissipation (Including Output Drivers) Conditions 1.7 1.7 3.0 Full-channel mode CW Doppler mode with four channels enabled Full-channel mode, no signal CW Doppler mode with four channels enabled Power-Down Dissipation Standby Power Dissipation Power Supply Rejection Ratio (PSRR) ADC RESOLUTION ADC REFERENCE Output Voltage Error (VREF = 1 V) Load Regulation @ 1.0 mA (VREF = 1 V) Input Resistance 1 2 3 Min AD9271-25 Typ 1.8 1.8 3.3 505 136 46.7 993 Max Min 1.9 1.9 3.6 1.7 1.7 3.0 1063 192 AD9271-40 Typ 1.8 1.8 3.3 613 160 48.7 1190 Max Min 1.9 1.9 3.6 1.7 1.7 3.0 1280 216 AD9271-50 Typ 1.8 1.8 3.3 742 170 50 1425 Max Unit 1.9 1.9 3.6 V V mA mA 1494 224 mA mW mW 4.5 4.5 4.5 mW 101.7 112.5 120.6 mW 1 1 1 mV/V 12 12 12 Bits ±20 ±20 ±20 mV 3 3 3 mV 6 6 6 kΩ See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. SE = single ended. The overrange condition is specified as being 6 dB more than the full-scale input range. Rev. B | Page 6 of 60 AD9271 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 400 mV p-p differential input, 1.0 V internal ADC reference, AIN = −0.5 dBFS, unless otherwise noted. Table 2. Parameter 1 CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage 2 Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, STBY, SCLK) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (CSB) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO) 3 Logic 1 Voltage (IOH = 800 μA) Logic 0 Voltage (IOL = 50 μA) DIGITAL OUTPUTS (D+, D−), (ANSI-644)1 Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) DIGITAL OUTPUTS (D+, D−), (LOW POWER, REDUCED SIGNAL OPTION)1 Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) 1 2 3 Temperature Min Full Full 25°C 25°C 250 Full Full 25°C 25°C 1.2 Full Full 25°C 25°C 1.2 Full Full 25°C 25°C 1.2 0 Typ Max Unit CMOS/LVDS/LVPECL mV p-p V kΩ pF 1.2 20 1.5 3.6 0.3 V V kΩ pF 3.6 0.3 V V kΩ pF DRVDD + 0.3 0.3 V V kΩ pF 30 0.5 70 0.5 30 2 Full Full 1.79 0.05 V V 454 1.375 mV V 250 1.30 mV V LVDS Full Full 247 1.125 Offset binary LVDS Full Full 150 1.10 Offset binary See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Specified for LVDS and LVPECL only. Specified for 13 SDIO pins sharing the same connection. Rev. B | Page 7 of 60 AD9271 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 400 mV p-p differential input, 1.0 V internal ADC reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3. Parameter 1 CLOCK 2 Maximum Clock Rate Minimum Clock Rate Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) OUTPUT PARAMETERS2, 3 Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) FCO Propagation Delay (tFCO) DCO Propagation Delay (tCPD) 4 DCO to Data Delay (tDATA)4 DCO to FCO Delay (tFRAME)4 Data-to-Data Skew (tDATA-MAX − tDATA-MIN) Wake-Up Time (Standby), VGAIN = 0.5 V Wake-Up Time (Power-Down) Pipeline Latency APERTURE Aperture Uncertainty (Jitter) Temp Min Full Full Full Full 50 Full Full Full Full Full 1.5 Full Full Full 25°C 25°C Full (tSAMPLE/24) − 300 (tSAMPLE/24) − 300 Typ Max 10 10.0 10.0 1.5 25°C 2.3 300 300 2.3 tFCO + (tSAMPLE/24) (tSAMPLE/24) (tSAMPLE/24) ±50 1 1 8 <1 1 3.1 3.1 (tSAMPLE/24) + 300 (tSAMPLE/24) + 300 ±200 Unit MSPS MSPS ns ns ns ps ps ns ns ps ps ps μs ms Clock cycles ps rms See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Can be adjusted via the SPI interface. 3 Measurements were made using a part soldered to FR-4 material. 4 tSAMPLE/24 is based on the number of bits divided by 2, because the delays are based on half duty cycles. 2 Rev. B | Page 8 of 60 AD9271 ADC TIMING DIAGRAMS N–1 AIN tA N tEH tEL CLK– CLK+ tCPD DCO– DCO+ tFRAME tFCO FCO– FCO+ tPD tDATA MSB N–9 D10 N–9 D9 N–9 D8 N–9 D7 N–9 D6 N–9 D5 N–9 D4 N–9 D3 N–9 D2 N–9 D1 N–9 D0 N–9 MSB N–8 D10 N–8 D7 N–9 D8 N–9 D9 N–9 D10 N–9 LSB N–8 D0 N–8 DOUTx+ 06304-002 DOUTx– Figure 2. 12-Bit Data Serial Stream (Default) N–1 AIN tA N tEH tEL CLK– CLK+ tCPD DCO– DCO+ tFRAME tFCO FCO– FCO+ tPD tDATA DOUTx– D0 N–9 D1 N–9 D2 N–9 D3 N–9 D4 N–9 D5 N–9 D6 N–9 06304-004 LSB N–9 DOUTx+ Figure 3. 12-Bit Data Serial Stream, LSB First Rev. B | Page 9 of 60 AD9271 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter ELECTRICAL AVDD DRVDD CWVDD GND AVDD Digital Outputs (DOUTx+, DOUTx−, DCO+, DCO−, FCO+, FCO−) CLK+, CLK− LI-x LO-x LOSW-x CWDx−, CWDx+ SDIO, GAIN+, GAIN− PDWN, STBY, SCLK, CSB REFT, REFB, RBIAS VREF, SENSE ENVIRONMENTAL Operating Temperature Range (Ambient) Storage Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) With Respect To Rating GND GND GND GND DRVDD GND −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to +0.3 V −2.0 V to +2.0 V −0.3 V to +2.0 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL IMPEDANCE Table 5. GND LG-x LG-x LG-x GND GND GND GND GND −0.3 V to +3.9 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to +2.0 V −0.3 V to +2.0 V Air Flow Velocity (m/s) 0.0 1.0 2.5 1 θJA1 20.3 14.4 12.9 θJB θJC 7.6 4.7 Unit °C/W °C/W °C/W θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad soldered to PCB. ESD CAUTION −40°C to +85°C −65°C to +150°C 150°C 300°C Rev. B | Page 10 of 60 AD9271 76 LOSW-D 77 LO-D 78 CWD0– 79 CWD0+ 80 CWD1– 81 CWD1+ 82 CWD2– 83 CWD2+ 84 CWVDD 85 GAIN– 86 GAIN+ 87 RBIAS 88 SENSE 89 VREF 90 REFB 91 REFT 92 AVDD 93 CWD3– 94 CWD3+ 95 CWD4– 96 CWD4+ 97 CWD5– 98 CWD5+ 99 LO-E 100 LOSW-E PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR LI-D 74 LG-D AVDD 3 73 AVDD AVDD 4 72 AVDD 71 LO-C LOSW-F 6 70 LOSW-C LI-F 7 69 LI-C 68 LG-C 67 AVDD AVDD 10 66 AVDD LO-G 11 65 LO-B LOSW-G 12 64 LOSW-B LI-G 13 63 LI-B LG-G 14 62 LG-B AVDD 15 61 AVDD AVDD 16 60 AVDD LO-H 17 59 LO-A LOSW-H 18 58 LOSW-A LI-H 19 57 LI-A LG-H 20 56 LG-A AVDD 21 55 AVDD AVDD 22 54 AVDD CLK– 23 53 CSB CLK+ 24 52 SDIO AVDD 25 51 SCLK LI-E 1 EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) LO-F 5 AD9271 LG-F 8 AVDD 50 PDWN 49 STBY 48 DRVDD 47 DOUTA+ 46 DOUTA– 45 DOUTB+ 44 DOUTB– 43 DOUTC+ 42 DOUTC– 41 DOUTD+ 40 DOUTD– 39 FCO+ 38 FCO– 37 DCO– 35 DOUTE+ 34 DOUTE– 33 DOUTF+ 32 DOUTF– 31 DOUTG+ 30 DOUTG– 29 DOUTH+ 28 DRVDD 26 DOUTH– 27 DCO+ 36 TOP VIEW (Not to Scale) AVDD 9 Figure 4. 100-Lead TQFP Pin Configuration Table 6. Pin Function Descriptions Pin No. 0 3, 4, 9, 10, 15, 16, 21, 22, 25, 50, 54, 55, 60, 61, 66, 67, 72, 73, 92 26, 47 84 1 2 5 6 7 8 11 12 13 14 17 Name GND AVDD Description Ground (exposed paddle should be tied to a quiet analog ground) 1.8 V Analog Supply DRVDD CWVDD LI-E LG-E LO-F LOSW-F LI-F LG-F LO-G LOSW-G LI-G LG-G LO-H 1.8 V Digital Output Driver Supply 3.3 V Analog Supply LNA Analog Input for Channel E LNA Ground for Channel E LNA Analog Output for Channel F LNA Analog Output Complement for Channel F LNA Analog Input for Channel F LNA Ground for Channel F LNA Analog Output for Channel G LNA Analog Output Complement for Channel G LNA Analog Input for Channel G LNA Ground for Channel G LNA Analog Output for Channel H Rev. B | Page 11 of 60 06304-005 75 LG-E 2 AD9271 Pin No. 18 19 20 23 24 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 48 49 51 52 53 56 57 58 59 62 63 64 65 68 69 70 71 74 75 76 77 78 79 80 81 82 83 85 Name LOSW-H LI-H LG-H CLK− CLK+ DOUTH− DOUTH+ DOUTG− DOUTG+ DOUTF− DOUTF+ DOUTE− DOUTE+ DCO− DCO+ FCO− FCO+ DOUTD− DOUTD+ DOUTC− DOUTC+ DOUTB− DOUTB+ DOUTA− DOUTA+ STBY PDWN SCLK SDIO CSB LG-A LI-A LOSW-A LO-A LG-B LI-B LOSW-B LO-B LG-C LI-C LOSW-C LO-C LG-D LI-D LOSW-D LO-D CWD0− CWD0+ CWD1− CWD1+ CWD2− CWD2+ GAIN− Description LNA Analog Output Complement for Channel H LNA Analog Input for Channel H LNA Ground for Channel H Clock Input Complement Clock Input True ADC H Digital Output Complement ADC H Digital Output True ADC G Digital Output Complement ADC G Digital Output True ADC F Digital Output Complement ADC F Digital Output True ADC E Digital Output Complement ADC E Digital Output True Data Clock Digital Output Complement Data Clock Digital Output True Frame Clock Digital Output Complement Frame Clock Digital Output True ADC D Digital Output Complement ADC D Digital Output True ADC C Digital Output Complement ADC C Digital Output True ADC B Digital Output Complement ADC B Digital Output True ADC A Digital Output Complement ADC A Digital Output True Standby Power-Down Full Power-Down Serial Clock Serial Data Input/Output Chip Select Bar LNA Ground for Channel A LNA Analog Input for Channel A LNA Analog Output Complement for Channel A LNA Analog Output for Channel A LNA Ground for Channel B LNA Analog Input for Channel B LNA Analog Output Complement for Channel B LNA Analog Output for Channel B LNA Ground for Channel C LNA Analog Input for Channel C LNA Analog Output Complement for Channel C LNA Analog Output for Channel C LNA Ground for Channel D LNA Analog Input for Channel D LNA Analog Output Complement for Channel D LNA Analog Output for Channel D CW Doppler Output Complement for Channel 0 CW Doppler Output True for Channel 0 CW Doppler Output Complement for Channel 1 CW Doppler Output True for Channel 1 CW Doppler Output Complement for Channel 2 CW Doppler Output True for Channel 2 Gain Control Voltage Input Complement Rev. B | Page 12 of 60 AD9271 Pin No. 86 87 88 89 90 91 93 94 95 96 97 98 99 100 Name GAIN+ RBIAS SENSE VREF REFB REFT CWD3− CWD3+ CWD4− CWD4+ CWD5− CWD5+ LO-E LOSW-E Description Gain Control Voltage Input True External Resistor to Set the Internal ADC Core Bias Current Reference Mode Selection Voltage Reference Input/Output Differential Reference (Negative) Differential Reference (Positive) CW Doppler Output Complement for Channel 3 CW Doppler Output True for Channel 3 CW Doppler Output Complement for Channel 4 CW Doppler Output True for Channel 4 CW Doppler Output Complement for Channel 5 CW Doppler Output True for Channel 5 LNA Analog Output for Channel E LNA Analog Output Complement for Channel E Rev. B | Page 13 of 60 AD9271 EQUIVALENT CIRCUITS AVDD AVDD VCM 15kΩ 350Ω LI-x, LG-x SDIO 06304-008 06304-073 30kΩ Figure 8. Equivalent SDIO Input Circuit Figure 5. Equivalent LNA Input Circuit DRVDD AVDD V V DOUTx– DOUTx+ 06304-075 V V 06304-009 10Ω LO-x, LOSW-x DRGND Figure 9. Equivalent Digital Output Circuit Figure 6. Equivalent LNA Output Circuit 10Ω CLK+ 10kΩ 1.25V 10kΩ SCLK OR PDWN OR STBY 10Ω 30kΩ 06304-010 06304-007 CLK– 1kΩ Figure 7. Equivalent Clock Input Circuit Figure 10. Equivalent SCLK Input Circuit Rev. B | Page 14 of 60 AD9271 AVDD 100Ω RBIAS AVDD 6kΩ 06304-014 06304-011 VREF Figure 14. Equivalent VREF Circuit Figure 11. Equivalent RBIAS Circuit AVDD 70kΩ 1kΩ CSB 50Ω 06304-012 06304-074 GAIN+ Figure 15. Equivalent GAIN+ Input Circuit Figure 12. Equivalent CSB Input Circuit 1kΩ SENSE 40kΩ +0.5V 06304-112 06304-013 GAIN– Figure 13. Equivalent SENSE Circuit Figure 16. Equivalent GAIN− Input Circuit 10Ω 06304-076 CWDx+, CWDx– Figure 17. Equivalent CWDx± Output Circuit Rev. B | Page 15 of 60 AD9271 TYPICAL PERFORMANCE CHARACTERISTICS fSAMPLE = 50 MSPS, fIN = 5 MHz, LPF = 1/3 × fSAMPLE, HPF = 700 kHz, LNA gain = 6×. 25 2.0 SAMPLE SIZE = 720 CHANNELS 1.5 PERCENT OF UNITS (%) ABSOLUTE ERROR (dB) 20 1.0 0.5 +85°C 0 +25°C –40°C –0.5 –1.0 15 10 06304-019 –2.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 06304-121 5 –1.5 0 1.0 –1.0 –0.8 VGAIN (V) –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 GAIN ERROR (dB) Figure 21. Gain Error Histogram with VGAIN = 0.9 V Figure 18. Gain Error vs. VGAIN at Three Temperatures 20 30 SAMPLE SIZE = 720 CHANNELS 18 25 PERCENT OF UNITS (%) 14 12 10 8 6 4 15 10 06304-120 5 2 0 20 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 06304-118 PERCENT OF UNITS (%) 16 0 1.0 –1.25 –1.00 –0.75 –0.50 –0.25 GAIN ERROR (dB) 0 0.25 0.50 0.75 1.00 1.25 CHANNEL-TO-CHANNEL GAIN MATCHING (dB) Figure 19. Gain Error Histogram with VGAIN = 0.1 V Figure 22. Gain Match Histogram for VGAIN = 0.2 V 30 16 SAMPLE SIZE = 720 CHANNELS 25 PERCENT OF UNITS (%) 12 10 8 6 20 15 10 4 06304-116 0 –1.25 –1.00 –0.75 –0.50 –0.25 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 0.1 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 –0.8 –0.9 0 06304-117 5 2 –1.0 PERCENT OF UNITS (%) 14 0 0.25 0.50 0.75 1.00 CHANNEL-TO-CHANNEL GAIN MATCHING (dB) GAIN ERROR (dB) Figure 23. Gain Match Histogram for VGAIN = 0.8 V Figure 20. Gain Error Histogram with VGAIN = 0.5 V Rev. B | Page 16 of 60 1.25 AD9271 –131 1800000 –132 1400000 1200000 1000000 800000 600000 06304-022 400000 200000 0 –5 –4 –3 –2 –1 0 1 2 3 4 LNA GAIN = 8× –133 –134 –135 LNA GAIN = 6× –136 –137 –138 –139 –140 5 LNA GAIN = 5× 06304-021 NUMBER OF HITS 1600000 OUTPUT-REFERRED NOISE (dBFS/ Hz) 2000000 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VGAIN (V) CODES Figure 27. Short-Circuit, Output-Referred Noise vs. VGAIN Figure 24. Output-Referred Noise Histogram with VGAIN = 0.0 V 1200000 64.0 63.5 SNR (dBFS) 1000000 800000 62.5 SNR/SINAD NUMBER OF HITS 63.0 600000 400000 SINAD (dBFS) 62.0 61.5 61.0 60.5 –5 –4 –3 –2 –1 0 1 2 3 4 06304-020 0 06304-023 200000 60.0 59.5 5 0 0.1 0.2 0.3 CODES 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VGAIN (V) Figure 25. Output-Referred Noise Histogram with VGAIN = 1.0 V Figure 28. SNR/SINAD vs. VGAIN, AIN = −6.5 dBFS 1.70 4.5 3.0 2.5 2.0 LNA GAIN = 5× 1.5 LNA GAIN = 6× LNA GAIN = 8× 1.0 0.5 0 0 5 10 15 20 25 1.65 1.60 1.55 1.50 1.45 1.40 –40 06304-024 INPUT-REFERRED NOISE (nV/ Hz) 3.5 06304-025 INPUT-REFERRED NOISE (nV/ Hz) 4.0 –20 0 20 40 60 80 TEMPERATURE (°C) FREQUENCY (MHz) Figure 29. Short-Circuit, Input-Referred Noise vs. Temperature Figure 26. Short-Circuit, Input-Referred Noise vs. Frequency Rev. B | Page 17 of 60 AD9271 0 –50 –55 –3dB LINE –10 (1/3) × 50MSPS THIRD HARMONIC (dBFS) FUNDAMENTAL (dBFS) –5 –15 (1/3) × 40MSPS –20 –25 –30 (1/3) × 25MSPS VGAIN = 1V –60 –65 VGAIN = 0.5V –70 –75 VGAIN = 0.2V 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 –85 25.0 06304-029 –40 –80 06304-030 –35 2 4 6 8 FREQUENCY (MHz) 10 12 14 16 fIN (MHz) Figure 30. Antialiasing Filter (AAF) Pass-Band Response, No HPF Applied Figure 33. Third-Order Harmonic Distortion vs. Frequency, AIN = −0.5 dBFS 300 –40 VGAIN = 0.5V –50 250 SECOND HARMONIC (dBFS) 150 100 VGAIN = 0V 50 1 10 V GAIN = 1V –70 VGAIN = 0V –80 –90 –100 06304-033 0 0.1 –60 VGAIN = 0.5V –110 –40 100 –35 ANALOG INPUT FREQUENCY (MHz) –55 –50 VGAIN = 1V THIRD HARMONIC (dBFS) SECOND HARMONIC (dBFS) –40 –65 –70 –75 VGAIN = 0.5V 06304-028 –80 –85 2 4 6 8 10 12 –25 –20 –15 –10 –5 0 Figure 34. Second-Order Harmonic Distortion vs. ADC Output Level –50 VGAIN = 0.2V –30 ADC OUTPUT LEVEL (dBFS) Figure 31. Antialiasing Filter (AAF) Group Delay Response –60 06304-114 200 14 16 fIN (MHz) –60 V GAIN = 1V –70 VGAIN = 0V –80 –90 –100 06304-115 GROUP DELAY (ns) VGAIN = 1.0V VGAIN = 0.5V –110 –40 –35 –30 –25 –20 –15 –10 –5 0 ADC OUTPUT LEVEL (dBFS) Figure 32. Second-Order Harmonic Distortion vs. Frequency, AIN = −0.5 dBFS Rev. B | Page 18 of 60 Figure 35. Third-Order Harmonic Distortion vs. ADC Output Level AD9271 0 0 –10 AIN1 = AIN2 = –7dBFS AIN1 = AIN2 = –7dBFS f1 = 5MHz f2 = 6MHz IMD2 = –70.59dBc IMD3 = –64.45dBc VGAIN = 1V –20 –20 AMPLITUDE (dBFS) IMD3 (dBFS) –30 –40 –50 8MHz AND 10.3MHz –60 –70 –40 –60 –80 –80 –90 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Figure 36. IMD3 vs. VGAIN f1 = 5MHz f2 = 6MHz –20 –40 –50 –60 –70 VGAIN = 0.5V VGAIN = 0V –90 06304-107 IMD3 (dBFS) –30 VGAIN = 1V –100 –110 –60 –55 –50 –45 –40 –35 –30 5 10 15 20 Figure 38. Typical IMD3 and IMD2 Performance 0 –80 0 FREQUENCY (MHz) VGAIN (V) –10 –120 06304-108 –110 0.2 2.3MHz AND 3.5MHz 5MHz AND 6MHz 06304-106 –100 –100 –25 –20 –15 –10 –5 INPUT AMPLITUDE (dBFS) Figure 37. IMD3 vs. Amplitude Rev. B | Page 19 of 60 25 AD9271 THEORY OF OPERATION following the TGC amplifier, and then beam forming is accomplished digitally. ULTRASOUND The primary application for the AD9271 is medical ultrasound. Figure 39 shows a simplified block diagram of an ultrasound system. A critical function of an ultrasound system is the time gain control (TGC) compensation for physiological signal attenuation. Because the attenuation of ultrasound signals is exponential with respect to distance (time), a linear-in-dB VGA is the optimal solution. The ADC resolution of 12 bits with up to 50 MSPS sampling satisfies the requirements of both general-purpose and highend systems. Power consumption and low cost are of primary importance in low-end and portable ultrasound machines, and the AD9271 is designed for these criteria. Key requirements in an ultrasound signal chain are very low noise, active input termination, fast overload recovery, low power, and differential drive to an ADC. Because ultrasound machines use beam-forming techniques requiring large binaryweighted numbers (for example, 32 to 512) of channels, the lowest power at the lowest possible noise is of key importance. For additional information regarding ultrasound systems, refer to “How Ultrasound System Considerations Influence Front-End Component Choice,” Analog Dialogue, Volume 36, Number 3, May–July 2002, and “The AD9271—A Revolutionary Solution for Portable Ultrasound,” Analog Dialogue, Volume 41, Number 7, July 2007. Most modern machines use digital beam forming. In this technique, the signal is converted to digital format immediately Tx HV AMPs BEAM FORMER CENTRAL CONTROL Tx BEAM FORMER MULTICHANNELS T/R SWITCHES LNA AAF BIDIRECTIONAL CABLE Rx BEAM FORMER (B AND F MODES) AD9271 CW TRANSDUCER ARRAY 128, 256, ETC., ELEMENTS ADC VGA CW (ANALOG) BEAM FORMER SPECTRAL DOPPLER PROCESSING MODE AUDIO OUTPUT Figure 39. Simplified Ultrasound System Block Diagram Rev. B | Page 20 of 60 IMAGE AND MOTION PROCESSING (B MODE) COLOR DOPPLER (PW) PROCESSING (F MODE) DISPLAY 06304-077 HV MUX/ DEMUX AD9271 RFB1 LO-x TO SWITCH ARRAY gm CFB RFB2 TRANSDUCER T/R SWITCH CS CDWx+ CDWx– LOSW-x LI-x ATTENUATOR –30dB TO 0dB LNA CSH CLG +24dB AAF LG-x 12-BIT PIPELINE ADC DOUTx– DOUTx+ AD9271 06304-071 GAIN– GAIN+ GAIN INTERPOLATOR SERIAL LVDS Figure 40. Simplified Block Diagram of a Single Channel CHANNEL OVERVIEW Each channel contains both a TGC signal path and a CW Doppler signal path. Common to both signal paths, the LNA provides useradjustable input impedance termination. The CW Doppler path includes a transconductance amplifier and a crosspoint switch. The TGC path includes a differential X-AMP® VGA, an antialiasing filter, and an ADC. Figure 40 shows a simplified block diagram with external components. The signal path is fully differential throughout to maximize signal swing and reduce even-order distortion; however, the LNA is designed to be driven from a single-ended signal source. Low Noise Amplifier (LNA) Good noise performance relies on a proprietary ultralow noise LNA at the beginning of the signal chain, which minimizes the noise contribution in the following VGA. Active impedance control optimizes noise performance for applications that benefit from input impedance matching. A simplified schematic of the LNA is shown in Figure 41. LI-x is capacitively coupled to the source. An on-chip bias generator establishes dc input bias voltages of around 1.4 V and centers the output common-mode levels at 0.9 V (VDD/2). A capacitor, CLG, of the same value as the input coupling capacitor, CS, is connected from the LG-x pin to ground. CFB RFB1 RFB2 AVDD2 VO+ VCM VCM LO-x LI-x CSH Low value feedback resistors and the current-driving capability of the output stage allow the LNA to achieve a low input-referred noise voltage of 1.2 nV/√Hz. This is achieved with a current consumption of only 16 mA per channel (30 mW). On-chip resistor matching results in precise single-ended gains, which are critical for accurate impedance control. The use of a fully differential topology and negative feedback minimizes distortion. Low HD2 is particularly important in second-harmonic ultrasound imaging applications. Differential signaling enables smaller swings at each output, further reducing third-order distortion. Active Impedance Matching The LNA consists of a single-ended voltage gain amplifier with differential outputs and the negative output externally available. For example, with a fixed gain of 6× (15.6 dB), an active input termination is synthesized by connecting a feedback resistor between the negative output pin, LO-x, and the positive input pin, LI-x. This technique is well known and results in the input resistance shown in Equation 1: R IN = LG-x CLG 06304-101 TRANSDUCER T/R SWITCH CS VO– LOSW-x The LNA supports differential output voltages as high as 2 V p-p with positive and negative excursions of ±0.5 V from a commonmode voltage of 0.9 V. The LNA differential gain sets the maximum input signal before saturation. One of three gains is set through the SPI. The corresponding input full scale for the gain settings of 5, 6, or 8 is 400 mV p-p, 333 mV p-p, and 250 mV p-p, respectively. Overload protection ensures quick recovery time from large input voltages. Because the inputs are capacitively coupled to a bias voltage near midsupply, very large inputs can be handled without interacting with the ESD protection. R FB (1 + A 2) where A/2 is the single-ended gain or the gain from the LI-x inputs to the LO-x outputs. Figure 41. Simplified LNA Schematic Rev. B | Page 21 of 60 (1) AD9271 Because the amplifier has a gain of 6× from its input to its differential output, it is important to note that the gain A/2 is the gain from Pin LI-x to Pin LO-x, and it is 6 dB less than the gain of the amplifier, or 9.6 dB (3×). The input resistance is reduced by an internal bias resistor of 15 kΩ in parallel with the source resistance connected to Pin LI-x, with Pin LG-x ac grounded. Equation 2 can be used to calculate the needed RFB for a desired RIN, even for higher values of RIN. R IN = R FB || 15 k Ω (1 + 3) (2) For example, to set RIN to 200 Ω, the value of RFB is 845 Ω. If the simplified equation (Equation 2) is used to calculate RIN, the value is 190 Ω, resulting in a gain error less than 0.5 dB. Some factors, such as the presence of a dynamic source resistance, might influence the absolute gain accuracy more significantly. At higher frequencies, the input capacitance of the LNA needs to be considered. The user must determine the level of matching accuracy and adjust RFB accordingly. The bandwidth (BW) of the LNA is about 70 MHz. Ultimately the BW of the LNA limits the accuracy of the synthesized RIN. For RIN = RS up to about 200 Ω, the best match is between 100 kHz and 10 MHz, where the lower frequency limit is determined by the size of the ac-coupling capacitors, and the upper limit is determined by the LNA BW. Furthermore, the input capacitance and RS limit the BW at higher frequencies. Figure 42 shows RIN vs. frequency for various values of RFB. 1k RS = 500Ω, RFB = 2kΩ Table 7. Active Termination External Component Values LNA Gain 5× 6× 8× 5× 6× 8× 5× 6× 8× RIN (Ω) 50 50 50 100 100 100 200 200 200 RFB (Ω) 175 200 250 350 400 500 700 800 1000 Minimum CSH (pF) 90 70 50 30 20 10 N/A N/A N/A LNA Noise The short-circuit noise voltage (input-referred noise) is an important limit on system performance. The short-circuit noise voltage for the LNA is 1.2 nV/√Hz or 1.4 nV/√Hz (at 15.6 dB LNA gain), including the VGA noise. These measurements, which were taken without a feedback resistor, provide the basis for calculating the input noise and noise figure (NF) performance of the configurations shown in Figure 43. Figure 44 and Figure 45 are simulations of noise figure vs. RS results using these configurations and an input-referred noise voltage of 4 nV/√Hz for the VGA. Unterminated (RFB = ∞) operation exhibits the lowest equivalent input noise and noise figure. Figure 45 shows the noise figure vs. source resistance rising at low RS—where the LNA voltage noise is large compared with the source noise—and at high RS due to the noise contribution from RFB. The lowest NF is achieved when RS matches RIN. INPUT IMPEDANCE (Ω) UNTERMINATED RIN RS = 200Ω, RFB = 800Ω RS RS = 100Ω, RFB = 400Ω, CSH = 20pF VIN 100 + VOUT – RS = 50Ω, RFB = 200Ω, CSH = 70pF RESISTIVE TERMINATION RIN 06304-105 RS 1M 10M VIN + RS VOUT – 50M FREQUENCY (Hz) ACTIVE IMPEDANCE MATCH RFB R Figure 42. RIN vs. Frequency for Various Values of RFB (Effects of RSH and CSH Are Also Shown) IN RS Note that at the lowest value, 50 Ω, in Figure 42, RIN peaks at frequencies greater than 10 MHz. This is due to the BW roll-off of the LNA, as mentioned previously. However, as can be seen for larger RIN values, parasitic capacitance starts rolling off the signal BW before the LNA can produce peaking. CSH further degrades the match; therefore, CSH should not be used for values of RIN that are greater than 100 Ω. Table 7 lists the recommended values for RFB and CSH in terms of RIN. CFB is needed in series with RFB because the dc levels at Pin LO-x and Pin LI-x are unequal. Rev. B | Page 22 of 60 VIN + VOUT – RIN = RFB 1 + A/2 Figure 43. Input Configurations 06304-104 10 100k BW (MHz) 49 59 73 49 59 73 49 49 49 AD9271 16 INPUT OVERDRIVE Excellent overload behavior is of primary importance in ultrasound. Both the LNA and VGA have built-in overdrive protection and quickly recover after an overload event. 14 UNTERMINATED NOISE FIGURE (dB) 12 RESISTIVE TERMINATION 10 Input Overload Protection ACTIVE TERMINATION 8 As with any amplifier, voltage clamping prior to the inputs is highly recommended if the application is subject to high transient voltages. 6 4 100 1000 RS (Ω) Figure 44. Noise Figure vs. RS for Resistive Termination, Active Termination Matched, and Unterminated Inputs, VGain = 1 V, 15.6 dB LNA Gain 16 NOISE FIGURE (dB) 14 12 RIN = 50Ω 10 RIN = 75Ω 8 RIN = 100Ω 6 2 0 10 06304-102 4 RIN = 200Ω UNTERMINATED 100 1000 RS (Ω) Figure 45. Noise Figure vs. RS for Various Fixed Values of RIN, Active Termination Matched Inputs, VGain = 1 V, 15.6 dB LNA Gain The primary purpose of input impedance matching is to improve the transient response of the system. With resistive termination, the input noise increases due to the thermal noise of the matching resistor and the increased contribution of the LNA’s input voltage noise generator. With active impedance matching, however, the contributions of both are smaller (by a factor of 1/(1 + LNA Gain)) than they would be for resistive termination. Figure 44 shows the relative noise figure performance. In this graph, the input impedance was swept with RS to preserve the match at each point. The noise figures for a source impedance of 50 Ω are 7.1 dB, 4.1 dB, and 2.5 dB for the resistive termination, active termination, and unterminated configurations, respectively. The noise figures for 200 Ω are 4.6 dB, 2.0 dB, and 1.0 dB, respectively. A block diagram of a simplified ultrasound transducer interface is shown in Figure 46. A common transducer element serves the dual functions of transmitting and receiving ultrasound energy. During the transmitting phase, high voltage pulses are applied to the ceramic elements. A typical transmit/receive (T/R) switch can consist of four high voltage diodes in a bridge configuration. Although the diodes ideally block transmit pulses from the sensitive receiver input, diode characteristics are not ideal, and resulting leakage transients imposed on the LI-x inputs can be problematic. Because ultrasound is a pulse system and time-of-flight is used to determine depth, quick recovery from input overloads is essential. Overload can occur in the preamp and the VGA. Immediately following a transmit pulse, the typical VGA gains are low, and the LNA is subject to overload from T/R switch leakage. With increasing gain, the VGA can become overloaded due to strong echoes that occur near field echoes and acoustically dense materials, such as bone. Figure 46 illustrates an external overload protection scheme. A pair of back-to-back Schottky diodes is installed prior to installing the ac-coupling capacitors. Although the BAS40 diodes are shown, any diode is prone to exhibiting some amount of shot noise. Many types of diodes are available for achieving the desired noise performance. The configuration shown in Figure 46 tends to add 2 nV/√Hz of input-referred noise. Decreasing the 5 kΩ resistor and increasing the 2 kΩ resistor may improve noise contribution, depending on the application. With the diodes shown in Figure 46, clamping levels of ±0.5 V or less significantly enhance the overload performance of the system. Figure 45 shows the noise figure as it relates to RS for various values of RIN, which is helpful for design purposes. Rev. B | Page 23 of 60 +5V Tx DRIVER 5kΩ AD9271 HV BAS40-04 10nF LNA 2kΩ 5kΩ 10nF TRANSDUCER –5V Figure 46. Input Overload Protection 06304-100 0 10 06304-103 2 AD9271 gain, and it defines a focal point within the body from which the location of the returning echo is derived. CW DOPPLER OPERATION Modern ultrasound machines used for medical applications employ a 2N binary array of receivers for beam forming, with typical array sizes of 16 or 32 receiver channels phase-shifted and summed together to extract coherent information. When used in multiples, the desired signals from each channel can be summed to yield a larger signal (increased by a factor N, where N is the number of channels), and the noise is increased by the square root of the number of channels. This technique enhances the signal-to-noise performance of the machine. The critical elements in a beam-former design are the means to align the incoming signals in the time domain and the means to sum the individual signals into a composite whole. The AD9271 includes the front-end components needed to implement analog beam forming for CW Doppler operation. These components allow CW channels with similar phases to be coherently combined before phase alignment and down mixing, thus reducing the number of delay lines or adjustable phase shifters/ down mixers (AD8333 or AD8339) required. Next, if delay lines are used, the phase alignment is performed and then the channels are coherently summed and down converted by a dynamic range I/Q demodulator. Alternatively, if phase shifters/down mixers, such as the AD8333 and AD8339, are used, phase alignment and downconversion are done before coherently summing all channels into I/Q signals. In either case, the resultant I and Q signals are filtered and sampled by two high resolution ADCs, and the sampled signals are processed to extract the relevant Doppler information. Beam forming, as applied to medical ultrasound, is defined as the phase alignment and summation of signals that are generated from a common source but received at different times by a multielement ultrasound transducer. Beam forming has two functions: it imparts directivity to the transducer, enhancing its AD9271 LNA gm LNA gm SWITCH ARRAY 8 × CHANNEL AD8333 600nH gm LNA 2.5V 700Ω 600nH gm LNA 600nH 2.5V 700Ω 600nH AD8333 AD9271 600nH 700Ω 2.5V gm LNA gm 600nH 600nH 2.5V 600nH 700Ω SWITCH ARRAY 8 × CHANNEL LNA gm LNA gm I 16-BIT ADC Q Figure 47. Typical CW Doppler System Using the AD9271 and AD8333 or AD8339 Rev. B | Page 24 of 60 16-BIT ADC 06304-096 LNA AD9271 Crosspoint Switch The system gain is distributed as listed in Table 8. Each LNA is followed by a transconductance amp for V/I conversion. Currents can be routed to one of six pairs of differential outputs or to 12 single-ended outputs for summing. Each CWD output pin sinks 2.4 mA dc current, and the signal has a full-scale current of ±2 mA for each channel selected by the crosspoint switch. For example, if four channels were to be summed on one CWD output, the output would sink 9.6 mA dc and have a full-scale current output of ±8 mA. The maximum number of channels combined must be considered when setting the load impedance for I/V conversion to ensure that the full-scale swing and common-mode voltage are within the operating limits of the AD9271. When interfacing to the AD8339, a commonmode voltage of 2.5 V and a full-scale swing of 2.8 V p-p are desired. This can be accomplished by connecting an inductor between each CWD output and a 2.5 V supply, and then connecting either a single-ended or differential load resistance to the CWD± outputs. The value of resistance should be calculated based on the maximum number of channels that can be combined. CWD± outputs are required under full-scale swing to be greater than 1.5 V and less than CWVDD (3.3 V supply). TGC OPERATION The TGC signal path is fully differential throughout to maximize signal swing and reduce even-order distortion; however, the LNAs are designed to be driven from a single-ended signal source. Gain values are referenced from the single-ended LNA input to the differential ADC input. A simple exercise in understanding the maximum and minimum gain requirements is shown in Figure 48. ADC FS (2V p-p) ~5dB MARGIN MINIMUM GAIN LNA FS (0.333V p-p SE) 70dB ADC 87dB >8dB MARGIN ADC NOISE FLOOR (224µV rms) LNA VGA GAIN RANGE > 30dB MAX CHANNEL GAIN > 40dB 06304-097 MAXIMUM GAIN LNA INPUT-REFERRED NOISE FLOOR (5.4µV rms) @ AAF BW = 15MHz LNA + VGA NOISE = 1.4nV/ Hz Figure 48. Gain Requirements of TGC for a 12-Bit, 40 MSPS ADC In summary, the maximum gain required is determined by (ADC Noise Floor/VGA Input Noise Floor) + Margin = 20 log(224/5.4) + 8 dB = 40.3 dB The minimum gain required is determined by (ADC Input FS/VGA Input FS) + Margin = 20 log(2/0.333) – 5 dB = 10.6 dB Therefore, a 12-bit, 40 MSPS ADC with 15 MHz of bandwidth should suffice in achieving the dynamic range required for most of today’s ultrasound systems. Table 8. Channel Gain Distribution Section LNA Attenuator VGA Amp Filter ADC Total Nominal Gain (dB) 14/15.6/18 0 to −30 24 0 0 8.4 to 38.4/10 to 40/12.4 to 42.4 The linear-in-dB gain (law conformance) range of the TGC path is 30 dB, extending from 10 dB to 40 dB. The slope of the gain control interface is 31.6 dB/V, and the gain control range is 0 V to 1 V as specified in Equation 3. Equation 4 is the expression for channel gain. VGAIN (V ) = (GAIN +) − (GAIN −) + 0.5 Gain (dB) = 31.6 dB VGAIN + ICPT V (3) (4) where ICPT is the intercept point of the TGC gain. In its default condition, the LNA has a gain of 15.6 dB (6×) and the VGA gain is −6 dB if the voltage on the GAIN± pins is 0 V. This gives rise to a total gain (or ICPT) of 10 dB through the TGC path if the LNA input is unmatched, or of 4 dB if the LNA is matched to 50 Ω (RFB = 200 Ω). If the voltage on the GAIN± pins is 1 V, however, the VGA gain is 24 dB. This gives rise to a total gain of 40 dB through the TGC path if the LNA input is unmatched, or of 34 dB if the LNA input is matched. Each LNA output is dc-coupled to a VGA input. The VGA consists of an attenuator with a range of 30 dB followed by an amplifier with 24 dB of gain for a net gain range of −6 dB to +24 dB. The X-AMP gain-interpolation technique results in low gain error and uniform bandwidth, and differential signal paths minimize distortion. At low gains, the VGA should limit the system noise performance (SNR); at high gains, the noise is defined by the source and LNA. The maximum voltage swing is bound by the full-scale peak-to-peak ADC input voltage (2 V p-p). Both the LNA and VGA have limitations within each section of the TGC path, depending on the voltage applied to the GAIN+ and GAIN− pins. The LNA has three limitations, or full-scale settings, depending on the gain selection applied through the SPI interface. When a voltage of 0.2 V or less is applied to the GAIN± pins, the LNA operates near the full-scale input range to maximize the dynamic range of the ADC without clipping the signal. When more than 0.2 V is applied to the GAIN± pins, the input signal to the LNA must be lowered to keep it within the full-scale range of the ADC (see Figure 49). Rev. B | Page 25 of 60 AD9271 0.450 slope is monotonic with respect to the control voltage and is stable with variations in process, temperature, and supply. LNA GAIN = 5x The X-AMP inputs are part of a 24 dB gain feedback amplifier that completes the VGA. Its bandwidth is about 70 MHz. The input stage is designed to reduce feedthrough to the output and to ensure excellent frequency response uniformity across the gain setting. 0.350 LNA GAIN = 6x 0.300 0.250 0.200 LNA GAIN = 8x 0.150 Gain Control 0.100 The gain control interface, GAIN±, is a differential input. The VGA gain, VGAIN, is shown in Equation 3. VGAIN varies the gain of all VGAs through the interpolator by selecting the appropriate input stages connected to the input attenuator. The nominal VGAIN range for 30 dB/V is 0 V to 1 V, with the best gain linearity from about 0.1 V to 0.9 V, where the error is typically less than ±0.5 dB. For VGAIN voltages greater than 0.9 V and less than 0.1 V, the error increases. The value of VGAIN can exceed the supply voltage by 1 V without gain foldover. 06304-110 INPUT FULL-SCALE (V p-p) 0.400 0.050 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VGAIN (V) Figure 49. LNA/VGA Full-Scale Limitations Variable Gain Amplifier The differential X-AMP VGA provides precise input attenuation and interpolation. It has a low input-referred noise of 4 nV/√Hz and excellent gain linearity. A simplified block diagram is shown in Figure 50. There are two ways in which the GAIN+ and GAIN− pins can be interfaced. Using a single-ended method, a Kelvin type of connection to ground can be used as shown in Figure 51. For driving multiple devices, it is preferable to use a differential method, as shown in Figure 52. In either method, the GAIN+ and GAIN− pins should be dc-coupled and driven to accommodate a 1 V full-scale input. GAIN GAIN INTERPOLATOR + POSTAMP gm VIP Gain control response time is less than 750 ns to settle within 10% of the final value for a change from minimum to maximum gain. 3dB VIN AD9271 100Ω 0 TO 1V DC GAIN+ 50Ω GAIN– KELVIN CONNECTION 0.01µF Figure 50. Simplified VGA Schematic Figure 51. Single-Ended GAIN± Pins Configuration The input of the VGA is a 12-stage differential resistor ladder with 3.01 dB per tap. The resulting total gain range is 30 dB, which allows for range loss at the endpoints. The effective input resistance per side is 180 Ω nominally for a total differential resistance of 360 Ω. The ladder is driven by a fully differential input signal from the LNA. LNA outputs are dc-coupled to avoid external decoupling capacitors. The common-mode voltage of the attenuator and the VGA is controlled by an amplifier that uses the same midsupply voltage derived in the LNA, permitting dc coupling of the LNA to the VGA without introducing large offsets due to commonmode differences. However, any offset from the LNA will be amplified as the gain is increased, producing an exponentially increasing VGA output offset. The input stages of the X-AMP are distributed along the ladder, and a biasing interpolator, controlled by the gain interface, determines the input tap point. With overlapping bias currents, signals from successive taps merge to provide a smooth attenuation range from 0 dB to −30 dB. This circuit technique results in linear-in-dB gain law conformance and low distortion levels—only deviating ±0.5 dB or less from the ideal. The gain 499Ω AD9271 GAIN+ 100Ω 0.01µF GAIN– ±0.25DC AT 0.5V CM 499Ω 26kΩ ±0.5V DC AD8138 0.5V CM 50Ω 523Ω 100Ω 0.01µF AVDD 10kΩ ±0.25DC AT 0.5V CM 499Ω 06304-098 POSTAMP 06304-109 – 06304-078 0.01µF Figure 52. Differential GAIN± Pins Configuration VGA Noise In a typical application, a VGA compresses a wide dynamic range input signal to within the input span of an ADC. The input-referred noise of the LNA limits the minimum resolvable input signal, whereas the output-referred noise, which depends primarily on the VGA, limits the maximum instantaneous dynamic range that can be processed at any one particular gain control voltage. This latter limit is set in accordance with the total noise floor of the ADC. Output-referred noise as a function of VGAIN is shown in Figure 24 and Figure 25 for the short-circuit input conditions. The input Rev. B | Page 26 of 60 AD9271 noise voltage is simply equal to the output noise divided by the measured gain at each point in the control range. The output-referred noise is a flat 63 nV/√Hz over most of the gain range, because it is dominated by the fixed output-referred noise of the VGA. At the high end of the gain control range, the noise of the LNA and source prevail. The input-referred noise reaches its minimum value near the maximum gain control voltage, where the input-referred contribution of the VGA is miniscule. At lower gains, the input-referred noise and, therefore, the noise figure increases as the gain decreases. The instantaneous dynamic range of the system is not lost, however, because the input capacity increases as the input-referred noise increases. The contribution of the ADC noise floor has the same dependence. The important relationship is the magnitude of the VGA output noise floor relative to that of the ADC. Gain control noise is a concern in very low noise applications. Thermal noise in the gain control interface can modulate the channel gain. The resultant noise is proportional to the output signal level and is usually evident only when a large signal is present. The gain interface includes an on-chip noise filter, which significantly reduces this effect at frequencies above 5 MHz. Care should be taken to minimize noise impinging at the GAIN± input. An external RC filter can be used to remove VGAIN source noise. The filter bandwidth should be sufficient to accommodate the desired control bandwidth. Antialiasing Filter The filter that the signal reaches prior to the ADC is used to reject dc signals and to band limit the signal for antialiasing. Figure 53 shows the architecture of the filter. 1C* 56pF/112pF 2kΩ 7.5C* 2kΩ 2kΩ A third-order Butterworth low-pass filter is used to reduce noise bandwidth and provide antialiasing for the ADC. The filter uses on-chip tuning to trim the capacitors and in turn set the desired cutoff frequency and reduce variations. The default −3 dB cutoff is 1/3 the ADC sample clock rate. The cutoff can be scaled to 0.7, 0.8, 0.9, 1, 1.1, 1.2, or 1.3 times this frequency through the SPI. The cutoff can be set from 8 MHz to 18 MHz. Tuning is normally off to avoid changing the capacitor settings during critical times. The tuning circuit is enabled and disabled through the SPI. Initializing the tuning of the filter must be done after initial power-up and after reprogramming the filter cutoff scaling or ADC sample rate. Occasional retuning during an idle time is recommended to compensate for temperature drift. ADC The AD9271 architecture consists of a pipelined ADC divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined into a 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline except for the last consists of a low resolution flash ADC connected to a switched-capacitor DAC and interstage residue amplifier (for example, a multiplying digital-to-analog converter (MDAC)). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage consists of a flash ADC. 4kΩ 2kΩ The filter can be configured for dc coupling or to have a single pole for high-pass filtering at either 700 kHz or 350 kHz (programmed through the SPI). The high-pass pole, however, is not tuned and can vary by ±30%. 2kΩ The output staging block aligns the data, carries out error correction, and passes the data to the output buffers. The data is then serialized and aligned to the frame and output clock. 6.5C* 2kΩ 1C* 4kΩ *C = 0.5pF TO 3.1pF 06304-099 56pF/112pF Figure 53. Simplified Filter Schematic Rev. B | Page 27 of 60 AD9271 For optimum performance, the AD9271 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally and require no additional bias. Figure 54 shows the preferred method for clocking the AD9271. A low jitter clock source, such as the Valpey Fisher oscillator VFAC3-BHL-50MHz, is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the secondary transformer limit clock excursions into the AD9271 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9271, and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance. In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be driven directly from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 57). Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages of up to 3.3 V, making the selection of the drive logic voltage very flexible. 3.3V VFAC3 OUT EN ADC AD9271 CLK 0.1µF CLK– 0.1µF *50Ω RESISTOR IS OPTIONAL. CLK+ OUT EN CLK– CLK 50Ω * OPTIONAL 0.1µF 100Ω CMOS DRIVER VFAC3 06304-050 SCHOTTKY DIODES: HSM2812 AD951x FAMILY 0.1µF ADC AD9271 0.1µF CLK 0.1µF If a low jitter clock is available, another option is to ac-couple a differential PECL signal to the sample clock input pins as shown in Figure 55. The AD951x family of clock drivers offers excellent jitter performance. 3.3V AD951x FAMILY 0.1µF 0.1µF CLK+ CLK 0.1µF 100Ω PECL DRIVER 0.1µF 240Ω 06304-051 240Ω *50Ω ADC AD9271 CLK– CLK RESISTOR IS OPTIONAL. Figure 55. Differential PECL Sample Clock 3.3V 50Ω * AD951x FAMILY 0.1µF 0.1µF CLK+ CLK 0.1µF LVDS DRIVER 100Ω 0.1µF CLK *50Ω RESISTOR IS OPTIONAL. Figure 56. Differential LVDS Sample Clock ADC AD9271 CLK– 06304-052 VFAC3 OUT EN 0.1µF CLK+ ADC AD9271 CLK– Figure 54. Transformer-Coupled Differential Clock 50Ω * VFAC3 OUT EN 39kΩ 3.3V 50Ω 100Ω 0.1µF CLK+ Figure 57. Single-Ended 1.8 V CMOS Sample Clock MINI-CIRCUITS ADT1-1WT, 1:1Z 0.1µF XFMR VFAC3 OPTIONAL 0.1µF 100Ω 50Ω* *50Ω RESISTOR IS OPTIONAL. 06304-054 EN OUT CLK CMOS DRIVER 3.3V 0.1µF AD951x FAMILY 0.1µF 06304-053 CLOCK INPUT CONSIDERATIONS Figure 58. Single-Ended 3.3 V CMOS Sample Clock Clock Duty Cycle Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9271 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9271. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See the Memory Map section for more details on using this feature. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new rate. Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by SNR Degradation = 20 × log 10[1/2 × π × fA × tJ] Rev. B | Page 28 of 60 AD9271 190 In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter. IF undersampling applications are particularly sensitive to jitter (see Figure 59). 180 POWER/CHANNEL (mW) 170 The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9271. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources, such as the Valpey Fisher VFAC3 series. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock during the last step. 50MSPS SPEED GRADE 160 150 140 40MSPS SPEED GRADE 130 120 06304-031 25MSPS SPEED GRADE 110 100 0 10 20 30 40 50 SAMPLING FREQUENCY (MSPS) Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about how jitter performance relates to ADCs (visit www.analog.com). Figure 61. Power per Channel vs. fSAMPLE for fIN = 7.5 MHz By asserting the PDWN pin high, the AD9271 is placed into power-down mode. In this state, the device typically dissipates 2 mW. During power-down, the LVDS output drivers are placed into a high impedance state. The AD9271 returns to normal operating mode when the PDWN pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant. 130 RMS CLOCK JITTER REQUIREMENT 120 110 16 BITS 90 14 BITS SNR (dB) 100 80 12 BITS 70 10 BITS 60 50 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps 8 BITS 40 1 10 100 ANALOG INPUT FREQUENCY (MHz) 06304-038 30 1000 Figure 59. Ideal SNR vs. Input Frequency and Jitter Power Dissipation and Power-Down Mode As shown in Figure 61, the power dissipated by the AD9271 is proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers (Figure 60). 800 IAVDD , 50MSPS SPEED GRADE 700 IAVDD , 40MSPS SPEED GRADE 500 IAVDD , 25MSPS SPEED GRADE 400 300 200 100 06304-032 CURRENT (mA) 600 IDRVDD 0 0 10 20 30 40 50 SAMPLING FREQUENCY (MSPS) Figure 60. Supply Current vs. fSAMPLE for fIN = 7.5 MHz By asserting the STBY pin high, the AD9271 is placed into a standby mode. In this state, the device typically dissipates 65 mW. During standby, the entire part is powered down except the internal references. The LVDS output drivers are placed into a high impedance state. This mode is well suited for applications that require power savings because it allows the device to be powered down when not in use and then quickly powered up. The time to power the device back up is also greatly reduced. The AD9271 returns to normal operating mode when the STBY pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant. In power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, PLL, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering power-down mode and must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode: shorter cycles result in proportionally shorter wake-up times. To restore the device to full operation, approximately 1 ms is required when using the recommended 0.1 μF and 4.7 μF decoupling capacitors on the REFT and REFB pins and the 0.01 μF decoupling capacitors on the GAIN± pins. Most of this time is dependent on the gain decoupling; higher value decoupling capacitors on the GAIN± pins result in longer wake-up times. There are a number of other power-down options available when using the SPI port interface. The user can individually power down each channel or put the entire device into standby mode. This allows the user to keep the internal PLL powered up when fast wake-up times are required. The wake-up time is slightly dependent on gain. To achieve a 1 μs wake-up time when the device is in standby mode, 0.5 V must be applied to the GAIN± pins. See the Memory Map section for more details on using these features. Rev. B | Page 29 of 60 AD9271 The AD9271 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option similar to the IEEE 1596.3 standard by using the SDIO pin or via the SPI. This LVDS standard can further reduce the overall power dissipation of the device by approximately 36 mW. See the SDIO Pin section or Table 15 for more information. The LVDS driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. The AD9271 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 Ω termination resistor placed as close to the receiver as possible. No far-end receiver termination and poor differential trace routing may result in timing errors. It is recommended that the trace length be no longer than 24 inches and that the differential output traces be kept close together and at equal lengths. An example of the FCO, DCO, and data stream with proper trace length and position can be found in Figure 62. Additional SPI options allow the user to further increase the internal termination (and therefore increase the current) of all eight outputs in order to drive longer trace lengths (see Figure 65). Even though this produces sharper rise and fall times on the data edges, is less prone to bit errors, and improves frequency distribution (see Figure 65), the power dissipation of the DRVDD supply increases when this option is used. In cases that require increased driver strength to the DCO± and FCO± outputs because of load mismatch, Register 0x15 allows the user to double the drive strength. To do this, first set the appropriate bit in Register 0x05. Note that this feature cannot be used with Bit 4 and Bit 5 in Register 0x15 because these bits take precedence over this feature. See the Memory Map section for more details. 600 EYE: ALL BITS 400 EYE DIAGRAM VOLTAGE (V) Digital Outputs and Timing ULS: 2398/2398 200 100 0 –100 –200 –400 –600 –1.5ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns 5.0ns/DIV Figure 62. LVDS Output Timing Example in ANSI-644 Mode (Default) An example of the LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths of less than 24 inches on regular FR-4 material is shown in Figure 63. Figure 64 shows an example of the trace lengths exceeding 24 inches on regular FR-4 material. Notice that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position; therefore, the user must determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. 20 15 10 5 0 –200ps 06304-035 CH1 500mV/DIV Ω CH2 500mV/DIV Ω CH3 500mV/DIV Ω TIE JITTER HISTOGRAM (Hits) 06304-034 25 –100ps 0ps 100ps 200ps Figure 63. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of Less Than 24 Inches on Standard FR-4 Rev. B | Page 30 of 60 AD9271 400 600 EYE: ALL BITS 300 EYE: ALL BITS ULS: 2399/2399 ULS: 2396/2396 EYE DIAGRAM VOLTAGE (V) EYE DIAGRAM VOLTAGE (V) 400 200 100 0 –100 –200 200 0 –200 –400 –300 –1.0ns –0.5ns 0ns 0.5ns 1.0ns –600 1.5ns 25 20 20 TIE JITTER HISTOGRAM (Hits) 25 15 10 5 0 –200ps –100ps 0ps 100ps –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns 15 10 5 0 –200ps 200ps Figure 64. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of Greater Than 24 Inches on Standard FR-4 –1.5ns 06304-037 –1.5ns 06304-036 TIE JITTER HISTOGRAM (Hits) –400 –100ps 0ps 100ps 200ps Figure 65. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Termination On and Trace Lengths of Greater Than 24 Inches on Standard FR-4 Rev. B | Page 31 of 60 AD9271 The format of the output data is offset binary by default. An example of the output coding format can be found in Table 9. To change the output data format to twos complement, see the Memory Map section. Table 9. Digital Output Coding Code 4095 2048 2047 0 (VIN+) − (VIN−), Input Span = 2 V p-p (V) +1.00 0.00 −0.000488 −1.00 Digital Output Offset Binary (D11 ... D0) 1111 1111 1111 1000 0000 0000 0111 1111 1111 0000 0000 0000 Data from each ADC is serialized and provided on a separate channel. The data rate for each serial stream is equal to 12 bits times the sample clock rate, with a maximum of 600 Mbps (12 bits × 50 MSPS = 600 Mbps). The lowest typical conversion rate is 10 MSPS, but the PLL can be set up for encode rates as low as 5 MSPS via the SPI if lower sample rates are required for a specific application. See the Memory Map section for details on enabling this feature. Two output clocks are provided to assist in capturing data from the AD9271. DCO± is used to clock the output data and is equal to six times the sampling clock rate. Data is clocked out of the AD9271 and must be captured on the rising and falling edges of the DCO± that supports double data rate (DDR) capturing. The frame clock output (FCO±) is used to signal the start of a new output byte and is equal to the sampling clock rate. See the timing diagram shown in Figure 2 for more information. Table 10. Flexible Output Test Modes Output Test Mode Bit Sequence 0000 0001 Pattern Name Off (default) Midscale short 0010 +Full-scale short 0011 −Full-scale short 0100 Checkerboard 0101 0110 0111 PN sequence long 1 PN sequence short1 One-/zero-word toggle 1000 1001 User input 1-/0-bit toggle 1010 1× sync 1011 One bit high 1100 Mixed bit frequency 1 Digital Output Word 1 N/A 1000 0000 (8 bits) 10 0000 0000 (10 bits) 1000 0000 0000 (12 bits) 10 0000 0000 0000 (14 bits) 1111 1111 (8 bits) 11 1111 1111 (10 bits) 1111 1111 1111 (12 bits) 11 1111 1111 1111 (14 bits) 0000 0000 (8 bits) 00 0000 0000 (10 bits) 0000 0000 0000 (12 bits) 00 0000 0000 0000 (14 bits) 1010 1010 (8 bits) 10 1010 1010 (10 bits) 1010 1010 1010 (12 bits) 10 1010 1010 1010 (14 bits) N/A N/A 1111 1111 (8 bits) 11 1111 1111 (10 bits) 1111 1111 1111 (12 bits) 11 1111 1111 1111 (14 bits) Register 0x19 and Register 0x1A 1010 1010 (8 bits) 10 1010 1010 (10 bits) 1010 1010 1010 (12 bits) 10 1010 1010 1010 (14 bits) 0000 1111 (8 bits) 00 0001 1111 (10 bits) 0000 0011 1111 (12 bits) 00 0000 0111 1111 (14 bits) 1000 0000 (8 bits) 10 0000 0000 (10 bits) 1000 0000 0000 (12 bits) 10 0000 0000 0000 (14 bits) 1010 0011 (8 bits) 10 0110 0011 (10 bits) 1010 0011 0011 (12 bits) 10 1000 0110 0111 (14 bits) Digital Output Word 2 N/A Same Subject to Data Format Select N/A Yes Same Yes Same Yes 0101 0101 (8 bits) 01 0101 0101 (10 bits) 0101 0101 0101 (12 bits) 01 0101 0101 0101 (14 bits) N/A N/A 0000 0000 (8 bits) 00 0000 0000 (10 bits) 0000 0000 0000 (12 bits) 00 0000 0000 0000 (14 bits) Register 0x1B and Register 0x1C N/A No N/A No N/A No N/A No Yes Yes No No No All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver. Rev. B | Page 32 of 60 AD9271 When using the serial port interface (SPI), the DCO± phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO± timing, as shown in Figure 2, is 90° relative to the output data edge. An 8-, 10-, and 14-bit serial stream can also be initiated from the SPI. This allows the user to implement different serial streams to test the device’s compatibility with lower and higher resolution systems. When changing the resolution to an 8- or 10-bit serial stream, the data stream is shortened. When using the 14-bit option, the data stream stuffs two 0s at the end of the normal 14-bit serial data. When using the SPI, all of the data outputs can also be inverted from their nominal state. This is not to be confused with inverting the serial stream to an LSB-first mode. In default mode, as shown in Figure 2, the MSB is represented first in the data output serial stream. However, this can be inverted so that the LSB is represented first in the data output serial stream (see Figure 3). There are 12 digital output test pattern options available that can be initiated through the SPI. This feature is useful when validating receiver capture and timing. Refer to Table 10 for the output bit sequencing options available. Some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. It should be noted that some patterns may not adhere to the data format select option. In addition, customer user patterns can be assigned in the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver. SDIO Pin This pin is required to operate the SPI. It has an internal 30 kΩ pull-down resistor that pulls this pin low and is only 1.8 V tolerant. If applications require that this pin be driven from a 3.3 V logic level, insert a 1 kΩ resistor in series with this pin to limit the current. SCLK Pin This pin is required to operate the SPI port interface. It has an internal 30 kΩ pull-down resistor that pulls this pin low and is both 1.8 V and 3.3 V tolerant. CSB Pin This pin is required to operate the SPI port interface. It has an internal 70 kΩ pull-down resistor that pulls this pin low and is both 1.8 V and 3.3 V tolerant. RBIAS Pin To set the internal core bias current of the ADC, place a resistor that is nominally equal to 10.0 kΩ between the RBIAS pin and ground. Using a resistor of another value degrades the performance of the device. Therefore, it is imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance. Voltage Reference A stable and accurate 0.5 V voltage reference is built into the AD9271. This is gained up internally by a factor of 2, setting VREF to 1.0 V, which results in a full-scale differential input span of 2.0 V p-p for the ADC. VREF is set internally by default, but the VREF pin can be driven externally with a 1.0 V reference to achieve more accuracy. However, full-scale ranges below 2.0 V p-p are not supported by this device. The PN sequence short pattern produces a pseudorandom bit sequence that repeats itself every 29 − 1 bits, or 511 bits. A description of the PN sequence and how it is generated can be found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The only difference is that the starting value is a specific value instead of all 1s (see Table 11 for the initial values). When applying the decoupling capacitors to the VREF, REFT, and REFB pins, use ceramic low ESR capacitors. These capacitors should be close to reference pins and on the same layer of the PCB as the AD9271. The recommended capacitor values and configurations for the AD9271 reference pin can be found in Figure 66. The PN sequence long pattern produces a pseudorandom bit sequence that repeats itself every 223 − 1 bits, or 8,388,607 bits. A description of the PN sequence and how it is generated can be found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The only differences are that the starting value is a specific value instead of all 1s and the AD9271 inverts the bit stream with relation to the ITU standard (see Table 11 for the initial values). Table 12. Reference Settings Selected Mode External Reference Internal, 2 V p-p FSR Table 11. PN Sequence Sequence PN Sequence Short PN Sequence Long Initial Value 0x0df 0x29b80a First Three Output Samples (MSB First) 0xdf9, 0x353, 0x301 0x591, 0xfd7, 0xa3 Consult the Memory Map section for information on how to change these additional digital output timing features through the SPI. Rev. B | Page 33 of 60 SENSE Voltage AVDD Resulting VREF (V) N/A AGND to 0.2 V 1.0 Resulting Differential Span (V p-p) 2 × external reference 2.0 AD9271 Internal Reference Operation External Reference Operation A comparator within the AD9271 detects the potential at the SENSE pin and configures the reference. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 66), setting VREF to 1 V. The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve thermal drift characteristics. Figure 69 shows the typical drift characteristics of the internal reference in 1 V mode. The REFT and REFB pins establish their input span of the ADC core from the reference configuration. The analog input fullscale range of the ADC equals twice the voltage at the reference pin for either an internal or an external reference configuration. When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. The external reference is loaded with an equivalent 6 kΩ load. An internal reference buffer generates the positive and negative full-scale references, REFT and REFB, for the ADC core. Therefore, the external reference must be limited to a nominal voltage of 1.0 V. VIN+ VIN– 5 REFT ADC CORE 0.1µF 0.1µF + 0 4.7µF 0.1µF VREF 1µF VREF ERROR (%) REFB 0.1µF 0.5V SELECT LOGIC SENSE –5 –10 –15 –25 06304-017 06304-064 –20 0 0.5 Figure 66. Internal Reference Configuration 1.0 1.5 2.0 2.5 3.0 3.5 CURRENT LOAD (mA) Figure 68. VREF Accuracy vs. Load, AD9271-50 0.02 VIN+ 0 VIN– REFT + –0.04 4.7µF 0.1µF VREF 0.1µF* 0.5V SELECT LOGIC –0.06 –0.08 –0.10 –0.12 –0.14 –0.16 SENSE 06304-015 AVDD 0.1µF REFB EXTERNAL REFERENCE 1µF* 0.1µF VREF ERROR (%) ADC CORE –0.02 –0.18 –0.20 –40 –20 0 20 40 60 06304-065 TEMPERATURE (°C) *OPTIONAL. Figure 67. External Reference Operation Rev. B | Page 34 of 60 Figure 69. Typical VREF Drift, AD9271-50 80 AD9271 SERIAL PORT INTERFACE (SPI) The AD9271 serial port interface allows the user to configure the signal chain for specific functions or operations through a structured register space provided inside the chip. This offers the user added flexibility and customization depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, as documented in the Memory Map section. Detailed operational information can be found in the Analog Devices, Inc., AN-877 Application Note, Interfacing to High Speed ADCs via SPI. In addition to the operation modes, the SPI port can be configured to operate in different manners. For example, CSB can be tied low to enable 2-wire mode. When CSB is tied low, SCLK and SDIO are the only pins required for communication. Although the device is synchronized during power-up, caution must be exercised when using this mode to ensure that the serial port remains synchronized with the CSB line. When operating in 2-wire mode, it is recommended that a 1-, 2-, or 3-byte transfer be used exclusively. Without an active CSB line, streaming mode can be entered but not exited. Three pins define the serial port interface, or SPI: the SCLK, SDIO, and CSB pins. The SCLK (serial clock) is used to synchronize the read and write data presented to the device. The SDIO (serial data input/output) is a dual-purpose pin that allows data to be sent to and read from the device’s internal memory map registers. The CSB (chip select bar) is an active low control that enables or disables the read and write cycles (see Table 13). In addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. SDIO CSB Function Serial Clock. The serial shift clock input. SCLK is used to synchronize serial interface reads and writes. Serial Data Input/Output. A dual-purpose pin. The typical role for this pin is as an input or output, depending on the instruction sent and the relative position in the timing frame. Chip Select Bar (Active Low). This control gates the read and write cycles. The falling edge of the CSB in conjunction with the rising edge of the SCLK determines the start of the framing sequence. During an instruction phase, a 16-bit instruction is transmitted, followed by one or more data bytes, which is determined by Bit Field W0 and Bit Field W1. An example of the serial timing and its definitions can be found in Figure 71 and Table 14. In normal operation, CSB is used to signal to the device that SPI commands are to be received and processed. When CSB is brought low, the device processes SCLK and SDIO to process instructions. Normally, CSB remains low until the communication cycle is complete. However, if connected to a slow device, CSB can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. CSB can be stalled when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until the CSB is taken high to end the communication cycle. This allows complete memory transfers without having to provide additional instructtions. Regardless of the mode, if CSB is taken high in the middle of any byte transfer, the SPI state machine is reset and the device waits for a new instruction. HARDWARE INTERFACE The pins described in Table 13 constitute the physical interface between the user’s programming device and the serial port of the AD9271. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. In cases where multiple SDIO pins share a common connection, care should be taken to ensure that proper VOH levels are met. Figure 70 shows the number of SDIO pins that can be connected together, assuming the same load as the AD9271 and the resulting VOH level. Rev. B | Page 35 of 60 1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715 0 10 20 30 40 50 60 70 80 90 NUMBER OF SDIO PINS CONNECTED TOGETHER Figure 70. SDIO Pin Loading 100 06304-113 Pin SCLK VOH (V) Table 13. Serial Port Pins Data can be sent in MSB- or LSB-first mode. MSB-first mode is the default at power-up and can be changed by adjusting the configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. AD9271 This interface is flexible enough to be controlled by either serial PROMs or PIC mirocontrollers. This provides the user an alternative method, other than a full SPI controller, to program the device (see the AN-812 Application Note). tDS tS tHI tCLK tDH tH tLO CSB SCLK DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE 06304-068 SDIO DON’T CARE DON’T CARE Figure 71. Serial Timing Details Table 14. Serial Timing Definitions Parameter tDS tDH tCLK tS tH tHI tLO tEN_SDIO Minimum Timing (ns) 5 2 40 5 2 16 16 10 tDIS_SDIO 10 Description Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the clock Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 71) Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 71) Rev. B | Page 36 of 60 AD9271 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the device index and transfer register map (Address 0x04, Address 0x05, and Address 0xFF), and the ADC functions register map (Address 0x08 to Address 0x2D). The leftmost column of the memory map indicates the register address number; the default value is shown in the second rightmost column. The Bit 7 (MSB) column is the start of the default hexadecimal value given. For example, Address 0x09, the clock register, has a default value of 0x01, meaning that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. This setting is the default for the duty cycle stabilizer in the on condition. By writing 0 to Bit 0 of this address followed by writing 0x01 in Register 0xFF (transfer bit), the duty cycle stabilizer turns off. It is important to follow each writing sequence with a transfer bit to update the SPI registers. All registers, except Register 0x00, Register 0x02, Register 0x04, Register 0x05, and Register 0xFF, are buffered with a master-slave latch and require writing to the transfer bit. For more information on this and other functions, consult the AN877 Application Note, Interfacing to High Speed ADCs via SPI. RESERVED LOCATIONS Undefined memory locations should not be written to except when writing the default values suggested in this data sheet. Addresses that have values marked as 0 should be considered reserved and have 0 written into their registers during power-up. DEFAULT VALUES After a reset, critical registers are automatically loaded with default values. These values are indicated in Table 15, where an X refers to an undefined feature. LOGIC LEVELS An explanation of various registers follows: “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Similarly, “clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” Rev. B | Page 37 of 60 AD9271 Table 15. Memory Map Register 1 Addr. Bit 7 (Hex) Register Name (MSB) Chip Configuration Registers 00 chip_port_config 0 01 chip_id 02 chip_grade Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB first 1 = on 0 = off (default) Soft reset 1 = on 0 = off (default) 1 1 Soft reset 1 = on 0 = off (default) LSB first 1 = on 0 = off (default) Default Value Notes/ Comments 0 0x18 The nibbles should be mirrored so that LSB- or MSB-first mode is set correctly regardless of shift mode. Default is unique chip ID, different for each device. This is a readonly register. Child ID used to differentiate graded devices. Chip ID Bits [7:0] (AD9271 = 0x13), (default) X X Child ID [5:4] (identify device variants of Chip ID) 00 = 50 MSPS (default) 01 = 40 MSPS 10 = 25 MSPS Read only X X X X 0x00 Data Channel H 1 = on (default) 0 = off Data Channel D 1 = on (default) 0 = off X Data Channel G 1 = on (default) 0 = off Data Channel F 1 = on (default) 0 = off Data Channel E 1 = on (default) 0 = off 0x0F Bits are set to determine which on-chip device receives the next write command. Data Channel C 1 = on (default) 0 = off X Data Channel B 1 = on (default) 0 = off X Data Channel A 1 = on (default) 0 = off SW transfer 1 = on 0 = off (default) 0x0F Bits are set to determine which on-chip device receives the next write command. Synchronously transfers data from the master shift register to the slave. Internal power-down mode 000 = chip run (default) 001 = full power-down 010 = standby 011 = reset 100 = CW mode (TGC PDWN) X X Duty cycle stabilizer 1 = on (default) 0 = off Device Index and Transfer Registers 04 device_index_2 X X X X 05 device_index_1 X X FF device_update X X Clock Channel DCO± 1 = on 0 = off (default) X Clock Channel FCO± 1 = on 0 = off (default) X ADC Functions Registers 08 modes X X X X LNA bypass 1 = on 0 = off (default) 09 X X X X X clock Bit 0 (LSB) Rev. B | Page 38 of 60 0x00 0x00 Determines various generic modes of chip operation. 0x01 Turns the internal duty cycle stabilizer on and off. AD9271 Addr. (Hex) 0D Register Name test_io Bit 7 (MSB) Bit 6 User test mode 00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once 0F flex_channel_input 10 flex_offset 11 flex_gain Filter cutoff frequency control 0000 = 1.3 × 1/3 × fSAMPLE 0001 = 1.2 × 1/3 × fSAMPLE 0010 = 1.1 × 1/3 × fSAMPLE 0011 = 1.0 × 1/3 × fSAMPLE 0100 = 0.9 × 1/3 × fSAMPLE 0101 = 0.8 × 1/3 × fSAMPLE 0110 = 0.7 × 1/3 × fSAMPLE X X 6-bit LNA offset adjustment 011001 = 50 MSPS speed grade 011010 = 40 MSPS speed grade 011111 = 25 MSPS speed grade X X X X X 14 output_mode X 15 output_adjust X 0 = LVDS ANSI-644 (default) 1 = LVDS low power, (IEEE 1596.3 similar) X 16 output_phase X X Bit 5 Reset PN long gen 1 = on 0 = off (default) X Bit 4 Reset PN short gen 1 = on 0 = off (default) X Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Output test mode—see Table 10 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = −FS short 0100 = checkerboard output 0101 = PN sequence long 0110 = PN sequence short 0111 = one-/zero-word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency (format determined by output_mode) X X X X X 0x30 Antialiasing filter cutoff (global). 0x20 LNA force offset correction (local). LNA gain adjustment (global). 0x01 0x00 Configures the outputs and the format of the data. X 0x00 Determines LVDS or other output prop erties. Primarily functions to set the LVDS span and commonmode levels in place of an external resistor. On devices that utilize global clock divide, determines which phase of the divider output is used to supply the output clock. Internal latching is unaffected. Output invert 1 = on 0 = off (default) Output driver termination 00 = none (default) 01 = 200 Ω 10 = 100 Ω 11 = 100 Ω X X X 0011 = output clock phase adjust (0000 through 1010) (Default: 180° relative to data edge) 0000 = 0° relative to data edge 0001 = 60° relative to data edge 0010 = 120° relative to data edge 0011 = 180° relative to data edge 0100 = 240° relative to data edge 0101 = 300° relative to data edge 0110 = 360° relative to data edge 0111 = 420° relative to data edge 1000 = 480° relative to data edge 1001 = 540° relative to data edge 1010 = 600° relative to data edge 1011 to 1111 = 660° relative to data edge Rev. B | Page 39 of 60 Notes/ Comments When this register is set, the test data is placed on the output pins in place of normal data. (Local, expect for PN sequence.) LNA gain 00 = 5× 01 = 6× 10 = 8× 00 = offset binary (default) 01 = twos complement X X Default Value 0x00 DCO± and FCO± 2× drive strength 1 = on 0 = off (default) 0x03 AD9271 Addr. (Hex) 19 Register Name user_patt1_lsb Bit 7 (MSB) B7 Bit 6 B6 Bit 5 B5 Bit 4 B4 Bit 3 B3 Bit 2 B2 Bit 1 B1 Bit 0 (LSB) B0 Default Value 0x00 1A user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 1B user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 1C user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 21 serial_control LSB first 1 = on 0 = off (default) X X X 000 = 12 bits (default, normal bit stream) 001 = 8 bits 010 = 10 bits 011 = 12 bits 100 = 14 bits 22 serial_ch_stat X X X X <10 MSPS, low encode rate mode 1 = on 0 = off (default) X X 2B flex_filter X Enable automatic low-pass tuning 1 = on 0 = off (default) X X X X 2C analog_input X X X X X X 2D cross_point_switch X X X Crosspoint switch enable 0 0000 = CWD0± (differential) 0 0001 = CWD1± (differential) 0 0010 = CWD2± (differential) 0 0011 = CWD3± (differential) 0 0100 = CWD4± (differential) 0 0101 = CWD5± (differential) 0 0111 = power down CW channel 1 0000 = CWD0+ (single ended) 1 0001 = CWD1+ (single ended) 1 0010 = CWD2+ (single ended) 1 0011 = CWD3+ (single ended) 1 0100 = CWD4+ (single ended) 1 0101 = CWD5+ (single ended) 1 0111 = power down CW channel 1 1000 = CWD0− (single ended) 1 1001 = CWD1− (single ended) 1 1010 = CWD2− (single ended) 1 1011 = CWD3− (single ended) 1 1100 = CWD4− (single ended) 1 1101 = CWD5− (single ended) 1 1111 = power down CW channel 1 X = an undefined feature Rev. B | Page 40 of 60 Channel Channel poweroutput down reset 1 = on 1 = on 0 = off 0 = off (default) (default) High-pass filter cutoff 00 = dc (default) 01 = 700 kHz 10 = 350 kHz X LOSW-x 1 = on 0 = off (default) 0x00 Notes/ Comments User-defined pattern, 1 LSB (global). User-defined pattern, 1 MSB (global). User-defined pattern, 2 LSB (global). User-defined pattern, 2 MSB (global). Serial stream control. Default causes MSB first and the native bit stream (global). 0x00 Used to power down individ ual sections of a converter (local). 0x00 Filter cutoff (global). 0x00 LNA active termination/ input impedance (global). Crosspoint switch enable (local). 0x07 AD9271 APPLICATIONS INFORMATION DESIGN GUIDELINES Exposed Paddle Thermal Heat Slug Recommendations Before starting design and layout of the AD9271 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. It is required that the exposed paddle on the underside of the device be connected to the analog ground (AGND) to achieve the best electrical and thermal performance of the AD9271. An exposed continuous copper plane on the PCB should mate to the AD9271 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be filled or plugged with nonconductive epoxy. Power and Ground Recommendations When connecting power to the AD9271, it is recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). The AD9271 also requires a 3.3 V supply (CWVDD) for the crosspoint section. If only one 1.8 V supply is available, it should be routed to the AVDD first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the DRVDD. The user should employ several decoupling capacitors on all supplies to cover both high and low frequencies. These capacitors should be located close to the point of entry at the PC board level and close to the parts with minimal trace lengths. To maximize the coverage and adhesion between the device and PCB, partition the continuous copper pad by overlaying a silkscreen or solder mask to divide it into several uniform sections. This ensures several tie points between the two during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the AD9271 and PCB. See Figure 72 for a PCB layout example. For more detailed information on packaging and for more PCB layout examples, see the AN-772 Application Note. SILKSCREEN PARTITION PIN 1 INDICATOR 06304-069 A single PC board ground plane should be sufficient when using the AD9271. With proper decoupling and smart partitioning of the PC board’s analog, digital, and clock sections, optimum performance can be easily achieved. Figure 72. Typical PCB Layout Rev. B | Page 41 of 60 AD9271 EVALUATION BOARD The AD9271 evaluation board provides all the support circuitry required to operate the AD9271 in its various modes and configurations. The LNA is driven differentially through a transformer. Figure 73 shows the typical bench characterization setup used to evaluate the ac performance of the AD9271. It is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the signal chain. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance. SPI and alternate clock options, a separate 3.3 V analog supply is needed in addition to the other supplies. The 3.3 V supply, or AVDD_3.3 V, should have a 1 A current capability. To bias the crosspoint switch circuitry or CW section, separate +5 V and −5 V supplies are required at P511. These should each have 1 A current capability. This section cannot be biased from a 6 V, 2 A wall supply. Separate supplies are required at P511. INPUT SIGNALS When connecting the clock and analog source, use clean signal generators with low phase noise, such as Rohde & Schwarz SMA or HP8644B signal generators or the equivalent. Use a 1 m, shielded, RG-58, 50 Ω coaxial cable for making connections to the evaluation board. Enter the desired frequency and amplitude from the specifications tables. The evaluation board is set up to be clocked from the crystal oscillator, OSC401. If a different or external clock source is desired, follow the instructions for CLOCK outlined in the Default Operation and Jumper Selection Settings section. Typically, most Analog Devices evaluation boards can accept ~2.8 V p-p or 13 dBm sine wave input for the clock. When connecting the analog input source, it is recommended to use a multipole, narrow-band, band-pass filter with 50 Ω terminations. Analog Devices uses TTE and K&L Microwave, Inc., band-pass filters. The filter should be connected directly to the evaluation board. See the Quick Start Procedure section to get started and Figure 75 to Figure 86 for the complete schematics and layout diagrams that demonstrate the routing and grounding techniques that should be applied at the system level. POWER SUPPLIES This evaluation board comes with a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Connect the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter jack that connects to the PCB at P701. Once on the PC board, the 6 V supply is fused and conditioned before connecting to three low dropout linear regulators that supply the proper bias to each of the various sections on the board. When operating the evaluation board in a nondefault condition, L702 to L704 can be removed to disconnect the switching power supply. This enables the user to bias each section of the board individually. Use P501 to connect a different supply for each section. At least one 1.8 V supply is needed with a 1 A current capability for AVDD_DUT and DRVDD_DUT; however, it is recommended that separate supplies be used for both analog and digital domains. To operate the evaluation board using the OUTPUT SIGNALS The default setup uses the FIFO5 high speed, dual-channel FIFO data capture board (HSC-ADC-EVALCZ). Two of the eight channels can then be evaluated at the same time. For more information on channel settings on these boards and their optional settings, visit www.analog.com/FIFO. WALL OUTLET 100V TO 240V AC 47Hz TO 63Hz AD9271 PS – CH A TO CH H 12-BIT SERIAL LVDS HSC-ADC-EVALCZ FIFO DATA CAPTURE BOARD SPI EVALUATION BOARD Figure 73. Evaluation Board Connection Rev. B | Page 42 of 60 PC RUNNING ADC ANALYZER OR VISUAL ANALOG USER SOFTWARE FPGA CW OUTPUT VFAC3 OSCILLATOR CLK + VREG + GND GND – SPI USB CONNECTOR (DATA/SPI) 06304-070 ROHDE & SCHWARZ, FS5A20 SPECTRUM ANALYZER BAND-PASS FILTER 3.3V + AVDD_3.3V ANALOG INPUT ROHDE & SCHWARZ, SMA, 2V p-p SIGNAL SYNTHESIZER 1.8V – DRVDD_DUT 1.8V + GND – GND SWITCHING POWER SUPPLY AVDD_DUT 6V DC 2A MAX AD9271 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS • PDWN: To enable the power-down feature, short P303 to the on position (AVDD) on the PDWN pin. The following is a list of the default and optional settings or modes allowed on the AD9271 Rev. B evaluation board. • STBY: To enable the standby feature, short P302 to the on position (AVDD) on the STBY pin. • Power: Connect the switching power supply that is supplied in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P701. • • AIN: The evaluation board is set up for a transformercoupled analog input with an optimum 50 Ω impedance match of 18 MHz of bandwidth. For a different bandwidth response, use the antialiasing filter settings. GAIN+, GAIN−: To change the VGA attenuation, drive the GAIN+ pin from 0 V to 1 V on J301. This changes the VGA gain from 0 dB to 30 dB. This feature can also be driven from the R335 and R336 on-board resistive divider by installing a 0 Ω resistor in R337. • Non-SPI Mode: For users who wish to operate the DUT without using the SPI, remove the jumpers on J501. This disconnects the CSB, SCLK, and SDIO pins from the control bus, allowing the DUT to operate in its simplest mode. Each of these pins has internal termination and will float to its respective level. Note that the device will only work in its default condition. • CWD+, CWD−: To view the CWD2+/CWD2− and CWD3+/ CWD3− outputs, jumper together the appropriate outputs on P403. All outputs are summed together on IOP and ION buses, fed to a 1:4 impedance ratio transformer, and buffered so that the user can view the output on a spectrum analyzer. This can be configured to be viewed in singleended mode (default) or in differential mode. To set the voltage for the appropriate number of channels to be summed, change the value of R447 and R448 on the primary transformer (T402). • VREF: VREF is set to 1.0 V by tying the SENSE pin to ground, R317. This causes the ADC to operate in 2.0 V p-p full-scale range. A separate external reference option using the ADR510 or ADR520 is also included on the evaluation board. Populate R311 and R315 with 0 Ω resistors and remove C307. Proper use of the VREF options is noted in the Voltage Reference section. Note that ADC full-scale ranges less than 2.0 V p-p are not supported by this device. • RBIAS: RBIAS has a default setting of 10 kΩ (R301) to ground and is used to set the ADC core bias current. However, note that using other than a 10 kΩ resistor for RBIAS may degrade the performance of the device, depending on the resistor chosen. • Clock: The default clock input circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T401) that adds a very low amount of jitter to the clock path. The clock input is 50 Ω terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs. Upon shipment, the CWD0+/CWD0−, CWD1+/CWD1−, CWD4+/CWD4−, and CWD5+/CWD5− outputs are properly biased and ready to use with the AD8339 quad I/Q demodulator and phase shifter. The AD9271 evaluation board simply snaps into place on the AD8339 evaluation board (AD8339-EVALZ). Remove the jumpers connected to P3A and P4A on the AD8339 evaluation board, and snap the standoffs labeled MH502, MH504, and MH505 that are provided with the AD9271 into the AD8339 evaluation board standoff holes in the center of the board. The standoffs automatically lock into place and create a direct connection between the AD9271 CWDx± outputs and the AD8339 inputs. The evaluation board is already set up to be clocked from the crystal oscillator, OSC401. This oscillator is a low phase noise oscillator from Valpey Fisher (VFAC3-BHL-50MHz). If a different clock source is desired, remove R403, set Jumper J401 to disable the oscillator from running, and connect the external clock source to the SMA connector, P401. A differential LVPECL clock driver can also be used to clock the ADC input using the AD9515 (U401). Populate R406 and R407 with 0 Ω resistors and remove R415 and R416 to disconnect the default clock path inputs. In addition, populate C405 and C406 with a 0.1 μF capacitor and remove C409 and C410 to disconnect the default clock path outputs. The AD9515 has many pin-strappable options that are set to a default mode of operation. Consult the AD9515 data sheet for more information about these and other options. • Rev. B | Page 43 of 60 DOUTx+, DOUTx−: If an alternative data capture method to the setup described in Figure 80 is used, optional receiver terminations, R601 to R610, can be installed next to the high speed backplane connector. AD9271 QUICK START PROCEDURE 4. The following is a list of the default and optional settings when using the AD9271 either on the evaluation board or at the system level design. In SPI Controller, select Controller Dialog from the Config menu. In the PROGRAM CONTROL box, ensure that Enable Auto Channel Update is selected and click OK. 5. In the Global tab of SPI Controller, find the DEVICE INDEX(4/5) box. In the ADC column, click S so that the adjustment in the next step applies to all channels. 6. In the ADC A tab of SPI Controller, find the OFFSET(10) box and use the drop-down menu labeled Offset Adj to select the correct LNA offset correction: 25 decimal for the 50 MSPS speed grade, 26 decimal for the 40 MSPS speed grade, or 31 decimal for the 25 MSPS speed grade. 7. Click FFT ( If an evaluation board is not being used, follow only the SPI controller steps. When using the AD9271 evaluation board, 1. Open ADC Analyzer on a PC, click Configuration, and select the appropriate product configuration file. If the correct product configuration file is not available, choose a similar product configuration file or click Cancel and create a new one. See the ADC Analyzer User Manual located at www.analog.com/FIFO. ) in Visual Analog. 0 From the Config menu, choose Channel Select. To evaluate Channel A on the ADC evaluation board, ensure that only the Channel B checkbox in ADC Analyzer is selected. –30 Channel E through Channel H correspond to Channel A in ADC Analyzer. Click SPI in ADC Analyzer to open the SPI controller software. If prompted for a configuration file, select the appropriate one. If not, look at the title bar of the window to see which configuration is loaded. If necessary, choose Cfg Open from the File menu and select the appropriate one. Note that the CHIP ID(1) field may be filled in regardless of whether the correct SPI controller configuration file is loaded. When using the AD9271 evaluation board or system level design, 1. Click New DUT ( 2. In the Global tab of SPI Controller, find the CHIP GRADE(2) box and use the drop-down menu to select the correct speed grade. 3. In the ADCGlobal 0 tab of SPI Controller, find the HIGHPASS(2B) box and select the Manual Tune box to calibrate the antialiasing filter. LNA = 6× VGAIN = 1V FILTER TUNED HPF = 700kHz –20 Channel A through Channel D correspond to Channel B in ADC Analyzer. –40 –50 –60 –70 –80 –90 –100 –110 06304-119 3. fIN = 3.5MHz @ –1dBFS –10 AMPLITUDE (dBFS) 2. –120 –130 0 5 10 15 20 25 FREQUENCY (MHz) Figure 74. Typical FFT, AD9271-50 8. Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the Fund: reading in the left panel of the ADC Analyzer FFT window.) If the GAIN± pins voltage is low (near 0 V), it may not be possible to reach full scale without distortion. Use a higher gain setting or a lower input level to avoid distortion. 9. Right-click the FFT plot and select Comments. Use this box to record information such as the serial number of the board, the channel, the input and clock frequencies, the GAIN± pins voltage, and the date. Press the PRINT SCREEN key and save the FFT screenshot if desired. ) in the SPI Controller software. Rev. B | Page 44 of 60 Rev. B | Page 45 of 60 J10 2 R10 4 0-DN P 0 R11 1 Figure 75. Evaluation Board Schematic, DUT Analog Input Circuits C11 8 0.1UF-DN P R11 2 0 R13 8 0 GND B 3 5 1 3 5 1 CT A CT B C11 7 0.1UF-DN P R13 7 0 R14 9 0 GND A R10 1 49.9-DN P 0 R10 2 R11 0 49.9-DN P AIN CHB R15 0 0-DN P J10 1 AIN CHA 6 R14 4 10K-DN P R14 3 10K-DN P AVD D T10 2 2 4 ADT1-1WT + R14 2 10K-DN P R14 1 10K-DN P AVD D T10 1 6 2 4 ADT1-1WT + 0 R11 4 CT B R15 1 0 0-DN P R15 5 0 CTA R13 0 0 0-DN P R15 4 R10 5 0 R15 9 49.9 0 R16 2 R15 8 49.9 R13 2 0.1U F C10 5 0.1U F C12 2 0.1U F C10 1 0.1U F C12 1 R11 8 0-DN P C10 8 C10 6 R11 5 0 0.1UF-DN P 200 R11 7 22PF 0.1U F C10 7 1K-DN P R11 6 R10 9 0-DN P C10 4 C10 2 R10 6 0 0.1UF-DN P 200 R10 8 22PF 0.1U F C10 3 R10 7 LGB LIB LOSW B LO- B LGA LIA LOSW A LO- A R12 2 0-DN P J10 4 0 R12 9 C12 0 0.1UF-DN P R13 1 0 R14 0 0 GND D 3 5 1 3 5 1 CT C CT D C11 9 0.1UF-DN P R12 1 0 R13 9 0 GND C R11 9 49.9-DN P 0 R10 3 R12 8 49.9-DN P AIN CHD R11 3 0-DN P J10 3 AIN CHC 6 R14 8 10K-DN P R14 7 10K-DN P AVD D T10 4 2 4 ADT1-1WT + R14 6 10K-DN P R14 5 10K-DN P AVD D T10 3 6 2 4 ADT1-1WT + 0 R12 3 CT D R15 3 0 0-DN P R15 7 0 CT C R15 2 0 0-DN P R15 6 R12 0 0 R16 1 49.9 0 R16 4 R16 0 49.9 R16 3 0.1U F C11 3 0.1U F C12 4 0.1U F C10 9 0.1U F C12 3 R13 6 0-DN P C11 6 C11 4 R13 3 0 0.1UF-DN P 200 R13 5 22PF 0.1U F C11 5 1K-DN P R13 4 R12 7 0-DN P C11 2 C11 0 R12 4 0 0.1UF-DN P 200 R12 6 22PF 0.1U F C11 1 R12 5 1K-DN P LGD LID LOSW D LO- D LG C LIC LOSW C LO- C 06304-086 1K-DN P AD9271 SCHEMATICS AND ARTWORK Rev. B | Page 46 of 60 R22 2 0-DN P J20 2 0 R21 1 Figure 76. Evaluation Board Schematic, DUT Analog Input Circuits (Continued) C21 8 0.1UF-DN P R2 3 0 0 R2 3 8 0 GND F 3 3 1 1 CT E 5 CT F 5 C21 7 0.1UF-DN P R22 1 0 R20 3 0 GND E R20 1 49.9-DN P 0 R20 2 R2 1 0 49 .9-DN P AIN CHF R21 2 0-DN P J20 1 AIN CHE 4 2 6 4 2 6 R24 4 10K-DN P R20 4 10K-DN P AVD D ADT1-1WT + T20 2 R24 3 10K-DN P R24 2 10K-DN P AVD D ADT1-1WT + T20 1 0 R25 9 49.9 0 0 R26 2 R25 8 49.9 R23 2 R21 4 CT F R25 0 0 0-DN P R25 5 0 CT E R24 9 0 0-DN P R25 4 R20 5 0.1U F C20 5 0.1U F C22 2 0.1UF C20 1 0.1UF C22 1 C20 3 R21 8 0-DN P C20 8 R21 5 0 0.1UF-DN P C20 6 200 R21 7 22PF 0.1UF C20 7 1K-DN P R21 6 R20 9 0-DN P C20 4 C20 2 R20 6 0 0.1UF-DN P 200 R20 8 22PF 0.1U F R20 7 LGF LIF LOSW F LO- F LG E LIE LOSW E LO- E R24 1 0-DN P J20 4 0 R22 9 C22 0 0.1UF-DN P R25 3 0 R24 0 0 GND H 3 3 1 1 CT G5 CTH5 C21 9 0.1UF-DN P R23 7 0 R23 9 0 GND G R21 9 49.9-DN P 0 R21 3 R22 8 49.9-DN P AIN CHH R23 1 0-DN P J20 3 AIN CHG 4 2 6 4 2 6 R24 8 10K-DN P R24 7 10K-DN P AVD D ADT1-1WT + T20 4 R24 6 10K-DN P R24 5 10K-DN P AVD D ADT1-1WT + T20 3 0 R22 3 CT H R25 2 0 0-DN P R25 7 0 CT G R25 1 0 0-DN P R25 6 R22 0 0 R26 1 49.9 0 R26 4 R26 0 49.9 R26 3 0.1U F C21 3 0.1U F C22 4 0.1U F C20 9 0.1U F C22 3 C21 1 R23 3 0 C21 4 22PF 0.1U F C21 5 R22 4 0 C21 0 22PF 0.1U F R22 5 R23 6 0-DN P C21 6 0.1UF-DN P 200 R23 5 1K-DN P R23 4 R22 7 0-DN P C21 2 0.1UF-DN P 200 R22 6 1K-DN P LGH LIH LOSW H LO- H LG G LIG LOSW G LO- G 06304-087 1K-DN P AD9271 AVDD CLK CLK AVDD LGH LIH LOSWH LO-H AVDD LGG LIG LOSWG LO-G AVDD LGF LIF LOSWF LO-F AVDD LGE LIE 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AVDD CLK+ CLK- AVDD AVDD LGH LIH LOSWH LO-H AVDD AVDD LGG LIG LOSWG LO-G AVDD AVDD LGF LIF LOSWF LO-F AVDD AVDD LGE LIE U301 101 PAD R301 10K VSENSE_DUT CWD4+ CWD5- C302 CWD5+ C304 0.1UF 100 4.7UF 97 CWD5- C303 0.1UF 26 AVDD_3.3V VREF_DUT 0.1UF C309 0.1UF C308 AD9271BSVZ-50 DOUTC+ LOSWE LOSWE DRVDD CWD2+ DOUTB- LO-E 99 LO-E DOUTH27 DOUTB+ 98 CWD5+ DOUTH+ 28 DOUTA- 96 C301 CWD495 CWD4DOUTF31 DOUTF+ 32 CWD4+ CWD393 CWD3DOUTE33 DOUTG+ AVDD 92 RAVDD DOUTE+ 34 DCO35 DCO+ 36 FCO37 FCO+ 38 DOUTG29 87 RBIAS DOUTD39 DOUTD+ 40 DOUTC41 Figure 77. Evaluation Board Schematic, DUT, VREF, and Gain Circuitry 42 CHA AVDD 1K R326 2 1K R325 P303 0 R304 GGND 1 DRVDD_DUT 2 AVDD 1 P302 R302 49.9 100 R303 SCLK SDIO CSB AVDD AVDD LGA LIA LOSWA LO-A AVDD AVDD LGB LIB LOSWB LO-B AVDD AVDD LGC LIC LOSWC LO-C AVDD AVDD LGD LID J301 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 0 R331 R319 IN AVDD LGA LIA 1K LOSWA LO-A AVDD LGB LIB LOSWB LO-B AVDD LGC LIC LOSWC LO-C AVDD LGD LID 0-DNP R337 R336 10K R335 8.06K SCLK_DU T SDIO_DU T CSB_DU T 10K R338 AVDD CW 1UF C307 0.1UF C306 CW R310 10K 0.1UF C305 2 AVDD VSENSE_DU T VREF_DU T 1K R309 Reference Circuitry R317 43 R316 30 CWD282 CWD2- 0.1UF CWD3+ 94 CWD3+ 91 REFT 90 REFB 89 VREF 88 SENSE 86 GAIN+ 85 GAIN- 84 CWVDD 83 CWD2+ CWD1+ 81 CWD1+ CWD180 CWD1DOUTA+ CWD078 CWD0STDBY R308 470K VR312 DNP 44 Rev. B | Page 47 of 60 R315 45 0-DNP 46 LO-D 77 LO-D CWD0+ 79 CWD0+ DRVDD V+ R311 47 LOSWD 76 LOSWD AVDD ADR510ART Z PDWN TRIM/NC 1 48 U302 50 3 49 AVDD AVDD 06304-088 GAIN DRIVE INPUT AD9271 Vref Selec t 0-DNP Vref = External 0-DNP Vref=0.5V(1+R313/R312) R313 DNP 0 Vref=1V Remove C307 when using external Vref CHA CHB CHB CHC CHC CHD CHD FCO FCO DCO DCO CHE CHE CHF CHF CHG CHG CHH CHH DRVDD_DUT 5 7 CWD3- ION OPT_CLK OPT_CLK Figure 78. Evaluation Board Schematic, Clock and CW Doppler Circuitry 0 C411 0.1UF 0 R417 0 R418 R413 10K R410 10K AVDD_3.3V R411 49.9-DNP R409 DNP R466 0 CWD2 R450 0 0 R452 +IN 1 + AD822ARTZ + +IN2 5 -IN2 6 OUT2 7 V+ 8 750 R454 +5V R464 0 R461 0-DNP C422 0.1UF R463 0 CWD2 AOUT 5 3 2 1 SYNCB CLKB CLK U401 R414 4.12K AVDD_3.3V 22 23 SIGNAL=AVDD_3.3V;4,17,20,21,24,26,29,3 0 19 OUT1 SIGNAL=DNC;27,28 18 OUT1B OUT0B AD9515BCPZ GND_PAD OUT0 CR401 HSMS-2812 CLK CLIPSINEOUT (DEFAULT) CLK C412 0.1UF AVDD_3.3V 240 R420 OPTION AL CLOCK DRIVE CIRCUI T C421 0.1UF 4 V- 3 2 -IN1 S10 4 2 6 R412 DNP R408 DNP R449 0-DNP CWD1 ADT1-1W+ T401 1 R465 0-DNP ADTT4-1T+ 2 -5V 750 S9 1 5 3 0-DNP R407 0-DNP R406 6 5 0 R451 U402 C420 0.1UF S5 R416 0 R415 OPT_CLK OPT_CLK R448 127 R447 127 3 1 OUT1 C419 0.1UF S4 R405 0 R404 49.9 R403 0 R402 10K ENABLE J401 DISABLE R401 10K 0 R446 E402 T402 R453 R462 0 R458 49.9 S3 P402 GN D 2 1 2 CWD2- CWD2+ 4 R460 0 R455 49.9 J403 S0 ENC P401 ENC OU T TRI STAT E OSC401 VC C C401 0.1UF AVDD_3.3V 8 6 4 2 VFAC3H-L-50MHZ 3 4 AVDD_3.3V 3 IOP CWD3+ 1 CWD1 E401 P403 1 C402 C403 S10 CW DOPPLER CIRCUITR Y 0.1UF 0.1UF VREF 6 S9 8 R459 0-DNP 9 S8 32 RSET 1 VS 31 GND S6 11 S7 10 S7 C410 S6 0.1UF 7 33 AOUT S2 C409 S1 S1 0.1UF S5 12 S4 13 S3 14 S2 15 Rev. B | Page 48 of 60 S0 3 16 AVDD_3.3V 25 C413 AVDD_2.5V 100 C407 C408 0.1UF C415 0.1UF 0.1UF-DNP C406 0.1UF-DNP C414 L406 CLK 0.1UF C416 L408 C417 AVDD_3.3V AVDD_3.3V AVDD_3.3V AVDD_3.3V AVDD_3.3V AVDD_3.3V CWD5- CWD5+ CWD4- CWD4+ CWD1- CWD1+ CWD0- CWD0+ C418 0.1UF 560UH 560UH L402 0.1UF LVPECLOUTPUT CLK AVDD_2.5V L407 560UH R470 750 750 R467 560UH L401 AVDD_2.5V LVDSOUTPUT 560UH 560UH L404 0.1UF-DNP 0.1UF-DNP R422 C405 AVDD_2.5V L405 560UH R469 750 750 R468 560UH L403 240 R421 0.1UF R423 100 2 1 1 2 2 1 1 2 2 1 1 2 2 1 1 2 J402 S5 S4 S3 S2 S1 S0 2 4 6 8 2 4 6 8 0-DNP R434 0-DNP R432 0-DNP R430 0-DNP R428 0-DNP R426 0-DNP R424 1 P406 3 5 7 1 P405 3 5 7 0 R435 0 R433 0 R431 0 R429 0 R427 0 R425 AVDD_3.3V AVDD_3.3V AVDD_3.3V AVDD_3.3V AVDD_3.3V S10 S9 S8 S7 S6 0-DNP R444 0-DNP R442 0-DNP R440 0-DNP R438 0 R436 0 R445 0 R443 0 R441 0 R439 0-DNP R437 AD9515Pin-strapsettings TO AD8339 EVAL BOARD OPTION AL CONNECTIO N AD9271 S8 2 1 3 1 06304-089 Figure 79. Evaluation Board Schematic, Power Supply and SPI Interface Circuitry 1UF C716 PWR_OUT 1UF C714 PWR_OUT 6 J501 4 2 3 3 INPUT U704 INPUT U707 10K R714 8 GND Y2 4 5 VCC Y1 6 U703 3 A2 2 OUTPUT 1 OUTPUT 4 ADP3339AKCZ-1.8-R L 2 OUTPUT 1 OUTPUT 4 4 4 Y2 4 5 VCC 2 GND Y1 6 1 A1 NC7WZ16P6X_N L U702 3 A2 ADP3339AKCZ-1.8-R L 10K R715 10K R711 2 1 A1 NC7WZ07P6X_N L C703 10UH L705 PWR_IN 1UF DUT_DRVD D C719 2 DUT_AVDD U705 3 INPUT 1UF C722 8 3 GND OUT OUT OUT 1 2 3 100P F C721 2 2 OUTPUT 1 OUTPUT 4 ADP3339AKCZ-3.3-R L 6 SD IN IN 4 5 NR ADP333 5 U706 ADP3335ACPZ-2. 5 7 3 2 1 P511 2.5MM JACK 7.5VPOWER 1 Z5.531.3325. 0 CW +/- 5V POWER INPUT AVDD_3.3 V 1UF 10UH L706 2 CSB_DUT AVDD C717 1 1UF C715 1 0.1UF AVDD 1K R710 P70 1 6V, 2A ma x 4 1UF 2 10UH 1UF C720 1 AVDD_2.5 V 10UH L502 10UH 2 10UF L707 NANOSMDC110 F70 1 C704 L501 C723 1 1 Power Supply Inpu t L704 10UH L702 10UH L703 2 2 2 C733 10UF C709 2 3.3V_AVD D 0.1UF C751 0.1UF C740 0.1UF AVDD_3.3 V C745 0.1UF 0.1UF C744 AVDD 0.1UF C730 0.1UF C742 DRVDD_DUT 0.1UF C746 0.1UF C732 10UH 0.1UF C743 0.1UF C747 0.1UF 0.1UF C748 0.1UF 0.1UF C712 0.1UF C708 0.1UF D703 0.1UF C735 DRVDD_DUT AVDD 2 S2A-TP 1 AVDD_3.3 V R716 240 PWR_IN C710 CR702 GREEN C734 10UF C711 10UF 1 1 1 0.1UF C731 DUT_DRVD D DUT_AVDD 3.3V_AVD D 2 S2A-TP 10UF AVDD Z5.531.3625. 0 6 5 4 3 2 1 P501 D702 1 C707 -5V CG 6 CG 5 CG 4 CB 2 OPTIONALPOWERINPUT BNX016-0 1 C504 0.1UF 10UF +5V 3 PSG 1 BIAS L701 C503 C502 2A D701 C501 F 2 1 AVDD_3.3 V SCLK_DUT 1K R713 0.1UF C702 R712 1K SDIO_DUT SPI BUS DISCONNECT OPTION 1 GND 1 GND D704 2 D705 2 PWR_OUT BOARD MOUNTING HOLE S S2A-TP 1 +1.8v +1.8v +3.3v GND Test Points MH505 MH504 MH503 MH502 MH501 PopulateMH503-505for dockingwith AD8339Eval Board PopulateMH501-504for standardboardevaluation S2A-TP 1 E707 1 GND 1 E705 1 Rev. B | Page 49 of 60 1 1 E706 1 3 E701 1 CSB1_CHA 5 E702 1 SCLK_CH A 7 E703 E708 1 SDI_CHA E704 1 SDO_CHA 06304-090 SPI CIRCUITRY FROM FIFO AD9271 AD9271 Digital Outputs FIFO5: DATA BUS 1 CONNECTOR P60 1 FIFO5: HS - SERIAL/SPI/AUX CONNECTOR 6469169-1 P60 2 GNDCD1 0 GNDCD1 0 60 60 C1 0 D1 0 40 50 C1 0 GNDCD 9 C9 D9 39 49 C9 GNDCD 8 C8 D8 38 48 C8 GNDCD 7 C7 D7 37 47 C7 GNDCD 6 C6 D6 36 46 C6 C5 D5 35 45 C5 C4 D4 34 44 C4 C3 D3 33 43 C3 C2 D2 C1 42 D1 R601-R610 Optional Output Terminations 32 29 C1 B1 0 100-DNP 20 DCO 10 A1 0 B9 100-DNP 19 CHA 7 9 A9 B8 100-DNP 18 CHB 6 8 A8 B7 100-DNP 17 CHC 5 7 A7 B6 100-DNP 16 CHD CSB1_CHA CHF 4 6 A6 B5 100-DNP 15 CHE CSB2_CHA CHG 3 5 A5 B4 100-DNP 14 CHF CSB3_CHA CHH 2 4 A4 B3 100-DNP 13 CHG CSB4_CHA FCO 1 A1 SDI_CHA B4 14 SDO_CHA 3 A3 B3 13 B2 100-DNP 12 22 CHH 2 A2 GNDAB 1 21 15 GNDAB 2 R609 A2 B5 23 GNDAB 2 22 SCLK_CHA GNDAB 3 R608 A3 16 24 GNDAB 3 23 B6 GNDAB 4 R607 A4 17 25 GNDAB 4 24 B7 GNDAB 5 R606 A5 18 26 GNDAB 5 CHE B8 GNDAB 6 R605 A6 25 19 27 GNDAB 6 CHD B9 GNDAB 7 R604 A7 26 20 28 GNDAB 7 27 B1 0 GNDAB 8 R603 A8 41 29 GNDAB 8 28 D1 30 GNDAB 9 R602 A9 42 GNDAB1 0 R601 A1 0 D2 51 GNDAB 9 CHC 43 GNDCD 1 31 41 C2 GNDAB1 0 30 8 D3 52 51 CHB 44 GNDCD 2 GNDCD 1 9 D4 GNDCD 3 52 CHA 45 53 GNDCD 2 10 D5 GNDCD 4 GNDCD 3 DCO 46 54 53 31 D6 GNDCD 5 GNDCD 4 32 47 55 54 33 D7 GNDCD 6 GNDCD 5 34 48 56 55 35 D8 GNDCD 7 57 56 36 49 58 57 37 D9 GNDCD 8 58 38 50 59 59 39 D1 0 GNDCD 9 B2 12 GNDAB 1 R610 B1 100-DNP 11 21 FCO 1 A1 Figure 80. Evaluation Board Schematic, Digital Output Interface Rev. B | Page 50 of 60 B1 11 06304-111 40 6469169-1 06304-084 AD9271 06304-083 Figure 81. Evaluation Board Layout, Top Side Figure 82. Evaluation Board Layout, Ground Plane (Layer 2) Rev. B | Page 51 of 60 06304-081 AD9271 06304-082 Figure 83. Evaluation Board Layout, Power Plane (Layer 3) Figure 84. Evaluation Board Layout, Power Plane (Layer 4) Rev. B | Page 52 of 60 06304-080 AD9271 06304-085 Figure 85. Evaluation Board Layout, Ground Plane (Layer 5) Figure 86. Evaluation Board Layout, Bottom Side Rev. B | Page 53 of 60 AD9271 Table 16. Evaluation Board Bill of Materials (BOM) 1 Item 1 Qty. 70 2 1 3 9 4 8 5 Reference Designator C101, C103, C105, C107, C109, C111, C113, C115, C121, C122, C123, C124, C201, C203, C205, C207, C209, C211, C213, C215, C221, C222, C223, C224, C301, C303, C304, C305, C306, C308, C309, C401, C402, C403, C409, C410, C411, C412, C413, C414, C415, C416, C417, C418, C419, C420, C421, C422, C502, C504, C702, C703, C708, C710, C712, C730, C731, C732, C733, C734, C735, C740, C742, C743, C744, C745, C746, C747, C748, C751 C302 Device Capacitor Package 402 Description 0.1 μF, ceramic, X5R, 10 V, 10% tol Manufacturer Panasonic AVX Murata RoHS Part Number ECJ-0EB1A104K 2 0402YD104KAT2A2 GRM155R71C104KA88D2 Capacitor 603 C307, C714, C715, C716, C717, C719, C720, C722, C723 C102, C106, C110, C114, C202, C206, C210, C214 Capacitor 603 AVX Murata Panasonic Murata 06036D475KAT2A GRM188R60J475KE19D ECJ-1VB0J105K2 GRM188R61C105KA93D2 Capacitor 402 1 C721 Capacitor 402 Kemet AVX Murata Murata C0402C220J5GACTU2 04025A220JAT2A2 GRM1555C1H220JZ01D2 GRM1555C1H101JZ01D2 6 1 C704 Capacitor 1812 Taiyo Yuden UMK432C106MM-T2 7 5 C501, C503, C707, C709, C711 Capacitor 603 Panasonic Murata ECJ-1VB0J106M2 GRM188R60J106M2 8 1 CR401 Diode SOT23 4.7 μF, 6.3 V, X5R, 10% tol 1 μF, ceramic, X5R, 6.3 V, 10% tol 22 pF, ceramic, NPO, 5% tol, 50 V 100 pF, ceramic, COG, 50 V, 5% tol 10 μF, X5S, 50 V, 20% tol 10 μF, ceramic, X5R, 6.3 V, 20% tol 30 V, 20 mA, dual Schottky HSMS-2812-TR1G 9 1 CR702 LED 603 Avago Technologies Limited (Agilent) Panasonic 10 5 D701, D702, D703, D704, D705 Diode DO-214AB S2A-TP2 11 1 F701 Fuse 1210 Micro Commercial Co. Tyco/Raychem 12 8 L401, L402, L403, L404, L405, L406, L407, L408 Inductor 1210 Murata LQH32MN561J23L2 13 8 L501, L502, L702, L703, L704, L705, L706, L707 Ferrite bead 1210 Murata BLM31PG500SH1L2 14 1 L701 Choke coil 5-pin Murata BNX016-01 Rev. B | Page 54 of 60 Green, 4 V, 5 m candela 3 A, 30 V, SMC 6.0 V, 2.2 A trip current resettable fuse 560 μH, test freq 1 kHz, 5% tol, 40 mA 10 μH, test freq 100 MHz, 25% tol, 500 mA 25 V dc, 15 A, 100 kHz to 1 GHz, 40 dB insertion loss LNJ314G8TRA2 NANOSMDC110F-22 AD9271 Item 15 Qty. 2 Reference Designator J501, P403 Device Connector Package 8-pin 16 2 P302, P303 Connector 2-pin 17 2 P405, P406 Connector 8-pin 18 1 P511 Connector 3-pin 19 1 J401 Connector 3-pin 20 13 Connector SMA 21 2 J101, J102, J103, J104, J201, J202, J203, J204, J301, J402, J403, P401, P402 P601, P602 Connector HEADER 22 1 P701 Connector 0.08", PCMT 23 85 Resistor 402 24 8 Resistor 402 25 12 Resistor 402 26 9 R102, R103, R105, R106, R111, R112, R114, R115, R120, R121, R123, R124, R129, R130, R131, R132, R133, R137, R138, R139, R140, R149, R151, R152, R153, R162, R163, R164, R202, R203, R205, R206, R211, R213, R214, R215, R220, R221, R223, R224, R229, R230, R232, R233, R237, R238, R239, R240, R249, R250, R251, R252, R253, R262, R263, R264, R304, R317, R331, R403, R405, R415, R416, R417, R418, R425, R427, R429, R431, R433, R435, R436, R439, R441, R443, R445, R446, R450, R451, R452, R460, R462, R463, R464, R466 R108, R117, R126, R135, R208, R217, R226, R235 R158, R159, R160, R161, R258, R259, R260, R261, R302, R404, R455, R458 R301, R338, R401, R402, R410, R413, R711, R714, R715 Resistor 402 Rev. B | Page 55 of 60 Description 100 mil header, male, 2 × 4 double row straight 100 mil header jumper, 1 × 2 100 mil header, female, 2 × 4 double row straight 3.5 mm header strip, male, 1 × 3 single row straight 100 mil header jumper, 1 × 3 Side mount SMA for 0.063 in. board thickness 1469169-1, right angle 2-pair, 25 mm, header assembly RAPC722, power supply connector 0 Ω, 1/16 W, 5% tol Manufacturer Samtec RoHS Part Number TSW-104-08-T-D2 Samtec TSW-102-07-G-S2 Samtec SSW-104-06-G-D2 Wieland Z5.531.3325.02 Samtec TSW-103-07-G-S2 Samtec SMA-J-P-H-ST-EM12 Tyco/AMP 1469169-1 NEW 6469169-1 Switchcraft RAPC722X2 Panasonic KOA Yageo NIC Components ERJ-2GE0R00X2 RK73Z1ETTP2 RC0402JR-070RL2 NRC04Z0TRF2 200 Ω, 1/16 W, 5% tol 49.9 Ω, 1/16 W, 0.5% tol NIC Components Susumu Co. NRC04J201TRF2 10 kΩ, 1/16 W, 5% tol Panasonic KOA Yageo NIC Components ERJ-2GEJ103X2 RK73B1ETTP103J2 RC0402JR-0710KL2 NRC04J103TRF2 RR0510R-49R9-D2 AD9271 Item 27 Qty. 3 Reference Designator R303, R422, R423 Device Resistor Package 402 Description 100 Ω, 1/16 W, 1% tol Manufacturer Panasonic KOA Yageo 28 7 R309, R319, R325, R326, R710, R712, R713 Resistor 402 1 kΩ, 1/16 W, 1% tol 29 1 R308 Resistor 402 470 kΩ, 1/16 W, 5% tol 30 2 R310, R336 Potentiometer 3-lead 31 1 R414 Resistor 402 10 kΩ, cermet trimmer potentiometer, 18-turn top adjust, 10%, 1/2 W 4.12 kΩ, 1/16 W, 1% tol Panasonic KOA Yageo NIC Components Panasonic KOA Yageo NIC Components Murata 32 3 R420, R421, R716 Resistor 402 240 Ω, 1/16 W, 5% tol 33 1 R335 Resistor 402 34 2 R447, R448 Resistor 402 35 6 Resistor 402 36 1 R453, R454, R467, R468, R469, R470 OSC401 Oscillator Surface mount 37 9 T101, T102, T103, T104, T201, T202, T203, T204, T401 Transformer CD542 38 1 T402 Transformer CD637 39 1 U301 IC SV-100-3 40 1 U302 IC SOT23 41 1 U401 IC LFCSP32-5X5 8.06 kΩ, 1/16 W, 1% tol 127 Ω, 1/16 W, 1% tol 750 Ω, 1/16 W, 5% tol Osc clock 50.000 MHz SMD 75 Ω, 1:1 impedance ratio transformer, 0.4 MHz to 800 MHz 50 Ω, 1:4 impedance ratio transformer, 0.2 MHz to 120 MHz Octal LNA/VGA/ AAF/ADC and crosspoint switch 1.0 V precision low noise shunt voltage reference Clock dist. Rev. B | Page 56 of 60 Panasonic NIC Components Yageo NIC Components NIC Components NIC Components NIC Components Valpey Fisher CTS RoHS Part Number ERJ-2RKF1000X2 RK73H1ETTP1000F2 RC0402FR-07100RL2 NRC04F1000TRF2 ERJ-2RKF1001X2 RK73H1ETTP1001F2 RC0402FR-071KL2 NRC04F1001TRF2 ERJ-2GEJ474X2 RK73B1ETTP474J2 RC0402JR-07470KL2 NRC04J474TRF2 PVA2A103A01R002 ERJ-2RKF4121X2 NRC04F4121TRF2 RC0402JR-07240RL2 NRC04J241TRF2 NRC04F8061TRF2 NRC04F1270TRF2 NRC04J751TRF2 VFAC3-BHL-50MHz CB3LV-3C-50M0000-T Mini-Circuits® ADT1-1WT+ Mini-Circuits ADTT4-1+ Analog Devices AD9271BSVZ-50 Analog Devices ADR510ARTZ Analog Devices AD9515BCPZ AD9271 Item 42 Qty. 1 Reference Designator U402 Device IC Package SO8 43 1 U706 IC CP-8 44 2 U704, U707 IC SOT223-2 Description Dual current feedback op amp, SO8 500 mA, low noise, low dropout reg Regulator 45 1 U705 IC SOT223-2 Regulator 46 1 U702 IC SC88 47 1 U703 IC SC88 NC7WZ07, dual buffer, SC88 NC7WZ16P6X, UHS dual buffer, SC88 1 2 This BOM is RoHS compliant. May use suitable alternative. Rev. B | Page 57 of 60 Manufacturer Analog Devices RoHS Part Number AD812ARZ Analog Devices ADP3335ACPZ-2.5 Analog Devices Analog Devices Fairchild ADP3339AKCZ-1.8 ADP3339AKCZ-3.3 Fairchild NC7WZ16P6X_NL2 NC7WZ07P6X_NL2 AD9271 OUTLINE DIMENSIONS 0.75 0.60 0.45 16.00 BSC SQ 1.20 MAX 14.00 BSC SQ 100 1 76 75 76 75 100 1 PIN 1 EXPOSED PAD TOP VIEW (PINS DOWN) 9.50 SQ 0° MIN 1.05 1.00 0.95 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY 25 26 51 50 BOTTOM VIEW (PINS UP) 51 26 0.50 BSC LEAD PITCH VIEW A 25 50 0.27 0.22 0.17 VIEW A ROTATED 90° CCW 080706-A COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD NOTES: THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS. Figure 87. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-3) Dimensions shown in millimeters ORDERING GUIDE Model AD9271BSVZ-50 1 AD9271BSVZRL-501 AD9271BSVZ-401 AD9271BSVZRL-401 AD9271BSVZ-251 AD9271BSVZRL-251 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel Z = RoHS Compliant Part. Rev. B | Page 58 of 60 Package Option SV-100-3 SV-100-3 SV-100-3 SV-100-3 SV-100-3 SV-100-3 AD9271 NOTES Rev. B | Page 59 of 60 AD9271 NOTES ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06304-0-5/09(B) Rev. B | Page 60 of 60