® LY62L204916A 2048K X 16 BIT LOW POWER CMOS SRAM Rev.1.3 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Description Initial Issue Typo error on page 9, revised as 8mmx10mm. Issue Date Nov. 06. 2012 Dec.18. 2012 Rev. 1.2 1. Revise ISB1 on page 4 & IDR on page 8 2. Revise VIH(max) & VIL(min) note on page 4 VIH(max) = VCC + 2.0V for pulse width less than 6ns. VIL(min) = VSS - 2.0V for pulse width less than 6ns. Jun. 10. 2013 Rev. 1.3 Deleted WRITE CYCLE Notes : Jun. 29. 2016 1.WE#,CE#, LB#, UB# must be high or CE2 must be low during all address transitions. In page 7 Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 0 ® LY62L204916A 2048K X 16 BIT LOW POWER CMOS SRAM Rev.1.3 FEATURE GENERAL DESCRIPTION Fast access time : 55/70ns Low power consumption: Operating current : 45/30mA (TYP.) Standby current : 6μA (TYP.) SL-version The LY62L204916A is a 33,554,432-bit low power CMOS static random access memory organized as 2,097,152 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. Single 2.7V ~ 3.6V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) Data retention voltage : 1.2V (MIN.) Green package available Package : 48-ball 8mm x 10mm TFBGA The LY62L204916A is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The LY62L204916A operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family LY62L204916A LY62L204916A(I) Operating Temperatur e 0 ~ 70℃ -40 ~ 85℃ Power Dissipation Vcc Range Speed 2.7 ~ 3.6V 2.7 ~ 3.6V 55/70ns 55/70ns FUNCTIONAL BLOCK DIAGRAM DQ0-DQ7 Lower Byte DQ8-DQ15 Upper Byte CE# CE2 WE# OE# LB# UB# Operating(Icc,TYP.) 6µA(SL) 6µA(SL) 45/30mA 45/30mA PIN DESCRIPTION Vcc Vss A0-A20 Standby(ISB1,TYP.) SYMBOL DESCRIPTION A0 – A20 Address Inputs DQ0 – DQ15 Data Inputs/Outputs DECODER I/O DATA CIRCUIT 2048Kx16 MEMORY ARRAY CE#, CE2 Chip Enable Input WE# Write Enable Input OE# Output Enable Input LB# Lower Byte Control UB# Upper Byte Control VCC Power Supply VSS Ground COLUMN I/O CONTROL CIRCUIT Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 1 ® LY62L204916A 2048K X 16 BIT LOW POWER CMOS SRAM Rev.1.3 PIN CONFIGURATION A LB# OE# A0 A1 B DQ8 UB# A3 A4 CE# DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D Vss DQ11 A17 A7 DQ3 Vcc E Vcc DQ12 NC A16 DQ4 Vss F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 A19 A12 A13 WE# DQ7 A9 A10 H A18 A8 A2 A11 CE2 A20 1 2 3 4 5 6 TFBGA(See through with Top View) ABSOLUTE MAXIMUN RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS SYMBOL VT1 VT2 Operating Temperature TA Storage Temperature Power Dissipation DC Output Current TSTG PD IOUT RATING -0.5 to 4.6 -0.5 to VCC+0.5 0 to 70(C grade) -40 to 85(I grade) -65 to 150 1 50 UNIT V V ℃ ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# CE2 OE# WE# LB# UB# H X X L L L L L L L L X L X H H H H H H H H X X X H H L L L X X X X X X H H H H H L L L X X H L X L H L L H L X X H X L H L L H L L I/O OPERATION SUPPLY CURRENT DQ0-DQ7 DQ8-DQ15 High – Z High – Z ISB,ISB1 High – Z High – Z High – Z High – Z High – Z High – Z ICC,ICC1 High – Z High – Z DOUT High – Z ICC,ICC1 DOUT High – Z DOUT DOUT DIN High – Z ICC,ICC1 DIN High – Z DIN DIN H = VIH, L = VIL, X = Don't care. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 2 ® LY62L204916A 2048K X 16 BIT LOW POWER CMOS SRAM Rev.1.3 DC ELECTRICAL CHARACTERISTICS SYMBOL TEST CONDITION PARAMETER Supply Voltage VCC *1 Input High Voltage VIH *2 Input Low Voltage VIL Input Leakage Current ILI VCC ≧ VIN ≧ VSS Output Leakage VCC ≧ VOUT ≧ VSS ILO Current Output Disabled Output High Voltage VOH IOH = -1mA Output Low Voltage VOL IOL = 2mA ICC Average Operating Power supply Current ICC1 ISB Standby Power Supply Current ISB1 MIN. 2.7 2.2 - 0.2 -1 Cycle time = Min. CE# = VIL and CE2 = VIH II/O = 0mA Other pins at VIL or VIH *4 MAX. 3.6 VCC+0.3 0.6 1 UNIT V V V µA -1 - 1 µA 2.2 - 2.7 - 0.4 V V - 55 - 45 80 mA - 70 - 30 60 mA - 10 20 mA 2 mA Cycle time = 1µs CE#≦0.2V and CE2≧VCC-0.2V II/O = 0mA Other pins at 0.2V or VCC-0.2V CE# = VIH or CE2 = VIL Other pins at VIL or VIH - 0.3 25℃ - 6 16 µA 40℃ - 6 16 µA -SL - 6 60 µA -SLI - 6 80 µA - SL - SLI CE# ≧VCC-0.2V or CE2≦0.2V Other pins at 0.2V or VCC-0.2V TYP. 3.0 - Notes: 1. VIH(max) = VCC + 2.0V for pulse width less than 6ns. 2. VIL(min) = VSS - 2.0V for pulse width less than 6ns. 3. Over/Undershoot specifications are characterized on engineering evaluation stage, not for mass production test. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP.) and TA = 25℃ CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 6 8 Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 3 UNIT pF pF ® LY62L204916A 2048K X 16 BIT LOW POWER CMOS SRAM Rev.1.3 AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change LB#, UB# Access Time LB#, UB# to High-Z Output LB#, UB# to Low-Z Output (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z LB#, UB# Valid to End of Write SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH tBA tBHZ* tBLZ* SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* tBW LY62L204916A-55 MIN. MAX. 55 55 55 30 10 5 20 20 10 55 25 10 - LY62L204916A-70 MIN. MAX. 70 70 70 35 10 5 25 25 10 70 30 10 - UNIT LY62L204916A-55 MIN. MAX. 55 50 50 0 45 0 25 0 5 20 45 - LY62L204916A-70 MIN. MAX. 70 60 60 0 55 0 30 0 5 25 60 - UNIT *These parameters are guaranteed by device characterization, but not production tested. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ® LY62L204916A 2048K X 16 BIT LOW POWER CMOS SRAM Rev.1.3 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE CE2 LB#,UB# tBA OE# tOE tOH tOHZ tBHZ tCHZ tOLZ tBLZ tCLZ Dout High-Z Data Valid High-Z Notes : 1.WE#is high for read cycle. 2.Device is continuouSLy selected OE# = low, CE# = low, CE2 = high, LB# or UB# = low. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high, LB# or UB# = low transition; otherwise tAA is the limiting parameter. 4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 5 ® LY62L204916A 2048K X 16 BIT LOW POWER CMOS SRAM Rev.1.3 WRITE CYCLE 1 (WE# Controlled) (1,2,4,5) tWC Address tAW CE# tCW CE2 tBW LB#,UB# tAS tWP tWR WE# tWHZ Dout TOW High-Z (4) tDW (4) tDH Data Valid Din WRITE CYCLE 2 (CE# and CE2 Controlled) (1,4,5) tWC Address tAW CE# tAS tWR tCW CE2 tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW Din tDH Data Valid Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 6 ® LY62L204916A 2048K X 16 BIT LOW POWER CMOS SRAM Rev.1.3 WRITE CYCLE 3 (LB#,UB# Controlled) (1,4,5) tWC Address tAW tWR CE# tAS tCW CE2 tBW LB#,UB# tWP WE# tWHZ Dout High-Z (4) tDW tDH Data Valid Din Notes : 1.A write occurs during the overlap of a low CE#, high CE2, low WE#, LB# or UB# = low. 2.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 3.During this period, I/O pins are in the output state, and input signals must not be applied. 4.If the CE#, LB#, UB# low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 5.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 7 ® LY62L204916A 2048K X 16 BIT LOW POWER CMOS SRAM Rev.1.3 DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION VCC for Data Retention VDR CE#≧VCC - 0.2V or CE2≦0.2V Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time IDR tCDR -SL VCC = 1.2V -SLI CE# ≧VCC-0.2V or CE2≦0.2V -SL other pins at 0.2V or VCC-0.2V -SLI See Data Retention Waveforms (below) 25℃ 40℃ tR DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) VDR ≧ 1.2V Vcc Vcc(min.) Vcc(min.) tCDR CE# VIH tR CE# ≧ Vcc-0.2V VIH Low Vcc Data Retention Waveform (2) (CE2 controlled) VDR ≧ 1.2V Vcc Vcc(min.) Vcc(min.) tCDR CE2 tR CE2 ≦ 0.2V VIL VIL Low Vcc Data Retention Waveform (3) (LB#, UB# controlled) VDR ≧ 1.2V Vcc Vcc(min.) Vcc(min.) tCDR LB#,UB# VIH tR LB#,UB# ≧ Vcc-0.2V VIH Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 8 MIN. TYP. MAX. UNIT 1.2 3.6 V 6 16 µA 6 16 µA 6 60 µA 6 80 µA 0 - - ns tRC* - - ns ® LY62L204916A Rev.1.3 2048K X 16 BIT LOW POWER CMOS SRAM PACKAGE OUTLINE DIMENSION 48-ball 8mm × 10mm TFBGA Package Outline Dimension Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 9 ® LY62L204916A 2048K X 16 BIT LOW POWER CMOS SRAM Rev.1.3 ORDERING INFORMATION Package Access Time Type (Speed)(ns) 48-ball 8mmx10mm TFBGA 55 Power Type Special Ultra Low Power Temperature Range(℃) 0℃~70℃ -40℃~85℃ 70 Special Ultra Low Power 0℃~70℃ -40℃~85℃ Packing Type Tray LY62L204916AGL-55SL Tape Reel LY62L204916AGL-55SLT Tray LY62L204916AGL-55SLI Tape Reel LY62L204916AGL-55SLIT Tray LY62L204916AGL-70SL Tape Reel LY62L204916AGL-70SLT Tray LY62L204916AGL-70SLI Tape Reel LY62L204916AGL-70SLIT Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 10 Lyontek Item No. ® LY62L204916A Rev.1.3 2048K X 16 BIT LOW POWER CMOS SRAM THIS PAGE IS LEFT BLANK INTENTIONASLY. Lyontek Inc. reserves the rights to change the specifications and products without notice. 2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 11