TI1 LM5066PMHNOPB High voltage system power management and protection ic with pmbus Datasheet

LM5066
LM5066 High Voltage System Power Management and Protection IC with PMBus
Literature Number: SNVS655F
LM5066
High Voltage System Power Management and Protection
IC with PMBus
General Description
Features
The LM5066 combines a high performance hot swap controller with a PMBus™ compliant SMBus/I 2C interface to accurately measure, protect and control the electrical operating
conditions of systems connected to a backplane power bus.
The LM5066 continuously supplies real-time power, voltage,
current, temperature and fault data to the system management host via the SMBus interface.
The LM5066 control block includes a unique hot swap architecture that provides current and power limiting to protect
sensitive circuitry during insertion of boards into a live system
backplane, or any other "hot" power source. A fast acting circuit breaker prevents damage in the event of a short circuit
on the output. The input under-voltage and over-voltage levels and hysteresis are configurable, as well as the insertion
delay time and fault detection time. A temperature monitoring
block on the LM5066 interfaces with a low-cost external diode
for monitoring the temperature of the external MOSFET or
other thermally sensitive components. The PGD output provides a fast indicator when the input and/or output voltages
are outside their programmed ranges. LM5066 current measurement accuracy is ±4.5% over the operating temperature
range.
The LM5066 monitoring block computes both the real-time
and average values of subsystem operating parameters
(VIN, IIN, PIN, VOUT) as well as the peak power. Accurate power
averaging is accomplished by averaging the product of the
input voltage and current. A black box (Telemetry/Fault Snapshot) function captures and stores telemetry data and device
status in the event of a warning or a fault.
■ Input voltage range: 10V to 80V
■ Programmable 26 mV or 50 mV Current Limit Threshold
with Power Limiting (MOSFET Power Dissipation Limiting)
■ Real time monitoring of VIN, VOUT, IIN, PIN, VAUX with 12-bit
resolution and 1 kHz sampling rate
■ Configurable Circuit Breaker protection for hard shorts
■ Configurable Under-Voltage and Over-Voltage protection
■ Remote temperature sensing with programmable warning
■
■
■
■
■
■
■
■
■
and shutdown thresholds
Detection and notification of damaged MOSFET condition
Power measurement accuracy: ±4.5% over temperature
True Input Power averages dynamic power readings
Averaging of VIN, IIN, PIN, and VOUT over programmable
interval ranging from 0.001 to 4 seconds
Programmable WARN and FAULT thresholds with
SMBA notification
Black box capture of telemetry measurements and device
status triggered by WARN or FAULT condition
I2C/SMBus interface and PMBus compliant command
structure
Full featured application development software
eTSSOP-28 package
Applications
■ Server Backplane Systems
■ Base Station Power Distribution Systems
■ Solid State Circuit Breaker
Typical Application Schematic
30115911
© 2011 National Semiconductor Corporation
301159
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LM5066 High Voltage System Power Management and Protection IC with PMBus™
August 22, 2011
LM5066
Connection Diagram
Solder exposed pad to ground.
30115902
Ordering Information
Order Number
Package Type
Package Drawing
Supplied As
LM5066PMH NOPB
eTSSOP-28
MXA28A
48 units in rail
LM5066PMHE NOPB
eTSSOP-28
MXA28A
250 units in tape and reel
LM5066PMHX NOPB
eTSSOP-28
MXA28A
2,500 units in tape and reel
Pin Descriptions
Pin
No.
Name
Pad Exposed Pad
Description
Exposed pad of TSSOP
package
Applications Information
Solder to the ground plane to reduce thermal resistance
1
OUT
Output feedback
Connect to the output rail (external MOSFET source). Internally used to
determine the MOSFET VDS voltage for power limiting, and to monitor the output
voltage.
2
GATE
Gate drive output
Connect to the external MOSFET's gate.
3
SENSE
Current sense input
4
VIN_K
5
VIN
Positive supply kelvin pin The input voltage is measured on this pin.
Positive supply input
6
N/C
No connection
7
UVLO/EN
Under-voltage lockout
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The voltage across the current sense resistor (RS) is measured from VIN_K to
this pin. If the voltage across RS reaches over-current threshold the load current
is limited and the fault timer activates.
This pin is the input supply connection for the device.
An external resistor divider from the system input voltage sets the under-voltage
turn-on threshold. An internal 20 µA current source provides hysteresis. The
enable threshold at the pin is nominally 2.48V. This pin can also be used for
remote shutdown control.
2
Name
Description
8
OVLO
Over-voltage lockout
Applications Information
An external resistor divider from the system input voltage sets the over-voltage
turn-off threshold. An internal 21 µA current source provides hysteresis. The
disable threshold at the pin is 2.46V.
9
AGND
Circuit ground
10
GND
Circuit ground
Analog device ground. Connect to GND at the pin.
11
SDAI
SMBus data input pin
Data input pin for SMBus. Connect to SDAO if the application does not require
unidirectional isolation devices.
12
SDAO
SMBus data output pin
Data output pin for SMBus. Connect to SDAI if the application does not require
unidirectional isolation devices.
13
SCL
SMBus clock
14
SMBA
SMBus alert line
Clock pin for SMBus.
15
VREF
Internal Reference
Internally generated precision reference used for analog to digital conversion.
Connect a 1 µF capacitor on this pin to ground for bypassing.
16
DIODE
External diode
Connect this to a diode-configured MMBT3904 NPN transistor for temperature
monitoring.
17
VAUX
Auxiliary voltage input
Auxiliary pin allows voltage telemetry from an external source. Full scale input
of 2.97V.
18
ADR2
SMBUS address line 2
Tri- state address line. Should be connected to GND, VDD, or left floating.
19
ADR1
SMBUS address line 1
Tri - state address line. Should be connected to GND, VDD, or left floating.
20
ADR0
SMBUS address line 0
Tri - state address line. Should be connected to GND, VDD, or left floating.
21
VDD
Internal sub-regulator
output
Internally sub-regulated 4.85V bias supply. Connect a 1 µF capacitor on this
pin to ground for bypassing.
22
CL
Current limit range
Connect this pin to GND or leave floating to set the nominal over-current
threshold at 50mV. Connecting CL to VDD will set the over-current threshold
to be 26mV.
23
FB
Power Good feedback
An external resistor divider from the output sets the output voltage at which the
PGD pin switches. The threshold at the pin is nominally 2.46V. An internal 20
µA current source provides hysteresis.
24
RETRY
Fault retry input
This pin configures the power up fault retry behavior. When this pin is connected
to GND or left floating, the device will continually try to engage power during a
fault. If the pin is connected to VDD, the device will latch off during a fault.
25
TIMER
Timing capacitor
An external capacitor connected to this pin sets the insertion time delay, fault
timeout period and restart timing.
26
PWR
Power limit set
An external resistor connected to this pin, in conjunction with the current sense
resistor (RS), sets the maximum power dissipation allowed in the external series
pass MOSFET.
27
N/C
No Connection
28
PGD
Power Good indicator
Alert pin for SMBus, active low.
An open drain output. This output is high when the voltage at the FB pin is above
VFBTH (nominally 2.46V) and the input supply is within its under-voltage and
over-voltage thresholds. Connect to the output rail (external MOSFET source)
or any other voltage to be monitored.
3
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LM5066
Pin
No.
LM5066
ESD Rating (Note 2)
Human Body Model
Storage Temperature
Junction Temperature
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VIN, VIN_K, GATE, UVLO/EN, OUT,
SENSE, PGD to GND (Note 6)
OVLO, FB, TIMER, PWR to GND
SCL, SDAI, SDAO, CL, ADR0, ADR1,
ADR2, VDD, VAUX, DIODE, RETRY to
GND
SENSE to VIN_K, VIN to VIN_K, AGND to
GND
2kV
-65°C to +150°C
+150°C
Operating Ratings
-0.3V to 100V
-0.3V to 7.0V
VIN, SENSE, OUT voltage
10V to 80V
Junction Temperature
-40°C to +125°C
-0.3V to 6.0V
-0.3V to +0.3V
Electrical Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the
junction temperature (TJ) range of -40°C to +125°C unless otherwise stated. Minimum and Maximum limits are guaranteed through
test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for
reference purposes only. Unless otherwise stated the following conditions apply: VIN = 48V. See (Note 3) and (Note 7).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Input (VIN Pin)
IIN-EN
Input Current, enabled
VUVLO = 3V and VOVLO = 2V
7.2
9.5
mA
PORIT
Power On Reset threshold at VIN to
trigger insertion timer
VIN Increasing
7.8
9.0
V
POREN
Power On Reset threshold at VIN to
enable all functions
VIN Increasing
8.6
9.9
V
PORHYS
POREN Hysteresis
VIN Decreasing
120
mV
VDD Regulator (VDD pin)
VDD
IVDD = 0 mA
4.60
IVDD = 10 mA
VDDILIM
VDD Current Limit
VDDPOR
VDD Voltage Reset threshold
4.90
5.15
V
-42
mA
4.85
-25
VDD Rising
-30
V
4.1
V
UVLO/EN, OVLO Pins
UVLOTH
UVLO threshold
VUVLO Falling
2.41
2.48
2.55
V
UVLOHYS
UVLO hysteresis current
UVLO = 1V
UVLODEL
UVLO delay
Delay to GATE high
13
20
9
26
µA
Delay to GATE low
13
UVLOBIAS
UVLO bias current
UVLO = 3V
1
µA
OVLOTH
OVLO threshold
VOVLO Rising
2.39
2.46
2.53
V
OVLOHYS
OVLO hysteresis current
OVLO = 1V
-26
-21
-13
µA
OVLODEL
OVLO delay
Delay to GATE high
13
Delay to GATE low
10
OVLOBIAS
OVLO bias current
OVLO = 1V
µs
µs
1
µA
110
mV
1
µA
Power Good (PGD pin)
PGDVOL
Output low voltage
ISINK = 2 mA
PGDIOH
Off leakage current
VPGD = 80V
FBTH
FB Threshold
VUVLO = 3V and VOVLO = 2V
FBHYS
FB Hysteresis Current
FBDEL
FB Delay
60
FB Pin
FBLEAK
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Off Leakage Current
2.41
2.46
2.52
V
-25
-20
-15
µA
Delay to PGD high
7.6
µs
Delay to PGD low
9.2
µs
VFB = 2.3V
4
1
µA
Parameter
Conditions
Min
Typ
Max
Units
16.5
19.5
22.5
mV
Power Limit (PWR Pin)
PWRLIM
IPWR
RSAT(PWR)
Power limit sense voltage (VINSENSE)
SENSE-OUT = 48V, RPWR = 121 kΩ
SENSE-OUT = 24V, RPWR = 75 kΩ
23
mV
PWR pin current
VPWR = 2.5V
-20
µA
PWR pin impedance when disabled
UVLO = 2V
135
Ω
Gate Control (GATE Pin)
IGATE
Source current
Normal Operation
-26
-20
-10
µA
Fault Sink current
UVLO = 2V
3.4
4.2
5.3
mA
POR Circuit Breaker sink current
VIN - SENSE = 150 mV or VIN <
PORIT, VGATE = 5V
50
115
180
mA
15
16.5
18
V
VGATEZ
Reverse-bias voltage of GATE to OUT GATE - OUT
zener diode
VGATECP
Peak charge pump voltage in normal GATE - OUT
operation (VIN = VOUT)
13.6
V
OUT Pin
IOUT-EN
OUT bias current, enabled
OUT = VIN, Normal operation
78
µA
IOUT-DIS
OUT bias current, disabled (Note 4)
Disabled, OUT = 0V, SENSE = VIN
-50
µA
Current limit threshold voltage (VIN VSENSE)
CL = VDD
23
26
29
CL = GND
47
50
53
Response time
VIN-SENSE stepped from 0 mV to 80
mV
45
µs
SENSE input current
Enabled, SENSE = OUT
25
µA
Disabled, OUT = 0V
66
Enabled, OUT = 0V
220
Current Limit
VCL
tCL
ISENSE
mV
Circuit Breaker
RTCB
Circuit Breaker to Current Limit Ratio: CB/CL ratio bit = 0, ILim = 50 mV
(VIN -VSENSE)CB/VCL
CB/CL ratio bit = 1, ILim = 50 mV
1.64
1.94
2.23
3.28
3.87
4.45
CB/CL ratio bit = 0, ILim = 26 mV
1.88
CB/CL ratio bit = 1, ILim = 26 mV
VCB
tCB
Circuit Breaker Threshold Voltage:
(VIN - VSENSE)
Response time
V/V
3.75
CB/CL ratio bit = 0, ILim = 50 mV
80
96
110
CB/CL ratio bit = 1, ILim = 50 mV
164
193
222
CB/CL ratio bit = 0, ILim = 26 mV
39
48
57
CB/CL ratio bit = 1, ILim = 26 mV
79
96
113
0.42
0.83
µs
3.74
3.9
4.07
V
0.98
1.1
1.24
V
VIN - SENSE stepped from 0 mV to
150 mV, time to GATE low, no load
mV
Timer (TIMER pin)
VTMRH
Upper threshold
VTMRL
Lower threshold
Restart cycles
End of
8th
cycle
0.3
Re-enable Threshold
ITIMER
Insertion time current
TIMER pin = 2V
V
0.3
-5.9
-4.8
V
-3.3
µA
Sink current, end of insertion time
1.0
1.5
2.0
mA
Fault detection current
-95
-75
-50
µA
Fault sink current
1.7
2.5
3.2
µA
DCFAULT
Fault Restart Duty Cycle
tFAULT_DELAY
Fault to GATE low delay
TIMER pin reaches the upper
threshold
0.5
%
12
µs
Internal Reference
VREF
Reference Voltage
2.93
5
2.97
3.02
V
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LM5066
Symbol
LM5066
Symbol
Parameter
Conditions
Min
Typ
Max
Units
ADC and MUX
Resolution
12
Bits
Integral Non-Linearity
ADC only
±4
LSB
tACQUIRE
Acquisition + Conversion Time
Any Channel
100
µs
tRR
Acquisition Round Robin Time
Cycle all channels
1
ms
CL = GND
75.8
mV
CL = VDD
38.2
mV
CL = GND
18.5
µV
CL = VDD
9.3
µV
2.97
V
INL
Telemetry Accuracy
IINFSR
IINLSB
Current input full scale range
Current input LSB
VAUXFSR
VAUX input full scale range
VAUXLSB
VAUX input LSB
725
µV
VINFSR
Input voltage full scale range
89.3
V
VINLSB
Input voltage LSB
IINACC
Input Current Accuracy
VIN – SENSE = 50mV, CL = GND
-3.0
+3.0
%
VACC
VAUX, VIN, VOUT
VIN, VOUT = 48V
VAUX = 2.8V
-2.7
+2.7
%
Input Power Accuracy
VIN = 48V, VIN – SENSE = 50mV,
CL = VDD
-4.5
+4.5
%
10
°C
PINACC
21.8
mV
Remote Diode Temperature Sensor
TACC
Temperature Accuracy Using Local
Diode
TA = 25°C to 85°C
2
Remote Diode Resolution
IDIODE
External Diode Current Source
9
High Level
250
Low Level
9.4
Diode Current Ratio
bits
325
µA
µA
25.9
PMBus Pin Thresholds (SMBA, SDA, SCL)
VIL
Data, Clock Input Low Voltage
VIH
Data, Clock Input High Voltage
VOL
Data Output Low Voltage
ISINK = 3 mA
ILEAK
Input Leakage Current
SDAI,SMBA,SCL = 5V
0.9
V
2.1
5.5
V
0
0.4
V
1
µA
Configuration Pin Thresholds (CL, RETRY)
VIH
ILEAK
Threshold Voltage
Input Leakage Current
V
3
CL, RETRY = 5V
5
µA
Thermal (Note 5)
θJA
Junction to Ambient
29
°C/W
θJC
Junction to Case
4
°C/W
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and conditions see the Electrical Characteristics.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. 2 kV rating for all pins except GATE which is rated for
1 kV.
Note 3: Current out of a pin is indicated as a negative value.
Note 4: OUT bias current (disabled) due to leakage current through an internal 1 MΩ resistance from SENSE to VOUT.
Note 5: Junction to ambient thermal resistance is highly application and board layout dependent. Specified thermal resistance values for the package specified
is based on a 4-layer, 4"x3", 2/1/1/2 oz. Cu board with 15 vias with 8 mil. diameter under the DAP.
Note 6: The GATE pin voltage is typically 13.6V above VIN when the LM5066 is enabled. Therefore, the Absolute Maximum Rating for VIN applies only when
the LM5066 is disabled, or for a momentary surge to that voltage since the Absolute Maximum Rating for the GATE pin is also 100V.
Note 7: All limits are guaranteed. All electrical characteristics having room temperature limits are tested during production at TA = 25°C. All hot and cold limits
are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
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6
LM5066
Typical Performance Characteristics
Unless otherwise specified the following conditions
apply: TJ = 25°C, VIN = 48V. All graphs show junction temperature.
VIN Pin Current
Sense Pin Current (Enabled)
7.5
SENSE PIN CURRENT (ENABLED) (μA)
VIN INPUT CURRENT (mA)
8.0
VIN = 80V
7.0
6.5
VIN = 48V
6.0
5.5
VIN = 10V
5.0
30
29
28
27
26
25
24
23
22
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
30115976
30115971
Out Pin Current (Disabled)
150
120
OUTPUT PIN CURRNET (DISABLED) (μA)
OUTPUT PIN CURRENT (ENABLED) (μA)
Out Pin Current (Enabled)
VIN = 80V
90
60
VIN = 48V
30
VIN = 10V
0
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
0
-20
-40
VIN = 80V
VIN = 48V
-60
-80
VIN = 10V
-100
-60 -40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
30115974
30115973
Gate Zener Reverse Bias Voltage (VGATE - VOUT)
Gate Pin Source Current
-18.0
GATE PIN SOURCE CURRENT (μA)
18.0
GATE PIN VOLTAGE (V)
17.8
17.6
17.4
17.2
17.0
16.8
VIN = 10V to 80V
16.6
16.4
16.2
16.0
-18.5
-19.0
-19.5
-20.0
-60 -40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
-60 -40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
30115977
30115972
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LM5066
UVLO Threshold
2.50
30
UVLO THRESHOLD (V)
VSNS AT POWER THRESHOLD (mV)
VSNS at Power Limit Threshold
RPWR = 75 kΩ
25
VIN = 24V
20
VIN = 48V
15
10
2.48
VIN = 10V
2.46
2.44
VIN = 48V, 80V
VIN = 80V
5
2.42
0
-40 -20
-60 -40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
0 20 40 60 80 100 120 140
TEMPERATURE (°C)
30115981
30115989
UVLO Hysteresis Current
FB Threshold
2.48
20.7
20.6
FB THRESHOLD (V)
UVLO HYSTERESIS CURRENT (μA)
20.8
VIN = 10V to 80V
20.5
2.46
2.44
2.42
20.4
-60 -40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
-60 -40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
30115982
30115979
OVLO Threshold
OVLO Hysteresis
-18
OVLO HYSTERESIS CURRENT (μA)
OVLO THRESHOLD (V)
2.48
VIN = 10V to 80V
2.46
2.46
2.44
-60 -40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
-22
VIN = 10V to 80V
-24
-26
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
30115983
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-20
30115984
8
Current Limit Threshold
-23.0
CURRENT LIMIT THRESHOLD (mV)
55
-23.5
FB HYSTERESIS (μA)
LM5066
FB Pin Hysteresis
-24.0
-24.5
-25.0
-25.5
-26.0
-60 -40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
50
45
CL = GND
40
35
30
CL = VDD
25
20
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
30115980
30115986
Reference Voltage
2.965
200
180
CL = GND, CB/CL BIT = HIGH
2.960
160
140
120
VREF (V)
CIRCUIT BREAKER THRESHOLD (mV)
Circuit Breaker Threshold
CL = GND, CB/CL BIT = LOW
100
2.950
80
60
2.955
CL = VDD, CB/CL BIT = LOW
40
2.945
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
-60 -40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
30115988
30115990
PIN Measurement Accuracy
(VIN - SENSE = 50 mV)
0.5
1.0
0.4
0.8
0.3
0.6
PIN ERROR (% OF FSR)
IIN ERROR ( % OF FSR)
IIN Measurement Accuracy
(VIN - SENSE = 50 mV)
0.2
0.1
0.0
-0.1
-0.2
-0.3
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.4
-0.8
-0.5
-1.0
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE ( °C)
-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
301159a8
301159a9
9
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300
Startup (Insertion Delay)
Rs = 3 mΩ
Rs = 5 mΩ
Rs = 10 mΩ
Rs = 20 mΩ
250
PMOSFET(LIM) (W)
LM5066
MOSFET Power Dissipation Limit vs. RPWR and RS
(VIN = 48V)
200
150
100
50
30115991
100 ms/DIV
0
0
25
50
75
100
RPWR (kΩ)
125
150
301159f2
Startup (Short circuit VOUT)
Startup (1A Load)
30115993
30115992
1s/DIV
50 ms/DIV
Startup (UVLO/EN, OVLO)
Startup (PGD)
30115994
30115995
200 ms/DIV
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200 ms/DIV
10
LM5066
Current Limit Event (CL = VDD)
Circuit Breaker Event (CL = VDD)
30115996
30115997
2 ms/DIV
500 µs/DIV
Retry Event (RETRY = GND)
Latch Off (RETRY = VDD)
30115999
200 ms/DIV
30115998
500 ms/DIV
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LM5066
Block Diagram
30115910
RETRY pin. Once started, the number of retries can be set to
none, 1, 2, 4, 8, 16, or infinite. The circuit breaker function
quickly switches off the series pass device upon detection of
a severe over-current condition. Programmable under-voltage lockout (UVLO) and over-voltage lockout (OVLO) circuits
shut down the LM5066 when the system input voltage is outside the desired operating range.
The telemetry capability of the LM5066 provides intelligent
monitoring of the input voltage, output voltage, input current,
input power, temperature, and an auxiliary input. The LM5066
also provides a peak capture of the input power and programmable hardware averaging of the input voltage, current,
power, and output voltage. Warning thresholds which trigger
the SMBA pin may be programmed for input and output voltage, current, power and temperature via the PMBus interface.
Additionally, the LM5066 is capable of detecting damage to
the external MOSFET, Q1.
Functional Description
The inline protection functionality of the LM5066 is designed
to control the in-rush current to the load upon insertion of a
circuit card into a live backplane or other “hot” power source,
thereby limiting the voltage sag on the backplane’s supply
voltage, and the dV/dt of the voltage applied to the load. The
effects on other circuits in the system are minimized by preventing possible unintended resets. A controlled shutdown
when the circuit card is removed can also be implemented
using the LM5066.
In addition to a programmable current limit, the LM5066 monitors and limits the maximum power dissipation in the series
pass device to maintain operation within the device Safe Operating Area (SOA). Either current limiting or power limiting
for an extended period of time results in the shutdown of the
series pass device. In this event, the LM5066 can latch off or
repetitively retry based on the hardware setting of the
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12
LM5066
30115911
FIGURE 1. Typical Application Circuit
As the voltage at the OUT pin increases, the LM5066 monitors
the drain current and power dissipation of MOSFET Q1. Inrush current limiting and/or power limiting circuits actively
control the current delivered to the load. During the in-rush
limiting interval (t2 in Figure 2) an internal 75 µA fault timer
current source charges CT. If Q1’s power dissipation and the
input current reduce below their respective limiting thresholds
before the TIMER pin reaches 3.9V, the 75 µA current source
is switched off, and CT is discharged by the internal 2.5 µA
current sink (t3 in Figure 2). The in-rush limiting will no longer
engage unless a current-limit condition occurs.
If the TIMER pin voltage reaches 3.9V before in-rush current
limiting or power limiting ceases during t2, a fault is declared
and Q1 is turned off. See the Fault Timer & Restart section for
a complete description of the fault mode.
The LM5066 will assert the SMBA pin after the input voltage
has exceeded its POR threshold to indicate that the volatile
memory and device settings are in their default state. The
CONFIG_PRESET bit within the STATUS_MFR_SPECIFIC
register (80h) indicates default configuration of warning
thresholds and device operation and will remain high until a
CLEAR_FAULTS command is received.
Power Up Sequence
The VIN operating range of the LM5066 is 10V to 80V, with a
transient capability to 100V. Referring to Figure 1 and Figure
2, as the voltage at VIN initially increases, the external Nchannel MOSFET (Q1) is held off by an internal 115 mA pulldown current at the GATE pin. The strong pull-down current
at the GATE pin prevents an inadvertent turn-on as the
MOSFET’s gate-to-drain (Miller) capacitance is charged. Additionally, the TIMER pin is initially held at ground. When the
VIN voltage reaches the POR threshold the insertion time begins. During the insertion time, the capacitor at the TIMER pin
(CT) is charged by a 4.8 µA current source, and Q1 is held off
by a 4.2 mA pull-down current at the GATE pin regardless of
the input voltage. The insertion time delay allows ringing and
transients at VIN to settle before Q1 is enabled. The insertion
time ends when the TIMER pin voltage reaches 3.9V. CT is
then quickly discharged by an internal 1.5 mA pull-down current. The GATE pin then switches on Q1 when VIN exceeds
the UVLO threshold. If VIN is above the UVLO threshold at the
end of the insertion time, Q1 the GATE pin charge pump
sources 20 µA to charge the gate capacitance of Q1. The
maximum voltage from the gate to source of the Q1 is limited
by an internal 16.5V zener diode.
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LM5066
30115913
FIGURE 2. Power Up Sequence (Current Limit Only)
or an automatic retry is attempted (RETRY pin to GROUND
or floating). See the Fault Timer & Restart section. If the system input voltage falls below the UVLO threshold, or rises
above the OVLO threshold, the GATE pin is pulled low by the
4.2 mA pull-down current to switch off Q1.
Gate Control
A charge pump provides the voltage at the GATE pin to enhance the N-Channel MOSFET’s gate (Q1). During normal
operating conditions (t3 in Figure 2) the gate of Q1 is held
charged by an internal 20 µA current source. The charge
pump peak voltage is roughly 13.5V, which will force a VGS
across Q1 of 13.5V under normal operation. When the system
voltage is initially applied, the GATE pin is held low by a 115
mA pull-down current. This helps prevent an inadvertent turnon of Q1 through its drain-gate capacitance as the applied
system voltage increases.
During the insertion time (t1 in Figure 2) the GATE pin is held
low by a 4.2 mA pull-down current. This maintains Q1 in the
off-state until the end of t1, regardless of the voltage at VIN or
UVLO. Following the insertion time, during t2 in Figure 2 the
gate voltage of Q1 is modulated to keep the current or power
dissipation level from exceeding the programmed levels.
While in the current or power limiting mode, the TIMER pin
capacitor is charging. If the current and power limiting cease
before the TIMER pin reaches 3.9V the TIMER pin capacitor
then discharges, and the circuit begins normal operation. If
the in-rush limiting condition persists such that the TIMER pin
reached 3.9V during t2, the GATE pin is then pulled low by the
4.2 mA pull-down current. The GATE pin is then held low until
either a power up sequence is initiated (RETRY pin to VDD),
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Current Limit
The current limit threshold is reached when the voltage across
the sense resistor RS (VIN to SENSE) exceeds the internal
voltage limit of 26 mV or 50 mV depending on whether the CL
pin is connected to VDD or GND, respectively. In the current
limiting condition, the GATE voltage is controlled to limit the
current in MOSFET Q1. While the current limit circuit is active,
the fault timer is active as described in the Fault Timer &
Restart section. If the load current falls below the current limit
threshold before the end of the Fault Timeout Period, the
LM5066 resumes normal operation. If the current limit condition persists for longer than the Fault Timeout Period set by
CT, the IIN OC Fault bit in the STATUS_INPUT (7Ch) register,
the INPUT bit in the STATUS_WORD (79h) register, and
IIN_OC/PFET_OP_FAULT bit in the DIAGNOSTIC_WORD
(E1h) register will be toggled high and SMBA pin will be asserted. SMBA toggling can be disabled using the
ALERT_MASK (D8h) register. For proper operation, the RS
resistor value should be no higher than 200 mΩ. Higher val14
Fault Timer & Restart
When the current limit or power limit threshold is reached
during turn-on, or as a result of a fault condition, the gate-tosource voltage of Q1 is modulated to regulate the load current
and power dissipation in Q1. When either limiting function is
active, a 75 µA fault timer current source charges the external
capacitor (C T) at the TIMER pin as shown in Figure 2 (Fault
Timeout Period). If the fault condition subsides during the
Fault Timeout Period before the TIMER pin reaches 3.9V, the
LM5066 returns to the normal operating mode and CT is discharged by the 1.5 mA current sink. If the TIMER pin reaches
3.9V during the Fault Timeout Period, Q1 is switched off by a
4.2 mA pull-down current at the GATE pin. The subsequent
restart procedure then depends on the selected retry configuration.
If the RETRY pin is high, the LM5066 latches the GATE pin
low at the end of the Fault Timeout Period. CT is then discharged to ground by the 2.5 µA fault current sink. The GATE
pin is held low by the 4.2 mA pull-down current until a power
up sequence is externally initiated by cycling the input voltage
(VIN), or momentarily pulling the UVLO/EN pin below its
threshold with an open-collector or open-drain device as
shown in Figure 3. The voltage at the TIMER pin must be
<0.3V for the restart procedure to be effective. The
TIMER_LATCHED_OFF bit in the DIAGNOSTIC_WORD
(E1h) register will remain high while the latched off condition
persists.
Circuit Breaker
If the load current increases rapidly (e.g., the load is short
circuited) the current in the sense resistor (RS) may exceed
the current limit threshold before the current limit control loop
is able to respond. If the current exceeds 1.94x or 3.87x (CL
= GND) the current limit threshold, Q1 is quickly switched off
by the 115 mA pull-down current at the GATE pin, and a Fault
Timeout Period begins. When the voltage across RS falls below the circuit breaker (CB) threshold, the 115 mA pull-down
current at the GATE pin is switched off, and the gate voltage
of Q1 is then determined by the current limit or the power limit
functions. If the TIMER pin reaches 3.9V before the current
limiting or power limiting condition ceases, Q1 is switched off
by the 4.2 mA pull-down current at the GATE pin as described
in the Fault Timer & Restart section. A circuit breaker event
will cause the CIRCUIT BREAKER FAULT bit in the
STATUS_MFR_SPECIFIC (80h) and DIAGNOSTIC_WORD
(E1h) registers to be toggled high and SMBA pin will be asserted unless this feature is disabled using the ALERT_MASK
(D8h) register. The circuit breaker pin configuration may be
overridden by setting appropriate bits in the DEVICE_SETUP
(D9h) register.
Power Limit
An important feature of the LM5066 is the MOSFET power
limiting. The Power Limit function can be used to maintain the
maximum power dissipation of MOSFET Q1 within the device
SOA rating. The LM5066 determines the power dissipation in
Q1 by monitoring its drain-source voltage (SENSE to OUT),
and the drain current through the RS (VIN to SENSE). The
product of the current and voltage is compared to the power
limit threshold programmed by the resistor at the PWR pin. If
the power dissipation reaches the limiting threshold, the
GATE voltage is modulated to regulate the current in Q1.
While the power limiting circuit is active, the fault timer is active as described in the Fault Timer & Restart section. If the
power limit condition persists for longer than the Fault Timeout Period set by the timer capacitor, CT, the IIN OC Fault bit
in the STATUS_INPUT (7Ch) register, the INPUT bit in the
STATUS_WORD (79h) register, and the IIN_OC/
PFET_OP_FAULT bit in the DIAGNOSTIC_WORD (E1h)
register will be toggled high and SMBA pin will be asserted
unless this feature is disabled using the ALERT_MASK (D8h)
register.
30115915
FIGURE 3. Latched Fault Restart Control
The LM5066 provides an automatic restart sequence which
consists of the TIMER pin cycling between 3.9V and 1.1V
seven times after the Fault Timeout Period, as shown in Figure 4. The period of each cycle is determined by the 75 µA
charging current, and the 2.5 µA discharge current, and the
value of the capacitor CT. When the TIMER pin reaches 0.3V
during the eighth high-to-low ramp, the 20 µA current source
at the GATE pin turns on Q1. If the fault condition is still
present, the Fault Timeout Period and the restart sequence
repeat. The RETRY pin allows selecting no retries or infinite
retries. Finer control of the retry behavior can be achieved
through the DEVICE_SETUP (D9h) register. Retry counts of
0, 1, 2, 4, 8, 16 or infinite may be selected by setting the appropriate bits in the DEVICE_SETUP (D9h) register.
15
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LM5066
ues may create instability in the current limit control loop. The
current limit threshold pin value may be overridden by setting
appropriate bits in the DEVICE_SETUP register (D9h).
LM5066
30115916
FIGURE 4. Restart Sequence
register and the VIN_OVERVOLTAGE_FAULT bit in the
DIAGNOSTIC_WORD (E1h) register. The SMBA pin will be
pulled low unless this feature is disabled using the
ALERT_MASK (D8h) register.
See the Applications Section for a procedure to calculate the
threshold setting resistor values.
Under-Voltage Lockout (UVLO)
The series pass MOSFET (Q1) is enabled when the input
supply voltage (VIN) is within the operating range defined by
the programmable under-voltage lockout (UVLO) and overvoltage lockout (OVLO) levels. Typically the UVLO level at
VIN is set with a resistor divider (R1-R3) as shown in Figure
5. Refering to the Block Diagram when VIN is below the UVLO
level, the internal 20 µA current source at UVLO is enabled,
the current source at OVLO is off, and Q1 is held off by the
4.2 mA pull-down current at the GATE pin. As VIN is increased, raising the voltage at UVLO above its threshold the
20 µA current source at UVLO is switched off, increasing the
voltage at UVLO, providing hysteresis for this threshold. With
the UVLO/EN pin above its threshold, Q1 is switched on by
the 20 µA current source at the GATE pin if the insertion time
delay has expired.
See the Applications Section for a procedure to calculate the
values of the threshold setting resistors (R1-R3). The minimum possible UVLO level at VIN can be set by connecting the
UVLO/EN pin to VIN. In this case Q1 is enabled after the insertion time when the voltage at VIN reaches the POR threshold. After power up an UVLO condition will cause the INPUT
bit in the STATUS_WORD (79h) register, the
VIN_UV_FAULT bit in the STATUS_INPUT (7Ch) register,
and the VIN_UNDERVOLTAGE_FAULT bit in the
DIAGNOSTIC_WORD (E1h) registers to be toggled high and
SMBA pin will be pulled low unless this feature is disabled
using the ALERT_MASK (D8h) register.
Shutdown Control
The load current can be remotely switched off by taking the
UVLO/EN pin below its threshold with an open collector or
open drain device, as shown in Figure 5. Upon releasing the
UVLO/EN pin the LM5066 switches on the load current with
in-rush current and power limiting.
30115917
FIGURE 5. Shutdown Control
Over-Voltage Lockout (OVLO)
Power Good Pin
The series pass MOSFET (Q1) is enabled when the input
supply voltage (VIN) is within the operating range defined by
the programmable under-voltage lockout (UVLO) and overvoltage lockout (OVLO) levels. If VIN raises the OVLO pin
voltage above its threshold, Q1 is switched off by the 4.2 mA
pull-down current at the GATE pin, denying power to the load.
When the OVLO pin is above its threshold, the internal 21 µA
current source at OVLO is switched on, raising the voltage at
OVLO to provide threshold hysteresis. When VIN is reduced
below the OVLO level Q1 is re-enabled. An OVLO condition
will toggle the VIN_OV_FAULT bit in the STATUS_INPUT
(7Ch) register, the INPUT bit in the STATUS_WORD (79h)
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The Power Good indicator pin (PGD) is connected to the drain
of an internal N-channel MOSFET capable of sustaining 80V
in the off-state, and transients up to 100V. An external pull-up
resistor is required at PGD to an appropriate voltage to indicate the status to downstream circuitry. The off-state voltage
at the PGD pin can be higher or lower than the voltages at
VIN and OUT. PGD is switched high when the voltage at the
FB pin exceeds the PGD threshold voltage. Typically the output voltage threshold is set with a resistor divider from output
to feedback, although the monitored voltage need not be the
output voltage. Any other voltage can be monitored as long
16
Erroneous temperature measurements may result when the
device input voltage is below the minimum operating voltage
(10V), due to VREF dropping out below the nominal voltage
(2.97V). At higher ambient temperatures, this measurement
could read a value higher than the OT_FAULT_LIMIT, and
will trigger a fault, disabling Q1. In this case, the faults should
be removed and the device reset by writing a 0h, followed by
an 80h to the OPERATION (03h) register.
Damaged MOSFET Detection
The LM5066 is able to detect whether the external MOSFET,
Q1, is damaged under certain conditions. If the voltage across
the sense resistor exceeds 4mV while the GATE voltage is
low or the internal logic indicates that the GATE should be
low,
the
EXT_MOSFET_SHORTED
bit
in
the
STATUS_MFR_SPECIFIC (80h) and DIAGNOSTIC_WORD
(E1h) registers will be toggled high and the SMBA pin will be
asserted unless this feature is disabled using the
ALERT_MASK register (D8h). This method effectively determines whether Q1 is shorted because of damage present
between the drain and gate and/or drain and source.
VDD Sub-Regulator
The LM5066 contains an internal linear sub-regulator which
steps down the input voltage to generate a 4.9V rail used for
powering low voltage circuitry. The VDD sub-regulator should
be used as the pull-up supply for the CL, RETRY, ADR2,
ADR1, ADR0 pins if they are to be tied high. It may also be
used as the pull-up supply for the PGD and the SMBus signals
(SDA, SCL, SMBA). The VDD sub-regulator is not designed
to drive high currents and should not be loaded with other
integrated circuits. The VDD pin is current limited to 30mA in
order to protect the LM5066 in the event of a short. The subregulator requires a ceramic bypass capacitance having a
value of 1 µF or greater to be placed as close to the VDD pin
as the PCB layout allows.
Enabling/Disabling and Resetting
The output can be disabled at any time during normal operation by either pulling the UVLO/EN pin to below its threshold
or the OVLO pin above its threshold, causing the GATE voltage to be forced low with a pulldown strength of 4.2mA.
Toggling the UVLO/EN pin will also reset the LM5066 from a
latched-off state due to an over-current or over-power limit
condition which has caused the maximum allowed number of
retries to be exceeded. While the UVLO/EN or OVLO pins can
be used to disable the output they have no effect on the
volatile memory or address location of the LM5066. User
stored values for address, device operation, and warning and
fault levels programmed via the SMBus are preserved while
the LM5066 is powered regardless of the state of the UVLO/
EN and OVLO pins.The output may also be enabled or disabled by writing 80h or 0h to the OPERATION (03h) register.
To re-enable after a fault, the fault condition should be cleared
and the OPERATION (03h) register with 0h and then 80h.
The SMBus address of the LM5066 is captured based on the
states of the ADR0, ADR1, and ADR2 pins (GND, NC, VDD)
during turn on and is latched into a volatile register once VDD
has exceeded its POR threshold of 4.1V. Reassigning or
postponing the address capture is accomplished by holding
the VREF pin to ground. Pulling the VREF pin low will also
reset the logic and erase the volatile memory of the LM5066.
Once released, the VREF pin will charge up to its final value
and the address will be latched into a volatile register once
the voltage at the VREF exceeds 2.55V.
Remote Temperature Sensing
The LM5066 is designed to measure temperature remotely
using an MMBT3904 NPN transistor. The base and collector
of the MMBT3904 should be connected to the DIODE pin and
the emitter to the LM5066 ground. Place the MMBT3904 near
the device that requires temperature sensing. If the temperature of the hot swap pass MOSFET, Q1, is to be measured,
the MMBT3904 should be placed as close to Q1 as the layout
allows. The temperature is measured by means of a change
in the diode voltage in response to a step in current supplied
by the DIODE pin. The DIODE pin sources a constant 9.4 µA
but pulses 250 µA once every millisecond in order to measure
the diode temperature. Care must be taken in the PCB layout
to keep the parasitic resistance between the DIODE pin and
the MMBT3904 low so as not to degrade the measurement.
Additionally, a small 1000 pF bypass capacitor should be
placed in parallel with the MMBT3904 to reduce the effects of
noise. The temperature can be read using the READ_TEMPERATURE_1 PMBus command (8Dh). The default limits of
the LM5066 will cause SMBA pin to be pulled low if the measured temperature exceeds 125°C and will disable Q1 if the
temperature exceeds 150°C. These thresholds can be reprogrammed via the PMBus interface using the OT_WARN_LIMIT (51h) and OT_FAULT_LIMIT (4Fh) commands. If the
temperature measurement and protection capability of the
LM5066 are not used, the DIODE pin should be grounded.
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LM5066
as the voltage at the FB pin does not exceed its maximum
rating. Referring to the Block Diagram, when the voltage at
the FB pin is below its threshold, the 20 µA current source at
FB is disabled. As the output voltage increases, taking FB
above its threshold, the current source is enabled, sourcing
current out of the pin, raising the voltage at FB to provide
threshold hysteresis. The PGD output is forced low when either the UVLO/EN pin is below its threshold or the OVLO pin
is above its threshold. The status of the PGD pin can be read
via the PMBus interface in either the STATUS_WORD (79h)
or DIAGNOSTIC_WORD (E1h) registers.
LM5066
Application Section
30115901
FIGURE 6. Typical Application Circuit
this data sheet, but should be verified experimentally. Review
the resulting insertion time and the restart timing if retry is
enabled.
UVLO, OVLO: Choose option A, B, C, or D from the UVLO,
OVLO section of the Application Information to set the UVLO
and OVLO thresholds and hysteresis. Use the procedure for
the appropriate option to determine the resistor values at the
UVLO/EN and OVLO pins.
Power Good: Choose the appropriate output voltage and
calculate the required resistor divider from the output voltage
to the FB pin. Choose either VDD or OUT to connect a properly sized pull-up resistor for the Power Good output (PGD).
Refer to Programming Guide section: After all hardware
design is complete, refer to the programming guide for a step
by step procedure regarding software.
DESIGN-IN PROCEDURE
Refer to Figure 6 for Typical Application Circuit. The following
is the step-by-step procedure for hardware design of the
LM5066. This procedure refers to section numbers that provide detailed information on the following design steps. The
recommended design-in procedure is as follows:
MOSFET Selection: Determine MOSFET based on breakdown voltage, current and power ratings.
Current Limit, RS: Determine the current limit threshold
(ILIM). This threshold must be higher than the normal maximum load current, allowing for tolerances in the current sense
resistor value and the LM5066 Current Limit threshold voltage. Use equation 1 to determine the value for RS.
Power Limit Threshold: Determine the maximum allowable
power dissipation for the series pass MOSFET (Q1), using the
device’s SOA information. Use equation 2 to determine the
value for RPWR. Note that many MOSFET manufacturers do
not accurately specify the device SOA so it is usually beneficial to choose a conservative value when selecting RPWR.
Turn-on Time and TIMER Capacitor, CT: Determine the value for the timing capacitor at the TIMER pin (CT) using equation 7 and 8. The fault timeout period (tFAULT) MUST be longer
than the circuit’s turn-on time. The turn-on time can be estimated using the equations in the TURN-ON TIME section of
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MOSFET SELECTION
It is recommended that the external MOSFET (Q1) selection
is based on the following criteria:
- The BVDSS rating should be greater than the maximum system voltage (VIN), plus ringing and transients which can occur
at VIN when the circuit card, or adjacent cards, are inserted or
removed.
18
(1)
where ILIM is the desired current limit threshold. If the voltage
across RS reaches VCL, the current limit circuit modulates the
gate of Q1 to regulate the current at ILIM. While the current
limiting circuit is active, the fault timer is active as described
in the Fault Timer & Restart section. For proper operation,
RS must be less than 200 mΩ.
VCL can be set to either 26 mV or 50 mV via hardware and/or
software. This setting defaults to use of CL pin which, when
connected to VDD is 26 mV, or grounded is 50 mV. The value,
when powered, can be set via the PMBus with the
MFR_SPECIFIC_DEVICE_SETUP command, which defaults to the 26 mV setting.
Once the desired setting is known, calculate the shunt based
on that input voltage and maximum current. While the maximum load current in normal operation can be used to determine the required power rating for resistor RS, basing it on the
current limit value provides a more reliable design since the
circuit can operate near the current limit threshold continuously. The resistor’s surge capability must also be considered
since the circuit breaker threshold is 1.94 or 3.87 times the
current limit threshold.
Connections from RS to the LM5066 should be made using
Kelvin techniques. In the suggested layout of Figure 7 the
small pads at the lower corners of the sense resistor connect
only to the sense resistor terminals, and not to the traces carrying the high current. With this technique, only the voltage
across the sense resistor is applied to VIN_K and SENSE,
eliminating the voltage drop across the high current solder
connections.
CURRENT LIMIT (RS)
The LM5066 monitors the current in the external MOSFET
Q1 by measuring the voltage across the sense resistor (RS),
connected from VIN to SENSE. The required resistor value is
calculated from:
30115919
FIGURE 7. Sense Resistor Connections
where PMOSFET(LIM) is the desired power limit threshold for
Q1, and RS is the current sense resistor described in the Current Limit section. For example, if RS is 5 mΩ, VIN = 48V, and
the desired power limit threshold is 50W, RPWR calculates to
24.9 kΩ. If Q1’s power dissipation reaches the threshold Q1’s
gate is modulated to regulate the load current, keeping Q1’s
power from exceeding the threshold. For proper operation of
the power limiting feature, RPWR must be ≤150 kΩ. While the
power limiting circuit is active, the fault timer is active as described in the Fault Timer & Restart section. Typically, power
limit is reached during startup, or if the output voltage falls due
POWER LIMIT THRESHOLD
The LM5066 determines the power dissipation in the external
MOSFET (Q1) by monitoring the drain current (the current in
RS) and the VDS of Q1 (SENSE to OUT pins). The resistor at
the PWR pin (RPWR) sets the maximum power dissipation for
Q1, and is calculated from the following equation:
(2)
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LM5066
- The maximum continuous current rating should be based on
the current limit threshold (e.g., 26 mV/RS for CL = VDD), not
the maximum load current, since the circuit can operate near
the current limit threshold continuously.
- The Pulsed Drain Current spec (IDM) must be greater than
the current threshold for the circuit breaker function
(48/96/193 mV/RS, depending on CL and CB configuration).
- The SOA (Safe Operating Area) chart of the device, and the
thermal properties, should be used to determine the maximum power dissipation threshold set by the RPWR resistor.
The programmed maximum power dissipation should have a
reasonable margin from the maximum power defined by the
MOSFET’s SOA curve. If the device is set to infinitely retry,
the MOSFET will be repeatedly stressed during fault restart
cycles. The MOSFET manufacturer should be consulted for
guidelines.
- RDS(on) should be sufficiently low such that the power dissipation at maximum load current (ILIM2 x RDS(on)) does not raise
its junction temperature above the manufacturer’s recommendation.
- The gate-to-source voltage provided by the LM5066 can be
as high as 16.5V, limited by the internal zener diode from
GATE to OUT. Q1 must be able to tolerate this voltage for its
VGS rating. An additional zener diode can be added from
GATE to OUT to lower this voltage and limit the peak VGS.
The zener diode’s forward current rating must be at least 110
mA to conduct the GATE pull-down current when a circuit
breaker condition is detected.
LM5066
the current limit threshold is less than the current defined by
the power limit threshold at maximum VDS the circuit operates
only at the current limit threshold during turn-on. Referring to
Figure 8A, as the load current reaches ILIM, the gate-to-source
voltage is controlled at VGSL to maintain the current at ILIM. As
the output voltage reaches its final value (VDS ≊ 0V) the drain
current reduces to its normal operating value. The time for the
OUT pin voltage to transition from zero volts to VIN is equal
to:
to a severe overload or short circuit. The programmed maximum power dissipation should have a reasonable margin
from the maximum power defined by the SOA chart, especially if retry is enabled, because the MOSFET will be repeatedly stressed during fault restart cycles. The MOSFET
manufacturer should be consulted for guidelines. If the application does not require use of the power limit function the
PWR pin can be left open. The accuracy of the power limit
function at turn-on may degrade if a very low power dissipation limit is set. The reason for this caution is that the voltage
across the sense resistor, which is monitored and regulated
by the power limit circuit, is lowest at turn-on when the regulated current is at a minimum. The voltage across the sense
resistor during power limit can be expressed as follows:
(4)
where CL is the load capacitance. For example, if VIN = 48V,
CL = 200 µF, and ILIM = 5A, tON calculates to 12 ms. The maximum instantaneous power dissipated in the MOSFET is
12W. This calculation assumes the time from t1 to t2 in Figure
9(a) is small compared to tON, the load does not draw any
current until after the output voltage has reached its final value, and PGD switches high (Figure 8A). The Fault Timeout
Period must be set longer than tON to prevent a fault shutdown
before the turn-on sequence is complete.
If the load draws current during the turn-on sequence (Figure
8B), the turn-on time is longer than the above calculation, and
is approximately equal to:
(3)
where ILIM is the current in RS, and VDS is the voltage across
Q1. For example, if the power limit is set at 75W with RS = 5
mΩ, and VDS = 48V the sense resistor voltage calculates to
7.8 mV, which is comfortably regulated by the LM5066. However, if the power limit is set lower (e.g., 25W), the sense
resistor voltage calculates to 2.6 mV. At this low level noise
and offsets within the LM5066 may degrade the power limit
accuracy. To maintain accuracy, the sense resistor voltage
should not be less than 3 mV.
(5)
TURN-ON TIME
The output turn-on time depends on whether the LM5066 operates in current limit, or in both power limit and current limit,
during turn-on.
A) Turn-on with current limit only: The current limit threshold (ILIM) is determined by the current sense resistor (RS). If
where RL is the load resistance. The Fault Timeout Period
must be set longer than tON to prevent a fault shutdown before
the turn-on sequence is complete.
30115922
30115923
A. No Load Current During Turn-On
B. Load Draws Current During Turn-On
FIGURE 8. Current During Turn-On
B) Turn-On with Power Limit and Current Limit: The maximum allowed power dissipation in Q1 (PMOSFET(LIM)) is defined by the resistor at the PWR pin, and the current sense
resistor RS. See the Power Limit Threshold section. If the current limit threshold (ILIM) is higher than the current defined by
the power limit threshold at maximum VDS (PMOSFET(LIM)/VIN)
the circuit operates initially in the power limit mode when the
VDS of Q1 is high, and then transitions to current limit mode
as the current increases to ILIM and VDS decreases. Assuming
the load (RL) is not connected during turn-on, the time for the
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output voltage to reach its final value is approximately equal
to:
(6)
For example, if VIN = 48V, CL = 200 µF, ILIM = 1A, and PMOSFET
(LIM) = 10W, tON calculates to ≊24 ms, and the initial current
level (IP) is approximately 0.208A. The Fault Timeout Period
must be set longer than tON.
20
LM5066
30115925
FIGURE 9. MOSFET Power Up Waveforms
expires, a restart sequence starts as described below
(Restart Timing). During consecutive cycles of the restart sequence, the fault timeout period is shorter than the initial fault
time out period described above by approximately 8% since
the voltage at the TIMER pin starts ramping up from 0.3V
rather than ground.
Since the LM5066 normally operates in power limit and/or
current limit during a power up sequence, the Fault Timeout
Period MUST be longer than the time required for the output
voltage to reach its final value. See the Turn-On Time section.
C) Restart Timing For the LM5066, after the Fault Timeout
Period described above, CT is discharged by the 2.5 µA current sink to 1.1V. The TIMER pin then cycles through seven
additional charge/discharge cycles between 1.1V and 3.9V as
shown in Figure 4. The restart time ends when the TIMER pin
voltage reaches 0.3V during the final high-to-low ramp. The
restart time, after the Fault Timeout Period, is equal to:
TIMER CAPACITOR, CT
The TIMER pin capacitor (CT) sets the timing for the insertion
time delay, fault timeout period, and the restart timing of the
LM5066.
A) Insertion Delay - Upon applying the system voltage (VIN)
to the circuit, the external MOSFET (Q1) is held off during the
insertion time (t1 in Figure 2) to allow ringing and transients at
VIN to settle. Since each backplane’s response to a circuit
card plug-in is unique, the worst case settling time must be
determined for each application. The insertion time starts
when VIN reaches the POR threshold, at which time the internal 4.8 µA current source charges CT from 0V to 3.9V. The
required capacitor value is calculated from:
(7)
For example, if the desired insertion delay is 250 ms, CT calculates to 0.3 µF. At the end of the insertion delay, CT is
quickly discharged by a 1.5 mA current sink.
B) Fault Timeout Period - During in-rush current limiting or
upon detection of a fault condition where the current limit and/
or power limit circuits regulate the current through Q1, the fault
timer current source (75 µA) is switched on to charge CT. The
Fault Timeout Period is the time required for the TIMER pin
voltage to reach 3.9V, at which time Q1 is switched off. The
required capacitor value for the desired Fault Timeout Period
tFAULT is calculated from:
(9)
= CT x 9.5 x 106
(10)
For example, if CT = 0.8 µF, tRESTART = 7.9 seconds. At the
end of the restart time, Q1 is switched on. If the fault is still
present, the fault timeout and restart sequence repeats. The
on-time duty cycle of Q1 is approximately 0.5% in this mode.
UVLO, OVLO
By programming the UVLO and OVLO thresholds the
LM5066 enables the series pass device (Q1) when the input
supply voltage (VIN) is within the desired operational range. If
VIN is below the UVLO threshold, or above the OVLO threshold, Q1 is switched off, denying power to the load. Hysteresis
is provided for each threshold.
Option A: The configuration shown in Figure 10 requires
three resistors (R1-R3) to set the thresholds.
(8)
For example, if the desired Fault Timeout Period is 15 ms,
CT calculates to 0.3 µF. CT is discharged by the 2.5 µA current
sink at the end of the Fault Timeout Period. After the Fault
Timeout Period, if retry is disabled, the LM5066 latches the
GATE pin low until a power up sequence is initiated by external circuitry. When the Fault Timeout Period of the LM5066
21
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LM5066
30115929
FIGURE 10. UVLO and OVLO Thresholds Set By R1-R3
The procedure to calculate the resistor values is as follows:
- Choose the upper UVLO threshold (VUVH), and the lower
UVLO threshold (VUVL).
- Choose the upper OVLO threshold (VOVH).
- The lower OVLO threshold (VOVL) cannot be chosen in advance in this case, but is determined after the values for R1R3 are determined. If VOVL must be accurately defined in
addition to the other three thresholds, see Option B below.
The resistors are calculated as follows:
(16)
(17)
The lower OVLO threshold calculates to 55.6V, and the OVLO
hysteresis is 4.4V. Note that the OVLO hysteresis is always
slightly greater than the UVLO hysteresis in this configuration.
When the R1-R3 resistor values are known, the threshold
voltages and hysteresis are calculated from the following:
(11)
(18)
(12)
(19)
VUV(HYS) = R1 x 20µA
(13)
The lower OVLO threshold is calculated from:
(20)
(14)
(21)
As an example, assume the application requires the following
thresholds: VUVH = 36V, VUVL = 32V, VOVH = 60V.
VOV(HYS) = (R1 + R2) x 21µA
Option B: If all four thresholds must be accurately defined,
the configuration in Figure 11 can be used.
(15)
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22
LM5066
30115941
FIGURE 11. Programming the Four Thresholds
The four resistor values are calculated as follows: - Choose
the upper and lower UVLO thresholds (VUVH) and (VUVL).
R3 = 190 kΩ, R4 = 8.1 kΩ
When the R1-R4 resistor values are known, the threshold
voltages and hysteresis are calculated from the following:
(22)
(26)
(23)
(27)
- Choose the upper and lower OVLO threshold (VOVH) and
(VOVL).
VUV(HYS) = R1 x 20 µA
(28)
(24)
(29)
(25)
Option C: The minimum UVLO level is obtained by connecting the UVLO/EN pin to VIN as shown in Figure 12. Q1 is
switched on when the VIN voltage reaches the POREN threshold (≊8.6V). The OVLO thresholds are set using R3, R4. Their
values are calculated using the procedure in Option B.
As an example, assume the application requires the following
thresholds: VUVH = 36V, VUVL = 32V, VOVH = 60V, and VOVL =
56V. Therefore VUV(HYS) = 4V, and VOV(HYS) = 4V. The resistor
values are:
R1 = 200 kΩ, R2 = 16.8 kΩ
30115950
FIGURE 12. UVLO = POREN
Option D: The OVLO function can be disabled by grounding
the OVLO pin. The UVLO thresholds are set as described in
Option B or Option C.
23
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LM5066
POWER GOOD PIN
When the voltage at the FB pin increases above its threshold
the internal pulldown acting on the PGD pin is disabled allowing PGD to rise to VPGD through the pull-up resistor, RPG,
as shown in Figure 14. The pull-up voltage (VPGD) can be as
high as 80V, and can be higher or lower than the voltages at
VIN and OUT. VDD is a convenient choice for VPGD as it allows interface to low voltage logic and avoids glitching on
PGD during power-up. If a delay is required at PGD, suggested circuits are shown in Figure 15. In Figure 15A, capacitor
CPG adds delay to the rising edge, but not to the falling edge.
In Figure 15B, the rising edge is delayed by RPG1 + RPG2 and
CPG, while the falling edge is delayed a lesser amount by
RPG2 and CPG. Adding a diode across RPG2 (Figure 15C) allows for equal delays at the two edges, or a short delay at the
rising edge and a long delay at the falling edge.
Setting the output threshold for the PGD pin requires two resistors (R4, R5) as shown in Figure 13. While monitoring the
output voltage is shown in Figure 13, R4 can be connected to
any other voltage which requires monitoring.
The resistor values are calculated as follows:
Choose the upper and lower threshold (VPGDH) and (VPGDL)
at VOUT.
301159a5
FIGURE 13. Programming the PGD Threshold
As an example, assume the application requires the following
thresholds: VPGDH = 40V, and VPGDL = 38V. Therefore VPGD
(HYS) = 2V. The resistor values are:
R4 = 100 kΩ, R5 = 6.55 kΩ
When the R4 and R5 resistor values are known, the threshold
voltages and hysteresis are calculated from the following:
30115951
FIGURE 14. Power Good Output
30115952
FIGURE 15. Adding Delay to the Power Good Output Pin
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24
30115954
FIGURE 16. Output Diode Required for Inductive Loads
cant current flow through the diodes, which can result in
device failure.
- The sense resistor (RS) should be placed close to the
LM5066. A trace should connect the VIN pad and Q1 pad of
the sense resistor to VIN_K and SENSE pins, respectively.
Connect RS using the Kelvin techniques shown in Figure 7.
- The high current path from the board’s input to the load (via
Q1), and the return path, should be parallel and close to each
other to minimize loop inductance.
- The AGND and GND connections should be connected at
the pins of the device.The ground connections for the various
components around the LM5066 should be connected directly to each other, and to the LM5066’s GND and AGND pin
connection, and then connected to the system ground at one
point. Do not connect the various component grounds to each
other through the high current ground line.
- Provide adequate thermal sinking for the series pass device
(Q1) to help reduce stresses during turn-on and turn-off.
- The board’s edge connector can be designed such that the
LM5066 detects via the UVLO/EN pin that the board is being
removed, and responds by turning off the load before the
supply voltage is disconnected. For example, in Figure 17, the
voltage at the UVLO/EN pin goes to ground before VIN is removed from the LM5066 as a result of the shorter edge
connector pin. When the board is inserted into the edge connector, the system voltage is applied to the LM5066’s VIN pin
before the UVLO voltage is taken high, thereby allowing the
LM5066 to turn on the output in a controlled fashion.
PC BOARD GUIDELINES
The following guidelines should be followed when designing
the PC board for the LM5066:
- Place the LM5066 close to the board’s input connector to
minimize trace inductance from the connector to the MOSFET.
- Place a TVS, Z1, directly adjacent to the VIN and GND pins
of the LM5066 to help minimize voltage transients which may
occur on the input supply line. The TVS should be chosen
such that the peak VIN is just lower the TVS reverse-bias voltage. Transients of 20 volts or greater over the nominal input
voltage can easily occur when the load current is shut off. A
small capacitor may be sufficient for low current sense applications (I < 2A). It is recommended to test the VIN input
voltage transient performance of the circuit by current limiting
or shorting the load and measuring the peak input voltage
transient.
- Place a 1 µF ceramic capacitor as close as possible to VREF
pin.
- Place a 1 µF ceramic capacitor as close as possible to VDD
pin.
- Minimize the inductance between the VIN and VIN_K pins.
There are anti-parallel diodes between these pins so any voltage greater than 0.3V in either polarity will cause significant
current flow through the diodes, which can result in device
failure. Do not place any resistors between these two nodes.
- Minimize the impedance between the VIN_K and SENSE
pins. There are anti-parallel diodes between these pins so any
voltage greater than 0.3V in either polarity will cause signifi-
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LM5066
For low current solutions (<2A), a capacitor may be sufficient
to limit the voltage surge, however this comes at the expense
of input surge current on card insertion.
If the load powered by the LM5066 hot swap circuit has inductive characteristics, a Schottky diode is required across
the LM5066’s output, along with some load capacitance. The
capacitance and the diode are necessary to limit the negative
excursion at the OUT pin when the load current is shut off. If
the OUT pin transitions more than 0.3V negative the LM5066
can be permanently damaged. See Figure 16.
SYSTEM CONSIDERATIONS
A) Continued proper operation of the LM5066 hot swap circuit
requires a voltage clamping element present on the supply
side of the connector into which the hot swap circuit is plugged
in. A TVS is ideal, as depicted in Figure 16. The TVS is necessary to absorb the voltage transient generated whenever
the hot swap circuit shuts off the load current. If the TVS is
not present, inductance in the supply lines will generate a
voltage transient at shut-off which can exceed the absolute
maximum rating of the LM5066, resulting in its destruction.
LM5066
30115953
FIGURE 17. Recommended Board Connector Design
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26
The device features an SMBus interface that allows the use
of PMBus commands to set warn levels, error masks, and get
TABLE 1. Supported PMBus Commands
Code
Name
Function
R/W
Number
Default
Of Data
Value
Bytes
01h
OPERATION
Retrieves or stores the operation status.
R/W
1
03h
CLEAR_FAULTS
Clears the status registers and re-arms the Black Box
registers for updating.
Send
Byte
0
80h
19h
CAPABILITY
Retrieves the device capability.
R
1
B0h
43h
VOUT_UV_WARN_LIMIT
Retrieves or stores output under-voltage warn limit
threshold.
R/W
2
0000h
4Fh
OT_FAULT_LIMIT
Retrieves or stores over temperature fault limit threshold.
R/W
2
0960h
(150°C)
51h
OT_WARN_LIMIT
Retrieves or stores over temperature warn limit threshold.
R/W
2
07D0h
(125°C)
57h
VIN_OV_WARN_LIMIT
Retrieves or stores input over-voltage warn limit threshold.
R/W
2
0FFFh
58h
VIN_UV_WARN_LIMIT
Retrieves or stores input under-voltage warn limit
threshold.
R/W
2
0000h
78h
STATUS_BYTE
Retrieves information about the parts operating status.
R
1
49h
79h
STATUS_WORD
Retrieves information about the parts operating status.
R
2
3849h
7Ah
STATUS_VOUT
Retrieves information about output voltage status.
R
1
00h
7Ch
STATUS_INPUT
Retrieves information about input status.
R
1
10h
7Dh
STATUS_TEMPERATURE
Retrieves information about temperature status.
R
1
00h
7Eh
STATUS_CML
Retrieves information about communications status.
R
1
00h
80h
STATUS_MFR_SPECIFIC
Retrieves information about circuit breaker and MOSFET
shorted status.
R
1
10h
88h
READ_VIN
Retrieves input voltage measurement.
R
2
0000h
8Bh
READ_VOUT
Retrieves output voltage measurement.
R
2
0000h
8Dh
READ_TEMPERATURE_1
Retrieves temperature measurement.
R
2
0190h
99h
MFR_ID
Retrieves manufacturer ID in ASCII characters (NSC).
R
3
4Eh
53h
43h
9Ah
MFR_MODEL
Retrieves Part number in ASCII characters. (LM5066\0\0).
R
8
4Ch
4Dh
35h
30h
36h
36h
0h
0h
9Bh
MFR_REVISION
Retrieves part revision letter/number in ASCII (e.g., AA).
R
2
41h
41h
D0h
MFR_SPECIFIC_00
READ_VAUX
Retrieves auxiliary voltage measurement.
R
2
0000h
D1h
MFR_SPECIFIC_01
MFR_READ_IIN
Retrieves input current measurement.
R
2
0000h
D2h
MFR_SPECIFIC_02
MFR_READ_PIN
Retrieves input power measurement.
R
2
0000h
D3h
MFR_SPECIFIC_03
MFR_IIN_OC_WARN_LIMIT
Retrieves or stores input current limit warn threshold.
R/W
2
0FFFh
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LM5066
telemetry on VIN, VOUT, IIN, VAUX, and PIN. The supported PMBus commands are shown in Table 1.
PMBus™ Command Support
LM5066
Number
Default
Of Data
Value
Bytes
Code
Name
Function
R/W
D4h
MFR_SPECIFIC_04
MFR_PIN_OP_WARN_LIMIT
Retrieves or stores input power limit warn threshold.
R/W
2
0FFFh
D5h
MFR_SPECIFIC_05
READ_PIN_PEAK
Retrieves measured peak input power measurement.
R
2
0000h
D6h
MFR_SPECIFIC_06
CLEAR_PIN_PEAK
Resets the contents of the peak input power register to
zero.
Send
Byte
0
D7h
MFR_SPECIFIC_07
GATE_MASK
Allows the user to disable MOSFET gate shutdown for
various fault conditions.
R/W
1
0000h
D8h
MFR_SPECIFIC_08
ALERT_MASK
Retrieves or stores user SMBA fault mask.
R/W
2
0820h
D9h
MFR_SPECIFIC_09
DEVICE_SETUP
Retrieves or stores information about number of retry
attempts.
R/W
1
0000h
DAh
MFR_SPECIFIC_10
BLOCK_READ
Retrieves most recent diagnostic and telemetry
information in a single transaction.
R
12
0190h
0000h
0000h
0000h
0000h
0000h
DBh
MFR_SPECIFIC_11
SAMPLES_FOR_AVG
Exponent value AVGN for number of samples to be
averaged (N = 2AVGN), range = 00h to 0Ch .
R/W
1
00h
DCh
MFR_SPECIFIC_12
READ_AVG_VIN
Retrieves averaged input voltage measurement.
R
2
0000h
DDh
MFR_SPECIFIC_13
READ_AVG_VOUT
Retrieves averaged output voltage measurement.
R
2
0000h
DEh
MFR_SPECIFIC_14
READ_AVG_IIN
Retrieves averaged input current measurement.
R
2
0000h
DFh
MFR_SPECIFIC_15
READ_AVG_PIN
Retrieves averaged input power measurement.
R
2
0000h
E0h
MFR_SPECIFIC_16
BLACK_BOX_READ
Captures diagnostic and telemetry information which are
latched when the first SMBA event after faults are cleared.
R
12
0000h
0000h
0000h
0000h
0000h
0000h
MFR_SPECIFIC_17
Manufacturer-specific parallel of the STATUS_WORD to
DIAGNOSTIC_WORD_READ convey all FAULT/WARN data in a single transaction.
R
2
08E0h
R
12
0000h
0000h
0000h
0000h
0000h
0000h
E1h
E2h
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MFR_SPECIFIC_18
AVG_BLOCK_READ
Retrieves most recent average telemetry and diagnostic
information in a single transaction.
28
OPERATION (01h)
The OPERATION command is a standard PMBus command
that controls the MOSFET switch. This command may be
used to switch the MOSFET ON and OFF under host control.
It is also used to re-enable the MOSFET after a fault triggered
shutdown. Writing an OFF command, followed by an ON
command, will clear all faults and re-enable the device. Writing only an ON after a fault-triggered shutdown will not clear
the fault registers or re-enable the device. The OPERATION
command is issued with the write byte protocol.
Meaning
Default
80h
Switch ON
80h
00h
Switch OFF
n/a
Meaning
Default
1h – 0FFFh
VOUT Undervoltage Warning
detection
threshold
0000h (disabled)
0000h
VOUT Undervoltage Warning
disabled
n/a
OT_FAULT_LIMIT (4Fh)
The OT_FAULT_LIMIT command is a standard PMBus command that allows configuring or reading the threshold for the
overtemperature fault detection. Reading and writing to this
register should use the coefficients shown in the Telemetry
and Warning Conversion Coefficients Table. Accesses to this
command should use the PMBus read or write word protocol.
If the measured temperature exceeds this value, an overtemperature fault is triggered and the MOSFET is switched off,
OT FAULT flags set, and the SMBA signal asserted. After the
measured temperature falls below the value in this register,
the MOSFET may be switched back on with the OPERATION
command. A single temperature measurement is an average
of 16 round-robin cycles; therefore, the minimum temperature
fault detection time is 16 ms.
TABLE 2. Recognized OPERATION Command Values
Value
Value
CLEAR FAULTS (03h)
The CLEAR_FAULTS command is a standard PMBus command that resets all stored warning and fault flags and the
SMBA signal. If a fault or warning condition still exists when
the CLEAR_FAULTS command is issued, the SMBA signal
may not clear or will re-assert almost immediately. Issuing a
CLEAR_FAULTS command will not cause the MOSFET to
switch back on in the event of a fault turnoff - that must be
done by issuing an OPERATION command after the fault
condition is cleared. This command uses the PMBus send
byte protocol.
TABLE 5. OT_FAULT_LIMIT Register
CAPABILITY (19h)
The CAPABILITY command is a standard PMBus command
that returns information about the PMBus functions supported
by the LM5066. This command is read with the PMBus read
byte protocol.
Value
Meaning
Default
0h – 0FFEh
Overtemperature
Fault threshold
value
0960h (150°C)
0FFFh
Overtemperature
Fault detection
disabled
n/a
TABLE 3. CAPABILITY Register
Value
Meaning
Default
B0h
Supports Packet
Error Check,
400Kbits/sec,
Supports SMBus
Alert
B0h
OT_WARN_LIMIT (51h)
The OT_WARN_LIMIT command is a standard PMBus command that allows configuring or reading the threshold for the
overtemperature warning detection. Reading and writing to
this register should use the coefficients shown in the Telemetry and Warning Conversion Coefficients Table. Accesses to
this command should use the PMBus read or write word protocol. If the measured temperature exceeds this value, an
Overtemperature warning is triggered and the OT WARN
flags set in the respective registers and the SMBA signal asserted. A single temperature measurement is an average of
16 round-robin cycles; therefore, the minimum temperature
warn detection time is 16 ms.
VOUT_UV_WARN_LIMIT (58h)
The VOUT_UV_WARN_LIMIT command is a standard PMBus command that allows configuring or reading the threshold
for the VOUT Under-voltage Warning detection. Reading and
writing to this register should use the coefficients shown in the
Telemetry and Warning Conversion Coefficients Table. Accesses to this command should use the PMBus read or write
word protocol. If the measured value of VOUT falls below the
value in this register, VOUT UV Warn flags are set and the
SMBA signal is asserted.
TABLE 6. OT_WARN_LIMIT Register
29
Value
Meaning
Default
0h – 0FFEh
Overtemperature
Warn Threshold
Value
07D0h (125°C)
0FFFh
Overtemperature
Warn detection
disabled
n/a
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LM5066
TABLE 4. VOUT_UV_WARN_LIMIT Register
Standard PMBus Commands
LM5066
to this register should use the coefficients shown in the
Telemetry and Warning Conversion Coefficients Table. Accesses to this command should use the PMBus read or write
word protocol. If the measured value of VIN falls below the
value in this register, VIN UV Warn flags are set in the respective register, and the SMBA signal is asserted.
VIN_OV_WARN_LIMIT (57h)
The VIN_OV_WARN_LIMIT command is a standard PMBus
command that allows configuring or reading the threshold for
the VIN over-voltage warning detection. Reading and writing
to this register should use the coefficients shown in the
Telemetry and Warning Conversion Coefficients Table. Accesses to this command should use the PMBus read or write
word protocol. If the measured value of VIN rises above the
value in this register, VIN OV Warn flags are set in the respective registers and the SMBA signal is asserted.
TABLE 8. VIN_UV_WARN_LIMIT Register
Value
Meaning
1h – 0FFFh
VIN Under-voltage 0000h (disabled)
Warning detection
threshold
0000h
VIN Under-voltage n/a
Warning disabled
TABLE 7. VIN_OV_WARN_LIMIT Register
Value
Meaning
0h – 0FFEh
VIN Over-voltage 0FFFh (disabled)
Warning detection
threshold
Default
0FFFh
VIN Over-voltage
Warning disabled
Default
STATUS_BYTE (78h)
The STATUS BYTE is a standard PMBus command that returns the value of a number of flags indicating the state of the
LM5066. Accesses to this command should use the PMBus
read byte protocol. To clear bits in this register, the underlying
fault should be removed on the system and a
CLEAR_FAULTS command issued.
n/a
VIN_UV_WARN_LIMIT (58h)
The VIN_UV_WARN_LIMIT command is a standard PMBus
command that allows configuring or reading the threshold for
the VIN under-voltage warning detection. Reading and writing
TABLE 9. STATUS_BYTE Definitions
Bit
NAME
Meaning
Default
7
BUSY
Not Supported, always 0
0
6
OFF
This bit is asserted if the MOSFET is not switched
on for any reason.
1
5
VOUT OV
Not Supported, always 0
0
4
IOUT OC
Not Supported, always 0
0
3
VIN UV Fault
A VIN Under-voltage Fault has occurred
1
2
TEMPERATURE
A Temperature Fault or Warning has occurred
0
1
CML
A Communication Fault has occurred
0
0
None of the Above
A fault or warning not listed in bits [7:1] has occurred
1
the underlying fault should be removed and a CLEAR
_FAULTS command issued. The INPUT and VIN UV flags will
default to 1 on startup, however, they will be cleared to 0 after
the first time the input voltage exceeds the resistor-programmed UVLO threshold.
STATUS_WORD (79h)
The STATUS_WORD command is a standard PMBus command that returns the value of a number of flags indicating the
state of the LM5066. Accesses to this command should use
the PMBus read word protocol. To clear bits in this register,
TABLE 10. STATUS_WORD Definitions
Bit
NAME
Meaning
Default
15
VOUT
An output voltage fault or warning has occurred
0
14
IOUT/POUT
Not Supported, always 0
0
13
INPUT
An input voltage or current fault has occurred
1
12
MFR
A Manufacturer Specific Fault or Warning has occurred
1
11
POWER GOOD
The Power Good signal has been negated
1
10
FANS
Not Supported, always 0
0
9
OTHER
Not Supported, always 0
0
8
UNKNOWN
Not Supported, always 0
0
7
BUSY
Not Supported, always 0
0
6
OFF
This bit is asserted if the MOSFET is not switched on
for any reason.
1
5
VOUT OV
Not Supported, always 0
0
4
IOUT OC
Not Supported, always 0
0
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30
NAME
Meaning
Default
3
VIN UV
A VIN Under-voltage Fault has occurred
1
2
TEMPERATURE
A Temperature Fault or Warning has occurred
0
1
CML
A Communication Fault has occurred
0
0
None of the Above
A fault or warning not listed in bits [7:1] has occurred
1
Accesses to this command should use the PMBus read byte
protocol. To clear bits in this register, the underlying fault
should be cleared and a CLEAR_FAULTS command issued.
STATUS_VOUT (7Ah)
The STATUS_VOUT command is a standard PMBus command that returns the value of the VOUT UV Warn flag.
TABLE 11. STATUS_VOUT Definitions
Bit
NAME
Meaning
Default
7
VOUT OV Fault
Not Supported, always 0
0
6
VOUT OV Warn
Not Supported, always 0
0
5
VOUT UV Warn
A VOUT Under-voltage Warning has occurred
0
4
VOUT UV Fault
Not Supported, always 0
0
3
VOUT Max
Not Supported, always 0
0
2
TON Max Fault
Not Supported, always 0
0
1
TOFF Max Fault
Not Supported, always 0
0
0
VOUT Tracking Error
Not Supported, always 0
0
register, the underlying fault should be cleared and a
CLEAR_FAULTS command issued. The VIN UV Warn flag
will default to 1 on startup, however, it will be cleared to 0 after
the first time the input voltage increases above the resistorprogrammed UVLO threshold.
STATUS_INPUT (7Ch)
The STATUS_INPUT command is a standard PMBus command that returns the value of a number of flags related to
input voltage, current, and power. Accesses to this command
should use the PMBus read byte protocol. To clear bits in this
TABLE 12. STATUS_INPUT Definitions
Bit
NAME
Meaning
Default
7
VIN OV Fault
A VIN Over-voltage Fault has occurred
0
6
VIN OV Warn
A VIN Over-voltage Warning has occurred
0
5
VIN UV Warn
A VIN Under-voltage Warning has occurred
1
4
VIN UV Fault
A VIN Under-voltage Fault has occurred
0
3
Insufficient Voltage
Not Supported, always 0
0
2
IIN OC Fault
An IIN Over-current Fault has occurred
0
1
IIN OC Warn
An IIN Over-current Warning has occurred
0
0
PIN OP Warn
A PIN Over-power Warning has occurred
0
mand should use the PMBus read byte protocol. To clear bits
in this register, the underlying fault should be cleared and a
CLEAR_FAULTS command issued.
STATUS_TEMPERATURE (7dh)
The STATUS_TEMPERATURE is a standard PMBus command that returns the value of the of a number of flags related
to the temperature telemetry value. Accesses to this com-
TABLE 13. STATUS_TEMPERATURE Definitions
Bit
NAME
Meaning
Default
7
Overtemp Fault
An Overtemperature Fault has occurred
0
6
Overtemp Warn
An Overtemperature Warning has occurred
0
5
Undertemp Warn
Not Supported, always 0
0
4
Undertemp Fault
Not Supported, always 0
0
3
reserved
Not Supported, always 0
0
2
reserved
Not Supported, always 0
0
1
reserved
Not Supported, always 0
0
0
reserved
Not Supported, always 0
0
31
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LM5066
Bit
LM5066
faults. Accesses to this command should use the PMBus read
byte protocol. To clear bits in this register, a CLEAR_FAULTS
command should be issued.
STATUS_CML (7Eh)
The STATUS_CML is a standard PMBus command that returns the value of a number of flags related to communication
TABLE 14. STATUS_CML Definitions
Bit
NAME
Default
7
Invalid or unsupported command received
0
6
Invalid or unsupported data received
0
5
Packet Error Check failed
0
4
Not supported, always 0
0
3
Not supported, always 0
0
2
Not supported, always 0
0
1
Miscellaneous communications fault has occurred
0
0
Not supported, always 0
0
TABLE 17. READ_VOUT Register
STATUS_MFR_SPECIFIC (80h)
The STATUS_MFR_SPECIFIC command is a standard PMBus command that contains manufacturer specific status information. Accesses to this command should use the
PMBus read byte protocol. To clear bits in this register, the
underlying fault should be removed and a CLEAR_FAULTS
command should be issued.
Meaning
Default
7
Circuit breaker fault
0
6
Ext. MOSFET shorted fault
0
5
Not Supported, Always 0
0
4
Defaults loaded
1
3
Not supported: Always 0
0
2
Not supported: Always 0
0
1
Not supported: Always 0
0
0
Not supported: Always 0
0
Meaning
Default
0h – 0FFFh
Measured value
for VOUT
0000h
READ_TEMPERATURE_1 (8Dh)
The READ_TEMPERATURE_1 command is a standard PMBus command that returns the signed value of the temperature measured by the external temperature sense diode.
Reading this register should use the coefficients shown in the
Telemetry and Warning Conversion Coefficients Table. Accesses to this command should use the PMBus read word
protocol. This value is also used internally for the Over Temperature Fault and Warning detection. This data has a range
of -256°C to + 255°C after the coefficients are applied.
TABLE 15. STATUS_MFR_SPECIFIC Definitions
Bit
Value
TABLE 18. READ_TEMPERATURE_1 Register
READ_VIN (88h)
The READ_VIN command is a standard PMBus command
that returns the 12-bit measured value of the input voltage.
Reading this register should use the coefficients shown in the
Telemetry and Warning Conversion Coefficients Table. Accesses to this command should use the PMBus read word
protocol. This value is also used internally for the VIN Over
and Under Voltage Warning detection.
Value
Meaning
Default
0h – 0FFFh
Measured value
for
TEMPERATURE
0000h
MFR_ID (99h)
The MFR_ID command is a standard PMBus command that
returns the identification of the manufacturer. To read the
MFR_ID, use the PMBus block read protocol.
TABLE 19. MFR_ID Register
TABLE 16. READ_VIN Register
Byte
Name
0
Number of bytes
Value
03h
4Eh ‘N’
Value
Meaning
Default
1
MFR ID-1
0h – 0FFFh
Measured value
for VIN
0000h
2
MFR ID-2
53h ‘S’
3
MFR ID-3
43h ‘C’
READ_VOUT (8Bh)
The READ_VOUT command is a standard PMBus command
that returns the 12-bit measured value of the output voltage.
Reading this register should use the coefficients shown in the
Telemetry and Warning Conversion Coefficients Table. Accesses to this command should use the PMBus read word
protocol. This value is also used internally for the VOUT Under Voltage Warning detection.
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MFR_MODEL (9Ah)
The MFR_MODEL command is a standard PMBus command
that returns the part number of the chip. To read the
MFR_MODEL, use the PMBus block read protocol.
32
Name
0
Number of bytes
08h
1
MFR ID-1
4Ch ‘L’
2
MFR ID-2
4Dh ‘M’
3
MFR ID-3
35h ‘5’
4
MFR ID-4
30h ‘0’
5
MFR ID-5
36h ‘6’
6
MFR ID-6
36h ‘6’
7
MFR ID-7
00h
8
Manufacturer Specific PMBus™
Commands
Value
MFR ID-8
MFR_SPECIFIC_00: READ_VAUX (D0h)
The READ_VAUX command will report the 12-bit ADC measured auxiliary voltage. Voltages greater than or equal to
2.97V to ground will be reported at plus full scale (0FFFh).
Voltages less than or equal to 0V referenced to ground will be
reported as 0 (0000h). To read data from the READ_VAUX
command, use the PMBus Read Word protocol.
TABLE 22. READ_VAUX Register
00h
MFR_REVISION (9Bh)
The MFR_REVISION command is a standard PMBus command that returns the revision level of the part. To read the
MFR_REVISION, use the PMBus block read protocol.
Name
Value
0
Number of bytes
02h
1
MFR ID-1
41h ‘A’
2
MFR ID-2
41h ‘A’
Meaning
Default
0h – 0FFFh
Measured value
for VAUX input
0000h
MFR_SPECIFIC_01: MFR_READ_IIN (D1h)
The MFR_READ_IIN command will report the 12-bit ADC
measured current sense voltage. To read data from the
MFR_READ_IIN command, use the PMBus Read Word protocol. Reading this register should use the coefficients shown
in the Telemetry and Warning Conversion Coefficients Table.
Please see the section on coefficient calculations to calculate
the values to use.
TABLE 21. MFR_REVISION Register
Byte
Value
TABLE 23. MFR_READ_IIN Register
Value
Meaning
Default
0h – 0FFFh
Measured value
for input current
sense voltage
0000h
MFR_SPECIFIC_02: MFR_READ_PIN (D2h)
The MFR_READ_PIN command will report the upper 12 bits
of the VIN x IIN product as measured by the 12-bit ADC. To
read data from the MFR_READ_PIN command, use the PMBus Read Word protocol. Reading this register should use the
coefficients shown in the Telemetry and Warning Conversion
Coefficients Table. Please see the section on coefficient calculations to calculate the values to use.
TABLE 24. MFR_READ_PIN Register
Value
Meaning
Default
0h – 0FFFh
Value for input
current x input
voltage
0000h
MFR_SPECIFIC_03: MFR_IN_OC_WARN_LIMIT (D3h)
The MFR_IIN_OC_WARN_LIMIT PMBus command sets the
input over-current warning threshold. In the event that the input current rises above the value set in this register, the IIN
Over-current flags are set in the respective registers and the
SMBA is asserted. To access the MFR_IIN_OC_WARN_LIMIT register, use the PMBus Read/Write Word protocol. Reading/writing to this register should use the coefficients shown
in the Telemetry and Warning Conversion Coefficients Table.
33
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LM5066
TABLE 20. MFR_MODEL Register
Byte
LM5066
TABLE 25. MFR_IIN_OC_WARN_LIMIT Register
Value
Meaning
Default
0h – 0FFEh
Value for input
over-current warn
limit
0FFFh
0FFFh
Input over-current n/a
warning disabled
MFR_SPECIFIC_07: GATE_MASK (D7h)
The GATE_MASK register allows the hardware to prevent
fault conditions from switching off the MOSFET. When the bit
is high, the corresponding FAULT has no control over the
MOSFET gate. All status registers will still be updated (STATUS, DIAGNOSTIC) and an SMBA will still be asserted. This
register is accessed with the PMBus Read / Write Byte protocol.
Warning: Inhibiting the MOSFET switch off in response to over-current or circuit breaker fault conditions will likely result in
the destruction of the MOSFET! This functionality should
be used with great care and supervision!
MFR_SPECIFIC_04: MFR_PIN_OP_WARN_LIMIT (D4h)
The MFR_PIN_OP_WARN_LIMIT PMBus command sets the
input over-power warning threshold. In the event that the input
power rises above the value set in this register, the PIN Overpower flags are set in the respective registers and the SMBA is asserted. To access the MFR_PIN_OP_WARN_LIMIT
register, use the PMBus Read/Write Word protocol. Reading/
writing to this register should use the coefficients shown in the
Telemetry and Warning Conversion Coefficients Table.
TABLE 28. MFR_SPECIFIC_07 GATE MASK Definitions
TABLE 26. MFR_PIN_OPWARN_LIMIT Register
Bit
NAME
Default
7
Not used, always 0
0
6
Not used, always 0
0
5
VIN UV FAULT
0
4
VIN OV FAULT
0
Value
Meaning
Default
3
IIN/PFET FAULT
0
0h – 0FFEh
Value for input
over power warn
limit
0FFFh
2
OVERTEMP FAULT
0
1
Not used, always 0
0
0
0
Input over power
warning disabled
n/a
CIRCUIT BREAKER
FAULT
0FFFh
The IIN/PFET Fault refers to the input current fault and the
MOSFET power dissipation fault. There is no input power fault
detection; only input power warning detection.
MFR_SPECIFIC_05: READ_PIN_PEAK (D5h)
The READ_PIN_PEAK command will report the maximum
input power measured since a Power On reset or the last
CLEAR_PIN_PEAK
command.
To
access
the
READ_PIN_PEAK command, use the PMBus Read Word
protocol. Use the coefficients shown in the Telemetry and
Warning Coefficients Table.
MFR_SPECIFIC_08: ALERT_MASK (D8h)
The ALERT_MASK command is used to mask the SMBA
when a specific fault or warning has occurred. Each bit corresponds to one of the 14 different analog and digital faults or
warnings that would normally result in an SMBA being asserted. When the corresponding bit is high, that condition will
not cause the SMBA to be asserted. If that condition occurs,
the registers where that condition is captured will still be updated (STATUS registers, DIAGNOSTIC_WORD) and the
external MOSFET gate control will still be active
(VIN_OV_FAULT, VIN_UV_FAULT, IIN/PFET_FAULT,
CB_FAULT, OT_FAULT). This register is accessed with the
PMBus Read / Write Word protocol. The VIN UNDERVOLTAGE FAULT flag will default to 1 on startup, however, it will
be cleared to 0 after the first time the input voltage increases
above the resistor-programmed UVLO threshold.
TABLE 27. READ_PIN_PEAK Register
Value
Meaning
0h – 0FFEh
Maximum Value
0h
for input current x
input voltage since
reset or last clear
Default
MFR_SPECIFIC_06: CLEAR_PIN_PEAK (D6h)
The CLEAR_PIN_PEAK command will clear the PIN PEAK
register. This command uses the PMBus Send Byte protocol.
TABLE 29. ALERT_MASK Definitions
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BIT
NAME
DEFAULT
15
VOUT UNDERVOLTAGE WARN
0
14
IIN LIMIT Warn
0
13
VIN UNDERVOLTAGE WARN
0
12
VIN OVERVOLTAGE WARN
0
11
POWER GOOD
1
10
OVERTEMP WARN
0
9
Not Used
0
8
OVERPOWER LIMIT WARN
0
7
Not Used
0
6
EXT_MOSFET_SHORTED
0
34
NAME
DEFAULT
5
VIN UNDERVOLTAGE FAULT
1
4
VIN OVERVOLTAGE FAULT
0
3
IIN/PFET FAULT
0
2
OVERTEMPERATURE FAULT
0
1
CML FAULT (Communications Fault)
0
0
CIRCUIT BREAKER FAULT
0
LM5066
BIT
terface is idle. BLOCK_READ also guarantees that the VIN,
VOUT, IIN and PIN measurements are all time-aligned. If
separate commands are used, individual samples may not be
time-aligned, because of the delay necessary for the communication protocol.
The Block Read command is read via the PMBus block read
protocol.
MFR_SPECIFIC_09: DEVICE_SETUP (D9h)
The DEVICE_SETUP command may be used to override pin
settings to define operation of the LM5066 under host control.
This command is accessed with the PMBus read / write byte
protocol.
TABLE 30. DEVICE_SETUP Byte Format
Bit
7:5
Name
Retry setting
TABLE 31. BLOCK_READ Register Format
Meaning
111 = Unlimited retries
110 = Retry 16 times
101 = Retry 8 times
100 = Retry 4 times
011 = Retry 2 times
010 = Retry 1 time
001 = No retries
Byte Count (always 12)
(1 byte)
DIAGNOSTIC_WORD
(1 Word)
IIN_BLOCK
(1 Word)
VOUT_BLOCK
(1 Word)
VIN_BLOCK
(1 Word)
PIN_BLOCK
(1 Word)
TEMP_BLOCK
(1 Word)
000 = Pin configured retries
4
Current limit setting
3
CB/CL Ratio
2
Current Limit
Configuration
MFR_SPECIFIC_11: SAMPLES_FOR_AVG (DBh)
The SAMPLES_FOR_AVG command is a manufacturer specific command for setting the number of samples used in
computing the average values for IIN, VIN, VOUT, PIN. The
decimal equivalent of the AVGN nibble is the power of 2 samples, (e.g. AVGN=12 equates to N=4096 samples used in
computing the average). The LM5066 supports average numbers of 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096.
The SAMPLES_FOR_AVG number applies to average values of IIN, VIN, VOUT, PIN simultaneously. The LM5066 uses
simple averaging. This is accomplished by summing consecutive results up to the number programmed, then dividing by
the number of samples. Averaging is calculated according to
the following sequence:
0 = High setting (50mV)
1 = Low setting (26mV)
0 = Low setting (1.9x)
1 = High setting (3.9x)
1
Unused
0
Unused
0 = Use pin settings
1 = Use SMBus settings
In order to configure the Current Limit Setting via this register,
it is necessary to set the Current Limit Configuration bit (2) to
1 to enable the register to control the current limit function and
the Current Limit Setting bit (4) to select the desired setting.
If the Current Limit Configuration bit is not set, the pin setting
will be used. The Circuit Breaker to Current Limit ratio value
is set by the CB / CL Ratio bit (3). Note that if the Current Limit
Configuration is changed, the samples for the telemetry averaging function will not be reset. It is recommeded to allow
a full averaging update period with the new Current Limit
Configuration before processing the averaged data.
Note that the Current Limit Configuration affects the coefficients used for the Current and Power measurements and
warning registers.
Y = (X(N) + X(N-1) + ... + X(0)) / N
When the averaging has reached the end of a sequence (for
example, 4096 samples are averaged), then a whole new sequence begins that will require the same number of samples
(in this example, 4096) to be taken before the new average is
ready.
TABLE 32. SAMPLES_FOR_AVG Register
MFR_SPECIFIC_10: BLOCK_READ (DAh)
The
BLOCK_READ
command
concatenates
the
DIAGNOSTIC_WORD with input and output telemetry information (IIN, VOUT, VIN, PIN) as well as TEMPERATURE to
capture all of the operating information of the LM5066 in a
single SMBus transaction. The block is 12 bytes long with
telemetry information being sent out in the same manner as
if an individual READ_XXX command had been issued
(shown below). The contents of the block read register are
updated every clock cycle (85ns) as long as the SMBus in-
35
AVGN
N = 2AVGN
Averaging/Register
Update Period (ms)
0000
1
1
0001
2
2
0010
4
4
0011
8
8
0100
16
16
0101
32
32
0110
64
64
0111
128
128
1000
256
256
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LM5066
AVGN
N = 2AVGN
Averaging/Register
Update Period (ms)
1001
512
512
1010
1024
1024
1011
2048
2048
1100
4096
4096
MFR_SPECIFIC_14: READ_AVG_IIN (DEh)
The READ_AVG_IIN command will report the 12-bit ADC
measured current sense average voltage. The returned value
will be the default value (0000h) or previous data when the
average data is not ready. This data is read with the PMBus
Read Word protocol. This register should use the coefficients
shown in the Telemetry and Warning Conversion Coefficients
Table.
Note that a change in the SAMPLES_FOR_AVG register will
not be reflected in the average telemetry measurements until
the present averaging interval has completed. The default
setting for AVGN is 0000, therefore, the average telemetry will
mirror the instantaneous telemetry until a value higher than
zero is programmed.
The SAMPLES_FOR_AVG register is accessed via the PMBus read / write byte protocol.
TABLE 36. READ_AVG_IIN Register
Value
Meaning
Default
0h – 0FFFh
Average of
measured values
for current sense
voltage
0000h
TABLE 33. SAMPLES_FOR_AVG Register
Value
Meaning
Default
0h – 0Ch
Exponent (AVGN) 00h
for number of
samples to
average over
MFR_SPECIFIC_15: READ_AVG_PIN
The READ_AVG_PIN command will report the upper 12-bits
of the average VIN x IIN product as measured by the 12-bit
ADC. You will read the default value (0000h) or previous data
when the average data is not ready. This data is read with the
PMBus Read Word protocol. This register should use the coefficients shown in the Telemetry and Warning Conversion
Coefficients Table.
MFR_SPECIFIC_12: READ_AVG_VIN (DCh)
The READ_AVG_VIN command will report the 12-bit ADC
measured input average voltage. If the data is not ready, the
returned value will be the previous averaged data. However,
if there is no previously averaged data, the default value
(0000h) will be returned. This data is read with the PMBus
Read Word protocol. This register should use the coefficients
shown in the Telemetry and Warning Conversion Coefficients
Table.
TABLE 37. READ_AVG_PIN Register
TABLE 34. READ_AVG_VIN Register
Value
Meaning
Default
0h – 0FFFh
Average of
measured values
for input voltage
0000h
TABLE 35. READ_AVG_VOUT Register
Meaning
Default
0h – 0FFFh
Average of
measured values
for output voltage
0000h
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Meaning
0h – 0FFFh
Average of
0000h
measured value
for input voltage x
input current sense
voltage
Default
MFR_SPECIFIC_16: BLACK_BOX_READ (E0h)
The BLACK BOX READ command retrieves the BLOCK
READ data which was latched in at the first assertion of SMBA by the LM5066. It is re-armed with the CLEAR_FAULTS
command. It is the same format as the BLOCK_READ registers, the only difference being that its contents are updated
with the SMBA edge rather than the internal clock edge. This
command is read with the PMBus Block Read protocol.
MFR_SPECIFIC_13: READ_AVG_VOUT (DDh)
The READ_AVG_VOUT command will report the 12-bit ADC
measured current sense average voltage. The returned value
will be the default value (0000h) or previous data when the
average data is not ready. This data is read with the PMBus
Read Word protocol. This register should use the coefficients
shown in the Telemetry and Warning Conversion Coefficients
Table.
Value
Value
36
TABLE 38. DIAGNOSTIC_WORD Format
Bit
Meaning
Default
15
VOUT_UNDERVOLTAGE_WARN
0
14
IIN_OP_WARN
0
13
VIN_UNDERVOLTAGE_WARN
0
12
VIN_OVERVOLTAGE_WARN
0
11
POWER GOOD
1
10
OVER_TEMPERATURE_WARN
0
9
TIMER_LATCHED_OFF
0
8
EXT_MOSFET_SHORTED
0
7
CONFIG_PRESET
1
6
DEVICE_OFF
1
5
VIN_UNDERVOLTAGE_FAULT
1
4
VIN_OVERVOLTAGE_FAULT
0
3
IIN_OC/PFET_OP_FAULT
0
2
OVER_TEMPERATURE_FAULT
0
1
CML_FAULT
0
0
CIRCUIT_BREAKER_FAULT
0
TABLE 39. AVG_BLOCK_READ Register Format
MFR_SPECIFIC_18: AVG_BLOCK_READ (E2h)
The AVG_BLOCK_READ command concatenates the
DIAGNOSTIC_WORD with input and output average telemetry information (IIN, VOUT, VIN, PIN) as well as temperature
to capture all of the operating information of the part in a single
PMBus transaction. The block is 12 bytes long with telemetry
information being sent out in the same manner as if an individual READ_AVG_XXX command had been issued (shown
below). AVG_BLOCK_READ also guarantees that the VIN,
VOUT, and IIN measurements are all time-aligned whereas
there is a chance they may not be if read with individual PMBus commands. To read data from the AVG_BLOCK_READ
command, use the SMBus Block Read protocol.
37
Byte Count
(always 12)
(1 byte)
DIAGNOSTIC_W
ORD
(1 word)
AVG_IIN
(1 word)
AVG_VOUT
(1 word)
AVG_VIN
(1 word)
AVG_PIN
(1 word)
TEMPERATURE
(1 word)
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LM5066
DIAGNOSTIC_WORD
register.
The
READ_DIAGNOSTIC_WORD command should be read with
the
PMBus
Read
Word
protocol.
The
READ_DIAGNOSTIC_WORD is also returned in the
BLOCK_READ,
BLACK_BOX_READ,
and
AVG_BLOCK_READ operations.
MFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h)
The READ_DIAGNOSTIC_WORD PMBus command will report all of the LM5066 faults and warnings in a single read
operation. The standard response to the assertion of the SMBA signal of issuing multiple read requests to various status
registers can be replaced by a single word read to the
LM5066
301159a2
FIGURE 18. Command/Register and Alert Flow Diagram
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38
All measured telemetry data and user programmed warning
thresholds are communicated in 12-bit two’s compliment binary numbers read/written in 2 byte increments conforming to
the Direct format as described in section 8.3.3 of the PMBus
Power System Management Protocol Specification 1.1 (Part
TABLE 40. Telemetry and Warning Word Format
Byte
B7
B6
B5
B4
B3
B2
B1
B0
1
Bit_7
Bit_6
Bit_5
Bit_4
Bit_3
Bit_2
Bit_1
Bit_0
2
0
0
0
0
Bit_11
Bit_10
Bit_9
Bit_8
Conversion from direct format to real-world dimensions of
current, voltage, power, and temperature is accomplished by
determining appropriate coefficients as described in section
7.2.1 of the PMBus Power System Management Protocol
Specification 1.1 (Part II). According to this specification, the
host system converts the values received into a reading of
volts, amperes, watts, or other units using the following relationship:
Where:
X: the calculated "real-world" value (volts, amps, watt, etc.)
m: the slope coefficient
Y: a two byte two's complement integer received from device
b: the offset, a two byte, two's complement integer
R: the exponent, a one byte two's complement integer
R is only necessary in systems where m is required to be an
integer (for example, where m may be stored in a register in
an integrated circuit). In those cases, R only needs to be large
enough to yield the desired accuracy.
TABLE 41. Telemetry and Warning Conversion Coefficients
Commands
Condition
Format
Number of
Data Bytes
m
b
R
Units
READ_VIN, READ_AVG_VIN
VIN_OV_WARN_LIMIT
VIN_UV_WARN_LIMIT
DIRECT
2
4587
-1200
-2
V
READ_VOUT, READ_AVG_VOUT
VOUT_UV_WARN_LIMIT
DIRECT
2
4587
-2400
-2
V
DIRECT
2
13793
0
-1
V
*READ_IIN, READ_AVG_IIN
MFR_IIN_OC_WARN_LIMIT
READ_VAUX
CL = VDD
DIRECT
2
10753
-1200
-2
A
*READ_IN, READ_AVG_IN
MFR_IIN_OC_WARN_LIMIT
CL = GND
DIRECT
2
5405
-600
-2
A
*READ_PIN, READ_AVG_PIN,
READ_PIN_PEAK
MFR_PIN_OP_WARN_LIMIT
CL = VDD
DIRECT
2
1204
-6000
-3
W
*READ_PIN, READ_AVG_PIN,
READ_PIN_PEAK
MFR_PIN_OP_WARN_LIMIT
CL = GND
DIRECT
2
605
-8000
-3
W
DIRECT
2
16000
0
-3
°C
READ_TEMPERATURE_1
OT_WARN_LIMIT
OT_FAULT_LIMIT
* The coefficients relating to current/power measurements and warning thresholds shown in Table 41 are normalized to a sense resistor (RS) value of 1mΩ. In
general, the current/power coefficients can be calculated using the relationships shown in Table 42.
39
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LM5066
II). The organization of the bits in the telemetry or warning
word is shown in Table 40, where Bit_11 is the most significant bit (MSB) and Bit_0 is the least significant bit (LSB). The
decimal equivalent of all warning and telemetry words are
constrained to be within the range of 0 to 4095, with the exception of temperature. The decimal equivalent value of the
temperature word ranges from 0 to 65535.
Reading and Writing Telemetry Data
and Warning Thresholds
LM5066
TABLE 42. Current and Power Telemetry and Warning Conversion Coefficients (RS in mΩ)
Commands
Condition
Format
Number of
Data Bytes
m
b
R
Units
*READ_IIN, READ_AVG_IIN
MFR_IIN_OC_WARN_LIMIT
CL = VDD
DIRECT
2
10753 x RS
-1200
-2
A
*READ_IIN, READ_AVG_IIN
MFR_IIN_OC_WARN_LIMIT
CL = GND
DIRECT
2
5405 x RS
-600
-2
A
*READ_PIN, READ_AVG_PIN,
READ_PIN_PEAK
MFR_PIN_OP_WARN_LIMIT
CL = VDD
DIRECT
2
1204 x RS
-6000
-3
W
*READ_PIN, READ_AVG_PIN,
READ_PIN_PEAK
MFR_PIN_OP_WARN_LIMIT
CL = GND
DIRECT
2
605 x RS
-8000
-3
W
Care must be taken to adjust the exponent coefficient, R, such
that the value of m remains within the range of -32768 to
+32767. For example, if a 5 mΩ sense resistor is used, the
correct coefficients for the READ_IIN command with CL =
VDD would be m = 5359, b = -120, R = -1.
A Note on the "b" Coefficient
Since b coefficients represent offset, for simplification b is set
to zero in the following discussions.
efficients enable the data output to be converted to amps. The
values shown in the example are based on having the device
programmed for a 26 mV current limit threshold (CL = VDD).
In the 26mV range, the LSB value is 9.3 µV and the full scale
range is 38.0 mV. In the 50mV range (CL = GND), the LSB
value is 18.5 µV and the full scale range in 76.0 mV.
Reading Current
The current register actually displays a value equivalent to a
voltage across the user specified sense resistor, RS. The coStep
1. Determine full scale current and shunt value based on 38.0
mV across shunt at full scale:
Example
Example: 8.6A application with 3 mΩ shunt.
or:
2. Determine m':
3. Determine exponent R necessary to set m' to integer value m: Select R to provide 16 bit accuracy for the integer value of m:
R = -1
4. Final values
m = 3233
R = -1
b=0
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40
Coefficients for VIN and VOUT are fixed and are consistent
between read telemetry measurements (e.g., READ_VIN,
READ_AVG_VIN)
and
warning
thresholds
(e.g.,
Step
Example
1. Determine m' based on full scale analog input and full scale
digital range:
2. Determine exponent R necessary to set m' to integer value m Select R to provide 16 bit accuracy for the integer value of m:
with desired accuracy:
(4585 in this example):
R = -2
3. Final values
m = 4586
R = -2
b =0
For this reason power coefficients will also vary depending on
the shunt value and must be calculated for each application.
The power LSB will vary depending on shunt value according
to 828 µW/Rsense for the 26mV range or 1.65 mW/Rsense
for the 50mV range.
Reading Power
The power calculation of the LM5066 is a relative power calculation meaning that full scale of the power register corresponds to simultaneous full scale values in the current
register and voltage register such that the power register has
the following relationship based on decimal equivalents of the
register contents:
Step
Example
1. Determine full scale power from known full scale of input
current and input voltage:
PIN_MAX = VIN_MAX x IIN_MAX
Example: 8.6A application with 3 mΩ shunt.
PIN_MAX = (89.3V) x (76 mV / 3 mΩ) = 2262W
2. Determine m':
3. Optional: Determine exponent R necessary to set m' to integer Select R to provide 16 bit accuracy for the integer value of m :
value m with desired accuracy:
R = -4
4. Final values
m = 18103
R = -4
b=0
41
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LM5066
VIN_UV_WARN_LIMIT). Input and output voltage values are
read/written in Direct format with 12-bit resolution and a 21.8
mV LSB. An example of calculating the PMBus coefficients
for input voltage is shown below.
Reading Input and Output Voltage
LM5066
4.
Determining Telemetry Coefficients
Empirically with Linear Fit
The coefficients for telemetry measurements and warning
thresholds presented in Table 41 are adequate for the majority of applications. Current and power coefficients must be
calculated per application as they are dependent on the value
of the sense resistor, RS, used. Table 42 provides the equations necessary for calculating the current and power coefficients for the general case. The small signal nature of the
current measurement make it and the power measurement
more susceptible to PCB parasitics than other telemetry
channels. This may cause slight variations in the optimum
coefficients (m, b, R) for converting from Direct format digital
values to real-world values (e.g., Amps and Watts). The optimum coefficients can be determined empirically for a specific application and PCB layout using two or more measurements of the telemetry channel of interest. The current
coefficients can be determined using the following method:
1. While the LM5066 is in normal operation measure the
voltage across the sense resistor using kelvin test points
and a high accuracy DVM while controlling the load
current. Record the integer value returned by the
READ_AVG_IIN command (with the
SAMPLES_FOR_AVG set to a value greater than 0) for
two or more voltages across the sense resistor. For best
results, the individual READ_AVG_IIN measurements
should span nearly the full scale range of the current (For
example, voltage across RS of 5mV and 20mV).
2. Convert the measured voltages to currents by dividing
them by the value of RS. For best accuracy the value of
RS should be measured. Table 43 assumes a sense
resistor value of 5mΩ.
5.
Where:
X: the calculated "real-world" value (volts, amps, watts, temperature)
m: the slope coefficient, is the two byte, two's complement
integer
Y: a two byte two's complement integer received from device
b: the offset, a two byte, two's complement integer
R: the exponent, a one byte two's complement integer
The above procedure can be repeated to determine the coefficients of any telemetry channel simply by substituting
measured current for some other parameter (e.g., power,
voltage, etc.).
Writing Telemetry Data
TABLE 43. Measurements for linear fit determination of
current coefficients:
Measured voltage Measured Current
across
(A)
RS (V)
3.
There are several locations that will require writing data if their
optional usage is desired. Use the same coefficients previously calculated for your application, and apply them using
this method as prescribed by the PMBus revision section
7.2.2 "Sending a Value"
READ_AVG_IIN
(integer value)
0.005
1
568
0.01
2
1108
0.02
4
2185
Y = (mX + b) x 10R
Where:
X: the calculated "real-world" value (volts, amps, watts, temperature)
m: the slope coefficient, is the two byte, two's complement
integer
Y: a two byte two's complement integer received from device
b: the offset, a two byte, two's complement integer
R: the exponent, a one byte two's complement integer
Using the spreadsheet or math program of your choice
determine the slope and the y-intercept of the data
returned by the READ_AVG_IIN command versus the
measured current. For the data shown in Table 42:
READ_AVG_IN value = slope x (Measured Current) + (yintercept)
slope = 538.9
y-intercept = 29.5
www.national.com
To determine the ‘m’ coefficient, simply shift the decimal
point of the calculated slope to arrive at at integer with a
suitable number of significant digits for accuracy
(typically 4) while staying with the range of -32768 to
+32767. This shift in the decimal point equates to the
‘R’ coefficient. For the slope value shown above, the
decimal point would be shifted to the right once hence
R = -1.
Once the ‘R’ coefficient has been determined, the ‘b’
coefficient is found by multiplying the y-intercept by
10-R. In this case the value of b = 295.
Calculated Current Coefficients:
m = 5389
b = 295
R = -1
42
The three address lines are to be set high (connect to VDD),
low (connect to GND), or open to select one of 27 addresses
TABLE 44. Device Addressing
ADR2
ADR1
ADR0
Decoded Address
Z
Z
Z
40h
Z
Z
0
41h
Z
Z
1
42h
Z
0
Z
43h
Z
0
0
44h
Z
0
1
45h
Z
1
Z
46h
Z
1
0
47h
Z
1
1
10h
0
Z
Z
11h
0
Z
0
12h
0
Z
1
13h
0
0
Z
14h
0
0
0
15h
0
0
1
16h
0
1
Z
17h
0
1
0
50h
0
1
1
51h
1
Z
Z
52h
1
Z
0
53h
1
Z
1
54h
1
0
Z
55h
1
0
0
56h
1
0
1
57h
1
1
Z
58h
1
1
0
59h
1
1
1
5Ah
43
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LM5066
for communicating with the LM5066. Table 44 depicts 7-bit
addresses (eighth bit is read/write bit):
PMBus™ Address Lines (ADR0,
ADR1, ADR2)
LM5066
SMBus Communications Timing
Requirements
301159a1
FIGURE 19. SMBus Timing Diagram
TABLE 45. SMBus Timing Definition
Symbol
Limits
Parameter
Min
Max
400
Units
FSMB
SMBus Operating Frequency
10
TBUF
Bus free time between Stop and Start Condition
1.3
µs
THD:STA
Hold time after (Repeated) Start Condition. After this
period, the first clock is generated.
0.6
µs
TSU:STA
Repeated Start Condition setup time
0.6
µs
TSU:STO
Stop Condition setup time
0.6
µs
THD:DAT
Data hold time
85
ns
TSU:DAT
Data setup time
100
TTIMEOUT
Clock low time-out
25
Comments
kHz
ns
35
ms
(Note 8)
TLOW
Clock low period
1.5
µs
THIGH
Clock high period
0.6
µs
(Note 9)
TLOW:SEXT
Cumulative clock low extend time (slave device)
25
ms
(Note 10)
TLOW:MEXT
Cumulative low extend time (master device)
10
ms
(Note 11)
TF
Clock or Data Fall Time
20
300
ns
(Note 12)
TR
Clock or Data Rise Time
20
300
ns
(Note 12)
Note 8: Devices participating in a transfer will timeout when any clock low exceeds the value of TTIMEOUT,MIN of 25 ms. Devices that have detected a timeout
condition must reset the communication no later than TTIMEOUT,MAX of 35 ms. The maximum value must be adhered to by both a master and a slave as it incorporates
the cumulative stretch limit for both a master (10ms) and a slave (25ms).
Note 9: THIGH MAX provides a simple method for devices to detect bus idle conditions.
Note 10: TLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to the stop. If a slave exceeds
this time, it is expected to release both its clock and data lines and reset itself.
Note 11: TLOW:MEXT is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, ackto-ack, or ack-to-stop.
Note 12: Rise and fall time is defined as follows:
• TR = ( VILMAX – 0.15) to (VIHMIN + 0.15)
• TF = 0.9 VDD to (VILMAX – 0.15)
www.national.com
44
The SMBA effectively has two masks:
1. The Alert Mask Register at D8h, and
2. The ARA Automatic Mask.
The ARA Automatic Mask is a mask that is set in response to
a successful ARA read. An ARA read operation returns the
PMBus address of the lowest addressed part on the bus that
has its SMBA asserted. A successful ARA read means that
THIS part was the one that returned its address. When a part
responds to the ARA read, it releases the SMBA signal. When
301159a0
FIGURE 20. Typical Flow Schematic for SMBA Fault
45
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LM5066
the last part on the bus that has an SMBA set has successfully
reported its address, the SMBA signal will de-assert.
The way that the LM5066 releases the SMBA signal is by
setting the ARA Automatic mask bit for all fault conditions
present at the time of the ARA read. All status registers will
still show the fault condition, but it will not generate and SMBA on that fault again until the ARA Automatic mask is cleared
by the host issuing a CLEAR_FAULTS command to this part.
This should be done as a routine part of servicing an SMBA
condition on a part, even if the ARA read is not done. Figure
20 depicts a schematic version of this flow.
SMBA Response
LM5066
Physical Dimensions inches (millimeters) unless otherwise noted
NS Package Number MXA28A
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46
LM5066
Notes
47
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LM5066 High Voltage System Power Management and Protection IC with PMBus™
Notes
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