2 GHz to 28 GHz, GaAs pHEMT MMIC Low Noise Amplifier HMC7950 Data Sheet 11 NIC GND RFOUT GND NIC 15 14 13 12 HMC7950 VDD 3 9 NIC PACKAGE BASE GND 15412-001 NIC GND RFIN VGG2 8 NIC 7 10 6 2 5 NIC 4 Test instrumentation Military and space 1 GND APPLICATIONS NIC NIC FUNCTIONAL BLOCK DIAGRAM Output power for 1 dB compression (P1dB): 16 dBm typical Saturated output power (PSAT): 19.5 dBm typical Gain: 15 dB typical Noise figure: 2.0 dB typical Output third-order intercept (IP3): 26 dBm typical Supply voltage: 5 V at 64 mA 50 Ω matched input/output 16 FEATURES Figure 1. GENERAL DESCRIPTION The HMC7950 is a gallium arsenide (GaAs), pseudomorphic high electron mobility transistor (pHEMT), monolithic microwave integrated circuit (MMIC). The HMC7950 is a wideband low noise amplifier that operates between 2 GHz and 28 GHz. The amplifier typically provides 15 dB of gain, 2.0 dB of noise figure, 26 dBm of output IP3, and 16 dBm of output power for 1 dB gain compression, requiring 64 mA from a 5 V supply. The HMC7950 Rev. A is self biased with only a single positive supply needed to achieve a drain current, IDD, of 64 mA. The HMC7950 also has a gain control option, VGG2. The HMC7950 amplifier input/outputs are internally matched to 50 Ω and dc blocked. It comes in a 6 mm × 6 mm, 16-terminal LCC SMT ceramic package that is easy to handle and assemble. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com HMC7950 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................5 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions..............................6 Functional Block Diagram .............................................................. 1 Interface Schematics .....................................................................6 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................7 Revision History ............................................................................... 2 Theory of Operation ...................................................................... 12 Specifications..................................................................................... 3 Applications Information .............................................................. 13 2 GHz to 5 GHz Frequency Range ............................................. 3 Evaluation Board ............................................................................ 14 5 GHz to 18 GHz Frequency Range ........................................... 3 Evaluation Board Schematic ..................................................... 15 18 GHz to 28 GHz Frequency Range ......................................... 4 Outline Dimensions ....................................................................... 16 DC Specifications ......................................................................... 4 Ordering Guide .......................................................................... 16 Absolute Maximum Ratings ............................................................ 5 Thermal Resistance ...................................................................... 5 REVISION HISTORY 9/2017—Rev. 0 to Rev. A Added Figure 37; Renumbered Sequentially .............................. 11 1/2017—Revision 0: Initial Version Rev. A | Page 2 of 16 Data Sheet HMC7950 SPECIFICATIONS 2 GHz TO 5 GHz FREQUENCY RANGE TA = 25°C, VDD = 5 V, VGG2 = open, unless otherwise stated. When using VGG2, it is recommended to limit VGG2 from −2 V to +2.6 V. POUT is output power. Table 1. Parameter FREQUENCY RANGE GAIN Gain Variation Over Temperature RETURN LOSS Input Output OUTPUT Output Power for 1 dB Compression Saturated Output Power Output Third-Order Intercept NOISE FIGURE Symbol P1dB PSAT IP3 NF Test Conditions/Comments Min 2 13.5 13 Measurement taken at POUT/tone = 4 dBm Typ Max 5 15.5 0.004 Unit GHz dB dB/°C 12 13 dB dB 16.5 20.5 26.5 3.0 dBm dBm dBm dB 4.5 5 GHz TO 18 GHz FREQUENCY RANGE TA = 25°C, VDD = 5 V, VGG2 = open, unless otherwise stated. When using VGG2, it is recommended to limit VGG2 from −2 V to +2.6 V. POUT is output power. Table 2. Parameter FREQUENCY RANGE GAIN Gain Variation Over Temperature RETURN LOSS Input Output OUTPUT Output Power for 1 dB Compression Saturated Output Power Output Third-Order Intercept NOISE FIGURE Symbol P1dB PSAT IP3 NF Test Conditions/Comments Min 5 13.3 13 Measurement taken at POUT/tone = 4 dBm Rev. A | Page 3 of 16 Typ Max 18 15 0.007 Unit GHz dB dB/°C 18 14 dB dB 16 19.5 26 2.0 dBm dBm dBm dB 3.5 HMC7950 Data Sheet 18 GHz TO 28 GHz FREQUENCY RANGE TA = 25°C, VDD = 5 V, VGG2 = open, unless otherwise stated. When using VGG2, it is recommended to limit VGG2 from −2 V to +2.6 V. POUT is output power. Table 3. Parameter FREQUENCY RANGE GAIN Gain Variation over Temperature RETURN LOSS Input Output OUTPUT Output Power for 1 dB Compression Saturated Output Power Output Third-Order Intercept NOISE FIGURE Symbol P1dB PSAT IP3 NF Test Conditions/Comments Min 18 13 Typ 10 Measurement taken at POUT/tone = 4 dBm Max 28 16.5 0.012 Unit GHz dB dB/°C 19 16 dB dB 14.5 17 24 2.8 dBm dBm dBm dB 5 DC SPECIFICATIONS Table 4. Parameter SUPPLY CURRENT Total Supply Current Total Supply Current vs. VDD IDD = 58 mA IDD = 61 mA IDD = 64 mA IDD = 66 mA IDD = 69 mA SUPPLY VOLTAGE VGG2 PIN Symbol Test Conditions/Comments Min IDD VDD VGG2 Normal condition is VGG2 = open Rev. A | Page 4 of 16 3 −2.0 Typ Max Unit 64 100 mA 7 2.6 V V V V V V V 3 4 5 6 7 5 Data Sheet HMC7950 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. Parameter Supply Voltage (VDD) Second Gate Bias Voltage (VGG2) Radio Frequency Input Power (RFIN) Channel Temperature Continuous Power Dissipation (PDISS), TA = 85°C (Derate 17.2 mW/°C Above 85°C) Maximum Peak Reflow Temperature (MSL3)1 Storage Temperature Range Operating Temperature Range ESD Sensitivity, Human Body Model (HBM) 1 Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Rating 8V −2.5 V to +3 V 20 dBm 175°C 1.55 W θJC is the junction to case thermal resistance. Table 6. Thermal Resistance 260°C −65°C to +150°C −40°C to +85°C 250 V (Class 1A) See the Ordering Guide section for more information. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Package Type EP-16-21 1 θJC 58 Unit °C/W Channel to ground pad. See JEDEC Standard JESD51-2 for additional information on optimizing the thermal impedance ESD CAUTION Rev. A | Page 5 of 16 HMC7950 Data Sheet NIC 12 TOP VIEW (Not to Scale) VGG2 4 GND 5 VDD 3 HMC7950 11 NIC 10 NIC 9 NIC NOTES 1. NIC = NO INTERNAL CONNECTION. NOTE THAT DATA SHOWN HEREIN WAS MEASURED WITH THESE PINS EXTERNALLY CONNECTED TO RF/DC GROUND. 2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF/DC GROUND. 15412-002 NIC 2 RFIN 6 GND 7 NIC 8 NIC 1 15 16 NIC GND 14 RFOUT 13 GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 7. Pin Function Descriptions Pin 1, 2, 8, 9, 10, 11, 12, 16 3 Mnemonic NIC 4 VGG2 5, 7, 13, 15 6 GND RFIN 14 RFOUT VDD EPAD (GND) Description No Internal Connection. Note that data shown herein was measured with these pins externally connected to RF/dc ground. See Figure 3 for the interface schematic. Power Supply Voltage for the Amplifier. Connect a dc bias to provide drain current (IDD). See Figure 4 for the interface schematic. Gain Control. This pin is dc-coupled and accomplishes gain control by reducing the internal voltage and becoming more negative. See Figure 5 for the interface schematic. These pins must be connected to RF/dc ground. See Figure 3 for the interface schematic. Radio Frequency (RF) Input. This pin is ac-coupled, but has a large resistor to GND for ESD protection, and matched to 50 Ω. See Figure 6 for the interface schematic. RF Output. This pin is ac-coupled, but has a large resistor to GND for ESD protection, and matched to 50 Ω. See Figure 7 for the interface schematic. Exposed Pad (Ground). The exposed pad must be connected to RF/dc ground. See Figure 3 for the interface schematic. INTERFACE SCHEMATICS 15412-007 GND RFIN 15412-003 Figure 3. GND Interface Schematic VDD 15412-005 Figure 6. RFIN Interface Schematic Figure 4. VDD Interface Schematic 15412-006 RFOUT Figure 7. RFOUT Interface Schematic 15412-004 VGG2 Figure 5. VGG2 Interface Schematic Rev. A | Page 6 of 16 Data Sheet HMC7950 TYPICAL PERFORMANCE CHARACTERISTICS 20 20 –40°C +25°C +85°C 15 18 5 16 GAIN (dB) RESPONSE (dB) 10 0 –5 –10 14 12 –15 35 30 25 20 FREQUENCY (GHz) 8 FREQUENCY (GHz) Figure 8. Response (Gain and Return Loss) vs. Frequency 0 Figure 11. Gain vs. Frequency at Various Temperatures 0 –40°C +25°C +85°C –5 –10 –10 –15 –15 –20 6 10 14 18 22 26 30 Figure 9. Input Return Loss vs. Frequency at Various Temperatures 6 –25 15412-009 2 10 6 14 18 22 26 30 FREQUENCY (GHz) Figure 12. Output Return Loss vs. Frequency at Various Temperatures 18 –40°C +25°C +85°C 5 2 15412-012 –20 FREQUENCY (GHz) –40°C +25°C +85°C 17 16 15 P1dB (dBm) 4 3 2 14 13 12 11 10 1 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 FREQUENCY (GHz) 8 2 4 6 8 10 12 14 16 18 20 22 24 26 28 FREQUENCY (GHz) Figure 10. Noise Figure vs. Frequency at Various Temperatures Figure 13. P1dB vs. Frequency at Various Temperatures Rev. A | Page 7 of 16 30 15412-013 9 15412-010 NOISE FIGURE (dB) –40°C +25°C +85°C RETURN LOSS (dB) RETURN LOSS (dB) –5 –25 30 26 22 18 14 10 6 2 15412-011 15 10 5 0 15412-008 –25 10 S21 S11 S22 –20 HMC7950 Data Sheet 17 19 16 18 15 P1dB (dBm) 20 17 16 15 14 13 12 14 11 13 10 12 9 11 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 FREQUENCY (GHz) 8 21 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Figure 17. P1dB vs. Frequency at Various Supply Voltages 30 4V 5V 6V 22 2 FREQUENCY (GHz) Figure 14. PSAT vs. Frequency at Various Temperatures 23 4V 5V 6V 18 15412-014 PSAT (dBm) 19 –40°C +25°C +85°C 21 15412-017 22 –40°C +25°C +85°C 28 26 19 IP3 (dBm) PSAT (dBm) 20 18 17 16 24 22 15 14 20 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 FREQUENCY (GHz) 18 15412-015 12 6 8 10 12 14 16 18 20 22 24 26 28 30 Figure 18. Output IP3 vs. Frequency at Various Temperatures, POUT/Tone = 4 dBm 60 4V 5V 6V 28 4 FREQUENCY (dBm) Figure 15. PSAT vs. Frequency at Various Supply Voltages 30 2 15412-018 13 4GHz 10GHz 16GHz 22GHz 28GHz 50 IMD3 (dBc) 24 40 22 30 18 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 FREQUENCY (dBm) 20 0 1 2 3 4 5 POUT/TONE (dBm) Figure 16. Output IP3 vs. Frequency at Various Supply Voltages POUT/Tone = 4 dBm 6 7 8 15412-019 20 15412-016 IP3 (dBm) 26 Figure 19. Output Third-Order Intermodulation Distortion (IMD3) vs. POUT/Tone at Various Frequencies, VDD = 4 V Rev. A | Page 8 of 16 Data Sheet HMC7950 40 30 0 1 2 3 4 5 6 7 8 POUT/TONE (dBm) 68 0.28 64 76 –6 –4 –2 0 2 4 6 8 60 4GHz 10GHz 16GHz 22GHz 28GHz 72 40 68 3 4 5 6 7 8 POUT/TONE (dBm) 60 –10 1 –2 0 2 4 6 8 70 IGG2 IDD 0 REVERSE ISOLATION (dB) –4 Figure 24. IDD vs. Input Power at Various Frequencies –40°C +25°C +85°C –10 –6 INPUT POWER (dBm) Figure 21. Output IMD3 vs. POUT/Tone at Various Frequencies, VDD = 6 V 0 –8 65 –1 60 –30 –2 55 –3 50 –50 –4 45 –60 –5 40 IGG2 (mA) –20 –70 2 6 10 14 18 FREQUENCY (GHz) 22 26 30 –6 –1.5 15412-022 –40 –1.1 –0.7 –0.3 0.1 0.5 0.9 1.3 1.7 2.1 35 2.5 VGG2 (V) Figure 22. Reverse Isolation vs. Frequency at Various Temperatures Figure 25. IGG2 and IDD vs. VGG2 at 14 GHz, Input Power (PIN) = 0 dBm Rev. A | Page 9 of 16 IDD (mA) 2 15412-025 1 15412-021 0 15412-024 64 30 20 –8 Figure 23. Power Dissipation and IDD vs. Input Power at Various Frequencies, 16 GHz, TA = 85°C IDD (mA) IMD3 (dBc) 0.32 4GHz 10GHz 16GHz 22GHz 28GHz 50 72 INPUT POWER (dBm) Figure 20. Output IMD3 vs. POUT/Tone at Various Frequencies, VDD = 5 V 60 0.36 0.24 –10 15412-020 20 76 4 GHz 10GHz 16GHz 22GHz 28GHz IDD AT 16GHz IDD (mA) POWER DISSIPATION (W) 50 IMD3 (dBc) 0.40 4GHz 10GHz 16GHz 22GHz 28GHz 15412-023 60 HMC7950 Data Sheet 22 20 –1.2V –0.8V –0.6V –0.4V –0.2V 0V 20 10 18 16 GAIN (dB) P1dB (dBm) 0 –10 –20 –40 0 5 10 15 20 25 30 0 2 6 10 14 18 22 26 30 FREQUENCY (GHz) Figure 29. P1dB vs. Frequency at Various VGG2 Voltage Levels 22 0V 0.4V 1V 1.6V 2.2V 2.6V –1.2V –0.8V –0.6V –0.4V –0.2V 0V 20 18 16 –10 PSAT (dBm) RETURN LOSS (dB) –5 8 2 Figure 26. Gain vs. Frequency at Various VGG2 Voltage Levels –2V –1.6V –1.4V –1.2V –1V –0.8V –0.4V 10 4 FREQUENCY (GHz) 0 12 15412-029 –30 14 6 0V 0.4V 1V 1.6V 2.2V 2.6V 15412-026 –2V –1.6V –1.4V –1.2V –1V –0.8V –0.4V 0.4V 0.8V 1.2V 1.6V 2V 2.4V –15 0.4V 0.8V 1.2V 1.6V 2V 2.4V 14 12 10 8 6 –20 4 5 10 15 20 25 30 FREQUENCY (GHz) 0 15412-027 0 –2V –1.6V –1.4V –1.2V –1V –0.8V –0.4V 10 14 18 22 26 30 Figure 30. PSAT vs. Frequency at Various VGG2 Voltage Levels 30 0V 0.4V 1V 1.6V 2.2V 2.6V 25 20 –10 IP3 (dBm) –15 15 10 –20 0 5 10 15 20 FREQUENCY (GHz) 25 30 15412-028 –25 –1.2V –0.8V –0.6V –0.4V 0V 0.4V 5 Figure 28. Output Return Loss vs. Frequency at Various VGG2 Voltage Levels Rev. A | Page 10 of 16 0 2 6 0.8V 1.2V 1.6V 2V 2.4V 10 14 18 FREQUENCY (GHz) 22 26 30 15412-031 RETURN LOSS (dB) –5 6 FREQUENCY (GHz) Figure 27. Input Return Loss vs. Frequency at Various VGG2 Voltage Levels 0 2 15412-030 2 –25 Figure 31. Output IP3 vs. Frequency at Various VGG2 Voltage Levels, POUT/Tone = 4 dBm Data Sheet HMC7950 45 15 40 10 35 0 –5 –10 –15 2.0 1.6 1.2 0.8 0.4 0 –0.4 –0.8 –1.2 –1.6 –2.0 20 15 10 VGG2 (V) 0 15412-032 –25 2.4 Figure 32. Gain vs. VGG2 at 14 GHz –40°C +25°C +85°C 2 6 8 10 12 14 16 18 20 22 24 FREQUENCY (GHz) 45 26 40 24 35 SECOND HARMONIC (dBc) 28 20 18 16 14 12 0dBm 5dBm 30 25 20 15 10 1.6 1.2 0.8 0.4 0 –0.4 –0.8 –1.2 VGG2 (V) 4 6 8 10 12 14 16 18 20 22 24 FREQUENCY (GHz) –70 –40°C +25°C +85°C 35 2 Figure 36. Second Harmonic vs. Frequency at Various Output Powers Figure 33. Output IP3 vs. VGG2 at 14 GHz 37 0 15412-033 2.0 15412-136 5 10 2.4 –80 –90 PHASE NOISE (dBc/Hz) 33 31 29 27 25 23 –100 –110 –120 –130 –140 21 –150 19 –160 2 4 6 8 10 12 14 16 18 20 22 24 FREQUENCY (GHz) Figure 34. Output IP2 vs. Frequency at Various Temperatures, POUT/Tone = 4 dBm –170 15412-034 17 4 Figure 35. Second Harmonic vs. Frequency at Various Temperatures, POUT = 0 dBm 22 IP3 (dBm) 25 5 –20 IP2 (dBm) 30 10 100 1k 10k OFFSET FREQUENCY (Hz) 100k 1M 15412-137 GAIN (dB) 5 15412-035 SECOND HARMONIC (dBc) 20 Figure 37. Additive Phase Noise vs. Offset Frequency, RF Frequency = 8 GHz, RF Input Power = 2.5 dBm (P1dB) Rev. A | Page 11 of 16 HMC7950 Data Sheet THEORY OF OPERATION The HMC7950 is a GaAs, pHEMT, MMIC low noise amplifier. Its basic architecture is that of a single-supply, biased cascode distributed amplifier with an integrated RF choke for the drain. The cascode distributed architecture uses a fundamental cell consisting of a stack of two field effect transistors (FETs) with the source of the upper FET connected to the drain of the lower FET. The fundamental cell is then duplicated several times, with a transmission line feeding the RFIN signal to the gates of the lower FETs and a separate transmission line interconnecting the drains of the upper FETs and routing the amplified signal to the RFOUT pin. Additional circuit design techniques around each cell optimize the overall performance for broadband operation. The major benefit of this architecture is that high performance is maintained across a bandwidth far greater than a single instance of the fundamental cell can provide. A simplified schematic of this architecture is shown in Figure 38. VDD Although the gate bias voltages of the upper FETs are set internally by a resistive voltage divider connected to VDD, the VGG2 pin provides the user with an optional means of changing the gate bias of the upper FETs. Application of a voltage to VGG2 allows the user to change the voltage output by the resistive divider, altering the gate bias of the upper FETs and thus changing the gain. Application of VGG2 voltages across the range of −2.0 V to +2.6 V affects gain changes of approximately 30 dB, depending on the frequency. Increasing the voltage applied to VGG2 increases the gain, whereas decreasing the voltage decreases the gain. For VDD = 5.0 V (nominal), the resulting VGG2 open circuit voltage is approximately 2.2 V. TRANSMISSION LINE RFOUT VGG2 TRANSMISSION LINE 15412-036 RFIN Figure 38. Architecture and Simplified Schematic Rev. A | Page 12 of 16 Data Sheet HMC7950 APPLICATIONS INFORMATION The recommended bias sequence during power-down is as follows: Capacitive bypassing is recommended for VDD, as shown in the typical application circuit in Figure 39. Gain control is possible through the application of a dc voltage to VGG2. If gain control is used, capacitive bypassing of VGG2 is recommended as shown in the typical application circuit. If gain control is not used, VGG2 can be either left open or capacitively bypassed as shown in Figure 39. 1. 2. 3. Power-up and power-down sequences can differ from the ones described, although care must always be taken to ensure adherence to the values shown in the Absolute Maximum Ratings section. The recommended bias sequence during power-up is as follows: 2. 3. Set VDD to 5.0 V (this results in an IDD near its specified typical value). If the gain control function is to be used, apply a voltage within the range of −2.0 V to +2.6 V to VGG2 until the desired gain setting is achieved. Apply the RF input signal. Unless otherwise noted, all measurements and data shown were taken using the typical application circuit as configured on the HMC7950 evaluation board. The bias conditions shown in the Specifications section are recommended to optimize the overall performance. Operation using other bias conditions may result in performance that differs from the data shown in this data sheet. VDD 4.7µF 10nF 100pF 3 VGG2 + 4.7µF 10nF 2 1 4 16 5 15 6 14 7 13 8 12 100pF RFOUT RFIN 9 10 11 PACKAGE BASE GND Figure 39. Typical Application Circuit Rev. A | Page 13 of 16 15412-037 1. Turn off the RF input signal. Remove the VGG2 voltage, or set it to 0 V. Set VDD to 0 V. HMC7950 Data Sheet EVALUATION BOARD J3 1 2 ANALOG DEVICES VDD C5 C 8 C9 C 7 H7950 U1 C3 C1 RFOUT C6 1 VGG 2 HMC7950LS6 EVAL RFIN 08-043402 REV B C2 C4 Figure 40. Evaluation PCB Table 8. Bill of Materials for Evaluation PCB EV1HMC7950LS6 Item RFIN, RFOUT C1, C7 C3, C8 C5, C9 U1 PCB VDD, VGG2 C2, C4, C6, J3, J4, VGG Description PCB mount, K connector, SRI Part Number 21-146-1000-92 100 pF capacitor, 5%, 50 V, C0G, 0402 package 10 nF capacitor, 10%, 16 V, X7R, 0402 package 4.7 µF tantalum capacitor, 10%, 20 V, 1206 package Amplifier, HMC7950LS6 Evaluation PCB; circuit board material: Rogers 4350 DC pins, Molex Part Number 87759-0414 Do not install (DNI) Rev. A | Page 14 of 16 15412-038 VGG2 2 The evaluation board schematic is shown in Figure 41. A fully populated and tested evaluation board, shown in Figure 40, is available from Analog Devices, Inc., upon request. 1 The evaluation board and populated components are designed to operate over the ambient temperature range of −40°C to +85°C. For the proper bias sequence, see the Applications Information section. J4 The HMC7950 evaluation board is a 2-layer board fabricated using Rogers 4350 and using best practices for high frequency RF design. The RF input and RF output traces have a 50 Ω characteristic impedance. Data Sheet HMC7950 EVALUATION BOARD SCHEMATIC VGG2 VDD 1 1 2 2 3 3 4 4 GND C9 4.7µF + C5 4.7µF C3 10nF C1 100pF GND C8 10nF C7 100pF 3 GND NIC HMC7950LS6 GND RFIN RFOUT GND 9 10 NIC NIC NIC GND EPAD NIC 16 15 RFOUT 14 13 12 11 VGG DNI 1 2 3 4 C2 DNI J3 DNI C4 DNI THRU_CAL Figure 41. Evaluation Board Schematic Rev. A | Page 15 of 16 GND + C6 DNI J4 DNI 15412-039 8 VGG2 NIC 7 NIC 6 1 NIC 5 RFIN VDD 4 2 HMC7950 Data Sheet OUTLINE DIMENSIONS PIN 1 INDICATOR 1.05 3.46 3.40 3.34 0.56 0.50 0.44 TOP VIEW 5.90 BSC SIDE VIEW 1.444 1.317 1.190 3.45 1.65 0.31 0.25 0.19 0.35 0.80 12 PKG-004903 1.00 BSC 11 1 9 3 8 1.21 1.15 1.09 2.06 2.00 1.94 4 BOTTOM VIEW 0.50 MAX COPLANARITY 0.08 0.44 BSC 16 4.70 4.65 4.60 0.63 0.57 0.51 3.55 SQ 0.90 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 12-06-2016-B 6.10 6.00 SQ 5.90 Figure 42. 16-Terminal Ceramic Leadless Chip Carrier with Heat Sink [LCC_HS] (EP-16-2) Dimensions shown in millimeters ORDERING GUIDE Model 1 HMC7950LS6 Temperature Range −40°C to +85°C MSL Rating 2 MSL3 Lead Finish Au Package Description 16-Terminal LCC_HS Package Option EP-16-2 HMC7950LS6TR −40°C to +85°C MSL3 Au 16-Terminal LCC_HS EP-16-2 EV1HMC7950LS6 1 2 3 Evaluation PCB The HMC7950LS6 and HMC7950LS6TR are RoHS compliant parts, made of low stress injection molded plastic. See the Absolute Maximum Ratings section for further information on the moisture sensitivity level (MSL) rating. XXXX is the four-digit lot number. ©2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D15412-0-9/17(A) Rev. A | Page 16 of 16 Branding 3 H7950 XXXX H7950 XXXX