H S9338 D ata Converter Line Complete µP Compatible 12-Bit D AC FEATURES • • • • • • • • Output ranges: 0 to +10V, ±10V . Coding: binary; offset binary Linearity: ±0.01% Settling time: 2.5 µS µP compatible 28-pin package CM OS, TTL compatible Double buffered inputs DESCRIPTION HS9338 is a µP-compatible, complete 12-bit double buffered digital-to-analog converter. To enhance application flexibility, the data input registers have been configured as 3 independent 4-bit bytes. This enables the user to directly interface to 4, 8, and 12-bit data buses. HS9338 comes complete with interface control logic. The three separate byte enable inputs latch data from the bus into the appropriate primary data latches. The LDA C input transfers data from the primary latches to the DA C register. In addition to these input functions are two chip select inputs and a read/write input allowing direct memory-map configurations. A ll input controls are static to allow hardwired configurations. FUNCTIONAL DIAGRAM DA TA INPUTS M SB 16 CS CS WR HBE M BE LBE LDA C 4 17 18 19 20 HIGH BY TE INPUT REG 3 21 22 23 LSB 24 M IDDLE BY TE INPUT REG 25 26 27 SUM JCT 12 5V RA NGE 10 LOW BY TE INPUT REG 2 6 CONTROL LOGIC 5 DA C REGISTER – + 12-BIT M DA C 7 1 REFERENCE – + HS 9338 28 +5V 15 9 8 10 – 15V +15V GND GA IN 10 BIPOLA R 165Cedar Hill Street,Marlborough,MA01752 Tel:508.485.6350 Fax: 508.485.5168 www.SpectrumMicrowave.com 11 V OUT HS9338 SPECIFICATIO N S (Typical @25ºC unless otherwise noted. Power supply voltages: +15V. –15V. +5V, (±5%) M ODEL HS 9338-2 HS9338-0 DIGITA L INPUT Resolution Unipolar Code Bipolar Code Logic Compatibility1 Control Logic Inputs I IH @V IH = 2.4V I IL @V IL = 0.4V Data Input Current 5 12 Bit Binary Offset Binary CM OS. TTL 20µA –0.36mA ±1µA A NA LOG OUTPUT Scale Factor A ccuracy2 Initial Offset 2 Bipolar Unipolar V oltage Range 2 Bipolar Unipolar ±0.1% FSR ±0.1% FSR max ± 0.05% FSR max ±10V . 0 to +10V STA TIC PERFORM A NCE Integral Linearity3 ±0.015% FSR max ±0.050% FSR max Differential Linearity ±0.024% FSR max ±0.097% FSR max M onotonicity 12 Bits 10 Bits DY NA M IC PERFORM A NCE Full Scale Transition Settling Time Full Scale Transition Slew Rate Delay to A nalog Output From Bits Input 4 From LDA C From CS4 or W E 4 5µS max 2.5µS max 10V /µS min 220nS 220nS 225nS STA BILITY Scale Factor Integral Linearity Differential Linearity Offset Drift Bipolar Unipolar M onotonicity Temperature Range 20ppm FSR 1 ppm FSR max 1 ppm FSR max 10ppm/ºC 5ppm/ºC 0ºC to +70ºC ± 15V POW ER SUPPLY + 15V Supply Current -15V Supply Current PSRR 12mA 10mA 0.005% /% + 5V POW ER SUPPLY + 5V Supply Current 24mA TEM PERA TURE RA NGE Operating Storage –55ºCto +125ºC –65ºCto +155ºC Continued on next page. HS9338 SPECIFICA TION (Continued) M ECHA NICA L Case Style Ceramic NOTES: 1. Control inputs are TTL and 5V CM OS only, data inputs are fully CM OS and TTL compatible. 2. See A PPLICA TION NOTES for adjustment procedures. 3 Specified as “ Best Straight Line” . 4. Operating the unit with the DA C Register transparent may result in output “ glitches” due to logic skewing with the unit. 5. Digital Input V oltage must not exceed supply voltage or go below –0.5V .“ 0” 0.8V , 2.4V “ 1” V DD . * Same as HS 9338-2 CA UTION: ESD (Electro-Static Discharge) sensitive device. Permanent damage may occur when unconnected devices are subjected to high energy electrostatic fields. Unless otherwise noted, the voltage at any digital input should never exceed the supply voltage by more than 0.5 volts or go below –0.5 volts. PIN PA CK A GE OUTLINE 0.705 (17.907) MAX 0.255 (6.477) M A X DIM ENSIONS inches (mm) 0.600 (15.240) 28 PIN 1 DOT 1 0.120 (3.048) 15 0.17 TY P (4.321) 14 BOTTOM V IEW 1.540 (43.911) MAX 0.100 (2.540) TY P 0.01 0.020 x (0.254) (0.508) ORDERING INFORM A TION M ODEL HS 9338-2 HS 9338- DESCRIPTION µP DA C, 0.01% Linearity µP DA C, 0.05% Linearity PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 DIA GRA M FUNCTION LOA C, LOA DS OA C REGISTER A ND CHA NGES OUTPUT W R, W RITE INPUT, A CTIV A TES A LL CONTROLS CS2, CHIP SELECT INPUT 2 CS1, CHIP SELECT INPUT 1 M BE, M IDDLE BY TE ENA BLE. D4 TO D7 HBE, HIGH BY TE ENA BLE. D8 TO D11 LBE, LOW BY TE ENA BLE. D0 TO D3 GND, GROUND, A NA LOG A ND DIGITA L GROUND CONNECTED INTERNA LLY V EE , – 15V SUPPLY N.C. V OUT DA C V OLTA GE OUTPUT SUM JCT. SUM M ING JUNCTION OF OUTPUT OPA M P BIPOLA R. CONNECTED TO SUM JCT FOR BIPOLA R OUTPUT RA NGE GA IN. INPUT TO A DJUST FULL SCA LE OUTPUT V OLTA GE V EE , -15V SUPPLY D11, DA TA INPUT, W EIGHT 2 -1 . M SB D10, DA TA INPUT, W EIGHT 2 -2 09, DA TA INPUT, W EIGHT 2 -3 08, DA TA INPUT, W EIGHT 2 -4 D7, DA TA INPUT, W EIGHT 2 -5 D6, DA TA INPUT, W EIGHT 2 -6 D5, DA TA INPUT, W EIGHT 2 -7 D4, DA TA INPUT, W EIGHT 2 -8 D3, DA TA INPUT, W EIGHT 2 -9 D2, DA TA INPUT, W EIGHT 2 -10 D1, DA TA INPUT, W EIGHT 2 -11 D0, DA TA INPUT, W EIGHT 2 -12 , LSB V DD , +5V SUPPLY, CONTROL LOGIC