Test instrumentation Microwave radios and very small aperture terminals (VSATs) Military radios, radars, and electronic counter measures (ECMs) Fiber optics and broadband telecommunications GND 1 19 GND 21 GND 22 GND 20 RF2 18 GND ADRF5040 GND 2 50Ω 50Ω 17 VDD RFC 3 16 V1 GND 4 15 V2 GND 5 14 VSS 50Ω 50Ω GND 6 PACKAGE BASE GND 14290-001 GND 12 RF3 11 9 GND GND 10 8 RF4 13 GND 7 APPLICATIONS 23 RF1 FUNCTIONAL BLOCK DIAGRAM Nonreflective 50 Ω design Positive control range: 0 V to 3.3 V Low insertion loss: 0.8 dB at 8.0 GHz High isolation: 34 dB at 8.0 GHz High power handling 33 dBm through path 27 dBm termination path High linearity 1 dB compression (P1dB): 37 dBm typical Input third-order intercept (IIP3): 58 dBm typical at 8.0 GHz ESD rating: 4 kV human body model (HBM) 4 mm × 4 mm, 24-lead LFCSP package No low frequency spurious RF settling time (0.05 dB margin of final RFOUT): 9 µs 24 GND FEATURES GND Data Sheet High Isolation, Silicon SP4T, Nonreflective Switch, 9 kHz to 12.0 GHz ADRF5040 Figure 1. GENERAL DESCRIPTION The ADRF5040 is a general-purpose, broadband high isolation, nonreflective single-pole, quad-throw (SP4T) switch in an LFCSP surface-mount package. Covering the 9 kHz to 12.0 GHz range, the switch offers high isolation and low insertion loss. The switch features 34 dB isolation and 0.8 dB insertion loss up to Rev. A 8.0 GHz, and a 9 µs settling time of 0.05 dB margin of the final radio frequency output (RFOUT). The switch operates using positive control voltage of 3.3 V and 0 V and requires +3.3 V and −3.3 V supplies. The ADRF5040 is packaged in a 4 mm × 4 mm, surface-mount LFCSP package. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADRF5040 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Interface Schematics .....................................................................7 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................8 Functional Block Diagram .............................................................. 1 Insertion Loss, Return Loss, and Isolation ................................8 General Description ......................................................................... 1 Input Power Compression and Input Third-Order Intercept ... 10 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Input Power Compression and Input Third-Order Intercept, 10 kHz to 1 GHz .......................................................................... 11 Electrical Specifications ............................................................... 3 Theory of Operation ...................................................................... 12 Digital Control Voltage Specifications....................................... 4 Applications Information .............................................................. 13 Bias and Supply Current Specifications ..................................... 4 Evaluation Board ........................................................................ 13 Absolute Maximum Ratings ............................................................ 5 Outline Dimensions ....................................................................... 14 ESD Caution .................................................................................. 5 Ordering Guide .......................................................................... 14 Pin Configuration and Function Descriptions ............................. 6 REVISION HISTORY 2/2017—Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 14 7/2016—Revision 0: Initial Version Rev. A | Page 2 of 14 Data Sheet ADRF5040 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VDD = 3.3 V, VSS = −3.3 V, V1 and V2 = 0 V or VDD, TA = 25°C, 50 Ω system, unless otherwise noted. Table 1. Parameter INSERTION LOSS Test Conditions/Comments Min Typ Max Unit 9 kHz to 4.0 GHz 9 kHz to 8.0 GHz 9 kHz to 10.0 GHz 9 kHz to 12.0 GHz 0.7 0.8 1.1 2 dB dB dB dB 9 kHz to 4.0 GHz 9 kHz to 8.0 GHz 9 kHz to 10.0 GHz 9 kHz to 12.0 GHz 44 34 29.2 20 dB dB dB dB 9 kHz to 4.0 GHz 9 kHz to 8.0 GHz 9 kHz to 10.0 GHz 9 kHz to 12.0 GHz 9 kHz to 4.0 GHz 9 kHz to 8.0 GHz 9 kHz to 10.0 GHz 9 kHz to 12.0 GHz 21 19 13.5 8 25 18.6 15.5 14.5 dB dB dB dB dB dB dB dB 50% V1/V2 to 0.05 dB margin of final RFOUT 50% V1/V2 to 0.1 dB margin of final RFOUT 9 7 µs µs 10% to 90% RFOUT 50% V1/V2 to 90%/10% RF 9 kHz to 12.0 GHz 1.3 3.5 µs µs 37 34 dBm dBm 62 58 53 dBm dBm dBm ISOLATION, RFC TO RF1 TO RF4 (WORST CASE) RETURN LOSS On State Off State RADIO FREQUENCY (RF) SETTLING TIME SWITCHING SPEED tRISE/tFALL tON/tOFF INPUT POWER 1 dB Compression (P1dB) 0.1 dB Compression (P0.1dB) INPUT THIRD-ORDER INTERCEPT (IIP3) RECOMMENDED OPERATING CONDITIONS Positive Supply Voltage (VDD) Negative Supply Voltage (VSS) Control Voltage (V1, V2) Range RF Input Power Through Path Termination Path Hot Switch Power Level Case Temperature Range (TCASE) Two-tone input power = 14 dBm at each tone 1 MHz to 2.0 GHz 1 MHz to 8.0 GHz 1 MHz to 12.0 GHz 3.0 −3.6 0 3.6 −3.0 VDD V V V −40 33 27 27 +85 dBm dBm dBm °C VDD = 3.3 V, VSS = −3.3 V, TA = 85°C, frequency = 2 GHz VDD = 3.3 V, TA = 85°C, frequency = 2 GHz Rev. A | Page 3 of 14 ADRF5040 Data Sheet DIGITAL CONTROL VOLTAGE SPECIFICATIONS VDD = 3.3 V ± 10%, VSS = −3.3 V ± 10%, TCASE = −40°C to +85°C, unless otherwise noted. Table 2. Parameter INPUT CONTROL VOLTAGE (V1, V2) Low High Symbol Min VIL VIH 0 1.4 Typ Max Unit 0.8 VDD + 0.3 V V Test Condition/Comments <1 µA typical BIAS AND SUPPLY CURRENT SPECIFICATIONS TCASE = −40°C to +85°C, unless otherwise noted. Table 3. Parameter SUPPLY CURRENT VDD = 3.3 V VSS = −3.3 V Symbol IDD ISS Min Typ Max Unit 20 20 100 100 µA µA Rev. A | Page 4 of 14 Data Sheet ADRF5040 ABSOLUTE MAXIMUM RATINGS 5 Table 4. 34 dBm 28 dBm 30 dBm 0 –5 –10 −65°C to +150°C 135°C –20 0.01 0.1 100 10 1 1k Figure 3. Power Derating for Terminated Path 83°C/W 100°C/W MSL3 5 4 kV (Class 3) 1.25 kV 0 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. –5 –10 –15 –20 0.01 0.1 1 10 100 FREQUENCY (MHz) Figure 4. Power Derating for Hot Switching Power 5 ESD CAUTION –5 –10 –15 –20 0.1 1 10 100 1k FREQUENCY (MHz) 10k 14290-002 POWER DERATING (dBm) 0 Figure 2. Power Derating for Through Path Rev. A | Page 5 of 14 1k 14290-004 For the recommended operating conditions, see Table 1. –25 0.01 10k FREQUENCY (MHz) 14290-003 –15 POWER DERATING (dBm) 1 Rating −0.3 V to +3.7 V −3.7 V to +0.3 V −0.3 V to VDD + 0.3 V POWER DERATING (dBm) Parameter Positive Supply Voltage (VDD) Range Negative Supply Voltage (VSS) Range Control Voltage (V1, V2) Range RF Input Power1 (VDD, V1, V2 = 3.3 V, VSS = −3.3 V, TA = 85°C, Frequency = 2 GHz) Through Path Termination Path Hot Switch Power Level (VDD = 3.3 V, TA = 85°C, Frequency = 2 GHz) Storage Temperature Range Channel Temperature Thermal Resistance (Channel to Package Bottom) Through Path Terminated Path MSL Rating ESD Sensitivity Human Body Model (HBM) Charged Device Model (CDM) ADRF5040 Data Sheet 19 GND 21 GND 20 RF2 22 GND 24 GND 23 RF1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 18 GND GND 1 GND 2 ADRF5040 GND 4 TOP VIEW (Not to Scale) 17 VDD 16 V1 GND 12 RF3 11 GND 10 13 GND GND 9 GND 6 RF4 8 15 V2 14 VSS GND 7 GND 5 PACKAGE BASE GND NOTES 1. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO THE RF/DC GROUND OF THE PRINTED CIRCUIT BOARD (PCB). 14290-005 RFC 3 Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1, 2, 4 to 7, 9, 10, 12, 13, 18, 19, 21, 22, 24 3 Mnemonic GND 8 RF4 11 RF3 14 15 16 17 20 VSS V2 V1 VDD RF2 23 RF1 RFC EPAD Description Ground. The package bottom has an exposed metal pad that must connect to the printed circuit board (PCB) RF/dc ground. See Figure 6 for the GND interface schematic. RF Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. RF4 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. RF3 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. Negative Supply Voltage Pin. Control Input Pin 2. See Table 2 and Table 6. Control Input Pin 1. See Table 2 and Table 6. Positive Supply Voltage. RF2 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. RF1 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line potential is not equal to 0 V dc. Exposed Pad. The exposed pad must be connected to the RF/dc ground of the PCB. Table 6. Truth Table V1 Low High Low High Digital Control Inputs V2 Low Low High High Signal Path State RFC to RF1 RFC to RF2 RFC to RF3 RFC to RF4 Rev. A | Page 6 of 14 Data Sheet ADRF5040 INTERFACE SCHEMATICS V1 14290-006 GND Figure 6. GND Interface Schematic Figure 8. V1 Interface Schematic 14290-007 VDD V2 14290-008 VDD Figure 7. V2 Interface Schematic Rev. A | Page 7 of 14 ADRF5040 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS INSERTION LOSS, RETURN LOSS, AND ISOLATION VDD = 3.3 V, VSS = −3.3 V, TCASE = 25°C, unless otherwise specified. 0 0 –0.5 INSERTION LOSS (dB) –1.0 RFC TO RFC TO RFC TO RFC TO –1.5 RF1 RF2 RF3 RF4 –2.0 –1.5 TCASE TCASE TCASE TCASE –2.0 4 6 8 10 12 FREQUENCY (GHz) –3.0 Figure 9. Insertion Loss vs. Frequency 0 2 4 6 8 10 12 FREQUENCY (GHz) 14290-012 2 14290-009 0 Figure 12. Insertion Loss vs. Frequency, RFC to RF1 On or RFC to RF4 On 0 0 –20 ISOLATION (dB) –0.5 –1.0 –1.5 = +105°C = +85°C = +25°C = –40°C 2 4 –60 RFC TO RF2 RFC TO RF3 RFC TO RF4 –80 6 8 10 12 FREQUENCY (GHz) –120 0 –20 –20 –40 –40 ISOLATION (dB) 0 RFC TO RF1 RFC TO RF3 RFC TO RF4 6 8 10 12 Figure 13. Isolation vs. Frequency, RFC to RF1 On 0 –80 4 FREQUENCY (GHz) Figure 10. Insertion Loss vs. Frequency, RFC to RF2 On or RFC to RF3 On –60 2 14290-013 –2.5 0 –40 –100 14290-010 TCASE TCASE TCASE TCASE –2.0 –100 –60 –80 RFC TO RF1 RFC TO RF2 RFC TO RF4 –100 –120 0 2 4 6 8 10 FREQUENCY (GHz) 12 14290-011 ISOLATION (dB) = +105°C = +85°C = +25°C = –40°C –2.5 –2.5 INSERTION LOSS (dB) –1.0 Figure 11. Isolation vs. Frequency, RFC to RF2 On –120 0 2 4 6 8 10 FREQUENCY (GHz) Figure 14. Isolation vs. Frequency, RFC to RF3 On Rev. A | Page 8 of 14 12 14290-014 INSERTION LOSS (dB) –0.5 Data Sheet ADRF5040 VDD = 3.3 V, VSS = −3.3 V, TCASE = 25°C, unless otherwise specified. 0 0 –20 –20 –60 –80 RFC TO RF1 RFC TO RF2 RFC TO RF3 –80 RF2 TO RF2 TO RF3 TO RF1 TO RF1 TO RF1 TO –100 –100 –120 0 2 4 6 8 10 12 FREQUENCY (GHz) Figure 15. Isolation vs. Frequency, RFC to RF4 On RF3 RF4 RF4 RF2 RF3 RF4 –140 14290-015 –120 0 2 4 6 8 10 12 FREQUENCY (GHz) Figure 17. Channel to Channel Isolation vs. Frequency, RFC to RF1 On 0 0 –5 –5 –10 RETURN LOSS (dB) –10 –15 –20 –25 RFC –30 –15 –20 –25 –30 CH1, CH2, CH3 AND CH4 (OFF) CH1, CH2, CH3 AND CH4 (ON) –35 –35 –40 0 2 4 6 8 10 FREQUENCY (GHz) 12 Figure 16. Return Loss vs. Frequency, RFC to RF4 On –45 0 2 4 6 8 10 FREQUENCY (GHz) Figure 18. Return Loss vs. Frequency, RFC to RF4 On Rev. A | Page 9 of 14 12 14290-018 –40 14290-016 RETURN LOSS (dB) –60 14290-017 ISOLATION (dB) ISOLATION (dB) –40 –40 ADRF5040 Data Sheet INPUT POWER COMPRESSION AND INPUT THIRD-ORDER INTERCEPT 44 44 42 42 0.1dB COMPRESSION POINT (dBm) 40 38 36 34 32 30 +85°C +25°C –40°C 28 26 36 34 32 3.6V 3.3V 3V 30 28 2 3 4 5 6 7 8 9 10 11 12 24 FREQUENCY (GHz) 0 42 1dB COMPRESSION POINT (dBm) 44 42 36 34 32 30 +85°C +25°C –40°C 28 3 4 5 6 7 8 9 10 11 12 Figure 22. 0.1 dB Compression Point vs. Frequency over Voltage, TCASE = 25°C 44 38 2 FREQUENCY (GHz) Figure 19. 0.1 dB Compression Point vs. Frequency over Temperature, VDD = 3.3 V, VSS = −3.3 V 40 1 14290-022 1 14290-019 0 26 40 38 36 34 32 3.6V 3.3V 3V 30 28 26 0 1 2 3 4 5 6 7 8 9 10 11 24 14290-020 24 12 FREQUENCY (GHz) 0 60 60 IIP3 (dBm) 65 TCASE = +85°C TCASE = +25°C TCASE = –40°C 2 4 6 8 10 12 FREQUENCY (GHz) Figure 21. Input Third-Order Intercept (IIP3) vs. Frequency over Temperature, VDD = 3.3 V, VSS = −3.3 V 5 6 7 8 9 10 11 12 3.6V 3.3V 3V 45 14290-021 0 4 55 50 45 3 Figure 23. 1 dB Compression Point vs. Frequency over Voltage, TCASE = 25°C 65 50 2 FREQUENCY (GHz) Figure 20. 1 dB Compression Point vs. Frequency over Temperature, VDD = 3.3 V, VSS = −3.3 V 55 1 14290-023 1dB COMPRESSION POINT (dBm) 38 26 24 IIP3 (dBm) 40 0 2 4 6 FREQUENCY (GHz) 8 10 12 14290-024 0.1dB COMPRESSION POINT (dBm) VDD = 3.3 V, VSS = −3.3 V, TCASE = 25°C, unless otherwise specified. Figure 24. Input Third-Order Intercept (IIP3) vs. Frequency over Voltage, TCASE = 25°C Rev. A | Page 10 of 14 Data Sheet ADRF5040 INPUT POWER COMPRESSION AND INPUT THIRD-ORDER INTERCEPT, 10 kHz TO 1 GHz 45 70 40 65 60 35 55 IIP3 (dBm) 30 25 20 15 45 40 30 5 25 0.1 1 10 100 FREQUENCY (MHz) 1k Figure 25. Input Compression Point vs. Frequency 20 0.01 0.1 1 10 100 FREQUENCY (MHz) Figure 26. Input Third-Order Intercept (IIP3) vs. Frequency Rev. A | Page 11 of 14 1k 14290-026 0 0.01 50 35 0.1dB COMPRESSION POINT 1dB COMPRESSION POINT 10 14290-025 INPUT COMPRESSION POINT (dBm) VDD = 3.3 V, VSS = −3.3 V at TCASE = 25°C. ADRF5040 Data Sheet THEORY OF OPERATION The ADRF5040 requires a positive supply voltage applied to the VDD pin and a negative voltage supply applied to the VSS pin. Bypassing capacitors are recommended on the supply lines to minimize RF coupling. The ADRF5040 is controlled via two digital control voltages applied to the V1 pin and the V2 pin. A small value bypassing capacitor is recommended on these digital signal lines to improve the RF signal isolation. The ADRF5040 is internally matched to 50 Ω at the RF input port (RFC) and the RF output ports (RF1, RF2, RF3, and RF4); therefore, no external matching components are required. The RF1 through RF4 pins are dc-coupled, and dc blocking capacitors are required on the RF paths. The design is bidirectional; the input and outputs are interchangeable. The ADRF5040 does not need any special power-up sequencing, and the relative order to power up the VDD and VSS supplies is not important. The V1 and V2 control signals can be applied only after VDD is powered up; this sequence avoids forward biasing and causing damage to the internal ESD protection circuits. Turn on the RF signal after the device supply settles to a steady state. Rev. A | Page 12 of 14 Data Sheet ADRF5040 APPLICATIONS INFORMATION EVALUATION BOARD leads and backside ground slug must be connected directly to the ground plane. The evaluation board is available from Analog Devices, Inc. upon request. The ADRF5040-EVALZ evaluation board shown in Figure 27 is designed using proper RF circuit design techniques. Signal lines at the RF port have 50 Ω impedance, and the package ground J4 RF2 V1 C6 J1 GND C1 U1 RFC VDD V2 RF4 RF3 VSS J3 14290-027 J2 THRU CAL RF1 600-00598-00-3 J5 Figure 27. Evaluation PCB Table 7. Bill of Materials for the ADRF5040-EVALZ Evaluation Board Item J1 to J5 TP1 to TP5 C1, C6 U1 PCB Description PC mount SMA RF connectors Through hole mount test points 100 pF capacitors, 0402 package ADRF5040 SP4T switch 600-00598-00-3 evaluation PCB, Rogers 4350 circuit board material Rev. A | Page 13 of 14 ADRF5040 Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.18 1 18 0.50 BSC 2.85 2.70 SQ 2.55 EXPOSED PAD 13 TOP VIEW PKG-004926/PKG-004866 0.90 0.85 0.80 0.50 0.40 0.30 6 12 7 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR 24 19 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8. 05-25-2016-B PIN 1 INDICATOR 4.10 4.00 SQ 3.90 Figure 28. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.85 mm Package Height (CP-24-16) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADRF5040BCPZ Temperature Range −40°C to +85°C MSL Rating 2 MSL3 Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP] Package Option CP-24-16 ADRF5040BCPZ-R7 −40°C to +85°C MSL3 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-16 ADRF5040-EVALZ Evaluation Board These models are RoHS Compliant Parts. See the Absolute Maximum Ratings section. 3 XXXXX is the 5-digit lot number. 1 2 ©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D14290-0-2/17(A) Rev. A | Page 14 of 14 Branding 3 ADRF 5040 # XXXXX ADRF 5040 # XXXXX