MB9A110K Series
32-bit ARM® Cortex®-M3
FM3 Microcontroller
The MB9A110K Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and
low cost.
These series are based on the ARM® Cortex®-M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions
such as Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I2C, LIN).
The products which are described in this datasheet are placed into TYPE5 product categories in "FM3 Family Peripheral Manual".
Features
32-bit ARM® Cortex®-M3 Core
Multi-function Serial Interface (Max 4 channels)
Processor version: r2p1
2 channels with 16-steps × 9-bits FIFO (ch.0, ch.1),
2 channels without FIFO (ch.3, ch.5)
Up to 40 MHz Frequency Operation
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task
management
Operation mode is selectable from the followings for each
channel.
(In ch.5, only UART and LIN are available.)
UART
CSIO
LIN
I2 C
On-chip Memories
[UART]
[Flash memory]
Full-duplex double buffer
This Series are based on two independent on-chip Flash
memories.
Selection with or without parity supported
Built-in dedicated baud rate generator
MainFlash
Up
to 128 KB
Read cycle: 0 wait-cycle
Security function for code protection
External clock available as a serial clock
Hardware Flow control: Automatically control the
transmission by CTS/RTS (only ch.4)
WorkFlash
32
KB
cycle: 0 wait-cycle
Security function is shared with code protection
Read
Various error detect functions available (parity errors,
framing errors, and overrun errors)
[CSIO]
[SRAM]
Full-duplex double buffer
This Series contain a total of up to 16 KB on-chip SRAM. This
is composed of two independent SRAM (SRAM0, SRAM1).
SRAM0 is connected to I-code bus and D-code bus of CortexM3 core. SRAM1 is connected to System bus.
Built-in dedicated baud rate generator
Overrun error detect function available
SRAM0: 8 KB
SRAM1: 8 KB
Cypress Semiconductor Corporation
Document Number: 002-05627 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 22, 2017
MB9A110K Series
[LIN]
General Purpose I/O Port
LIN protocol Rev.2.1 supported
This series can use its pins as General Purpose I/O ports
when they are not used for external bus or peripherals.
Moreover, the port relocate function is built in. It can set which
I/O port the peripheral function can be allocated.
Full-duplex double buffer
Master/Slave mode supported
LIN break field generate (can be changed 13 to 16-bit
length)
LIN break delimiter generate (can be changed 1 to 4-bit
length)
Various error detect functions available (parity errors,
framing errors, and overrun errors)
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up 36 fast General Purpose I/O Ports
Some pin is 5 V tolerant I/O.
See "Pin Description" to confirm the corresponding pins.
[I2C]
Standard mode (Max 100 kbps) / Fast-mode (Max 400 kbps)
supported
DMA Controller (4 channels)
DMA Controller has an independent bus for CPU, so CPU and
DMA Controller can process simultaneously.
8 independently configured and operated channels
Transfer can be started by software or request from the builtin peripherals
Transfer address area: 32-bit (4 GB)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Multi-function Timer
The Multi-function timer is composed of the following blocks.
16-bit free-run timer × 3 ch.
Input capture × 4 ch.
Output compare × 6 ch.
A/D activating compare × 3 ch.
Waveform generator × 3 ch.
16-bit PPG timer × 3 ch.
The following function can be used to achieve the motor
control.
Transfer data type: byte/half-word/word
PWM signal output function
Transfer block count: 1 to 16
DC chopper waveform output function
Number of transfers: 1 to 65536
Dead time function
A/D Converter (Max 8 channels)
Input capture function
[12-bit A/D Converter]
A/D convertor activate function
Successive Approximation Register type
DTIF (Motor emergency stop) interrupt function
Built-in 2 unit
Real-time clock (RTC)
Conversion time: 1.0 μs @ 5 V
Priority conversion available (priority at 2 levels)
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
Scanning conversion mode
Interrupt function with specifying date and time
Built-in FIFO for conversion data storage
(for SCAN conversion: 16 steps, for Priority conversion:
4 steps)
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
Timer interrupt function after set time or each set time.
Base Timer (Max 8 channels)
Operation mode is selectable from the followings for each
channel.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
Document Number: 002-05627 Rev. *B
Page 2 of 81
MB9A110K Series
Quadrature Position/Revolution Counter (QPRC)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use up/down counter.
The detection edge of the three external event input pins
Clock and Reset
[Clocks]
Five clock sources (2 external oscillators, 2 internal CR
oscillator, and Main PLL) that are dynamically selectable.
Main Clock:
4 MHz to 48 MHz
16-bit position counter
Sub Clock:
32.768 kHz
16-bit revolution counter
High-speed internal CR Clock: 4 MHz
Two 16-bit compare registers
Low-speed internal CR Clock: 100 kHz
AIN, BIN and ZIN is configurable.
Main PLL Clock
Dual Timer (32/16-bit Down Counter)
The Dual Timer consists of two programmable 32/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
[Resets]
Reset requests from INITX pin
Power on reset
Free-running
Software reset
Periodic (=Reload)
Watchdog timers reset
One-shot
Low-voltage detector reset
Clock supervisor reset
Watch Counter
The Watch counter is used for wake up from Low Power
Consumption mode.
Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
External Interrupt Controller Unit
Up to 6 external interrupt input pin
Include one non-maskable interrupt (NMI)
Watchdog Timer (2 channels)
Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to
supervise abnormality of the external clocks.
External OSC clock failure (clock stop) is detected, reset is
asserted.
External OSC frequency anomaly is detected, interrupt or
reset is asserted.
Low-Voltage Detector (LVD)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This Series include 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage has been set,
Low-Voltage Detector generates an interrupt or reset.
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
LVD1: error reporting via interrupt
"Hardware" watchdog timer is clocked by low-speed internal
CR oscillator. Therefore, ”Hardware" watchdog is active in any
power saving mode except RTC and STOP and Deep standby RTC and Deep stand-by STOP.
LVD2: auto-reset operation
CRC (Cyclic Redundancy Check) Accelerator
Low Power Consumption Mode
Six Low Power Consumption modes supported.
SLEEP
The CRC accelerator helps a verify data transmission or
storage integrity.
TIMER
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
STOP
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
RTC
Deep stand-by RTC
Deep stand-by STOP
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Power Supply
Wide range voltage: VCC = 2.7 V to 5.5 V
Document Number: 002-05627 Rev. *B
Page 3 of 81
MB9A110K Series
Contents
1. Product Lineup .................................................................................................................................................................. 6
2. Packages ........................................................................................................................................................................... 7
3. Pin Assignment ................................................................................................................................................................. 8
4. List of Pin Functions....................................................................................................................................................... 11
5. I/O Circuit Type................................................................................................................................................................ 21
6. Handling Precautions ..................................................................................................................................................... 26
6.1
Precautions for Product Design ................................................................................................................................... 26
6.2
Precautions for Package Mounting .............................................................................................................................. 27
6.3
Precautions for Use Environment ................................................................................................................................ 28
7. Handling Devices ............................................................................................................................................................ 29
8. Block Diagram ................................................................................................................................................................. 31
9. Memory Size .................................................................................................................................................................... 31
10. Memory Map .................................................................................................................................................................... 32
11. Pin Status in Each CPU State ........................................................................................................................................ 35
12. Electrical Characteristics ............................................................................................................................................... 40
12.1 Absolute Maximum Ratings ......................................................................................................................................... 40
12.2 Recommended Operating Conditions.......................................................................................................................... 42
12.3 DC Characteristics....................................................................................................................................................... 43
12.3.1 Current Rating .............................................................................................................................................................. 43
12.3.2 Pin Characteristics ....................................................................................................................................................... 46
12.4 AC Characteristics ....................................................................................................................................................... 47
12.4.1 Main Clock Input Characteristics .................................................................................................................................. 47
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 48
12.4.3 Internal CR Oscillation Characteristics ......................................................................................................................... 48
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL) .................................................. 49
12.4.5 Operating Conditions of Main PLL (In the case of using high-speed internal CR)........................................................ 49
12.4.6 Reset Input Characteristics .......................................................................................................................................... 50
12.4.7 Power-on Reset Timing................................................................................................................................................ 50
12.4.8 Base Timer Input Timing .............................................................................................................................................. 51
12.4.9 CSIO/UART Timing ...................................................................................................................................................... 52
12.4.10 External Input Timing ................................................................................................................................................ 60
12.4.11 Quadrature Position/Revolution Counter timing ........................................................................................................ 61
12.4.12 I2C Timing ................................................................................................................................................................. 63
12.4.13 JTAG Timing ............................................................................................................................................................. 64
12.5 12-bit A/D Converter .................................................................................................................................................... 65
12.6 Low-Voltage Detection Characteristics ........................................................................................................................ 68
12.6.1 Low-Voltage Detection Reset ....................................................................................................................................... 68
12.6.2 Interrupt of Low-voltage Detection ............................................................................................................................... 68
12.7 MainFlash Memory Write/Erase Characteristics .......................................................................................................... 69
12.7.1 Write / Erase time......................................................................................................................................................... 69
12.7.2 Erase/write cycles and data hold time .......................................................................................................................... 69
12.8 WorkFlash Memory Write/Erase Characteristics ......................................................................................................... 69
12.8.1 Write / Erase time......................................................................................................................................................... 69
12.8.2 Erase/write cycles and data hold time .......................................................................................................................... 69
12.9 Return Time from Low-Power Consumption Mode ...................................................................................................... 70
12.9.1 Return Factor: Interrupt/WKUP .................................................................................................................................... 70
12.9.2 Return Factor: Reset .................................................................................................................................................... 72
Document Number: 002-05627 Rev. *B
Page 4 of 81
MB9A110K Series
13. Ordering Information ...................................................................................................................................................... 74
14. Package Dimensions ...................................................................................................................................................... 75
15. Major Changes ................................................................................................................................................................ 78
Document History ................................................................................................................................................................. 80
Sales, Solutions, and Legal Information ............................................................................................................................. 81
Document Number: 002-05627 Rev. *B
Page 5 of 81
MB9A110K Series
1. Product Lineup
Memory Size
Product name
On-chip
Flash memory
On-chip SRAM
MB9AF111K
MB9AF112K
MainFlash
64 KB
128 KB
WorkFlash
32 KB
32 KB
SRAM0
8 KB
8 KB
SRAM1
8 KB
8 KB
16 KB
16 KB
Total
Function
Product name
Pin count
CPU
Freq.
Power supply voltage range
DMAC
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
Base Timer
(PWC/ Reload timer/PWM/PPG)
A/D activation
3 ch.
compare
Input capture
4 ch.
Free-run timer
3 ch.
MFOutput
Timer
6 ch.
compare
Waveform
3 ch.
generator
PPG
3 ch.
QPRC
Dual Timer
Real-time clock
Watch Counter
CRC Accelerator
Watchdog timer
External Interrupts
General Purpose I/O ports
12-bit A/D converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
High-speed
Built-in OSC
Low-speed
Debug Function
MB9AF111K
MB9AF112K
48/52
Cortex-M3
40 MHz
2.7 V to 5.5 V
4 ch. (Max)
4 ch. (Max)
with 16-steps × 9-bits FIFO: ch.0, ch.1
without FIFO: ch.3, ch.5 (In ch.5, only UART and LIN are available.)
8 ch. (Max)
1 unit (Max)
1 ch. (Max)
1 unit
1 unit
1 unit
Yes
1 ch. (SW) + 1 ch. (HW)
6 pins (Max) + NMI × 1
36 pins (Max)
8 ch. (2 units)
Yes
2 ch.
4 MHz
100 kHz
SWJ-DP
Note:
−
All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the General I/O port according to your function use.
See “12. Electrical Characteristics 12.4. AC Characteristics 12.4.3. Internal CR Oscillation Characteristics” for accuracy of
built-in CR.
Document Number: 002-05627 Rev. *B
Page 6 of 81
MB9A110K Series
2. Packages
Product name
Package
MB9AF111K
MB9AF112K
LQFP: LQA048 (0.5 mm pitch)
QFN:
VNA048 (0.5 mm pitch)
LQFP: LQC052 (0.65 mm pitch)
: Supported
Note:
−
See “14. Package Dimensions” for detailed information on each package.
Document Number: 002-05627 Rev. *B
Page 7 of 81
MB9A110K Series
3. Pin Assignment
LQA048
VSS
P81
P80
VCC
P60/SIN5_0/TIOA2_2/INT15_1/IC00_0/WKUP3
P61/SOT5_0/TIOB2_2/UHCONX/DTTI0X_2
P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
48
47
46
45
44
43
42
41
40
39
38
37
(TOP VIEW)
VCC
1
36
P21/SIN0_0/INT06_1/WKUP2
P50/INT00_0/AIN0_2/SIN3_1
2
35
P22/AN07/SOT0_0/TIOB7_1
P51/INT01_0/BIN0_2/SOT3_1
3
34
P23/AN06/SCK0_0/TIOA7_1
P52/INT02_0/ZIN0_2/SCK3_1
4
33
AVSS
P39/DTTI0X_0/ADTG_2
5
32
AVRH
P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2
6
31
AVCC
P3B/RTO01_0/TIOA1_1
7
30
P15/AN05/SOT0_1/IC03_2
P3C/RTO02_0/TIOA2_1
8
29
P14/AN04/SIN0_1/INT03_1/IC02_2
P3D/RTO03_0/TIOA3_1
9
28
P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1
P3E/RTO04_0/TIOA4_1
10
27
P12/AN02/SOT1_1/IC00_2
P3F/RTO05_0/TIOA5_1
11
26
P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0/WKUP1
VSS
12
25
P10/AN00
13
14
15
16
17
18
19
20
21
22
23
24
C
VCC
P46/X0A
P47/X1A
INITX
P49/TIOB0_0
P4A/TIOB1_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP - 48
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin.
Document Number: 002-05627 Rev. *B
Page 8 of 81
MB9A110K Series
VNA048
VSS
P81
P80
VCC
P60/SIN5_0/TIOA2_2/INT15_1/IC00_0/WKUP3
P61/SOT5_0/TIOB2_2/UHCONX/DTTI0X_2
P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
48
47
46
45
44
43
42
41
40
39
38
37
(TOP VIEW)
VCC
1
36
P21/SIN0_0/INT06_1/WKUP2
P50/INT00_0/AIN0_2/SIN3_1
2
35
P22/AN07/SOT0_0/TIOB7_1
P51/INT01_0/BIN0_2/SOT3_1
3
34
P23/AN06/SCK0_0/TIOA7_1
P52/INT02_0/ZIN0_2/SCK3_1
4
33
AVSS
P39/DTTI0X_0/ADTG_2
5
32
AVRH
P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2
6
31
AVCC
P3B/RTO01_0/TIOA1_1
7
30
P15/AN05/SOT0_1/IC03_2
P3C/RTO02_0/TIOA2_1
8
29
P14/AN04/SIN0_1/INT03_1/IC02_2
P3D/RTO03_0/TIOA3_1
9
28
P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1
P3E/RTO04_0/TIOA4_1
10
27
P12/AN02/SOT1_1/IC00_2
P3F/RTO05_0/TIOA5_1
11
26
P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0/WKUP1
VSS
12
25
P10/AN00
13
14
15
16
17
18
19
20
21
22
23
24
C
VCC
P46/X0A
P47/X1A
INITX
P49/TIOB0_0
P4A/TIOB1_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
QFN - 48
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin.
Document Number: 002-05627 Rev. *B
Page 9 of 81
MB9A110K Series
LQC052
VSS
P81
P80
VCC
P60/SIN5_0/TIOA2_2/INT15_1/IC00_0/WKUP3
P61/SOT5_0/TIOB2_2/UHCONX/DTTI0X_2
P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
NC
52
51
50
49
48
47
46
45
44
43
42
41
40
(TOP VIEW)
VCC
1
39
P21/SIN0_0/INT06_1/WKUP2
P50/INT00_0/AIN0_2/SIN3_1
2
38
P22/AN07/SOT0_0/TIOB7_1
P51/INT01_0/BIN0_2/SOT3_1
3
37
P23/AN06/SCK0_0/TIOA7_1
P52/INT02_0/ZIN0_2/SCK3_1
4
36
NC
NC
5
35
AVSS
P39/DTTI0X_0/ADTG_2
6
34
AVRH
P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2
7
33
AVCC
P3B/RTO01_0/TIOA1_1
8
32
P15/AN05/SOT0_1/IC03_2
P3C/RTO02_0/TIOA2_1
9
31
P14/AN04/SIN0_1/INT03_1/IC02_2
P3D/RTO03_0/TIOA3_1
10
30
P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1
P3E/RTO04_0/TIOA4_1
11
29
P12/AN02/SOT1_1/IC00_2
P3F/RTO05_0/TIOA5_1
12
28
P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0/WKUP1
VSS
13
27
P10/AN00
14
15
16
17
18
19
20
21
22
23
24
25
26
C
VCC
P46/X0A
P47/X1A
INITX
P49/TIOB0_0
P4A/TIOB1_0
NC
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP - 52
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin.
Document Number: 002-05627 Rev. *B
Page 10 of 81
MB9A110K Series
4. List of Pin Functions
List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR)
to select the pin.
Pin No
LQFP-48
QFN-48
1
Pin Name
LQFP-52
1
I/O circuit
type
Pin state
type
-
VCC
P50
2
2
INT00_0
AIN0_2
I*1
H
I*1
H
I*1
H
SIN3_1
P51
3
3
INT01_0
BIN0_2
SOT3_1
P52
4
4
INT02_0
ZIN0_2
SCK3_1
-
5
-
NC
P39
5
6
DTTI0X_0
E
I
G
I
G
I
G
I
G
I
G
I
ADTG_2
P3A
RTO00_0
6
7
TIOA0_1
RTCCO_2
SUBOUT_2
P3B
7
8
RTO01_0
TIOA1_1
P3C
8
9
RTO02_0
TIOA2_1
P3D
9
10
RTO03_0
TIOA3_1
P3E
10
11
RTO04_0
TIOA4_1
Document Number: 002-05627 Rev. *B
Page 11 of 81
MB9A110K Series
Pin No
LQFP-48
QFN-48
Pin Name
LQFP-52
I/O circuit
type
Pin state
type
G
I
P3F
11
12
RTO05_0
TIOA5_1
12
13
VSS
-
13
14
14
15
C
-
15
16
16
17
17
18
18
19
19
20
-
21
20
22
21
23
22
24
23
25
24
26
25
27
VCC
P46
X0A
P47
X1A
INITX
P49
TIOB0_0
P4A
TIOB1_0
D
M
D
N
B
C
E
I
E
I
-
NC
PE0
MD1
MD0
PE2
X0
PE3
X1
C
P
J
D
A
A
A
B
-
VSS
P10
AN00
F
K
F
F
F
K
P11
AN01
SIN1_1
26
28
INT02_1
FRCK0_2
IC02_0
WKUP1
P12
27
29
AN02
SOT1_1
IC00_2
Document Number: 002-05627 Rev. *B
Page 12 of 81
MB9A110K Series
Pin No
LQFP-48
QFN-48
Pin Name
LQFP-52
I/O circuit
type
Pin state
type
F
K
F
L
F
K
P13
AN03
28
30
SCK1_1
IC01_2
RTCCO_1
SUBOUT_1
P14
AN04
29
31
SIN0_1
INT03_1
IC02_2
30
32
31
32
33
-
33
34
35
36
34
37
35
38
36
39
-
40
37
41
38
42
39
43
40
44
41
45
Document Number: 002-05627 Rev. *B
P15
AN05
SOT0_1
IC03_2
AVCC
AVRH
AVSS
NC
P23
AN06
SCK0_0
TIOA7_1
P22
AN07
SOT0_0
TIOB7_1
P21
SIN0_0
INT06_1
WKUP2
NC
P00
TRSTX
P01
TCK
SWCLK
P02
TDI
P03
TMS
SWDIO
P04
TDO
SWO
F
K
F
K
E
G
-
E
E
E
E
E
E
E
E
E
E
Page 13 of 81
MB9A110K Series
Pin No
LQFP-48
QFN-48
Pin Name
LQFP-52
42
46
43
47
44
48
45
46
47
48
49
50
51
52
P0F
NMIX
CROUT_1
RTCCO_0
SUBOUT_0
WKUP0
P61
SOT5_0
TIOB2_2
UHCONX
DTTI0X_2
P60
SIN5_0
TIOA2_2
INT15_1
IC00_0
WKUP3
VCC
P80
P81
VSS
I/O circuit
type
Pin state
type
E
J
E
I
I[1]
G
H
H
O
O
-
*1: 5 V tolerant I/O
Document Number: 002-05627 Rev. *B
Page 14 of 81
MB9A110K Series
List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR)
to select the pin.
Module
ADC
Base Timer
0
Base Timer
1
Base Timer
2
Base Timer
3
Base Timer
4
Base Timer
5
Base Timer
7
Debugger
External
Interrupt
Pin name
Function
Pin No
LQFP-48
LQFP-52
QFN-48
5
6
25
27
26
28
27
29
28
30
29
31
30
32
34
37
35
38
6
7
18
19
7
8
19
20
8
9
44
48
43
47
ADTG_2
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
TIOA0_1
TIOB0_0
TIOA1_1
TIOB1_0
TIOA2_1
TIOA2_2
TIOB2_2
A/D converter external trigger input pin
TIOA3_1
Base timer ch.3 TIOA pin
9
10
TIOA4_1
Base timer ch.4 TIOA pin
10
11
TIOA5_1
Base timer ch.5 TIOA pin
11
12
TIOA7_1
TIOB7_1
SWCLK
SWDIO
SWO
TCK
TDI
TDO
TMS
TRSTX
INT00_0
INT01_0
INT02_0
INT02_1
INT03_1
INT06_1
INT15_1
NMIX
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
Serial wire debug interface clock input pin
Serial wire debug interface data input/output pin
Serial wire viewer output pin
JTAG test clock input pin
JTAG test data input pin
JTAG debug data output pin
JTAG test mode state input/output pin
JTAG test reset Input pin
External interrupt request 00 input pin
External interrupt request 01 input pin
34
35
38
40
41
38
39
41
40
37
2
3
4
26
29
36
44
42
37
38
42
44
45
42
43
45
44
41
2
3
4
28
31
39
48
46
Document Number: 002-05627 Rev. *B
A/D converter analog input pin.
ANxx describes ADC ch.xx.
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
External interrupt request 02 input pin
External interrupt request 03 input pin
External interrupt request 06 input pin
External interrupt request 15 input pin
Non-Maskable Interrupt input pin
Page 15 of 81
MB9A110K Series
Module
GPIO
Pin name
P00
P01
P02
P03
P04
P0F
P10
P11
P12
P13
P14
P15
P21
P22
P23
P39
P3A
P3B
P3C
P3D
P3E
P3F
P46
P47
P49
P4A
P50
P51
P52
P60
P61
P80
P81
PE0
PE2
PE3
Document Number: 002-05627 Rev. *B
Function
General-purpose I/O port 0
General-purpose I/O port 1
General-purpose I/O port 2
General-purpose I/O port 3
General-purpose I/O port 4
General-purpose I/O port 5
General-purpose I/O port 6
General-purpose I/O port 8
General-purpose I/O port E
Pin No
LQFP-48
LQFP-52
QFN-48
37
41
38
42
39
43
40
44
41
45
42
46
25
27
26
28
27
29
28
30
29
31
30
32
36
39
35
38
34
37
5
6
6
7
7
8
8
9
9
10
10
11
11
12
15
16
16
17
18
19
19
20
2
2
3
3
4
4
44
48
43
47
46
50
47
51
20
22
22
24
23
25
Page 16 of 81
MB9A110K Series
Module
Multi- function
Serial
0
Pin name
SIN0_0
SIN0_1
SOT0_0
(SDA0_0)
SOT0_1
(SDA0_1)
SCK0_0
(SCL0_0)
Multi- function
Serial
1
SIN1_1
SOT1_1
(SDA1_1)
SCK1_1
(SCL1_1)
Multi- function
Serial
3
SIN3_1
SOT3_1
(SDA3_1)
SCK3_1
(SCL3_1)
Multi- function
Serial
5
SIN5_0
SOT5_0
Document Number: 002-05627 Rev. *B
Function
Multi-function serial interface ch.0 input pin
Multi-function serial interface ch.0 output pin.
This pin operates as SOT0 when it is used in a
UART/CSIO/LIN (operation modes
0 to 3) and as SDA0 when it is used in an I2C (operation
mode 4).
Multi-function serial interface ch.0 clock I/O pin.
This pin operates as SCK0 when it is used in a CSIO
(operation modes 2) and as SCL0 when it is used in an
I2C (operation mode 4).
Multi-function serial interface ch.1 input pin
Multi-function serial interface ch.1 output pin.
This pin operates as SOT1 when it is used in a
UART/CSIO/LIN (operation modes
0 to 3) and as SDA1 when it is used in an I2C (operation
mode 4).
Multi-function serial interface ch.1 clock I/O pin.
This pin operates as SCK1 when it is used in a CSIO
(operation modes 2) and as SCL1 when it is used in an
I2C (operation mode 4).
Multi-function serial interface ch.3 input pin
Multi-function serial interface ch.3 output pin.
This pin operates as SOT3 when it is used in a
UART/CSIO/LIN (operation modes
0 to 3) and as SDA3 when it is used in an I2C (operation
mode 4).
Multi-function serial interface ch.3 clock I/O pin.
This pin operates as SCK3 when it is used in a CSIO
(operation modes 2) and as SCL3 when it is used in an
I2C (operation mode 4).
Multi-function serial interface ch.5 input pin
Multi-function serial interface ch.5 output pin.
This pin operates as SOT5 when it is used in a
UART/LIN (operation modes 0, 1, 3).
Pin No.
LQFP-48
LQFP-52
QFN-48
36
39
29
31
35
38
30
32
34
37
26
28
27
29
28
30
2
2
3
3
4
4
44
48
43
47
Page 17 of 81
MB9A110K Series
Module
Multi- function
Timer
0
Pin name
DTTI0X_0
DTTI0X_2
FRCK0_2
IC00_0
IC00_2
IC01_2
IC02_0
IC02_2
IC03_2
RTO00_0
(PPG00_0)
RTO01_0
(PPG00_0)
RTO02_0
(PPG02_0)
RTO03_0
(PPG02_0)
RTO04_0
(PPG04_0)
RTO05_0
(PPG04_0)
Document Number: 002-05627 Rev. *B
Function
Input signal controlling wave form generator outputs
RTO00 to RTO05 of multi-function timer 0.
16-bit free-run timer ch.0 external clock input pin
16-bit input capture ch.0 input pin of multi-function
timer 0.
ICxx describes channel number.
Wave form generator output pin of multi-function timer
0.
This pin operates as PPG00 when it is used in PPG0
output modes.
Wave form generator output pin of multi-function timer
0.
This pin operates as PPG00 when it is used in PPG0
output modes.
Wave form generator output pin of multi-function timer
0.
This pin operates as PPG02 when it is used in PPG0
output modes.
Wave form generator output pin of multi-function timer
0.
This pin operates as PPG02 when it is used in PPG0
output modes.
Wave form generator output pin of multi-function timer
0.
This pin operates as PPG04 when it is used in PPG0
output modes.
Wave form generator output pin of multi-function timer
0.
This pin operates as PPG04 when it is used in PPG0
output modes.
Pin No
LQFP-48
LQFP-52
QFN-48
5
6
43
26
44
27
28
26
29
30
47
28
48
29
30
28
31
32
6
7
7
8
8
9
9
10
10
11
11
12
Page 18 of 81
MB9A110K Series
Module
Quadrature
Position/
Revolution
Counter
0
Real-time clock
Pin name
Function
AIN0_2
QPRC ch.0 AIN input pin
2
2
BIN0_2
QPRC ch.0 BIN input pin
3
3
ZIN0_2
QPRC ch.0 ZIN input pin
4
4
42
28
6
42
28
6
42
26
36
44
46
30
7
46
30
7
46
28
39
48
RTCCO_0
RTCCO_1
0.5 seconds pulse output pin of Real-time clock pin
RTCCO_2
SUBOUT_0
SUBOUT_1
Sub clock output pin
SUBOUT_2
Low Power
Consumption
Mode
Pin No
LQFP-48
LQFP-52
QFN-48
WKUP0
Deep stand-by mode return signal input pin 0
WKUP1
Deep stand-by mode return signal input pin 1
WKUP2
Deep stand-by mode return signal input pin 2
WKUP3
Deep stand-by mode return signal input pin 3
Document Number: 002-05627 Rev. *B
Page 19 of 81
MB9A110K Series
Module
Reset
Pin name
VCC
VCC
VCC
VSS
VSS
VSS
X0
X0A
X1
X1A
CROUT_1
Built-in high-speed CR-osc clock output port
42
46
AVCC
A/D converter analog power pin
31
33
AVRH
A/D converter analog reference voltage input pin
32
34
AVSS
A/D converter GND pin
33
35
C
Power stabilization capacity pin
13
14
NC
NC pin.
NC pin should be kept open.
-
5
NC
NC pin.
NC pin should be kept open.
-
21
NC
NC pin.
NC pin should be kept open.
-
36
NC
NC pin.
NC pin should be kept open.
-
40
MD0
MD1
GND
Clock
Analog
Power
Analog
GND
C pin
NC pin
Pin No
LQFP-48
LQFP-52
QFN-48
External Reset Input.
A reset is valid when INITX="L".
Mode 0 pin.
During normal operation, MD0="L" must be input.
During serial programming to Flash memory, MD0="H"
must be input.
Mode 1 pin.
During serial programming to Flash memory, MD1="L"
must be input.
Power supply Pin
Power supply Pin
Power supply Pin
GND Pin
GND Pin
GND Pin
Main clock (oscillation) input pin
Sub clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) I/O pin
INITX
Mode
Power
Function
17
18
21
23
20
22
1
14
45
12
24
48
22
15
23
16
1
15
49
13
26
52
24
16
25
17
Note:
−
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant
to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in
other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 002-05627 Rev. *B
Page 20 of 81
MB9A110K Series
5. I/O Circuit Type
Type
A
Circuit
Remarks
It is possible to select the main
oscillation / GPIO function
Pull-up
When the main oscillation is
selected.
resistor
P-ch
P-ch
Digital output
−
X1
Oscillation feedback resistor
: Approximately 1 MΩ
−
N-ch
Digital output
R
Pull-up resistor control
Digital input
Standby mode Control
With Standby mode control
When the GPIO is selected.
−
CMOS level output.
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
: Approximately 50 kΩ
−
IOH = -4 mA, IOL = 4 mA
−
CMOS level hysteresis input
−
Pull-up resistor
Clock input
Feedback
resistor
Standby mode Control
Digital input
Standby mode Control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0
Pull-up resistor control
B
: Approximately 50 kΩ
Pull-up resistor
Digital input
Document Number: 002-05627 Rev. *B
Page 21 of 81
MB9A110K Series
Type
C
Circuit
Remarks
Digital input
−
Open drain output
−
CMOS level hysteresis input
Digital output
N-ch
D
It is possible to select the sub
oscillation / GPIO function
Pull-up
When the sub oscillation is
selected.
resistor
P-ch
P-ch
Digital output
−
X1A
Oscillation feedback resistor
: Approximately 5 MΩ
−
N-ch
Digital output
R
Pull-up resistor control
Digital input
Standby mode Control
With Standby mode control
When the GPIO is selected.
−
CMOS level output.
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
: Approximately 50 kΩ
−
IOH = -4 mA, IOL = 4 mA
Clock input
Feedback
resistor
Standby mode Control
Digital input
Standby mode Control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0A
Pull-up resistor control
Document Number: 002-05627 Rev. *B
Page 22 of 81
MB9A110K Series
Type
E
Circuit
P-ch
P-ch
Remarks
−
CMOS level output
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
Digital output
: Approximately 50 kΩ
−
IOH = -4 mA, IOL = 4 mA
−
When this pin is used as an I2C
pin, the digital output
N-ch
P-ch transistor is always off
Digital output
R
−
+B input is available
−
CMOS level output
−
CMOS level hysteresis input
−
With input control
−
Analog input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
Pull-up resistor control
Digital input
Standby mode Control
F
P-ch
P-ch
Digital output
: Approximately 50 kΩ
N-ch
Digital output
−
IOH = -4 mA, IOL = 4 mA
−
When this pin is used as an I2C
pin, the digital output
P-ch transistor is always off
−
R
+B input is available
Pull-up resistor control
Digital input
Standby mode Control
Analog input
Input control
Document Number: 002-05627 Rev. *B
Page 23 of 81
MB9A110K Series
Type
G
Circuit
P-ch
P-ch
N-ch
Remarks
−
CMOS level output
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
: Approximately 50 kΩ
Digital output
−
IOH = -12 mA, IOL = 12 mA
−
+B input is available
−
CMOS level output
−
CMOS level hysteresis input
−
With standby mode control
−
IOH = -20.5 mA, IOL = 18.5 mA
Digital output
R
Pull-up resistor control
Digital input
Standby mode Control
H
P-ch
N-ch
Digital output
Digital output
R
Digital input
Standby mode Control
Document Number: 002-05627 Rev. *B
Page 24 of 81
MB9A110K Series
Type
I
Circuit
P-ch
P-ch
Remarks
Digital output
−
CMOS level output
−
CMOS level hysteresis input
−
5 V tolerant
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
: Approximately 50 kΩ
N-ch
−
IOH = -4 mA, IOL = 4 mA
−
Available to control of PZR registers.
Digital output
R
Pull-up resistor control
Digital input
Standby mode Control
CMOS level hysteresis input
J
Mode input
Document Number: 002-05627 Rev. *B
Page 25 of 81
MB9A110K Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute maximum ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended operating conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the datasheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and protection of pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and
input/output functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess
of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of safety regulations and standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-safe design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Document Number: 002-05627 Rev. *B
Page 26 of 81
MB9A110K Series
Precautions related to usage of devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising
from such use without prior approval.
6.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead insertion type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board,
or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be
subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to
Cypress recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface mount type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily
deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open
connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-free packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction
strength may be reduced under some conditions of use.
Storage of semiconductor devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption
of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel,
reducing moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Document Number: 002-05627 Rev. *B
Page 27 of 81
MB9A110K Series
Static electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following
precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level
of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
6.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-05627 Rev. *B
Page 28 of 81
MB9A110K Series
7. Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each Power supply pins and GND pins of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pins
and GND pins, between AVCC pin and AVSS pin near this device.
Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended
operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that
the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC
value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a
momentary fluctuation on switching the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as
possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Using an external clock
When using an external clock, the clock signal should be input to the X0, X0A pin only and the X1, X1A pin should be kept open.
Example of Using an External Clock
Device
X0(X0A)
Open
X1(X1A)
Handling when using Multi-function serial pin as I2C pin
If it is using Multi-function serial pin as I2C pins, P-ch transistor of digital output is always disable. However, I 2C pins need to keep
the electrical characteristic like other pins and not to connect to external I2C bus system with power OFF.
Document Number: 002-05627 Rev. *B
Page 29 of 81
MB9A110K Series
C pin
This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation
(F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to
use by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7 μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance
stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
NC pins
NC pin should be kept open.
Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter, connect AVCC =VCC and AVSS = VSS.
Turning on: VCC → AVCC → AVRH
Turning off: AVRH → AVCC → VCC
Serial communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the
end. If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between Flash products and
MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics
among the products with different memory sizes and between Flash products and MASK products are different because chip
layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Pull-up function of 5 V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O.
Document Number: 002-05627 Rev. *B
Page 30 of 81
MB9A110K Series
8. Block Diagram
MB9AF111K, F112K
TRSTX,TCK,
TDI,TMS
TDO
SRAM0
8 Kbyte
SWJ-DP
ROM
Table
SRAM1
8 Kbyte
Multi-layer AHB (Max 42 MHz)
Cortex-M3 Core I
@40 MHz(Max)
D
NVIC
Sys
AHB-APB Bridge:
APB0(Max 42 MHz)
Dual-Timer
Watchdog Timer
(Software)
Clock Reset
Generator
INITX
Watchdog Timer
(Hardware)
MainFlash I/F
Security
MainFlash
64 Kbyte/
128 Kbyte
WorkFlash I/F
WorkFlash
32 Kbyte
DMAC
4ch.
CSV
X0
X1
X0A
Main
Osc
Sub
Osc
PLL
AHB-AHB
Bridge
CLK
Source Clock
CR
4MHz
CR
100kHz
CROUT
AVCC,
AVSS,
AVRH
12-bit A/D Converter
Unit 0
Power-On
Reset
AN[07:00]
Unit 1
LVD Ctrl
ADTG_2
AIN0
BIN0
ZIN0
QPRC
1ch.
A/D Activation Compare
3ch.
IC0x
FRCKx
16-bit Input Capture
4ch.
16-bit Free-Run Timer
3ch.
16-bit Output Compare
6ch.
DTTI0X
RTOx
Deep Standby Ctrl
AHB-APB Bridge : APB2 (Max 42 MHz)
TIOBx
Base Timer
16-bit 8ch./
32-bit 4ch.
AHB-APB Bridge : APB1 (Max 42 MHz)
TIOAx
LVD
Regulator
Waveform Generator
3ch.
16-bit PPG
3ch.
Multi-Function Timer
C
WKUP[3:0]
RTCCO,
SUBOUT
Real-Time Clock
IRQ-Monitor
CRC
Accelerator
Watch Counter
External Interrupt
Controller
6-pin + NMI
INTx
NMIX
MODE-Ctrl
GPIO
Multi-Function Serial I/F
4ch.
(with FIFO ch.0 - ch.1)
MD[1:0]
PIN-Function-Ctrl
P0x,
P1x,
.
.
.
PFx
SCKx
SINx
SOTx
9. Memory Size
See “Memory size” in “1. Product Lineup” to confirm the memory size.
Document Number: 002-05627 Rev. *B
Page 31 of 81
MB9A110K Series
10. Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0x4006_1000
0x4006_0000
DMAC
0xFFFF_FFFF
Reserved
Reserved
0xE010_0000
0xE000_0000
Cortex-M3 Private
Peripherals
Reserved
0x4003_C000
0x4003_B000
RTC
0x4003_A000
Watch Counter
0x4003_9000
CRC
0x4003_8000
MFS
0x7000_0000
External Device
Area
0x6000_0000
Reserved
0x4400_0000
0x4200_0000
32Mbyte
Bit band alias
Peripherals
0x4000_0000
Reserved
0x4003_6000
0x4003_5000
LVD/DS mode
0x4003_4000
Reserved
0x4003_3000
GPIO
0x4003_2000
Reserved
0x4003_1000
Int-Req. Read
0x4003_0000
EXTI
0x4002_F000
Reserved
CR Trim
0x4002_E000
Reserved
0x2400_0000
0x4002_7000
Reserved
A/DC
0x4002_6000
QPRC
Reserved
0x4002_5000
Base Timer
WorkFlash I/F
WorkFlash
Reserved
0x4002_4000
PPG
0x2000_0000
SRAM1
0x4002_1000
0x1FFF_0000
SRAM0
0x4002_0000
MFT unit0
0x4001_6000
Reserved
Dual Timer
0x2200_0000
0x200E_1000
0x200E_0000
0x200C_0000
0x2008_0000
See the next page
"Memory Map (2)" for
the memory size
details.
32Mbyte
Bit band alias
0x4002_8000
Reserved
0x0010_2000
0x0010_0000
0x4001_5000
Security/CR Trim
MainFlash
0x0000_0000
Document Number: 002-05627 Rev. *B
Reserved
0x4001_3000
0x4001_2000
Reserved
SW WDT
0x4001_1000
HW WDT
0x4001_0000
Clock/Reset
0x4000_1000
Reserved
0x4000_0000
MainFlash I/F
Page 32 of 81
MB9A110K Series
Memory Map (2)
MB9AF112K
MB9AF111K
0x200E_0000
0x200E_0000
Reserved
Reserved
0x200C_8000
SA0-3 (8KBx4)
0x200C_0000
WorkFlash
32Kbyte
SA0-3 (8KBx4)
WorkFlash
32Kbyte
0x200C_8000
0x200C_0000
Reserved
Reserved
0x2000_2000
0x2000_2000
SRAM1
8Kbyte
0x2000_0000
0x2000_0000
SRAM0
8Kbyte
0x1FFF_E000
0x1FFF_E000
Reserved
SRAM1
8Kbyte
SRAM0
8Kbyte
Reserved
0x0010_2000
0x0010_2000
0x0010_1000
CR trimming
0x0010_0000
Security
0x0010_1000
CR trimming
0x0010_0000
Security
Reserved
Reserved
0x0002_0000
SA4-7 (8KBx4)
0x0001_0000
SA8-9 (16KBx2)
0x0000_0000
MainFlash
64Kbyte
0x0000_0000
MainFlash
128Kbyte
SA8-9 (48KBx2)
SA4-7 (8KBx4)
See "MB9A310K/110K Series Flash programming Manual" for sector structure of Flash.
Document Number: 002-05627 Rev. *B
Page 33 of 81
MB9A110K Series
Peripheral Address Map
Start address
End address
Bus
Peripherals
0x4000_0000
0x4000_0FFF
0x4000_1000
0x4000_FFFF
0x4001_0000
0x4001_0FFF
Clock/Reset Control
0x4001_1000
0x4001_1FFF
Hardware Watchdog timer
0x4001_2000
0x4001_2FFF
0x4001_3000
0x4001_4FFF
0x4001_5000
0x4001_5FFF
Dual-Timer
0x4001_6000
0x4001_FFFF
Reserved
0x4002_0000
0x4002_0FFF
Multi-function timer unit0
0x4002_1000
0x4002_3FFF
Reserved
0x4002_4000
0x4002_4FFF
PPG
0x4002_5000
0x4002_5FFF
0x4002_6000
0x4002_6FFF
0x4002_7000
0x4002_7FFF
A/D Converter
0x4002_8000
0x4002_DFFF
Reserved
0x4002_E000
0x4002_EFFF
Internal CR trimming
0x4002_F000
0x4002_FFFF
Reserved
0x4003_0000
0x4003_0FFF
External Interrupt Controller
0x4003_1000
0x4003_1FFF
Interrupt Request Batch-Read Function
0x4003_2000
0x4003_2FFF
Reserved
0x4003_3000
0x4003_3FFF
GPIO
0x4003_4000
0x4003_4FFF
Reserved
0x4003_5000
0x4003_57FF
0x4003_5800
0x4003_5FFF
0x4003_6000
0x4003_7FFF
Reserved
0x4003_8000
0x4003_8FFF
Multi-function serial Interface
0x4003_9000
0x4003_9FFF
CRC
0x4003_A000
0x4003_AFFF
Watch Counter
0x4003_B000
0x4003_BFFF
Real-time clock
0x4003_C000
0x4003_FFFF
Reserved
0x4004_0000
0x4005_FFFF
Reserved
0x4006_0000
0x4006_0FFF
0x4006_1000
0x41FF_FFFF
0x200E_0000
0x200E_FFFF
Document Number: 002-05627 Rev. *B
AHB
APB0
MainFlash I/F register
Reserved
Software Watchdog timer
Reserved
Base Timer
APB1
Quadrature Position/Revolution Counter
Low Voltage Detector
APB2
AHB
Deep stand-by mode Controller
DMAC register
Reserved
WorkFlash I/F register
Page 34 of 81
MB9A110K Series
11. Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the "L" level.
INITX=1
This is the period when the INITX pin is the "H" level.
SPL=0
This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to "0".
SPL=1
This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to "1".
Input enabled
Indicates that the input function can be used.
Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
Hi-Z
Indicates that the output drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
GPIO selected
In Deep stand-by mode, pins switch to the general-purpose I/O port.
Document Number: 002-05627 Rev. *B
Page 35 of 81
MB9A110K Series
Pin status type
List of Pin Status
Function
group
Power-on
reset or
low-voltage
detection
state
Power
supply
unstable
-
INITX
input
state
Device
internal
reset
state
Power supply stable
INITX = 0
-
INITX = 1
-
Run
mode or
sleep
mode
state
Power
supply
stable
INITX = 1
-
Timer mode,
RTC mode, or
sleep mode state
Deep stand-by
RTC mode or Deep
stand-by STOP
mode state
Power supply
stable
Power supply
stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL = 1
Return
from
Deep
stand-by
mode
state
Power
supply
stable
INITX = 1
-
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Main crystal
oscillator
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
Maintain
previous
state /
When
oscillation
stop*1,
Hi-Z/
Internal
input
fixed
at "0"
Maintain
previous
state /
When
oscillation
stop*1,
Hi-Z/
Internal
input
fixed
at "0"
Maintain
previous
state /
When
oscillation
stop*1,
HiZ/Internal
input
fixed
at "0"
Maintain
previous
state /
When
oscillation
stop*1,
Hi-Z/
Internal
input fixed
at "0"
A
GPIO
selected
Setting
disabled
Setting
disabled
Main crystal
oscillator
output pin
Hi-Z/
Internal input
fixed at "0"/
or Input
enable
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state /
When
oscillation
stop*1,
Hi-Z/
Internal
input fixed
at "0"
C
INITX
input pin
Pull-up / Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
D
Mode
input pin
Input enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
JTAG
selected
Hi-Z
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
B
E
GPIO
selected
Setting
disabled
Document Number: 002-05627 Rev. *B
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Page 36 of 81
Pin status type
MB9A110K Series
Function
group
Power-on
reset or
low-voltage
detection
state
Power
supply
unstable
-
WKUP
enabled
Analog
input
selected
Device
internal
reset
state
Power supply stable
Run
mode or
sleep
mode
state
Power
supply
stable
INITX = 1
-
Timer mode,
RTC mode, or
sleep mode state
Deep stand-by
RTC mode or Deep
stand-by STOP
mode state
Power supply
stable
Power supply
stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL = 1
INITX = 0
-
INITX = 1
-
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
WKUP
input
enabled
Hi-Z
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
F
External
interrupt
enabled
selected
Resource
other than
above
selected
INITX
input
state
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
GPIO
selected
WKUP
enabled
G
External
interrupt
enabled
selected
Resource
other than
above
selected
Setting
disabled
Setting
disabled
Setting
disabled
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z
GPIO
selected
H
External
interrupt
enabled
selected
Resource
other than
above
selected
Setting
disabled
Hi-Z
GPIO
selected
Document Number: 002-05627 Rev. *B
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Setting
disabled
Setting
disabled
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input
fixed
at "0"
GPIO
selected
Hi-Z /
WKUP
input
enabled
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
WKUP
input
enabled
GPIO
selected
Maintain
previous
state
Power
supply
stable
INITX = 1
GPIO
selected
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
GPIO
selected
Maintain
previous
state
Hi-Z /
WKUP
input
enabled
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
GPIO
selected
Return
from
Deep
stand-by
mode
state
GPIO
selected
GPIO
selected
Maintain
previous
state
Hi-Z /
Internal
input
fixed
at "0"
GPIO
selected
Maintain
previous
state
Page 37 of 81
Pin status type
MB9A110K Series
Function
group
Power-on
reset or
low-voltage
detection
state
Power
supply
unstable
-
GPIO
selected
NMIX
selected
J
Resource
other than
above
selected
L
External
interrupt
enabled
selected
Resource
other than
above
selected
Power supply
stable
Power supply
stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL = 1
Power
supply
stable
INITX = 1
-
GPIO
selected
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0"
GPIO
selected
Maintain
previous
state
WKUP
input
enabled
Hi-Z /
WKUP
input
enabled
Hi-Z
Hi-Z /
Input
enabled
Maintain
previous
state
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z
Hi-Z
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0"
GPIO
selected
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Hi-Z
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
GPIO
selected
Analog
input
selected
Deep stand-by
RTC mode or Deep
stand-by STOP
mode state
Hi-Z /
Input
enabled
Power supply stable
Maintain
previous
state
Setting
disabled
GPIO
selected
Document Number: 002-05627 Rev. *B
Setting
disabled
Setting
disabled
Maintain
previous
state
Return
from
Deep
stand-by
mode
state
Timer mode,
RTC mode, or
sleep mode state
INITX = 1
-
K
Resource
other than
above
selected
Run
mode or
sleep
mode
state
INITX = 0
-
GPIO
selected
Analog
input
selected
Device
internal
reset
state
Power
supply
stable
INITX = 1
-
Resource
selected
I
INITX
input
state
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0"
GPIO
selected
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
GPIO
selected
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0" /
Analog
input
enabled
Hi-Z /
Internal
input
fixed at
"0"
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
GPIO
selected
Maintain
previous
state
Hi-Z /
Internal
input fixed
at "0" /
Analog
input
enabled
GPIO
selected
Maintain
previous
state
Page 38 of 81
Pin status type
MB9A110K Series
Function
group
Power-on
reset or
low-voltage
detection
state
Power
supply
unstable
-
INITX
input
state
Device
internal
reset
state
Power supply stable
INITX = 0
-
INITX = 1
-
Run
mode or
sleep
mode
state
Power
supply
stable
INITX = 1
-
Timer mode,
RTC mode, or
sleep mode state
Deep stand-by
RTC mode or Deep
stand-by STOP
mode state
Power supply
stable
Power supply
stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL = 1
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
Input
enabled
Input
enabled
Input
enabled
Input
enabled
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Sub crystal
oscillator
input pin
Input enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
M
P
Setting
disabled
Sub crystal
oscillator
output pin
Hi-Z/
Internal input
fixed at "0"/
or Input
enable
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at "0"
Maintain
previous
state
Maintain
previous
state
/When
oscillation
stop*2, HiZ/
Internal
input fixed
at "0"
GPIO
selected
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
Maintain
previous
state
Mode
input pin
Input enabled
Input
enabled
Input
enabled
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Input
enabled
Maintain
previous
state
Input
enabled
Maintain
previous
state
N
O
Setting
disabled
Power
supply
stable
INITX = 1
-
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Return
from
Deep
stand-by
mode
state
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
/When
oscillation
stop*2, HiZ/ Internal
input
fixed
at "0"
Hi-Z /
Internal
input
fixed
at "0"
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
Maintain
previous
state
/When
oscillation
stop*2, HiZ/ Internal
input
fixed
at "0"
Maintain
previous
state
Input
enabled
Maintain
previous
state
Hi-Z /
Internal
input
fixed at
"0"
Maintain
previous
state
/When
oscillation
stop*2, HiZ/ Internal
input
fixed
at "0"
Hi-Z /
Internal
input
fixed
at "0"
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
Maintain
previous
state
/When
oscillation
stop*2, HiZ/ Internal
input fixed
at "0"
Maintain
previous
state
Input
enabled
Maintain
previous
state
*1: Oscillation is stopped at sub timer mode, low-speed CR timer mode, RTC mode, stop mode, deep stand-by RTC mode, and
deep stand-by stop mode.
*2: Oscillation is stopped at stop mode and deep stand-by stop mode
Document Number: 002-05627 Rev. *B
Page 39 of 81
MB9A110K Series
12. Electrical Characteristics
12.1 Absolute Maximum Ratings
Parameter
Power supply voltage*1, *2
voltage*1, *3
Symbol
Rating
Unit
Min
Max
Vcc
Vss - 0.5
Vss + 6.5
V
AVcc
Vss - 0.5
Vss + 6.5
V
Analog reference voltage*1, *3
AVRH
Vss - 0.5
V
Input voltage
VI
Vss + 6.5
Vcc + 0.5
(≤ 6.5 V)
Vss + 6.5
AVcc + 0.5
(≤ 6.5 V)
Vcc + 0.5
(≤ 6.5 V)
+2
+20
10
20
39
4
12
18.5
100
50
- 10
- 20
- 39
-4
- 12
- 20.5
- 100
- 50
300
+ 150
Analog power supply
Vss - 0.5
Vss - 0.5
Analog pin input voltage
VIA
Vss - 0.5
Output voltage
VO
Vss - 0.5
Clamp maximum current
Clamp total maximum current
ICLAMP
Σ[ICLAMP]
"L" level maximum output current*4
IOL
-
"L" level average output current*5
IOLAV
-
"L" level total maximum output current
"L" level total average output current*6
∑IOL
∑IOLAV
-
"H" level maximum output current*4
IOH
-
"H" level average output current*5
IOHAV
-
"H" level total maximum output current
"H" level total average output current*6
Power consumption
Storage temperature
∑IOH
∑IOHAV
PD
TSTG
-2
- 55
Remarks
V
V
5 V tolerant
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
°C
*7
*7
4 mA type
12 mA type
P80, P81
4 mA type
12 mA type
P80, P81
4 mA type
12 mA type
P80, P81
4 mA type
12 mA type
P80, P81
*1: These parameters are based on the condition that VSS = AVSS = 0.0 V.
*2: Vcc must not drop below VSS - 0.5 V.
*3: Ensure that the voltage does not to exceed Vcc + 0.5 V, for example, when the power is turned on.
*4: The maximum output current is the peak value for a single pin.
*5: The average output is the average current for a single pin over a period of 100 ms.
*6: The total average output current is the average current for all pins over a period of 100 ms.
Document Number: 002-05627 Rev. *B
Page 40 of 81
MB9A110K Series
*7:
•
•
•
•
•
•
•
•
See "4. List of Pin Functions" and "5. I/O Circuit Type" about +B input available pin.
Use within recommended operating conditions.
Use at DC voltage (current) the +B input.
The +B signal should always be applied a limiting resistance placed between the +B signal and the device.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin
does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the device drive current is low, such as in the low-power consumption modes, the +B input potential may
pass through the protective diode and increase the potential at the VCC and AVCC pin, and this may affect other devices.
Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is provided from the
pins, so that incomplete operation may result.
The following is a recommended circuit example (I/O equivalent circuit).
Protection Diode
VCC
VCC
Limiting
resistor
P-ch
+B input (0V to 16V)
Digital output
N-ch
Digital input
R
AVCC
Analog input
WARNING:
−
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess
of absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-05627 Rev. *B
Page 41 of 81
MB9A110K Series
12.2 Recommended Operating Conditions
(Vss = AVss = 0.0 V)
Parameter
Symbol
Conditions
Value
Unit
Min
Max
5.5
V
Power supply voltage
Vcc
-
2.7*2
Analog power supply voltage
AVcc
-
2.7
5.5
V
Analog reference voltage
AVRH
-
2.7
AVcc
V
Smoothing capacitor
CS
-
1
10
μF
Operating temperature
TA
-
- 40
+ 105
°C
Remarks
AVcc=Vcc
For built-in
regulator*1
*1: See "C Pin" in "7. Handling Devices" for the connection of the smoothing capacitor.
*2: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage
or more, instruction execution and low voltage detection function by built-in High-speed CR (including Main PLL is used)
or built-in Low-speed CR is possible to operate only.
WARNING:
−
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges
may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating
conditions, or combinations not represented on the datasheet. Users considering application outside the listed conditions are
advised to contact their representatives beforehand.
Document Number: 002-05627 Rev. *B
Page 42 of 81
MB9A110K Series
12.3 DC Characteristics
12.3.1 Current Rating
(Vcc = AVcc = 2.7 V to 5.5 V, Vss = AVss = 0 V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin
name
Conditions
PLL
RUN mode
RUN
mode
current
Icc
High-speed
CR
RUN mode
VCC
Sub
RUN mode
Low-speed
CR
RUN mode
SLEEP
mode
current
Iccs
PLL
SLEEP mode
High-speed
CR
SLEEP mode
Sub
SLEEP mode
Low-speed
CR
SLEEP mode
CPU: 40 MHz,
Peripheral: 40 MHz,
MainFlash 0 Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
CPU: 40 MHz,
Peripheral: 40 MHz,
MainFlash 3 Wait
FRWTR.RWT = 00
FSYNDN.SD = 011
Value
Typ*3
Max*4
Unit
Remarks
32
41
mA
*1, *5
21
28
mA
*1, *5
3.9
7.7
mA
*1
0.15
3.2
mA
*1, *6
0.2
3.3
mA
*1
Peripheral: 40 MHz
10
15
mA
*1, *5
Peripheral: 4 MHz*2
1.2
4.4
mA
*1
Peripheral: 32 kHz
0.1
3.1
mA
*1, *6
Peripheral: 100 kHz
0.1
3.1
mA
*1
CPU/ Peripheral: 4 MHz*2
MainFlash 0 Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
CPU/ Peripheral: 32 kHz
MainFlash 0 Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
CPU/ Peripheral: 100 kHz
MainFlash 0 Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
*1: When all ports are input and are fixed at "0".
*2: When setting it to 4 MHz by trimming.
*3: TA=+25°C, VCC=5.5 V
*4: TA=+105°C, VCC=5.5 V
*5: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit)
Document Number: 002-05627 Rev. *B
Page 43 of 81
MB9A110K Series
(Vcc = AVcc = 2.7 V to 5.5 V, USBVcc = 3.0 V to 3.6 V, Vss = AVss = 0 V, TA = - 40°C to + 105°C)
Parameter
TIMER
mode
current
Symbol
Pin
name
Conditions
Main
TIMER
mode
ICCT
Sub
TIMER
mode
RTC
mode
current
ICCR
STOP
mode
current
ICCH
RTC mode
STOP mode
VCC
ICCRD
Deep
stand-by
RTC mode
Deep
stand-by
mode
current
ICCHD
Deep
stand-by
STOP mode
TA = + 25°C,
When LVD is off
TA = + 105°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 105°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 105°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 105°C,
When LVD is off
TA = + 25°C,
When LVD is off
RAM hold off
TA = + 25°C,
When LVD is off
RAM hold on
TA = + 105°C,
When LVD is off
RAM hold off
TA = + 105°C,
When LVD is off
RAM hold on
TA = + 25°C,
When LVD is off
RAM hold off
TA = + 25°C,
When LVD is off
RAM hold on
TA = + 105°C,
When LVD is off
RAM hold off
TA = + 105°C,
When LVD is off
RAM hold on
Value
Typ*2
Max*2
Unit
Remarks
5.2
6
mA
*1, *3
-
9
mA
*1, *3
60
230
μA
*1, *4
-
3.1
mA
*1, *4
50
210
μA
*1, *4
-
3.1
mA
*1, *4
35
200
μA
*1
-
3
mA
*1
30
160
μA
*1, *4
33
160
mA
*1, *4
-
600
μA
*1
-
610
mA
*1
20
150
μA
*1, *4
23
150
mA
*1, *4
-
600
μA
*1
-
610
mA
*1
*1: When all ports are input and are fixed at "0".
*2: VCC=5.5 V
*3: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit)
*4: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit)
Document Number: 002-05627 Rev. *B
Page 44 of 81
MB9A110K Series
Low-voltage detection current
(VCC = 2.7 V to 5.5 V, VSS = 0 V, TA = - 40°C to + 105°C)
Parameter
Low-voltage detection
circuit (LVD) power
supply current
Symbol
ICCLVD
Pin
name
VCC
Conditions
At operation
for interrupt
Vcc = 5.5 V
Value
Typ
Max
4
7
Unit
μA
Remarks
At not detect
Flash memory current
(VCC = 2.7 V to 5.5 V, VSS = 0 V, TA = - 40°C to + 105°C)
Parameter
Flash memory
write/erase
Current
Symbol
ICCFLASH
Pin
name
VCC
Conditions
MainFlash
At Write/Erase
WorkFlash
At Write/Erase
Value
Unit
Typ
Max
11.4
13.1
mA
11.4
13.1
mA
Remarks
A/D converter current
(VCC = AVCC = 2.7 V to 5.5 V, VSS = AVSS = AVRL = 0 V, TA = - 40°C to + 105°C)
Parameter
Power supply current
Reference power
supply current
Symbol
ICCAD
ICCAVRH
Pin
name
Conditions
Unit
Max
At 1 unit operation
0.57
0.72
mA
At stop
0.06
20
μA
1.1
1.96
mA
0.06
4
μA
Remarks
AVCC
AVRH
At 1 unit operation
AVRH=5.5 V
At stop
Document Number: 002-05627 Rev. *B
Value
Typ
Page 45 of 81
MB9A110K Series
12.3.2 Pin Characteristics
(Vcc = AVcc = 2.7 V to 5.5 V, Vss = AVss = 0 V, TA = - 40°C to + 105°C)
Parameter
Symbol
"H" level input
voltage
(hysteresis
input)
VIHS
"L" level
input
voltage
(hysteresis
input)
VILS
Pin name
CMOS
hysteresis
input pin,
MD0, MD1
5V tolerant
input pin
CMOS
hysteresis
input pin,
MD0, MD1
5V tolerant
input pin
VOH
12mA
type
12mA type
P80/P81
Input leak current
IIL
Pull-up resistance
value
RPU
Input capacitance
CIN
Unit
-
Vcc + 0.3
V
-
Vcc × 0.8
-
Vss + 5.5
V
-
Vss - 0.3
-
Vcc × 0.2
V
-
Vss - 0.3
-
Vcc × 0.2
V
Vcc - 0.5
-
Vcc
V
Vcc - 0.5
-
Vcc
V
Vcc - 0.4
-
Vcc
V
Vss
-
0.4
V
Vss
-
0.4
V
Vss
-
0.4
V
-5
-
+5
μA
Vcc ≥ 4.5 V
25
50
100
Vcc < 4.5 V
30
80
200
-
5
15
Vcc ≥ 4.5 V
IOH = - 20.5 mA
Vcc < 4.5 V
IOH = - 13.0 mA
Vcc ≥ 4.5 V
IOL = 4 mA
Vcc < 4.5 V
IOL = 2 mA
Vcc ≥ 4.5 V
IOL = 12 mA
Vcc < 4.5 V
IOL = 8 mA
Vcc ≥ 4.5 V
IOL = 18.5 mA
Vcc< 4.5 V
IOL = 10.5 mA
Pull-up pin
Other than
VCC,
VSS,
AVCC,
AVSS, AVRH
Document Number: 002-05627 Rev. *B
Max
Vcc × 0.8
Vcc < 4.5 V
IOH = - 8 mA
4mA type
VOL
Value
Typ
Remarks
Vcc < 4.5 V
IOH = - 2 mA
Vcc ≥ 4.5 V
IOH = - 12 mA
P80/P81
"L" level
output voltage
Min
-
Vcc ≥ 4.5 V
IOH = - 4 mA
4mA
type
"H" level
output voltage
Conditions
-
-
kΩ
pF
Page 46 of 81
MB9A110K Series
12.4 AC Characteristics
12.4.1 Main Clock Input Characteristics
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 105°C)
Parameter
Input frequency
Symbol
Pin
name
tCYLH
Input clock pulse width
-
Input clock rise time and
fall time
tCF,
tCR
Internal operating
clock frequency*1
Internal operating
clock cycle time*1
X0
X1
Value
Min
Max
4
4
4
4
20.83
50
48
20
48
20
250
250
45
-
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
PWH/tCYLH
PWL/tCYLH
FCH
Input clock cycle
Conditions
Unit
Remarks
MHz
When crystal oscillator is
connected
MHz
When using external clock
ns
When using external clock
55
%
When using external clock
-
5
ns
When using external clock
FCM
-
-
-
42
MHz
Master clock
FCC
-
-
-
42
MHz
Base clock (HCLK/FCLK)
FCP0
-
-
-
42
MHz
APB0 bus clock*2
FCP1
-
-
-
42
MHz
APB1 bus clock*2
FCP2
-
-
-
42
MHz
APB2 bus clock*2
tCYCC
tCYCP0
tCYCP1
tCYCP2
-
-
23.8
-
ns
Base clock (HCLK/FCLK)
-
-
23.8
-
ns
APB0 bus clock*2
-
-
23.8
-
ns
APB1 bus clock*2
-
-
23.8
-
ns
APB2 bus clock*2
*1: For more information about each internal operating clock, see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual".
*2: For about each APB bus which each peripheral is connected to, see "8. Block Diagram" in this datasheet.
X0
Document Number: 002-05627 Rev. *B
Page 47 of 81
MB9A110K Series
12.4.2 Sub Clock Input Characteristics
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 105°C)
Parameter
Input frequency
1/ tCYLL
Input clock cycle
tCYLL
Input clock pulse width
Pin
name
Symbol
Conditions
X0A
X1A
Value
Remarks
Typ
Max
-
-
32.768
-
kHz
-
32
-
100
kHz
When crystal oscillator is
connected
When using external clock
-
10
-
31.25
μs
When using external clock
45
-
55
%
When using external clock
PWH/tCYLL
PWL/tCYLL
-
Unit
Min
X0A
12.4.3 Internal CR Oscillation Characteristics
High-speed internal CR
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 105°C)
Parameter
Clock frequency
Symbol
FCRH
Conditions
Min
Typ
Max
TA = + 25°C
3.96
4
4.04
TA = 0°C to + 70°C
3.84
4
4.16
3.8
3
4
4
4.2
5
-
-
90
TA = - 40°C to + 85°C
TA = - 40°C to + 85°C
Frequency stability time
tCRWT
Value
-
Unit
MHz
Remarks
When trimming*1
When not trimming
μs
*2
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming.
*2: Frequency stable time is time to stable of the frequency of the High-speed CR clock after the trim value is set. After setting the
trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source clock.
Low-speed internal CR
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 105°C)
Parameter
Clock frequency
Symbol
FCRL
Document Number: 002-05627 Rev. *B
Conditions
-
Value
Min
Typ
Max
50
100
150
Unit
Remarks
kHz
Page 48 of 81
MB9A110K Series
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL)
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 105°C)
Parameter
Symbol
Value
Min
Typ
Max
Unit
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
FPLLI
FPLLO
FCLKPLL
4
13
200
-
-
16
75
300
40
MHz
multiple
MHz
MHz
Remarks
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual".
12.4.5 Operating Conditions of Main PLL (In the case of using high-speed internal CR)
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 105°C)
Parameter
Symbol
Value
Min
Typ
Max
Unit
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
FPLLI
FPLLO
FCLKPLL
3.8
50
190
-
4
-
4.2
71
300
42
MHz
multiple
MHz
MHz
Remarks
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual".
When setting PLL multiple rate, please take the accuracy of the built-in high-speed CR clock into account and prevent the
master clock from exceeding the maximum frequency.
Main PLL connection
Main clock (CLKMO)
High-speed CR clock (CLKHC)
K
divider
PLL input
clock
PLL macro
oscillation clock
Main
PLL
M
divider
Main PLL
clock
(CLKPLL)
N
divider
Document Number: 002-05627 Rev. *B
Page 49 of 81
MB9A110K Series
12.4.6 Reset Input Characteristics
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 105°C)
Parameter
Symbol
Reset input time
tINITX
Pin name
Value
Conditions
-
INITX
Min
Max
500
-
Unit
Remarks
ns
12.4.7 Power-on Reset Timing
(Vss = 0 V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin
Name
dV/dt
Power ramp rate
Time until releasing Power-on reset
VCC
Unit
Remarks
Min
Typ
Max
-
50
-
-
ms
*1
VCC: 0.2 V to 2.70 V
0.7
-
1000
mV/µs
*2
-
0.66
-
0.89
ms
tOFF
Power supply shut down time
Value
Conditions
tPRT
*1: VCC must be held below 0.2 V for a minimum period of tOFF. Improper initialization may occur if this condition is not met.
*2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>50 ms).
Note:
−
tOFF must be satisfied. When tOFF cannot be satisfied, assert external reset (INITX) at power-up and at any brownout event.
2.7V
VCC
VDH
0.2V
dV/dt
0.2V
tPRT
Internal RST
CPU Operation
RST Active
0.2V
tOFF
release
start
Glossary
VDH: detection voltage of Low-Voltage detection reset. See 12.6 Low-voltage Detection Characteristics.
Document Number: 002-05627 Rev. *B
Page 50 of 81
MB9A110K Series
12.4.8 Base Timer Input Timing
Timer input timing
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 105°C)
Parameter
Input pulse width
Symbol
tTIWH
tTIWL
Pin name
Conditions
TIOAn/TIOBn
(when using as ECK,
TIN)
-
tTIWH
Value
Min
Max
2tCYCP
-
Unit
Remarks
ns
tTIWL
ECK
VIHS
TIN
VIHS
VILS
VILS
Trigger input timing
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 105°C)
Parameter
Input pulse width
Symbol
tTRGH
tTRGL
Pin name
Conditions
TIOAn/TIOBn
(when using as
TGIN)
-
tTRGH
TGIN
VIHS
Value
Min
Max
2tCYCP
-
Unit
Remarks
ns
tTRGL
VIHS
VILS
VILS
Note:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Base Timer is connected to, see “8. Block Diagram" in this datasheet.
Document Number: 002-05627 Rev. *B
Page 51 of 81
MB9A110K Series
12.4.9 CSIO/UART Timing
CSIO (SPI = 0, SCINV = 0)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Baud rate
-
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK fall time
SCK rise time
tF
tR
Pin
name
SCKx
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
Conditions
-
Master mode
Slave mode
Vcc < 4.5 V
Min
Max
8
4tCYCP
-
Vcc ≥ 4.5 V
Min
Max
8
4tCYCP
-
Unit
Mbps
ns
-30
+30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram" in this datasheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance = 30 pF.
Document Number: 002-05627 Rev. *B
Page 52 of 81
MB9A110K Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
VIH
VIL
SIN
tSHIXI
VIH
VIL
Master mode
tSLSH
SCK
VIH
tF
SOT
SIN
VIL
tSHSL
VIL
VIH
VIH
tR
tSLOVE
VOH
VOL
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
Document Number: 002-05627 Rev. *B
Page 53 of 81
MB9A110K Series
CSIO (SPI = 0, SCINV = 1)
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin
name
Conditions
-
-
-
Vcc < 4.5 V
Min
Max
Vcc ≥ 4.5 V
Min
Max
Unit
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
Mbp
s
ns
SCK ↑ → SOT delay time
tSHOVI
SCKx
SOTx
-30
+30
- 20
+ 20
ns
SIN → SCK ↓ setup time
tIVSLI
50
-
30
-
ns
SCK ↓ → SIN hold time
tSLIXI
0
-
0
-
ns
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
SCK ↑ → SOT delay time
tSHOVE
-
50
-
30
ns
SIN → SCK ↓ setup time
tIVSLE
10
-
10
-
ns
SCK ↓ → SIN hold time
tSLIXE
20
-
20
-
ns
SCK fall time
SCK rise time
tF
tR
-
5
5
-
5
5
ns
ns
Baud rate
SCKx
SINx
SCKx
SINx
SCKx
SCKx
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
Master mode
Slave mode
-
8
-
8
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see “8. Block Diagram" in this datasheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance = 30 pF.
Document Number: 002-05627 Rev. *B
Page 54 of 81
MB9A110K Series
tSCYC
VOH
SCK
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
VIH
VIL
SIN
tSLIXI
VIH
VIL
Master mode
tSHSL
SCK
tSLSH
VIH
VIH
VIL
tR
VIL
tF
tSHOVE
SOT
SIN
VIL
VOH
VOL
tIVSLE
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
Document Number: 002-05627 Rev. *B
Page 55 of 81
MB9A110K Series
CSIO (SPI = 1, SCINV = 0)
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 105°C)
Parameter
Symbol
Baud rate
-
Pin
name
-
Serial clock cycle time
tSCYC
SCKx
SCK ↑ → SOT delay time
tSHOVI
SCKx
SOTx
SIN → SCK ↓ setup time
tIVSLI
SCK ↓ → SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓ → SIN hold time
tSLIXE
SCK fall time
SCK rise time
tF
tR
SCKx
SINx
SCKx
SINx
SCKx
SOTx
SCKx
SCKx
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
Conditions
-
Master mode
Slave mode
Vcc < 4.5 V
Min
Max
8
4tCYCP
-
Vcc ≥ 4.5 V
Min
Max
8
4tCYCP
-
Unit
Mbps
ns
-30
+30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 30
-
2tCYCP - 30
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see “8. Block Diagram” in this datasheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance = 30 pF.
Document Number: 002-05627 Rev. *B
Page 56 of 81
MB9A110K Series
tSCYC
VOH
VOL
SCK
SOT
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
VIH
VIL
Master mode
tSLSH
SCK
VIH
tR
VIH
tSHOVE
VOH
VOL
VOH
VOL
tIVSLE
SIN
VIH
VIL
tF
*
SOT
VIL
tSHSL
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
Document Number: 002-05627 Rev. *B
Page 57 of 81
MB9A110K Series
CSIO (SPI = 1, SCINV = 1)
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 105°C)
Parameter
Symbol
Baud rate
-
Pin
name
-
Serial clock cycle time
tSCYC
SCKx
SCK ↓ → SOT delay time
tSLOVI
SCKx
SOTx
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
SOT → SCK ↑ delay time
tSOVHI
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
SCK ↓→ SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK fall time
SCK rise time
tF
tR
SCKx
SINx
SCKx
SINx
SCKx
SOTx
SCKx
SCKx
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
Conditions
-
Master mode
Slave mode
Vcc < 4.5 V
Min
Max
8
4tCYCP
-
Vcc ≥ 4.5 V
Min
Max
8
4tCYCP
-
Unit
Mbps
ns
-30
+30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 30
-
2tCYCP - 30
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see “8. Block Diagram” in this datasheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance = 30 pF.
Document Number: 002-05627 Rev. *B
Page 58 of 81
MB9A110K Series
tSCYC
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
SOT
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VOH
VOL
VIH
VIL
Master mode
tSHSL
tR
SCK
tSLSH
VIH
VIH
VIL
tF
VIL
VIL
VIH
tSLOVE
VOH
VOL
SOT
VOH
VOL
tIVSHE
tSHIXE
VIH
VIL
SIN
VIH
VIL
Slave mode
UART external clock input (EXT = 1)
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 105°C)
Parameter
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK fall time
SCK rise time
Symbol
tSLSH
tSHSL
tF
tR
Conditions
CL = 30 pF
tR
SCK
VIL
Document Number: 002-05627 Rev. *B
Min
Max
Unit
tCYCP + 10
tCYCP + 10
-
5
5
ns
ns
ns
ns
tSHSL
VIH
tF
tSLSH
VIH
VIL
Remarks
VIL
VIH
Page 59 of 81
MB9A110K Series
12.4.10 External Input Timing
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Conditions
Value
Min
Max
Unit
ADTG
Input pulse width
tINH,
tINL
Remarks
A/D converter trigger input
FRCKx
ICxx
DTTIxX
INTxx
NMIX
*2
WKUPx
*4
-
2tCYCP*1
-
ns
-
2tCYCP*1
2tCYCP + 100*1
-
ns
ns
500
-
ns
External interrupt
NMI
820
-
ns
Deep stand-by wake up
*3
Free-run timer input clock
Input capture
Wave form generator
*1: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which A/D converter, Multi-function Timer, External interrupt are connected to, see
"8. Block Diagram" in this datasheet.
*2: When in Run mode, in Sleep mode.
*3: When in Stop mode, in RTC mode, in Timer mode.
*4: When in deep stand-by Stop mode, in deep stand-by RTC mode.
Document Number: 002-05627 Rev. *B
Page 60 of 81
MB9A110K Series
12.4.11 Quadrature Position/Revolution Counter timing
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 105°C)
Parameter
Symbol
AIN pin "H" width
AIN pin "L" width
BIN pin "H" width
BIN pin "L" width
BIN rise time from
AIN pin "H" level
AIN fall time from
BIN pin "H" level
BIN fall time from
AIN pin "L" level
AIN rise time from
BIN pin "L" level
AIN rise time from
BIN pin "H" level
BIN fall time from
AIN pin "H" level
AIN fall time from
BIN pin "L" level
BIN rise time from
AIN pin "L" level
ZIN pin "H" width
ZIN pin "L" width
AIN/BIN rise and fall time from
determined ZIN level
Determined ZIN level from AIN/BIN
rise and fall time
Value
Conditions
Min
Max
2tCYCP*1
-
Unit
-
tAHL
tALL
tBHL
tBLL
tAUBU
PC_Mode2 or PC_Mode3
tBUAD
PC_Mode2 or PC_Mode3
tADBD
PC_Mode2 or PC_Mode3
tBDAU
PC_Mode2 or PC_Mode3
tBUAU
PC_Mode2 or PC_Mode3
tAUBD
PC_Mode2 or PC_Mode3
tBDAD
PC_Mode2 or PC_Mode3
tADBU
PC_Mode2 or PC_Mode3
tZHL
tZLL
QCR:CGSC="0"
QCR:CGSC="0"
tZABE
QCR:CGSC="1"
tABEZ
QCR:CGSC="1"
ns
*1: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Quadrature Position/Revolution Counter is connected to, see “8. Block Diagram" in this
datasheet.
tALL
tAHL
AIN
tAUBU
tADBD
tBUAD
tBDAU
BIN
tBHL
Document Number: 002-05627 Rev. *B
tBLL
Page 61 of 81
MB9A110K Series
tBLL
tBHL
BIN
tBUAU
tBDAD
tAUBD
tADBU
AIN
tAHL
tALL
ZIN
ZIN
AIN/BIN
Document Number: 002-05627 Rev. *B
Page 62 of 81
MB9A110K Series
12.4.12 I2C Timing
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 105°C)
Parameter
SCL clock frequency
(Repeated) START condition hold time
SDA ↓→ SCL ↓
SCLclock "L" width
SCLclock "H" width
(Repeated) START setup time
SCL ↑→ SDA ↓
Data hold time
SCL ↓→ SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑→ SDA ↑
Bus free time between
"STOP condition" and
"START condition"
Noise filter
Symbol
Conditions
FSCL
Standard-mode
Min
Max
0
100
Fast-mode
Min
Max
0
400
Unit
kHz
tHDSTA
4.0
-
0.6
-
μs
tLOW
tHIGH
4.7
4.0
-
1.3
0.6
-
μs
μs
4.7
-
0.6
-
μs
0
3.45*2
0
0.9*3
μs
tSUDAT
250
-
100
-
ns
tSUSTO
4.0
-
0.6
-
μs
tBUF
4.7
-
1.3
-
μs
2 tCYCP*4
-
2 tCYCP*4
-
ns
tSUSTA
tHDDAT
tSP
CL = 30 pF,
R = (Vp/IOL)*1
-
Remarks
*1: R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it doesn't extend at least "L" period (tLOW) of device's SCL signal.
*3: Fast-mode I2C bus device can be used on Standard-mode I2C bus system as long as the device satisfies the requirement
of "tSUDAT ≥ 250 ns".
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see “8. Block Diagram" in this datasheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
Document Number: 002-05627 Rev. *B
Page 63 of 81
MB9A110K Series
12.4.13 JTAG Timing
(Vcc = 2.7 V to 5.5 V, Vss = 0 V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Conditions
TMS, TDI setup time
tJTAGS
TCK,
TMS, TDI
Vcc ≥ 4.5 V
TMS, TDI hold time
tJTAGH
TCK,
TMS, TDI
Vcc ≥ 4.5 V
TDO delay time
tJTAGD
TCK,
TDO
Min
Value
Max
Unit
15
-
ns
15
-
ns
Vcc ≥ 4.5 V
-
25
Vcc < 4.5 V
-
45
Vcc < 4.5 V
Vcc < 4.5 V
Remarks
ns
Note:
−
When the external load capacitance = 30 pF.
TCK
TMS/TDI
TDO
Document Number: 002-05627 Rev. *B
Page 64 of 81
MB9A110K Series
12.5 12-bit A/D Converter
Electrical characteristics for the A/D converter
(Vcc = AVcc = 2.7 V to 5.5 V, Vss = AVss = 0 V, TA = - 40°C to + 105°C)
Parameter
Symbol
-
Pin
name
-
Resolution
Integral nonlinearity
Differential nonlinearity
Zero transition voltage
VZT
ANxx
Full-scale transition voltage
VFST
ANxx
-
Conversion time
-
Min
- 4.5
-2.5
- 20
AVRH 20
1.0*1
1.2*1
*2
*2
Value
Typ
-
Max
12
+ 4.5
+ 2.5
+ 20
Unit
bit
LSB
LSB
mV
-
AVRH + 20
mV
-
-
μs
Sampling time
Ts
-
Compare clock cycle*3
Tcck
-
50
-
2000
ns
State transition time to
operation permission
Tstt
-
-
-
1.0
μs
Analog input capacity
CAIN
-
-
-
12.9
pF
Analog input resistance
RAIN
-
-
-
-
AVSS
2.7
-
Interchannel disparity
Analog port input leak current
Analog input voltage
Reference voltage
-
ANxx
ANxx
AVRH
2
3.8
4
5
AVRH
AVCC
ns
kΩ
Remarks
AVRH = 2.7 V to 5.5 V
AVcc ≥ 4.5 V
AVcc < 4.5 V
AVcc ≥ 4.5 V
AVcc < 4.5 V
AVcc ≥ 4.5 V
AVcc < 4.5 V
LSB
μA
V
V
*1: Conversion time is the value of sampling time (Ts) + compare time (Tc).
The condition of the minimum conversion time is the following.
AVcc ≥ 4.5 V, HCLK=40 MHz sampling time: 300 ns, compare time: 700 ns
AVcc < 4.5 V, HCLK=40 MHz sampling time: 500 ns, compare time: 700 ns
Ensure that it satisfies the value of sampling time (Ts) and compare clock cycle (Tcck).
For setting of sampling time and compare clock cycle, see "Chapter 1-1: A/D Converter" in "FM3 Family Peripheral Manual
Analog Macro Part".
The A/D Converter register is set at APB bus clock timing. The sampling clock and compare clock are set at Base clock
(HCLK).
About the APB bus number which the A/D Converter is connected to, see "8. Block Diagram" in this datasheet.
*2: A necessary sampling time changes by external impedance.
Ensure that it set the sampling time to satisfy (Equation 1).
*3: Compare time (Tc) is the value of (Equation 2).
Document Number: 002-05627 Rev. *B
Page 65 of 81
MB9A110K Series
Rext
ANxx
Analog input pin
Comparator
RAIN
Analog
signal source
CAIN
(Equation 1) Ts ≥ ( RAIN + Rext ) × CAIN × 9
Ts:
Sampling time
RAIN: Input resistance of A/D = 2 kΩ at 4.5 V < AVCC < 5.5 V
Input resistance of A/D = 3.8 kΩ at 2.7 V < AVCC < 4.5 V
CAIN: Input capacity of A/D = 12.9 pF at 2.7 V < AVCC < 5.5 V
Rext: Output impedance of external circuit
(Equation 2) Tc = Tcck × 14
Tc:
Compare time
Tcck: Compare clock cycle
Document Number: 002-05627 Rev. *B
Page 66 of 81
MB9A110K Series
Definition of 12-bit A/D converter terms
Resolution:
Analog variation that is recognized by an A/D converter.
Integral Nonlinearity:
Deviation of the line between the zero-transition point
(0b000000000000←→0b000000000001) and the full-scale transition point
(0b111111111110←→0b111111111111) from the actual conversion characteristics.
Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB.
Integral nonlinearity
Differential nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
Actual conversion
characteristics
0x(N+1)
{1 LSB(N-1) + VZT}
VFST
VNT
0x004
(Actuallymeasured
value)
(Actually-measured
value)
0x003
Digital output
Digital output
0xFFD
0xN
Ideal characteristics
V(N+1)T
0x(N-1)
(Actually-measured
value)
Actual conversion
characteristics
Ideal characteristics
0x002
VNT
(Actually-measured
value)
0x(N-2)
0x001
VZT (Actually-measured value)
AVss
Actual conversion characteristics
AVRH
AVss
Analog input
Integral nonlinearity of digital output N =
Differential nonlinearity of digital output N =
1LSB =
N:
VZT:
VFST:
VNT:
AVRH
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST - VZT
4094
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
Document Number: 002-05627 Rev. *B
Page 67 of 81
MB9A110K Series
12.6 Low-Voltage Detection Characteristics
12.6.1 Low-Voltage Detection Reset
(TA = - 40°C to + 105°C)
Parameter
Detected voltage
Released voltage
Symbol
Conditions
-
VDL
VDH
Min
2.25
2.30
Value
Typ
2.45
2.50
Max
2.65
2.70
Unit
V
V
Remarks
When voltage drops
When voltage rises
12.6.2 Interrupt of Low-voltage Detection
(TA = - 40°C to + 105°C)
Parameter
Symbol
Detected voltage
Released voltage
Detected voltage
VDL
VDH
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
LVD stabilization wait time
TLVDW
Conditions
SVHI = 0000
SVHI = 0001
SVHI = 0010
SVHI = 0011
SVHI = 0100
SVHI = 0111
SVHI = 1000
SVHI = 1001
-
Min
2.58
2.67
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
-
Value
Typ
2.8
2.9
3.0
3.1
3.2
3.3
3.6
3.7
3.7
3.8
4.0
4.1
4.1
4.2
4.2
4.3
-
Max
3.02
3.13
3.24
3.34
3.45
3.56
3.88
3.99
3.99
4.10
4.32
4.42
4.42
4.53
4.53
4.64
2240 × tCYCP*1
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Remarks
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
μs
*1: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05627 Rev. *B
Page 68 of 81
MB9A110K Series
12.7 MainFlash Memory Write/Erase Characteristics
12.7.1 Write / Erase time
(Vcc = 2.7 V to 5.5 V, TA = - 40°C to + 105°C)
Value
Parameter
Typ*1
Max*1
Large Sector
0.7
3.7
Small Sector
0.3
1.1
Half word (16-bit)
write time
12
Chip erase time
3.8
Unit
Remarks
s
Includes write time prior to internal erase
384
μs
Not including system-level overhead time
16.2
s
Includes write time prior to internal erase
Sector erase time
*1: The typical value is immediately after shipment, the maximum value is guarantee value under 100,000 cycle of erase/write.
12.7.2 Erase/write cycles and data hold time
Erase/write cycles (cycle)
Data hold time (year)
1,000
20*1
10,000
10*1
100,000
5*1
*1: At average + 85°C
12.8 WorkFlash Memory Write/Erase Characteristics
12.8.1 Write / Erase time
(Vcc = 2.7 V to 5.5 V, TA = - 40°C to + 105°C)
Parameter
Value
Unit
Remarks
Typ*1
Max*1
Sector erase time
0.3
1.5
s
Includes write time prior to internal erase
Half word (16-bit)
write time
20
384
μs
Not including system-level overhead time
Chip erase time
1.2
6
s
Includes write time prior to internal erase
*1: The typical value is immediately after shipment, the maximum value is guarantee value under 10,000 cycle of erase/write.
12.8.2 Erase/write cycles and data hold time
Erase/write cycles (cycle)
Data hold time (year)
1,000
20*1
10,000
10*1
*1: At average + 85C
Document Number: 002-05627 Rev. *B
Page 69 of 81
MB9A110K Series
12.9 Return Time from Low-Power Consumption Mode
12.9.1 Return Factor: Interrupt/WKUP
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the
program operation.
Return count time
(VCC = 2.7 V to 5.5 V, TA = - 40°C to + 105°C)
Parameter
Symbol
Value
Max*1
Typ
tCYCC
SLEEP mode
High-speed CR TIMER mode,
Main TIMER mode,
PLL TIMER mode
Unit
ns
40
80
μs
370
740
μs
Sub TIMER mode
699
929
μs
STOP mode
505
834
μs
Low-speed CR TIMER mode
Ticnt
Remarks
*1: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by external interrupt*1)
Ext.INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
*1: External interrupt is set to detecting fall edge.
Document Number: 002-05627 Rev. *B
Page 70 of 81
MB9A110K Series
Operation example of return from Low-Power consumption mode (by internal resource interrupt*1)
Internal
Resource INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
*1: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes.
See "Chapter 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3 Family Peripheral Manual about
the return factor from Low-Power consumption mode.
−
When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See "Chapter 6: Low Power Consumption Mode" in "FM3 Family Peripheral Manual".
Document Number: 002-05627 Rev. *B
Page 71 of 81
MB9A110K Series
12.9.2 Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program
operation.
Return count time
(VCC = 2.7 V to 5.5 V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Typ
Max*1
365
554
μs
365
554
μs
555
934
μs
Sub TIMER mode
608
976
μs
STOP mode
475
774
μs
SLEEP mode
High-speed CR TIMER mode,
Main TIMER mode,
PLL TIMER mode
Low-speed CR TIMER mode
Trcnt
Remarks
*1: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Document Number: 002-05627 Rev. *B
Start
Page 72 of 81
MB9A110K Series
Operation example of return from low power consumption mode (by internal resource reset*1)
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
*1: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes.
See "Chapter 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3 Family Peripheral Manual.
−
When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See "Chapter 6: Low Power Consumption Mode" in "FM3 Family Peripheral Manual".
−
The time during the power-on reset/low-voltage detection reset is excluded. See "12.4.7. Power-on Reset Timing in 12.4. AC
Characteristics in 12. Electrical Characteristics" for the detail on the time during the power-on reset/low -voltage detection
reset.
−
When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is
necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time.
−
The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-05627 Rev. *B
Page 73 of 81
MB9A110K Series
13. Ordering Information
Part number
On-chip
Flash
memory
On-chip
SRAM
MB9AF111KPMC-G-JNE2
Main: 64 KB
Work: 32 KB
16 KB
MB9AF112KPMC-G-JNE2
Main: 128 KB
Work: 32 KB
16 KB
MB9AF111KPMC1-G-JNE2
Main: 64 KB
Work: 32 KB
16 KB
MB9AF112KPMC1-G-JNE2
Main: 128 KB
Work: 32 KB
16 KB
MB9AF111KQN-G-AVE2
Main: 64 KB
Work: 32 KB
16 KB
MB9AF112KQN-G-AVE2
Main: 128 KB
Work: 32 KB
16 KB
Document Number: 002-05627 Rev. *B
Package
Packing
Plastic LQFP
48-pin (0.5 mm pitch),
(LQA048)
Plastic LQFP
52-pin (0.65 mm pitch),
(LQC052)
Tray
Plastic QFN
48-pin (0.5 mm pitch),
(VNA048)
Page 74 of 81
MB9A110K Series
14. Package Dimensions
Package Type
Package Code
LQFP 48pin (0.5mm pitch)
LQA048
4
D
D1
5 7
36
25
37
24
E1
24
37
13
48
E
5
7
3
36
25
4
6
48
13
1
12
e
1
12
2 5 7
0.10 C A-B D
3
0.20 C A-B D
b
0.80
C A-B
D
8
2
A
9
A
A'
0.80 C
SYMBOL
L1
0.25
L
A1
c
b
10
SECTION A-A'
DIMENSIONS
MIN.
NOM. MAX.
0.00
0.20
1.70
A
A1
SEATING
PLANE
b
0.15
0.27
c
0.09
0.20
D
9.00 BSC
D1
7.00 BSC
e
0.50 BSC
E
9.00 BSC
E1
7.00 BSC
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
0
8
PACKAGE OUTLINE, 48 LEAD LQFP
7.0X7.0X1.7 MM LQA048 REV**
002-13731 **
Document Number: 002-05627 Rev. *B
Page 75 of 81
MB9A110K Series
Package Type
Package Code
QFN 48pin (0.5mm pitch)
VNA048
0.10
D
C A B
D2
A
25
36
0.10 C
24
2X
(ND-1)
E
0.10
37
e
C A B
E2
5
13
9
INDEX MARK
8
48
12
R
1
L
B
TOP VIEW
e
b
4
0.10 C
0.10
0.05
C A B
C
BOTTOM VIEW
2X
0.10 C
A
0.05 C SEATING PLANE
A1
9
C
SIDE VIEW
DIMENSIONS
SYMBOL
MIN.
NOM.
A
A1
0.90
0.00
0.05
D
7.00 BSC
E
7.00 BSC
b
0.20
0.25
D2
5.50 BSC
E2
5.50 BSC
e
0.50 BSC
R
0.20 REF
L
MAX.
0.35
0.40
NOTE
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCINC CONFORMS TO ASME Y14.5-1994.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP.IF THE TERMINAL HAS
THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL. THE
DIMENSION "b"SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
5. ND REFER TO THE NUMBER OF TERMINALS ON D OR E SIDE.
0.30
6. MAX. PACKAGE WARPAGE IS 0.05mm.
7. MAXIMUM ALLOWABLE BURRS IS 0.076mm IN ALL DIRECTIONS.
8. PIN #1 ID ON TOP WILL BE LOCATED WITHIN INDICATED ZONE.
9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSEDHEAT
SINK SLUG AS WELL AS THE TERMINALS.
0.45
10. JEDEC SPEC
IFICATIONNO . REF : N/A
PACKAGE OUTLINE, 48 LEAD QFN
7.0X7.0X0.9 MMVNA048 5.5X5.5 MMEPAD(SAWN) REV**
002-15528 **
Document Number: 002-05627 Rev. *B
Page 76 of 81
MB9A110K Series
Package Type
Package Code
LQFP 52pin (0.65mm pitch)
LQC052
4
D
D1
39
5 7
27
26
40
39
27
26
40
14
52
E1 E
4
5
7
3
6
14
52
1
2 5 7
13
e
b
0.20 C A-B D
0.13
C A-B
1
13
0.10 C A-B D
3
BOTTOM VIEW
D
8
TOP VIEW
A
2
0.25
A
A'
0.10 C
SEAT ING
PLA NE
L1
L
A1
10
9
c
b
SECTION A-A'
SIDE VIEW
SYMBOL
DIMENSION
MIN.
NOM. MAX.
1.70
A
A1
0.00
0.20
b
0.265
c
0.09
0.30
0.365
0.20
D
12.00 BSC
D1
10.00 BSC
e
0.65 BSC
E
12.00 BSC
E1
10.00 BSC
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
0
PACKAGE OUTLINE, 52 LEAD LQFP
10.0X10.0X1.7 MM LQC052 REV**
002-13880 **
Document Number: 002-05627 Rev. *B
Page 77 of 81
MB9A110K Series
15. Major Changes
Spansion Publication Number: DS706-00030
Page
Section
Revision 1.0
PRODUCT LINEUP
7
Function
PACKAGES
8
I/O CIRCUIT TYPE
23
BLOCK DIAGRAM
34
ELECTRICAL CHARACTERISTICS
3. DC Characteristics
(1) Current Rating
45, 46
61
66
(9) External Input Timing
5. 12-bit A/D Converter
Electrical characteristics for the A/D converter
7. MainFlash Memory Write/Erase
Characteristics
Erase/write cycles and data hold time
70
8. WorkFlash Memory Write/Erase
Characteristics
Erase/write cycles and data hold time
Revision 1.1
Revision 2.0
25
I/O Circuit Type
25, 26
I/O Circuit Type
32
Handling Devices
Handling Devices
32
Crystal oscillator circuit
Handling Devices
33
C Pin
34
Block Diagram
Memory Map
35
Memory map(1)
Memory Map
36
Memory map(2)
43, 44
Electrical Characteristics
1. Absolute Maximum Ratings
45
Electrical Characteristics
2. Recommended Operation Conditions
46-48
Electrical Characteristics
3. DC Characteristics
(1) Current rating
Document Number: 002-05627 Rev. *B
Change Results
PRELIMINARY → Datasheet
Added the pin count.
Revised from "Planning".
Corrected the following description to "TypeB".
Digital output → Digital input
Corrected the following description.
AHB (Max 40MHz) → AHB (Max 42MHz)
APB0 (Max 40MHz) → APB0 (Max 42MHz)
APB1 (Max 40MHz) → APB1 (Max 42MHz)
APB2 (Max 40MHz) → APB2 (Max 42MHz)
Deleted the description for "USB Clock Ctrl / PLL".
Revised the value of "TBD".
Corrected the value.
- Power supply current (ICCR)
Typ: 60 → 50
- Power supply current (ICCRD) (RAM hold off)
Typ: 45 → 30
- Power supply current (ICCRD) (RAM hold on)
Typ: 48 → 33
Revised the value of "TBD".
Deleted "(Preliminary value)".
Corrected the value of "Compare clock cycle".
Max: 10000 → 2000
Deleted"(targeted value)".
Company name and layout design change
Added the description of I2C to the type of E and F
Added about +B input
Added "Stabilizing power supply voltage"
Added the following description
"Evaluate oscillation of your using crystal oscillator by your mount board."
Changed the description
Modified the block diagram
Modified the area of "External Device Area"
Added the summary of Flash memory sector and the note
Added the Clamp maximum current
Added the output current of P80 and P81
Added about +B input
Modified the minimum value of Analog reference voltage
Added Smoothing capacitor
Added the note about less than the minimum power supply voltage
Changed the table format
Added Main TIMER mode current
Added Flash Memory Current
Moved A/D Converter Current
Page 78 of 81
MB9A110K Series
Page
51
52
53
54
56-63
69
74-77
78
Section
Electrical Characteristics
4. AC Characteristics
(1) Main Clock Input Characteristics
Electrical Characteristics
4. AC Characteristics
(3) Built-in CR Oscillation Characteristics
Electrical Characteristics
4. AC Characteristics
(4-1) Operating Conditions of Main PLL
(4-2) Operating Conditions of Main PLL
Electrical Characteristics
4. AC Characteristics
(6) Power-on Reset Timing
Electrical Characteristics
4. AC Characteristics
(7) CSIO/UART Timing
Electrical Characteristics
5. 12bit A/D Converter
Electrical Characteristics
9. Return Time from Low-Power Consumption
Mode
Ordering Information
Change Results
Added Master clock at Internal operating clock frequency
Added Frequency stability time at Built-in high-speed CR
Added Main PLL clock frequency
Added the figure of Main PLL connection
Added Time until releasing Power-on reset
Changed the figure of timing
Modified from UART Timing to CSIO/UART Timing
Changed from Internal shift clock operation to Master mode
Changed from External shift clock operation to Slave mode
Added the typical value of Integral Nonlinearity, Differential Nonlinearity, Zero
transition voltage and Full-scale transition voltage
Added Conversion time at AVcc < 4.5 V
Modified Stage transition time to operation permission
Modified the minimum value of Reference voltage
Added Return Time from Low-Power Consumption Mode
Changed the description of part number
Note: Please see “Document History” about later revised information.
Document Number: 002-05627 Rev. *B
Page 79 of 81
MB9A110K Series
Document History
Document Title: MB9A110K Series 32-bit ARM® Cortex®-M3, FM3 Microcontroller
Document Number: 002-05627
Orig. of
Submission
Change
Date
–
TOYO
02/20/2015
5226072
TOYO
Revision
ECN
**
*A
Description of Change
Migrated to Cypress and assigned document number 002-05627.
No change to document contents or format.
04/18/2016
Updated to Cypress format.
Changed an explanation from “from 01 to 99” to “from 00 to 99” in Real-Time Clock
(RTC) (Page 2) of Features, and Deleted “Second/A day of the week” of interrupt
function.
Changed package code as the following in chapter :
2. Packages
3. Pin Assignment
13. Ordering Information
14. Package Dimensions.
FTP-48P-M49 -> LQA048, LCC-48P-M73 -> VNA048,
*B
5561750
YSKA
03/22/2017
FPT-52P-M02 -> LQC052
Corrected “J-TAG" to “JTAG" in 4. List of Pin Functions.
Added Note for JTAG pin in 4. List of Pin Functions.
Changed remark [1] to "When all ports are input and are fixed at "0"." in 12.3.1 Current
Rating.
Changed Parameter “Power supply rising time (tVCCR)” to “Power ramp rate (dV/dt)” in
12.4.7 Power-on Reset Timing, Changed the minimum to 0.7mV/μs, Changed the
maximum to 1000mV/μs, and Added remarks and note.
Corrected "Analog port input current" to "Analog port input leak current" in 12.5 12-bit
A/D Converter.
Added the Baud rate spec in “12.4.9 CSIO/UART Timing”(Page 52, 54, 56, 58)
Document Number: 002-05627 Rev. *B
Page 80 of 81
MB9A110K Series
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2012-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
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permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the applicati on or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It
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products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support
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failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-05627 Rev. *B
March 22, 2017
Page 81 of 81